Semiconductor structure and forming method thereof, and memory

Abstract

The present disclosure relates to a semiconductor structure, a method for forming the same, and a memory. The method comprises: forming an initial semiconductor structure comprising a substrate, a word line structure, and a gate structure, wherein the substrate comprises an array region and a peripheral region, and the word line structure extends from the array region to the peripheral region; the word line structure comprises a first conductive layer, a second conductive layer, and a word line cap layer; forming an opening of the first conductive layer exposing the peripheral region; forming a first insulating layer covering the opening and the gate structure; forming a second insulating layer filling the opening, wherein the top surface of the second insulating layer is flush with the top surface of the first insulating layer located on the top surface of the gate structure; forming a third insulating layer on the surface of a structure jointly constituted by the second insulating layer and the first insulating layer; etching the third insulating layer, the second insulating layer, and the first insulating layer to form a first contact hole and a second contact hole; forming a first contact plug in the first contact hole, and forming a second contact plug in the second contact hole.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration and fast transmission speed.

[0003] During the manufacturing process of the contact structure of the word line structure, structural defects are prone to occur due to the limitation of the process technology, and the product yield is low.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, and a memory, which can reduce structural defects and improve product yield.

[0006] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising:

[0007] forming an initial semiconductor structure, the initial semiconductor structure comprising a substrate, a word line structure, and a gate structure, the substrate comprising an array region and a peripheral region, the word line structure being located within the substrate and extending from the array region to the peripheral region; the word line structure comprising a first conductive layer, a second conductive layer, and a word line cap layer stacked and distributed in sequence from bottom to top in a direction perpendicular to the substrate, and the gate structure being located in the peripheral region;

[0008] Etching the word line capping layer and the second conductive layer in the peripheral region to form an opening in the peripheral region exposing the first conductive layer;

[0009] forming a first insulating layer conformally covering the opening and the gate structure;

[0010] forming a second insulating layer, wherein the second insulating layer fills the opening, and a top surface of the second insulating layer is flush with a top surface of the first insulating layer located on the top surface of the gate structure;

[0011] forming a third insulating layer on the second insulating layer and a top surface of the first insulating layer located on a top surface of the gate structure;

[0012] Etching the third insulating layer, the second insulating layer, and the first insulating layer to form a first contact hole exposing the first conductive layer in the peripheral region and a second contact hole exposing the substrate on one side of the gate structure;

[0013] A first contact plug is formed in the first contact hole, and a second contact plug is formed in the second contact hole.

[0014] In an exemplary embodiment of the present disclosure, the gate structure includes a gate dielectric layer, a gate conductive layer, and a gate cap layer stacked sequentially from bottom to top in a direction perpendicular to the substrate, and the forming method further includes:

[0015] During the process of etching to form the first contact hole and the second contact hole, the third insulating layer, the first insulating layer, and the gate cap layer located on the top surface of the gate structure are simultaneously etched to form a third contact hole exposing the gate conductive layer;

[0016] A third contact plug is formed in the third contact hole.

[0017] In an exemplary embodiment of the present disclosure, forming the initial semiconductor structure includes:

[0018] Providing a substrate, the substrate comprising an array region and a peripheral region;

[0019] forming a word line trench in the substrate, wherein the word line trench extends from the array region to the peripheral region;

[0020] forming a word line dielectric layer, a first conductive layer, a second conductive layer and a word line capping layer in the word line trench, wherein the first conductive layer, the second conductive layer and the word line capping layer together constitute the word line structure;

[0021] A gate structure is formed in the peripheral region, and an orthographic projection of the gate structure on the substrate does not overlap with an orthographic projection of the word line structure on the substrate.

[0022] In an exemplary embodiment of the present disclosure, the gate structure further includes a sidewall spacer, which covers the sidewalls of the gate dielectric layer, the gate conductive layer and the gate cap layer, and the first insulating layer covers the surface of the sidewall spacer and the gate cap layer.

[0023] In an exemplary embodiment of the present disclosure, forming the second insulating layer includes:

[0024] forming an insulating material layer on a surface of the first insulating layer, wherein the insulating material layer fills the opening;

[0025] The insulating material layer is subjected to chemical mechanical polishing to remove the insulating material layer on the surface of the first insulating layer on the gate structure, and to make the surface of the remaining insulating material layer flush with the surface of the first insulating layer on the gate structure.

[0026] In an exemplary embodiment of the present disclosure, the substrate is made of single-crystal silicon, and the second conductive layer is made of polycrystalline silicon.

[0027] In an exemplary embodiment of the present disclosure, a trench isolation structure is provided in the peripheral region. The trench isolation structure is located in an edge region of the peripheral region and is adjacent to the array region. The word line structure extends into the trench isolation structure.

[0028] In an exemplary embodiment of the present disclosure, the first insulating layer, the third insulating layer, and the gate cap layer are made of the same material, and the second insulating layer is made of a material different from that of the first insulating layer.

[0029] In an exemplary embodiment of the present disclosure, materials of the first insulating layer, the third insulating layer, and the gate cap layer are all silicon nitride, and material of the second insulating layer is silicon oxide.

[0030] According to one aspect of the present disclosure, there is provided a semiconductor structure comprising:

[0031] A substrate comprising an array region and a peripheral region, wherein the peripheral region is provided with a gate structure;

[0032] a word line structure located within the substrate and comprising a first conductive layer, a second conductive layer, and a word line cap layer stacked and distributed in sequence from bottom to top in a direction perpendicular to the substrate, wherein the first conductive layer extends from the array region to the peripheral region, and the orthographic projections of the second conductive layer and the word line cap layer on the substrate are both located within the array region;

[0033] a first insulating layer conformally covering the gate structure and a surface of the first conductive layer located in the peripheral region;

[0034] a second insulating layer, covering at least a surface of the first insulating layer located on a surface of the first conductive layer, and having a top surface flush with a top surface of the first insulating layer located on a top surface of the gate structure;

[0035] a third insulating layer covering the second insulating layer and a top surface of the first insulating layer located on a top surface of the gate structure;

[0036] a first contact plug, penetrating the first insulating layer, the second insulating layer, and the third insulating layer on the first conductive layer in the peripheral region, and contacting and connecting with the first conductive layer;

[0037] A second contact plug penetrates the first insulating layer, the second insulating layer and the third insulating layer located on one side of the gate structure and is in contact with the substrate.

[0038] In an exemplary embodiment of the present disclosure, the gate structure includes a gate dielectric layer, a gate conductive layer, and a gate cap layer stacked sequentially from bottom to top in a direction perpendicular to the substrate, and the semiconductor structure further includes:

[0039] A third contact plug penetrates the third insulating layer, the first insulating layer and the gate cap layer on the top surface of the gate structure, and is in contact with and connected to the gate conductive layer.

[0040] In an exemplary embodiment of the present disclosure, the gate structure further includes a sidewall spacer, which covers the sidewalls of the gate dielectric layer, the gate conductive layer and the gate cap layer, and the first insulating layer covers the surface of the sidewall spacer and the gate cap layer.

[0041] In an exemplary embodiment of the present disclosure, a trench isolation structure is provided in the peripheral region. The trench isolation structure is located in an edge region of the peripheral region and is adjacent to the array region. The word line structure extends into the trench isolation structure.

[0042] In an exemplary embodiment of the present disclosure, the first insulating layer, the third insulating layer, and the gate cap layer are made of the same material, and the second insulating layer is made of a material different from that of the first insulating layer.

[0043] According to one aspect of the present disclosure, a memory is provided, comprising any one of the semiconductor structures described above.

[0044] The disclosed semiconductor structure, formation method, and memory device, wherein the wordline capping layer and second conductive layer in the peripheral region are removed before forming the first insulating layer, allows the surfaces of the first conductive layer exposed in the substrate and the peripheral region to be sequentially covered with the first insulating layer, the second insulating layer, and the third insulating layer. During the subsequent etching process to form the first and second contact holes, the film structure on the substrate surface is substantially identical to the film structure on the surface of the first conductive layer in the peripheral region, minimizing the difference in etching rates between the first and second contact holes. This reduces overetching of the substrate during etching, helps reduce structural defects, and thereby improves product yield. Furthermore, since the first contact plug is formed within the first contact hole, it can be electrically connected to the first conductive layer of the wordline structure, facilitating application of a voltage to the wordline structure via the first contact plug. Simultaneously, since the second contact plug is formed within the second contact hole, it can be electrically connected to the substrate, facilitating application of a voltage to the substrate via the second contact plug.

[0045] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0047] Figure 1 Schematic diagram of a semiconductor structure in related art.

[0048] Figure 2 Flowchart of a method for forming a semiconductor structure in an embodiment of the present disclosure.

[0049] Figure 3 FIG. 1 is a schematic diagram of an array region of an initial semiconductor structure in an embodiment of the present disclosure.

[0050] Figure 4 FIG. 1 is a schematic diagram of a peripheral region of an initial semiconductor structure in an embodiment of the present disclosure.

[0051] Figure 5 Schematic diagram of the sidewall isolation layer in an embodiment of the present disclosure.

[0052] Figure 6 FIG. 4 is a top view of a word line trench in an embodiment of the present disclosure.

[0053] Figure 7 In the embodiment of the present disclosure, step S230 is completed. Figure 6 Cross-sectional view taken along the aa' direction.

[0054] Figure 8 Schematic diagram of the mask layer and the photoresist layer in the embodiment of the present disclosure.

[0055] Figure 9 This is a schematic diagram after step S120 is completed in the embodiment of the present disclosure.

[0056] Figure 10 Schematic diagram of the first insulating layer and the second insulating layer located in the array area in an embodiment of the present disclosure.

[0057] Figure 11 Schematic diagram of a first insulating layer and a second insulating layer located in a peripheral region in an embodiment of the present disclosure.

[0058] Figure 12 FIG. 1 is a schematic diagram of the array area after step S310 is completed in an embodiment of the present disclosure.

[0059] Figure 13 Schematic diagram of the peripheral area after step S310 is completed in an embodiment of the present disclosure.

[0060] Figure 14 Schematic diagram of the third insulating layer located in the array area in an embodiment of the present disclosure.

[0061] Figure 15 FIG. 4 is a schematic diagram of a third insulating layer located in the peripheral region in an embodiment of the present disclosure.

[0062] Figure 16 Schematic diagram of the first contact hole in an embodiment of the present disclosure.

[0063] Figure 17 Schematic diagram of the second contact hole in an embodiment of the present disclosure.

[0064] Figure 18 Schematic diagram of the first contact plug in an embodiment of the present disclosure.

[0065] Figure 19 Schematic diagram of the second contact plug in an embodiment of the present disclosure.

[0066] Figure 20 Schematic diagram of the third contact hole in the embodiment of the present disclosure.

[0067] Figure 21 Schematic diagram of the third contact plug in the embodiment of the present disclosure.

[0068] Description of reference numerals:

[0069] 11. Substrate; 111. Shallow trench isolation structure; 112. Active area; 12. Word line structure; 120. Word line trench; 121. First conductive layer; 122. Second conductive layer; 123. Word line cap layer; 124. Word line dielectric layer; 13. Gate structure; 131. Gate dielectric layer; 132. Gate conductive layer; 133. Gate cap layer; 134. Spacer spacer; 1341. First isolation layer; 1342. Second isolation layer; 101. Opening; 14. Trench isolation structure; 15. Bit line contact plug; 16, bit line conductive material layer; 17, bit line covering layer; 2, first insulating layer; 210, insulating material layer; 3, second insulating layer; 4, third insulating layer; 5, first contact plug; 6, second contact plug; 7, third contact plug; 100, first contact hole; 200, second contact hole; 300, third contact hole; 400, mask layer; 500, photoresist layer; 501, developing area; A, array area; B, peripheral area; x, first direction; y, second direction. DETAILED DESCRIPTION

[0070] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0071] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0072] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0073] like Figure 1As shown, a dynamic random access memory (DRAM) includes a substrate 10, a wordline structure 20 formed within the substrate 10, and a transistor (not shown) located on the substrate 10. To facilitate application of voltage to the substrate 10, the wordline structure 20, and the transistor, contact plugs are typically formed on the substrate 10, the wordline structure 20, and the transistor, respectively. The wordline structure 20 typically includes a stacked first conductive layer 201 and a second conductive layer 202. During the formation of the contact plugs, to reduce resistance, the second conductive layer 202 needs to be etched through when forming a via 30 to accommodate the contact plugs, thereby exposing the underlying first conductive layer 201. However, the physical and chemical properties of the material of the second conductive layer 202 (e.g., polysilicon) are typically similar to those of the active region in the substrate 10. Etching the second conductive layer 202 can easily damage the active region (e.g., severe overetching), resulting in a low product yield.

[0074] Based on this, the present disclosure provides a method for forming a semiconductor structure. Figure 2 A flow chart of a method for forming a semiconductor structure disclosed in the present invention is shown, Figure 2 As shown, the forming method includes steps S110 to S170, wherein:

[0075] Step S110, forming an initial semiconductor structure, the initial semiconductor structure comprising a substrate, a word line structure, and a gate structure, the substrate comprising an array region and a peripheral region, the word line structure being located within the substrate and extending from the array region to the peripheral region; the word line structure comprising a first conductive layer, a second conductive layer, and a word line cap layer stacked and distributed in sequence from bottom to top in a direction perpendicular to the substrate, and the gate structure being located in the peripheral region;

[0076] Step S120, etching the word line capping layer and the second conductive layer in the peripheral region to form an opening in the peripheral region exposing the first conductive layer;

[0077] Step S130 , forming a first insulating layer conformally covering the opening and the gate structure;

[0078] Step S140, forming a second insulating layer, wherein the second insulating layer fills the opening, and a top surface of the second insulating layer is flush with a top surface of the first insulating layer located on the top surface of the gate structure;

[0079] Step S150, forming a third insulating layer on the second insulating layer and the top surface of the first insulating layer located on the top surface of the gate structure;

[0080] Step S160, etching the third insulating layer, the second insulating layer, and the first insulating layer to form a first contact hole exposing the first conductive layer in the peripheral region and a second contact hole exposing the substrate on one side of the gate structure;

[0081] Step S170 , forming a first contact plug in the first contact hole, and forming a second contact plug in the second contact hole.

[0082] The disclosed method for forming a semiconductor structure removes the wordline capping layer and the second conductive layer in the peripheral region before forming the first insulating layer. This allows the surfaces of the first conductive layer exposed in the substrate and the peripheral region to be sequentially covered with the first insulating layer, the second insulating layer, and the third insulating layer. During the subsequent etching process to form the first and second contact holes, the film structure on the substrate surface is substantially identical to the film structure on the surface of the first conductive layer in the peripheral region, minimizing the difference in etching rates between the first and second contact holes. This reduces overetching of the substrate during the etching process, helps reduce structural defects, and thereby improves product yield. Furthermore, since the first contact plug is formed within the first contact hole, it can be electrically connected to the first conductive layer of the wordline structure, facilitating application of a voltage to the wordline structure via the first contact plug. Simultaneously, since the second contact plug is formed within the second contact hole, it can be electrically connected to the substrate, facilitating application of a voltage to the substrate via the second contact plug.

[0083] The following is a detailed description of the steps and details of the method for forming a semiconductor structure disclosed herein:

[0084] like Figure 2 As shown, in step S110, an initial semiconductor structure is formed, which includes a substrate, a word line structure and a gate structure. The substrate includes an array area and a peripheral area. The word line structure is located in the substrate and extends from the array area to the peripheral area. The word line structure includes a first conductive layer, a second conductive layer and a word line cap layer stacked and distributed in sequence from bottom to top along a direction perpendicular to the substrate. The gate structure is located in the peripheral area.

[0085] like Figure 3 and Figure 4As shown, the initial semiconductor structure may include a substrate 11, which may include an array region A and a peripheral region B. A wordline structure 12 may be embedded in the substrate 11 and may extend from the array region A to the peripheral region B. The wordline structure 12 may include a first conductive layer 121, a second conductive layer 122, and a wordline cap layer 123 stacked and arranged in a direction perpendicular to the substrate 11 from bottom to top. The first conductive layer 121 may be made of a metal material, for example, tungsten, titanium, or tantalum. The second conductive layer 122 may be made of a semiconductor material, for example, a material with a low work function, for example, polycrystalline silicon. While ensuring the turn-on voltage of the wordline structure 12, the second conductive layer 122 with a low work function is disposed on the surface of the first conductive layer 121, thereby reducing gate-induced drain leakage (GIDL). The word line capping layer 123 covers the surface of the second conductive layer 122. The material of the word line capping layer 123 can be an insulating material. The word line capping layer 123 can be used to insulate and protect the second conductive layer 122 of the word line structure 12, thereby reducing the risk of short circuit or coupling between the word line structure 12 and other surrounding structures, thereby helping to improve product yield.

[0086] The transistor in the peripheral region B may include a source region, a channel region and a drain region distributed in sequence, and a gate structure 13 located at the top of the channel region. The gate structure 13 may include a gate dielectric layer 131, a gate conductive layer 132 and a gate cap layer 133 stacked in sequence from bottom to top in a direction perpendicular to the substrate 11, wherein the gate dielectric layer 131 is located on the surface of the channel region, and the material of the gate dielectric layer 131 may be an insulating material, for example, it may be silicon oxide; the gate conductive layer 132 may be a composite film layer structure composed of multiple film layers, for example, it may include a polysilicon layer located on the surface of the gate dielectric layer 131, a titanium nitride layer located on the surface of the polysilicon layer, and a tungsten layer located on the surface of the titanium nitride layer. Since the titanium nitride layer has an ion blocking function, tungsten can be prevented from diffusing into the polysilicon layer through the titanium nitride layer, which helps to improve the stability of the device. The gate cap layer 133 can be located on the surface of the tungsten layer. The gate cap layer 133 can be made of an insulating material. The gate cap layer 133 can provide insulation protection for the gate conductive layer 132, thereby reducing the risk of short circuits or coupling between the gate structure 13 and other surrounding structures, further improving product yield. For example, the initial semiconductor structure can be the structure after the word line structure 12 and the transistors in the peripheral region B are formed during the memory manufacturing process.

[0087] In an exemplary embodiment of the present disclosure, Figure 5As shown, the gate structure 13 may further include a sidewall spacer 134. The sidewall spacer 134 may cover the sidewalls of the gate dielectric layer 131, the gate conductive layer 132, and the gate cap layer 133. The sidewall spacer 134 may be a single-layer film structure or a composite film structure composed of multiple film layers, without special limitation herein. For example, the sidewall spacer structure may include a first spacer 1341 and a second spacer 1342, wherein the first spacer 1341 may conformally cover the sidewalls of the gate dielectric layer 131, the gate conductive layer 132, and the gate cap layer 133. The material of the first spacer 1341 may be the same as that of the gate cap layer 133. For example, the material of the first spacer 1341 and the gate cap layer 133 may both be silicon nitride. During the manufacturing process, for convenience, a first isolation layer 1341 can be simultaneously formed on the sidewalls and surfaces of the substrate 11 and the gate structure 13. Subsequently, the first isolation layer 1341 located on the surface of the substrate 11 and on the top surface of the first isolation layer 1341 can be removed, leaving only the first isolation layer 1341 located on the sidewalls of the gate structure 13. A second isolation layer 1342 conformally covers the surface of the first isolation layer 1341. The material of the second isolation layer 1342 is different from that of the first isolation layer 1341. For example, the material of the second isolation layer 1342 can be silicon oxide. During the manufacturing process, the second isolation layer 1342 can be simultaneously formed on the surface of the structure composed of the gate structure 13, the first isolation layer 1341, and the substrate 11. Subsequently, the second isolation layer 1342 located on the surface of the substrate 11 and on the top surface of the gate structure 13 can be removed, leaving only the second isolation layer 1342 located on the sidewalls of the gate structure 13.

[0088] In some embodiments of the present disclosure, the initial semiconductor structure may further include a bit line contact plug 15, a bit line conductive material layer 16 and a bit line covering layer 17. During the subsequent manufacturing process, the bit line conductive material layer 16 and the bit line covering layer 17 will be etched to form a bit line structure. Since this part of the content does not involve the inventive concept of the present disclosure, it will not be described in detail.

[0089] In an exemplary embodiment of the present disclosure, forming an initial semiconductor structure may include steps S210 to S240, wherein:

[0090] In step S210 , a substrate 11 is provided. The substrate 11 includes an array region A and a peripheral region B.

[0091] The substrate 11 may be a flat plate structure, and may be rectangular, circular, elliptical, polygonal, or irregular in shape. The material of the substrate 11 may be a semiconductor material, such as single crystal silicon, but is not limited to silicon or other semiconductor materials. The shape and material of the substrate 11 are not particularly limited herein. For example, the substrate 11 may be a silicon substrate 11 having a shallow trench isolation structure 111 formed therein. The shallow trench isolation structure 111 can separate a plurality of active areas 112 on the substrate 11.

[0092] Please continue to see Figure 3 and Figure 4 As shown, substrate 11 may include an array region A and a peripheral region B. Array region A and peripheral region B may be adjacently located, with peripheral region B surrounding the periphery of array region A. Array region A may be used to form a capacitor array, a transistor array, a wordline structure 12 connecting the transistor array, and a bitline structure. Peripheral region B may be used to form wordline contact plugs and transistors. The wordline contact plugs may connect to wordline drivers, sense amplifiers, row decoders, column decoders, and special function control circuits located in peripheral region B. The control circuits may control the wordline structure 12 and bitline structure to implement storage and read functions of the transistor array and capacitor array.

[0093] In some embodiments of the present disclosure, please continue to refer to Figure 3 As shown, a trench isolation structure 14 may also be provided in the peripheral area B. The trench isolation structure 14 may be located in the edge area of ​​the peripheral area B close to the array area A. The trench isolation structure 14 may surround the array area A and be distributed adjacent to the array area A. The array area A and the peripheral area B may be separated by the trench isolation structure 14.

[0094] In step S220 , a word line trench 120 is formed in the substrate 11 , wherein the word line trench 120 extends from the array region A to the peripheral region B.

[0095] like Figure 6 As shown, the substrate 11 can be etched through an etching process to form word line trenches 120 in the substrate 11. The word line trenches 120 can extend along a first direction x. In the first direction x, the portion of the word line trenches 120 located in the array area A can penetrate the multiple active areas 112. The word line trenches 120 can extend from the array area A to the peripheral area B along the first direction x. For example, they can extend into the trench isolation structure 14 in the peripheral area B. There can be multiple word line trenches 120, and the multiple word line trenches 120 can be spaced apart along a second direction y. The first direction x and the second direction y can both be parallel to the substrate 11, and the second direction y can intersect with the first direction x. For example, the second direction y is perpendicular to the first direction x.

[0096] It should be noted that "perpendicular" can mean absolutely perpendicular or approximately perpendicular. Deviations are inevitable during the manufacturing process. In the present disclosure, angular deviations may occur due to manufacturing process limitations, resulting in a certain deviation in the angle between the first direction x and the second direction y. As long as the angular deviation between the first direction x and the second direction y is within a preset range, the first direction x and the second direction y can be considered perpendicular. For example, the preset range can be 10°, that is, the first direction x and the second direction y can be considered perpendicular as long as the angle between the first direction x and the second direction y is greater than or equal to 80° and less than or equal to 100°.

[0097] In step S230 , a word line dielectric layer 124 , a first conductive layer 121 , a second conductive layer 122 and a word line capping layer are formed in the word line trench 120 . The first conductive layer 121 , the second conductive layer 122 and the word line capping layer 123 together constitute the word line structure 12 .

[0098] like Figure 7 As shown, the wordline dielectric layer 124 can conformally cover the inner wall of the wordline trench 120 and can be made of silicon oxide. The wordline dielectric layer 124 can be formed on the inner wall of the wordline trench 120 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The first conductive layer 121 can be made of tungsten and can be formed within the wordline trench 120 having the wordline dielectric layer 124 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The second conductive layer 122 and the wordline capping layer 123 can be sequentially formed on the surface of the first conductive layer 121 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The surface of the wordline capping layer 123 can be flush with the surface of the substrate 11. The first conductive layer 121, the second conductive layer 122 and the word line capping layer 123 in the word line trench 120 can together constitute a word line structure 12. Since the word line trench 120 extends from the array area A to the trench isolation structure 14 in the peripheral area B, the word line structure 12 formed therein also extends into the trench isolation structure 14.

[0099] In step S240 , a gate structure 13 is formed in the peripheral region B, wherein an orthographic projection of the gate structure 13 on the substrate 11 does not overlap with an orthographic projection of the word line structure 12 on the substrate 11 .

[0100] Please continue to see Figure 4 As shown, a gate dielectric layer 131 can be formed on the surface of the channel region in the peripheral region B of the substrate 11 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or in-situ water-oxidation, a gate conductive layer 132 can be formed on the surface of the gate dielectric layer 131 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and a gate capping layer 133 can be formed on the surface of the gate conductive layer 132. It should be noted that the bit line conductive material layer 16 can be formed simultaneously during the formation of the gate conductive layer 132, and the bit line capping layer 17 can be formed simultaneously during the formation of the gate capping layer 133.

[0101] like Figure 2 As shown, in step S120 , the word line capping layer 123 and the second conductive layer 122 in the peripheral region B are etched to form an opening 101 in the peripheral region B exposing the first conductive layer 121 .

[0102] like Figure 8As shown, a mask layer 400 can be formed on the surface of the array region A and on the side of the wordline cap layer 123 away from the second conductive layer 122. For example, when the initial semiconductor structure also includes a bitline cap layer 17, the mask layer 400 can cover the bitline cap layer 17 and the surface of the peripheral region B. When the initial semiconductor structure does not include the bitline cap layer 17, the mask layer 400 can cover the wordline cap layer 123, other areas of the array region A, and the surface of the peripheral region B. The mask layer 400 can be a single-layer film structure or a composite film structure composed of multiple film layers, which is not specifically limited here. In an exemplary embodiment of the present disclosure, the mask layer 400 can include a spin-on carbon film layer (SOC) and a silicon oxynitride layer, wherein the silicon oxynitride layer is located on the side of the carbon film layer away from the substrate 11. A photoresist layer 500 can be formed on the surface of the mask layer 400 by spin coating or other methods. The material of the photoresist layer 500 can be a positive photoresist or a negative photoresist, which is not specifically limited here. The photoresist layer 500 may be exposed and developed to form a developed area 501. The projection of the developed area 501 in a direction perpendicular to the substrate 11 at least partially overlaps with the word line structure 12 located in the peripheral area B. The word line capping layer 123 and the second conductive layer 122 may be etched in the developed area 501, thereby removing the portion of the word line capping layer 123 and the second conductive layer 122 directly opposite the developed area 501, thereby forming an opening 101 that exposes at least a portion of the surface of the first conductive layer 121 located in the peripheral area B. In the embodiment of the present disclosure, the structure after completing step S120 is as follows: Figure 9 shown.

[0103] like Figure 2 As shown, in step S130 , a first insulating layer 2 is formed to conformally cover the opening 101 and the gate structure 13 .

[0104] The material of the first insulating layer 2 can be an insulating material, for example, silicon nitride. Figure 10 and Figure 11 As shown, the first insulating layer 2 can be formed on the opening 101 and the gate structure 13 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the first insulating layer 2 can also be formed by other methods, and the formation method of the first insulating layer 2 is not particularly limited here. The first insulating layer 2 can conformally cover the inner wall of the opening 101 and the surface of the gate structure 13. It should be noted that when the gate structure 13 includes a sidewall spacer 134, the first insulating layer 2 can cover the surface of the sidewall spacer 134 and the gate cap layer 133; when the initial semiconductor structure includes a bit line cover layer 17, the first insulating layer 2 can also cover the surface of the bit line cover layer 17 at the same time.

[0105] like Figure 2As shown, in step S140 , a second insulating layer 3 is formed. The second insulating layer 3 fills the opening 101 , and a top surface of the second insulating layer 3 is flush with a top surface of the first insulating layer 2 located on the top surface of the gate structure 13 .

[0106] Please continue to see Figure 10 and Figure 11 As shown, the material of the second insulating layer 3 can be an insulating material. The material of the second insulating layer 3 is different from that of the first insulating layer 2. The first insulating layer 2 and the second insulating layer 3 can balance structural stress, helping to reduce structural defects. For example, the material of the second insulating layer 3 can be silicon oxide. The second insulating layer 3 can be formed on the surface of the first insulating layer 2 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the second insulating layer 3 can also be formed by other methods. The formation method of the second insulating layer 3 is not particularly limited here. The second insulating layer 3 can fill the opening 101 and fill the height difference between the surface of the structure in the peripheral area B and the first insulating layer 2 on the top of the gate cap layer 133, thereby providing a flat base for subsequent processing and helping to reduce process complexity. That is, the second insulating layer 3 covers the surface of the first insulating layer 2 except for the area on the surface of the gate cap layer 133, and the top surface of the second insulating layer 3 (i.e., the surface away from the substrate 11) is flush with the top surface of the first insulating layer 2 on the surface of the gate cap layer 133.

[0107] In an exemplary embodiment of the present disclosure, forming the second insulating layer 3 may include steps S310 and S320, wherein:

[0108] In step S310 , an insulating material layer 210 is formed on the surface of the first insulating layer 2 , and the insulating material layer 210 fills the opening 101 .

[0109] The material of the insulating material layer 210 is different from that of the first insulating layer 2. For example, the insulating material layer 210 is made of silicon oxide. The insulating material layer 210 can be formed on the surface of the first insulating layer 2 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The insulating material layer 210 can fill the opening 101 and the height difference between the first insulating layer 2 on the top of the gate structure 13 and other structures in the peripheral area B. In the embodiment of the present disclosure, the structure after completing step S310 is as follows: Figure 12 and Figure 13 shown.

[0110] In step S320 , chemical mechanical polishing is performed on the insulating material layer 210 to remove the insulating material layer 210 on the surface of the first insulating layer 2 on the gate structure 13 and to make the surface of the remaining insulating material layer 210 flush with the surface of the first insulating layer 2 on the gate structure 13 .

[0111] The surface of the insulating material layer 210 can be planarized by a chemical mechanical polishing process. During this process, the insulating material layer 210 located on the top of the gate structure 13 and the top of the bit line cover layer can be removed, so that the top surface of the remaining insulating material layer 210 is flush with the top surface of the first insulating layer 2 on the top of the gate structure 13. The remaining insulating material layer 210 can be used as the second insulating layer 3. In the embodiment of the present disclosure, the structure after completing step S330 is as follows: Figure 10 and Figure 11 shown.

[0112] like Figure 2 As shown, in step S150 , a third insulating layer 4 is formed on the second insulating layer 3 and the top surface of the first insulating layer 2 located on the top surface of the gate structure 13 .

[0113] like Figure 14 and Figure 15 As shown, the third insulating layer 4 can be made of the same material as the first insulating layer 2 and the gate cap layer 133, and different from the material of the second insulating layer 3. For example, the first insulating layer 2, the third insulating layer 4, and the gate cap layer 133 can all be made of silicon nitride, while the second insulating layer 3 can be made of silicon oxide. The third insulating layer 4 can be formed on the surface of the structure formed by the second insulating layer 3 and the first insulating layer 2 on top of the gate structure 13 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the third insulating layer 4 can also be formed by other methods, and the method for forming the third insulating layer 4 is not particularly limited herein.

[0114] like Figure 2 As shown, in step S160, the third insulating layer 4, the second insulating layer 3, and the first insulating layer 2 are etched to form a first contact hole 100 exposing the first conductive layer 121 located in the peripheral area B and a second contact hole 200 exposing the substrate 11 located on one side of the gate structure 13.

[0115] like Figure 16 and Figure 17As shown, an etching process can be used to form a first contact hole 100 and a second contact hole 200 that penetrate the third insulating layer 4, the second insulating layer 3, and the first insulating layer 2. The projection of the first contact hole 100 in a direction perpendicular to the substrate 11 at least partially overlaps with the first conductive layer 121 located in the peripheral area B, and the first contact hole 100 can expose the surface of the first conductive layer 121 located in the peripheral area B, so that a first contact plug subsequently formed in the first contact hole 100 contacts the first conductive layer 121, thereby facilitating application of an electrical signal to the word line structure 12 through the first contact plug; the second contact hole 200 can be located on one side of the gate structure 13 and can expose the surface of the substrate 11 (corresponding to the source / drain region of the transistor), so that a second contact plug subsequently formed in the second contact hole 200 contacts the substrate 11, thereby facilitating application of an electrical signal to the source / drain region in the substrate 11 through the second contact plug.

[0116] The cross-section of the first contact hole 100 can be circular, rectangular, polygonal, or irregular. Of course, the cross-section of the first contact hole 100 can also be other shapes, which are not listed here. The shape of the second contact hole 200 can be the same as or different from the shape of the first contact hole 100, and is not particularly limited here.

[0117] In an exemplary embodiment of the present disclosure, the first contact hole 100 and the second contact hole 200 can be formed simultaneously through the same etching process. In this process, since the second semiconductor layer having physical and chemical properties similar to those of the material of the substrate 11 is removed first, there is no need to etch the film layer having properties similar to those of the material of the substrate 11 during the etching process, which helps to reduce etching damage to the substrate 11. At the same time, since the film layer structure on the surface of the substrate 11 is basically the same as the film layer structure on the surface of the first conductive layer 121 in the peripheral area B, the difference in etching rate between the first contact hole 100 and the second contact hole 200 during the etching process becomes smaller. Therefore, the degree of over-etching of the substrate 11 during the etching process can be reduced, which helps to reduce structural defects and thus improve product yield.

[0118] like Figure 2 As shown, in step S170 , a first contact plug 5 is formed in the first contact hole 100 , and a second contact plug 6 is formed in the second contact hole 200 .

[0119] like Figure 18 and Figure 19As shown, a conductive material can be filled in the first contact hole 100 and the second contact hole 200 by atomic layer deposition, physical vapor deposition or chemical vapor deposition, thereby forming a first contact plug 5 in the first contact hole 100 and a second contact plug 6 in the second contact hole 200. The conductive material may include a metal material, for example, it may include tungsten or copper; the conductive material may also include a barrier material, for example, it may include titanium nitride, tantalum or tantalum nitride. For example, a barrier layer can be formed in the first contact hole 100 and the second contact hole 200 by atomic layer deposition, physical vapor deposition, or chemical vapor deposition to conformally cover the inner walls of the first contact hole 100 and the second contact hole 200. The material of the barrier layer can be titanium nitride, tantalum, or tantalum nitride. Subsequently, a conductive material layer can be formed in the first contact hole 100 and the second contact hole 200 with the barrier layer by atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The material of the conductive material layer can be tungsten or copper. The conductive material layer can fill the first contact hole 100 and the second contact hole 200, and the top surface of the conductive material layer can be flush with the top surface of the third insulating layer 4. Because the material of the barrier layer has an ion barrier function, the barrier layer can prevent metal ions in the conductive material layer from diffusing into other surrounding structures, thereby helping to improve device stability.

[0120] In an exemplary embodiment of the present disclosure, the method for forming a semiconductor structure of the present disclosure may further include step S410 and step S420, wherein:

[0121] In step S410, during the process of etching to form the first contact hole 100 and the second contact hole 200, the third insulating layer 4 and the first insulating layer 2 and the gate cap layer 133 located on the top surface of the gate structure 13 are simultaneously etched to form a third contact hole 300 exposing the gate conductive layer 132.

[0122] In some embodiments of the present disclosure, Figure 20 As shown, the third contact hole 300 can be formed simultaneously during the process of forming the first contact hole 100 and the second contact hole 200. That is, the first contact hole 100, the second contact hole 200, and the third contact hole 300 can be formed simultaneously through the same etching process. The third contact hole 300 can penetrate the third insulating layer 4, the first insulating layer 2, and the gate cap layer 133, and expose the gate conductive layer 132 beneath the gate cap layer 133. The cross-section of the third contact hole 300 can be circular, rectangular, polygonal, or irregular. Of course, the cross-section of the third contact hole 300 can also have other shapes, which are not listed here.

[0123] In some embodiments of the present disclosure, the first insulating layer 2, the third insulating layer 4, and the gate cap layer 133 are made of the same material, while the second insulating layer 3 is made of a different material than the first insulating layer 2, the third insulating layer 4, and the gate cap layer 133. Furthermore, during the etching process, the etching rate of the second insulating layer 3 is greater than the etching rate of the materials of the first insulating layer 2, the third insulating layer 4, and the gate cap layer 133, while the etching rate of the substrate 11 is less than the etching rate of the first insulating layer 2. Consequently, during the simultaneous etching process to form the first contact hole 100, the second contact hole 200, and the third contact hole 300, etching damage to the substrate 11 can be reduced, thereby helping to improve product yield. For example, the first insulating layer 2, the third insulating layer 4, and the gate cap layer 133 are all made of silicon nitride, while the second insulating layer 3 is made of silicon oxide.

[0124] Step S420 , forming a third contact plug 7 in the third contact hole 300 .

[0125] like Figure 21 As shown, a conductive material can be filled in the third contact hole 300 by atomic layer deposition, physical vapor deposition or chemical vapor deposition, thereby forming a third contact plug 7 in the third contact hole 300. The material and structure of the third contact plug 7 are the same as those of the first contact plug 5 and the second contact plug 6. The specific details can be referred to the first contact plug 5 and the second contact plug 6, which will not be repeated here.

[0126] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0127] The present disclosure also provides a semiconductor structure, which is formed by the method for forming a semiconductor structure in any of the above embodiments. Figure 18 、 Figure 19 as well as Figure 21 As shown, the semiconductor structure includes a substrate 11, a word line structure 12, a first insulating layer 2, a second insulating layer 3, a third insulating layer 4, a first contact plug 5 and a second contact plug 6, wherein:

[0128] The substrate 11 includes an array region A and a peripheral region B, wherein the peripheral region B is provided with a gate structure 13;

[0129] The wordline structure 12 is located within the substrate 11 and includes a first conductive layer 121, a second conductive layer 122, and a wordline capping layer 123 stacked and arranged in a direction perpendicular to the substrate 11 from bottom to top. The first conductive layer 121 extends from the array region A to the peripheral region B. The orthographic projections of the second conductive layer 122 and the wordline capping layer 123 on the substrate 11 are both located within the array region A.

[0130] The first insulating layer 2 conformally covers the gate structure 13 and the surface of the first conductive layer 121 in the peripheral region B;

[0131] The second insulating layer 3 at least covers the surface of the first insulating layer 2 located on the surface of the first conductive layer 121, and the top surface thereof is flush with the top surface of the first insulating layer 2 located on the top surface of the gate structure 13;

[0132] The third insulating layer 4 covers the second insulating layer 3 and the top surface of the first insulating layer 2 located on the top surface of the gate structure 13;

[0133] The first contact plug 5 penetrates the first insulating layer 2, the second insulating layer 3 and the third insulating layer 4 on the first conductive layer 121 in the peripheral region B and contacts and connects to the first conductive layer 121;

[0134] The second contact plug 6 penetrates the first insulating layer 2 , the second insulating layer 3 and the third insulating layer 4 located on one side of the gate structure 13 and is in contact with the substrate 11 .

[0135] The following is a detailed description of each part of the semiconductor structure disclosed in the present invention:

[0136] The substrate 11 may be a flat plate structure, and may be rectangular, circular, elliptical, polygonal, or irregular in shape. The material of the substrate 11 may be a semiconductor material, such as single crystal silicon, but is not limited to silicon or other semiconductor materials. The shape and material of the substrate 11 are not particularly limited herein. For example, the substrate 11 may be a silicon substrate 11 having a shallow trench isolation structure formed therein. The shallow trench isolation structure can separate a plurality of active areas on the substrate 11.

[0137] The substrate 11 may include an array region A and a peripheral region B. The array region A and the peripheral region B may be adjacent to each other, and the peripheral region B may surround the periphery of the array region A. The array region A may be used to form a capacitor array, a transistor array, a wordline structure 12 connecting the transistor array, and a bitline structure. The peripheral region B may be used to form wordline contact plugs and transistors. The wordline contact plugs may connect to wordline drivers, sense amplifiers, row decoders, column decoders, and special function control circuits located in the peripheral region B. The control circuits may control the wordline structure 12 and bitline structure to implement storage and read functions of the transistor array and the capacitor array.

[0138] In some embodiments of the present disclosure, a trench isolation structure 14 may also be provided in the peripheral region B. The trench isolation structure 14 may be located in an edge area of ​​the peripheral region B close to the array region A. The trench isolation structure 14 may surround the array region A and be distributed adjacent to the array region A. The array region A and the peripheral region B may be separated by the trench isolation structure 14.

[0139] The peripheral region B may also include a transistor, which may include a source region, a channel region and a drain region distributed in sequence, and a gate structure 13 located on the top of the channel region. The gate structure 13 may include a gate dielectric layer 131, a gate conductive layer 132 and a gate cap layer 133 stacked in sequence from bottom to top in a direction perpendicular to the substrate 11, wherein the gate dielectric layer 131 is located on the surface of the channel region, and the material of the gate dielectric layer 131 may be an insulating material, for example, it may be silicon oxide; the gate conductive layer 132 may be a composite film layer structure composed of multiple film layers, for example, it may include a polycrystalline silicon layer located on the surface of the gate dielectric layer 131, a titanium nitride layer located on the surface of the polycrystalline silicon layer, and a tungsten layer located on the surface of the titanium nitride layer. Since the titanium nitride layer has an ion blocking function, tungsten can be prevented from diffusing into the polycrystalline silicon layer through the titanium nitride layer, which helps to improve the stability of the device. The gate cap layer 133 can be located on the surface of the tungsten layer. The gate cap layer 133 can be made of an insulating material. The gate cap layer 133 can provide insulation protection for the gate conductive layer 132, thereby reducing the risk of short circuits or coupling between the gate structure 13 and other surrounding structures, further improving product yield. For example, the initial semiconductor structure can be the structure after the word line structure 12 and the transistors in the peripheral region B are formed during the memory manufacturing process.

[0140] In an exemplary embodiment of the present disclosure, Figure 5 As shown, the gate structure 13 may further include a sidewall spacer 134. The sidewall spacer 134 may cover the sidewalls of the gate dielectric layer 131, the gate conductive layer 132, and the gate cap layer 133. The sidewall spacer 134 may be a single-layer film structure or a composite film structure composed of multiple film layers, which is not particularly limited here. For example, the sidewall spacer structure may include a first spacer 1341 and a second spacer 1342, wherein the first spacer 1341 may conformally cover the sidewalls of the gate dielectric layer 131, the gate conductive layer 132, and the gate cap layer 133. The material of the first spacer 1341 may be the same as that of the gate cap layer 133. For example, the materials of the first spacer 1341 and the gate cap layer 133 may both be silicon nitride. The second spacer 1342 conformally covers the surface of the first spacer 1341. The material of the second spacer 1342 is different from that of the first spacer 1341. For example, the material of the second spacer 1342 may be silicon oxide.

[0141] The wordline structure 12 may be embedded in the substrate 11 and may extend from the array region A to the peripheral region B. For example, the wordline structure 12 may extend into the trench isolation structure 14. The wordline structure 12 may include a first conductive layer 121, a second conductive layer 122, and a wordline capping layer 123 stacked and arranged in a direction perpendicular to the substrate 11 from bottom to top. The first conductive layer 121 may extend from the array region A to the peripheral region B. For example, the first conductive layer 121 may extend into the trench isolation structure 14 in the peripheral region B.

[0142] The material of the first conductive layer 121 can be a metal material, for example, tungsten, titanium, or tantalum. The material of the second conductive layer 122 can be a semiconductor material, which can be a material with a relatively low work function, for example, polycrystalline silicon. While ensuring the turn-on voltage of the wordline structure 12, the second conductive layer 122 with a relatively low work function is provided on the surface of the first conductive layer 121, thereby reducing the gate-induced drain leakage (GIDL) current through the second conductive layer 122. The wordline cap layer 123 covers the surface of the second conductive layer 122. The material of the wordline cap layer 123 can be an insulating material. The wordline cap layer 123 can be used to insulate and protect the second conductive layer 122 of the wordline structure 12, thereby reducing the risk of short circuit or coupling between the wordline structure 12 and other surrounding structures, thereby helping to improve product yield.

[0143] like Figure 10 and Figure 11 As shown, the first insulating layer 2 can conformally cover the gate structure 13 and the surface of the first conductive layer 121 located in the peripheral region B. The material of the first insulating layer 2 can be an insulating material, for example, silicon nitride. The first insulating layer 2 can conformally cover the surfaces of the substrate 11, the first conductive layer 121, and the gate structure 13 located in the peripheral region B. It should be noted that when the gate structure 13 includes a spacer spacer 134, the first insulating layer 2 can cover the surface of the spacer spacer 134 and the gate cap layer 133.

[0144] The second insulating layer 3 may at least cover the surface of the first insulating layer 2 located on the surface of the first conductive layer 121. The second insulating layer 3 may also cover the surface of the first insulating layer 2 located on the substrate 11 on at least one side of the gate structure 13, and may fill the height difference between the surface of the structure in the peripheral region B and the first insulating layer 2 on top of the gate cap layer 133, thereby providing a flat base for subsequent processes and helping to reduce process difficulty. In other words, the second insulating layer 3 covers the surface of the first insulating layer 2 except for the area located on the surface of the gate cap layer 133, and the top surface of the second insulating layer 3 (i.e., the surface away from the substrate 11) is flush with the top surface of the first insulating layer 2 located on the surface of the gate cap layer 133.

[0145] The material of the second insulating layer 3 can be an insulating material. The material of the second insulating layer 3 is different from the material of the first insulating layer 2. The first insulating layer 2 and the second insulating layer 3 can balance the structural stress and help reduce structural defects. For example, the material of the second insulating layer 3 can be silicon oxide.

[0146] like Figure 14 and Figure 15 As shown, the third insulating layer 4 covers the second insulating layer 3 and the top surface of the first insulating layer 2 located on the top surface of the gate structure 13. The third insulating layer 4 can be made of the same material as the first insulating layer 2 and the gate cap layer 133, and different from the material of the second insulating layer 3. For example, the first insulating layer 2, the third insulating layer 4, and the gate cap layer 133 can be made of silicon nitride, and the second insulating layer 3 can be made of silicon oxide.

[0147] like Figure 18 As shown, the first contact plug 5 may be columnar and may penetrate the first insulating layer 2, the second insulating layer 3, and the third insulating layer 4 on the first conductive layer 121 in the peripheral region B in a direction perpendicular to the substrate 11, and contact and connect with the first conductive layer 121. The first contact plug 5 may comprise a metal material, which may include tungsten or copper. The first contact plug 5 may also comprise a barrier material, which may include titanium nitride, tantalum, or tantalum nitride. For example, the first contact plug 5 may include a first barrier layer and a first conductive material layer. The first conductive material layer may be columnar and may extend in a direction perpendicular to the substrate. The material of the first conductive material layer may be tungsten or copper. The first barrier layer may conformally wrap around the sidewalls and bottom of the first conductive material layer, and the first barrier layer located at the bottom of the first conductive material layer may contact and connect with the first conductive layer 121. In some embodiments of the present disclosure, the material of the first barrier layer may be titanium nitride, tantalum, or tantalum nitride. The first contact structure plug 5 is flush with the top surface of the third insulating layer 4. In the first contact plug 5, since the material of the first barrier layer has an ion blocking function, the first barrier layer 51 can prevent metal ions in the first conductive material layer 52 from diffusing into other surrounding structures, which helps to improve device stability.

[0148] like Figure 19As shown, the second contact plug 6 may be located on one side of the gate structure 13 and may penetrate the first insulating layer 2, the second insulating layer 3, and the third insulating layer 4 located on one side of the gate structure 13, and may be in contact with the substrate 11. The second contact plug 6 may include a second barrier layer and a second conductive material layer. The second conductive material layer may be columnar and extend in a direction perpendicular to the substrate 11. The material of the second conductive material layer may be tungsten or copper. The second barrier layer may conformally cover the sidewalls and bottom of the second conductive material layer, and the second barrier layer located at the bottom of the second conductive material layer may be in contact with the substrate 11. In some embodiments of the present disclosure, the material of the second barrier layer may be titanium nitride, tantalum, or tantalum nitride. The second contact structure is flush with the top surface of the third insulating layer 4. In the second contact plug 6, because the material of the second barrier layer has an ion barrier function, the second barrier layer prevents metal ions in the second conductive material layer from diffusing into other surrounding structures, which helps further improve device stability.

[0149] The third contact plug 7 is located on top of the gate conductive layer 132 and may penetrate the third insulating layer 4, the first insulating layer 2, and the gate cap layer 133 located on the top surface of the gate structure 13. One end of the third contact structure may be in contact with the gate conductive layer 132, and the other end may be flush with the top surface of the third insulating layer 4. The third contact plug 7 may include a third barrier layer and a third conductive material layer. The third conductive material layer may be columnar and extend perpendicular to the substrate 11. The material of the third conductive material layer may be tungsten or copper. The third barrier layer may conformally cover the sidewalls and bottom of the third conductive material layer. The third barrier layer located at the bottom of the third conductive material layer may be in contact with the gate conductive layer 132. In some embodiments of the present disclosure, the material of the third barrier layer may be titanium nitride, tantalum, or tantalum nitride. In the third contact plug 7, because the material of the third barrier layer has an ion barrier function, it can prevent metal ions in the third conductive material layer from diffusing into other surrounding structures, thereby further improving device stability.

[0150] The embodiments of the present disclosure also provide a memory, which may include the semiconductor structure in any of the above-mentioned embodiments. Its specific details, formation process and beneficial effects have been described in detail in the corresponding semiconductor structure and the method for forming the semiconductor structure, and will not be repeated here.

[0151] For example, the memory may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. Of course, other storage devices may also be used, which are not listed here one by one.

[0152] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: forming an initial semiconductor structure, the initial semiconductor structure comprising a substrate, a word line structure, and a gate structure, the substrate comprising an array region and a peripheral region, the word line structure being located within the substrate and extending from the array region to the peripheral region; the word line structure comprising a first conductive layer, a second conductive layer, and a word line cap layer stacked and distributed in sequence from bottom to top in a direction perpendicular to the substrate, and the gate structure being located in the peripheral region; Etching the word line capping layer and the second conductive layer in the peripheral region to form an opening in the peripheral region exposing the first conductive layer; forming a first insulating layer conformally covering the opening and the gate structure; forming a second insulating layer, wherein the second insulating layer fills the opening, and a top surface of the second insulating layer is flush with a top surface of the first insulating layer located on the top surface of the gate structure; forming a third insulating layer on the second insulating layer and a top surface of the first insulating layer located on a top surface of the gate structure; Etching the third insulating layer, the second insulating layer, and the first insulating layer to form a first contact hole exposing the first conductive layer in the peripheral region and a second contact hole exposing the substrate on one side of the gate structure; A first contact plug is formed in the first contact hole, and a second contact plug is formed in the second contact hole.

2. The forming method according to claim 1, wherein: The gate structure includes a gate dielectric layer, a gate conductive layer, and a gate cap layer stacked in sequence from bottom to top in a direction perpendicular to the substrate, and the forming method further includes: During the process of etching to form the first contact hole and the second contact hole, the third insulating layer, the first insulating layer, and the gate cap layer located on the top surface of the gate structure are simultaneously etched to form a third contact hole exposing the gate conductive layer; A third contact plug is formed in the third contact hole.

3. The forming method according to claim 1, wherein: Forming the initial semiconductor structure includes: Providing a substrate, the substrate comprising an array region and a peripheral region; forming a word line trench in the substrate, wherein the word line trench extends from the array region to the peripheral region; forming a word line dielectric layer, a first conductive layer, a second conductive layer and a word line capping layer in the word line trench, wherein the first conductive layer, the second conductive layer and the word line capping layer together constitute the word line structure; A gate structure is formed in the peripheral region, and an orthographic projection of the gate structure on the substrate does not overlap with an orthographic projection of the word line structure on the substrate.

4. The forming method according to claim 2, wherein: The gate structure further includes a sidewall spacer, which covers the sidewalls of the gate dielectric layer, the gate conductive layer and the gate cap layer. The first insulating layer covers the surfaces of the sidewall spacer and the gate cap layer.

5. The forming method according to claim 4, wherein: Forming the second insulating layer includes: forming an insulating material layer on a surface of the first insulating layer, wherein the insulating material layer fills the opening; The insulating material layer is subjected to chemical mechanical polishing to remove the insulating material layer on the surface of the first insulating layer on the gate structure, and to make the surface of the remaining insulating material layer flush with the surface of the first insulating layer on the gate structure.

6. The forming method according to claim 1, wherein: The material of the substrate includes single crystal silicon, and the material of the second conductive layer includes polycrystalline silicon.

7. The forming method according to claim 1, wherein: A trench isolation structure is provided in the peripheral region. The trench isolation structure is located in an edge region of the peripheral region and is adjacent to the array region. The word line structure extends into the trench isolation structure.

8. The forming method according to claim 2, wherein: The first insulating layer, the third insulating layer, and the gate cap layer are made of the same material, and the second insulating layer is made of a material different from that of the first insulating layer.

9. The forming method according to claim 8, wherein: The first insulating layer, the third insulating layer, and the gate cap layer are all made of silicon nitride, and the second insulating layer is made of silicon oxide.

10. A semiconductor structure, characterized in that include: A substrate comprising an array region and a peripheral region, wherein the peripheral region is provided with a gate structure; a word line structure located within the substrate and comprising a first conductive layer, a second conductive layer, and a word line cap layer stacked and distributed in sequence from bottom to top in a direction perpendicular to the substrate, wherein the first conductive layer extends from the array region to the peripheral region, and the orthographic projections of the second conductive layer and the word line cap layer on the substrate are both located within the array region; a first insulating layer conformally covering the gate structure and a surface of the first conductive layer located in the peripheral region; a second insulating layer, covering at least a surface of the first insulating layer located on a surface of the first conductive layer, and having a top surface flush with a top surface of the first insulating layer located on a top surface of the gate structure; a third insulating layer covering the second insulating layer and a top surface of the first insulating layer located on a top surface of the gate structure; a first contact plug, penetrating the first insulating layer, the second insulating layer, and the third insulating layer on the first conductive layer in the peripheral region, and contacting and connecting with the first conductive layer; A second contact plug penetrates the first insulating layer, the second insulating layer and the third insulating layer located on one side of the gate structure and is in contact with the substrate.

11. The semiconductor structure according to claim 10, wherein: The gate structure includes a gate dielectric layer, a gate conductive layer, and a gate cap layer stacked in sequence from bottom to top in a direction perpendicular to the substrate. The semiconductor structure also includes: A third contact plug penetrates the third insulating layer, the first insulating layer and the gate cap layer on the top surface of the gate structure, and is in contact with and connected to the gate conductive layer.

12. The semiconductor structure according to claim 11, wherein: The gate structure further includes a sidewall spacer, which covers the sidewalls of the gate dielectric layer, the gate conductive layer and the gate cap layer. The first insulating layer covers the surfaces of the sidewall spacer and the gate cap layer.

13. The semiconductor structure according to claim 10, wherein: A trench isolation structure is provided in the peripheral region. The trench isolation structure is located in an edge region of the peripheral region and is adjacent to the array region. The word line structure extends into the trench isolation structure.

14. The semiconductor structure according to claim 11, wherein: The first insulating layer, the third insulating layer, and the gate cap layer are made of the same material, and the second insulating layer is made of a material different from that of the first insulating layer.

15. A memory, characterized in that: The semiconductor structure comprises the semiconductor structure according to any one of claims 10 to 14.

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