Array substrate and display panel

Abstract

The present application belongs to the field of display panel technology and provides an array substrate and a display panel, wherein the array substrate comprises a substrate, common electrode lines, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a planar layer, a common electrode layer, a third insulating layer, and a pixel electrode layer, which are stacked in sequence; the first metal layer is formed with scan lines, at least some of the common electrode lines are stacked with at least some of the scan lines; the common electrode layer is formed with spaced common electrodes and a first connecting portion; the second metal layer is formed with a drain electrode and a second connecting portion connected to the drain electrode; the pixel electrode layer is formed with a pixel electrode and a third connecting portion connected to the pixel electrode, and the first connecting portion is electrically connected between the second connecting portion and the third connecting portion. The array substrate provided by the present application has a large aperture ratio and a flat surface.

Description

Technical Field

[0001] The present application belongs to the technical field of display panels, and in application relates to an array substrate and a display panel. Background Art

[0002] Fringe Field Switching (FFS) technology is a current mainstream liquid crystal display technology. FFS liquid crystal panels have advantages such as fast response time and wide viewing angle.

[0003] However, for FFS liquid crystal panels with high PPI (pixels per inch, pixel density), common electrode lines are usually added, which reduces the opening area of ​​the pixels, lowers the aperture ratio and transmittance. In addition, the provision of common electrode lines makes the array substrate uneven, causing the spacers to slide and resulting in defects such as spacer debris and bright spots. Summary of the Invention

[0004] An object of the embodiments of the present application is to provide an array substrate and a display panel to improve the aperture ratio of the array substrate and improve the flatness of the array substrate.

[0005] To achieve the above objectives, the technical solution adopted in this application is:

[0006] In a first aspect, the present application provides an array substrate, comprising a substrate, a common electrode line, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a flat layer, a common electrode layer, a third insulating layer and a pixel electrode layer stacked in sequence; the first metal layer forms a scanning line, and at least part of the common electrode line is stacked with at least part of the scanning line; the common electrode layer forms a common electrode and a first connecting portion arranged at intervals, the second metal layer forms a drain and a second connecting portion connected to the drain, the pixel electrode layer forms a pixel electrode and a third connecting portion connected to the pixel electrode, and the first connecting portion is stacked between the second connecting portion and the third connecting portion.

[0007] The beneficial effects of the array substrate provided by the present application are as follows: compared with the prior art, on the one hand, the array substrate provided by the present application reduces the routing space occupied by the common electrode line by stacking the scanning line and the common electrode line in the thickness direction of the array substrate, thereby making the array substrate provided by the present application have the advantage of a large pixel aperture ratio; on the other hand, the common electrode line, the first metal layer and the second metal layer of the array substrate provided by the present application are all manufactured before the third insulating layer and the fourth insulating layer, thereby reducing the influence of the common electrode line, the first metal layer and the second metal layer on the surface flatness of the array substrate, further making the array substrate provided by the present application have the advantage of a flat surface, improving the flatness of the array substrate, and solving the problem of defects caused by sliding of the spacer column due to the uneven surface of the array substrate.

[0008] In addition, the array substrate provided in the present application is electrically connected between the second connection part and the third connection part through the first connection part. On the one hand, the second connection part is protected by the first connection part to prevent the second connection part from being damaged and causing defects in subsequent processing steps of the array substrate. On the other hand, the process matching degree is high when the first connection part is arranged between the second connection part and the third connection part.

[0009] In one embodiment, a first via hole is provided in the planar layer, and the first connecting portion is connected to the second connecting portion through the first via hole;

[0010] A second via hole is provided in the third insulating layer, and the third connecting portion is connected to the second connecting portion through the second via hole.

[0011] In one embodiment, a projection of the second via hole toward the second connecting portion is located within a projection of the first via hole toward the second connecting portion.

[0012] In one embodiment, the common electrode layer further comprises a fourth connection portion connected to the common electrode, and the fourth connection portion is electrically connected to the common electrode line.

[0013] In one embodiment, the common electrode line is provided with a protruding portion, and the fourth connecting portion is arranged to overlap with the protruding portion.

[0014] In one embodiment, the protrusion and the second connection portion are both located on the same side of the scan line or the common electrode line.

[0015] In one embodiment, the fourth connecting portion is arranged to overlap with the common electrode line;

[0016] A third via hole is provided in the first insulating layer, the second insulating layer, and the planar layer, and the fourth connecting portion and the common electrode line are connected through the third via hole.

[0017] In one embodiment, the fourth connecting portion is arranged to overlap with the common electrode line;

[0018] The second metal layer is further formed with a data line and a fifth connecting portion, and the first insulating layer and the second insulating layer are provided with a fourth via hole, and the common electrode line and the fifth connecting portion are connected through the fourth via hole;

[0019] The pixel electrode layer is formed with a sixth connecting portion spaced apart from the pixel electrode, the third insulating layer is provided with a fifth via hole, and the fifth connecting portion and the sixth connecting portion are connected through the fifth via hole;

[0020] A sixth via hole is provided in the planar layer and the third insulating layer, and the sixth connecting portion and the fifth connecting portion are connected through the sixth via hole.

[0021] In one embodiment, the planarization layer comprises a self-leveling insulating layer.

[0022] In a second aspect, the present application provides a display panel comprising the array substrate described in any one of the above embodiments.

[0023] The beneficial effects of the display panel provided by the present application are: compared with the prior art, on the one hand, the array substrate provided by the present application has the advantage of a high aperture ratio, thereby making the display panel provided by the present application have the advantage of high brightness; on the other hand, the array substrate provided by the present application has the advantage of a flat surface, thereby avoiding the generation of debris on the PS (photo-spacer) side of the display panel provided by the present application after the array substrate and the color film substrate are aligned, thereby making the display panel provided by the present application have the advantage of a low failure rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1 A schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0026] Figure 2 for Figure 1 A partial cross-sectional view at AA in the middle;

[0027] Figure 3 for Figure 1 A partial cross-sectional view of the middle BB;

[0028] Figure 4 A schematic structural diagram of an array substrate provided in another embodiment of the present application;

[0029] Figure 5 for Figure 4 A partial cross-sectional view of the CC in the middle;

[0030] Figure 6 for Figure 4 Schematic diagram of the local cross-section at DD in the middle.

[0031] Among them, the reference numerals in the figures are:

[0032] 100. Array substrate;

[0033] 000, substrate;

[0034] 10. Common electrode line; 11. Protrusion;

[0035] 20. a first insulating layer;

[0036] 30. First metal layer; 31. Scan line;

[0037] 40. second insulating layer;

[0038] 50. Second metal layer; 51. Fifth connecting portion; 52. Second connecting portion; 53. Drain; 54. Source; 55. Data line;

[0039] 60. Flat layer; 61. Self-leveling insulation layer; 62. Fourth insulation layer;

[0040] 70. Common electrode layer; 71. First connecting portion; 72. Fourth connecting portion; 73. Common electrode;

[0041] 80. The third insulating layer;

[0042] 90. pixel electrode layer; 91. third connecting portion; 92. pixel electrode; 93. sixth connecting portion;

[0043] 001, first via hole; 002, second via hole; 003, third via hole; 004, fourth via hole; 005, fifth via hole; 006, sixth via hole. DETAILED DESCRIPTION

[0044] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0045] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0046] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0048] Example 1

[0049] Please also refer to Figure 1 and Figure 2 , the array substrate 100 provided in an embodiment of the present application is now described.

[0050] The array substrate 100 includes a substrate 000, a common electrode line 10, a first insulating layer 20, a first metal layer 30, a second insulating layer 40, a second metal layer 50, a flat layer 60, a common electrode layer 70, a third insulating layer 80 and a pixel electrode layer 90, which are stacked in sequence; the first metal layer 30 is formed with a scanning line 31, and at least part of the common electrode line 10 and at least part of the scanning line 31 are stacked.

[0051] In use, the array substrate 100 extends within the plane of the x- and y-directions shown in the figure, and the thickness direction of the array substrate 100 is the z-direction shown in the figure. The substrate 000, common electrode lines 10, first insulating layer 20, first metal layer 30, second insulating layer 40, second metal layer 50, planar layer 60, common electrode layer 70, fourth insulating layer 62, and pixel electrode layer 90 are stacked along the z-direction in the figure. The scan lines 31 extend along the x-direction in the figure, and the common electrode lines 10 extend along the x-direction in the figure. The scan lines 31 and the common electrode lines 10 are stacked along the z-direction in the figure. The common electrode lines 10 are located on the side of the scan lines 31 facing the substrate 000 so that the projection of a portion of the common electrode lines 10 in the z-direction in the figure coincides with the projection of the scan lines 31 in the z-direction in the figure.

[0052] Therefore, the overlapping arrangement of the common electrode line 10 and the scan line 31 saves the wiring space between pixels, thereby increasing the aperture ratio of the pixels.

[0053] The common electrode layer 70 is formed with a common electrode 73 and a first connecting portion 71 arranged at intervals, the second metal layer 50 is formed with a drain electrode 53 and a second connecting portion 52 connected to the drain electrode 53, the pixel electrode layer 90 is formed with a pixel electrode 92 and a third connecting portion 91 connected to the pixel electrode 92, and the first connecting portion 71 is stacked between the second connecting portion 52 and the third connecting portion 91.

[0054] The common electrode 73 is disposed on a side of the pixel electrode 92 away from the substrate 000 , and a fringe electric field can be generated between the common electrode 73 and the pixel electrode 92 .

[0055] In application, the second metal layer 50 forms a data line 55, a source 54, a drain 53 and a second connecting portion 52. The array substrate 100 is applied to an FFS liquid crystal panel. A semiconductor layer is provided between the source 54 and the drain 53, and part of the scanning line 31 extends to one side of the semiconductor layer along the y direction in the figure to form a gate of a thin film transistor (TFT). The conduction state of the thin film semiconductor is controlled by the potential of the scanning line 31, thereby controlling the on and off between the source 54 and the drain 53. The second connecting portion 52 is connected to the third connecting portion 91, and the third connecting portion 91 is connected to the pixel electrode 92, so that the thin film semiconductor controls the potential in the pixel electrode 92 according to the potential of the scanning line 31, thereby realizing control of the pixel.

[0056] The third connection part 91 and the second connection part 52 are connected by a via. When the via is processed in the third insulating layer 80 between the third connection part 91 and the second connection part 52, the second connection part 52 will be exposed to the etching solution, causing defects in the second connection part 52. Therefore, by stacking the first connection part 71 between the third connection part 91 and the second connection part 52, the first connection part 71 can protect the second connection part 52 during the process of processing the via in the third insulating layer 80 between the third connection part 91 and the second connection part 52.

[0057] The array substrate 100 provided in the present application has the following beneficial effects: compared with the prior art, on the one hand, the array substrate 100 provided in the present application reduces the routing space occupied by the common electrode line 10 by stacking the scanning line 31 and the common electrode line 10 in the thickness direction of the array substrate 100, thereby making the array substrate 100 provided in the present application have the advantage of a large pixel aperture ratio; on the other hand, the common electrode line 10, the first metal layer 30 and the second metal layer 50 of the array substrate 100 provided in the present application are all manufactured before the third insulating layer 80 and the fourth insulating layer 62, thereby reducing the influence of the common electrode line 10, the first metal layer 30 and the second metal layer 50 on the surface flatness of the array substrate 100, further making the array substrate 100 provided in the present application have the advantage of a flat surface, improving the flatness of the array substrate 100, and solving the problem of defects caused by sliding of the spacer column due to the uneven surface of the array substrate 100.

[0058] In addition, the array substrate 100 provided in the present application is electrically connected between the second connecting portion 52 and the third connecting portion 91 through the first connecting portion 71. On the one hand, the second connecting portion 52 is protected by the first connecting portion 71 to prevent the second connecting portion 52 from being damaged and causing defects in subsequent processing steps of the array substrate 100. On the other hand, the process matching degree of arranging the first connecting portion 71 between the second connecting portion 52 and the third connecting portion 91 is high.

[0059] In one embodiment, a first via hole 001 is provided in the planar layer 60 , and the first connecting portion 71 is connected to the second connecting portion 52 through the first via hole 001 ;

[0060] The third insulating layer 80 is provided with a second via hole 002 , and the third connecting portion 91 is connected to the second connecting portion 52 through the second via hole 002 .

[0061] In application, the first via 001 penetrates the side of the flat layer 60 facing the substrate 000 and the side of the flat layer 60 away from the substrate 000, the first connecting portion 71 is connected to the second connecting portion 52 through the first via 001, the second via 002 penetrates the side of the third insulating layer 80 facing the substrate 000 and the side of the third insulating layer 80 away from the substrate 000, and the third connecting portion 91 is connected to the first connecting portion 71 through the second via 002.

[0062] Thus, the second connecting part 52 is connected to the third connecting part 91 through the first via hole 001 and the second via hole 002, and the first connecting part 71 is clamped between the second connecting part 52 and the third connecting part 91, so that when the second via hole 002 is opened in the third insulating layer 80, the second connecting part 52 is protected from corrosion by the etching solution, thereby reducing the failure rate of the array substrate 100 provided in the present application.

[0063] In one embodiment, a projection of the second via hole 002 toward the second connecting portion 52 is located within a projection of the first via hole 001 toward the second connecting portion 52 .

[0064] In applications, such as Figure 2 As shown, the first via 001 penetrates the flat layer 60 along the z direction in the figure, part of the first connecting portion 71 and part of the third insulating layer 80 are coated on the inner wall of the first via 001, part of the first connecting portion 71 and part of the third insulating layer 80 are coated on the opening of the first via 001 toward the second connecting portion 52, and the second via 002 is arranged in the third insulating layer 80 at the opening position of the first via 001 toward the second connecting portion 52, so that the first connecting portion 71 and the third connecting portion 91 at the opening of the first via 001 toward the second connecting portion 52 are connected through the second via 002.

[0065] Thus, the third connection portion 91 and the second connection portion 52 are connected through the first via 001 toward the portion of the first connection portion 71 at the opening of the second connection portion 52, reducing the path of current flowing in the first connection portion 71, thereby improving the efficiency of the electrical connection between the third connection portion 91 and the second connection portion 52.

[0066] In one embodiment, the common electrode layer 70 further includes a fourth connecting portion 72 connected to the common electrode 73 . The fourth connecting portion 72 is electrically connected to the common electrode line 10 .

[0067] In applications, in applications, such as Figure 1As shown, the common electrode layer 70 includes a common electrode 73 and a fourth connecting portion 72 protruding from the common electrode 73. The fourth connecting portion 72 extends toward the common electrode line 10 to connect the common electrode line 10 and the common electrode 73, and part of the fourth connecting portion 72 is arranged between the common electrode line 10 and the common electrode 73, thereby increasing the distribution uniformity of the ITO material between the common electrode 73 and the common electrode line 10, and further improving the flatness of the area between the common electrode 73 and the common electrode line 10.

[0068] In one embodiment, the common electrode line 10 is provided with a protruding portion 11 , and the fourth connecting portion 72 is arranged to overlap with the protruding portion 11 .

[0069] In applications, such as Figure 1 As shown, the protrusion 11 extends along the common electrode line 10 toward the pixel electrode 92, so that the protrusion 11 is located between the common electrode line 10 and the pixel electrode 92 in the y direction in the figure, and the fourth connecting portion 72 overlaps with part of the protrusion 11, that is, the fourth connecting portion 72 is located in the gap between the common electrode line 10 and the pixel electrode 92 in the y direction in the figure.

[0070] As a result, on the one hand, the uniformity of the conductive material in the spacing area between the common electrode line 10 and the pixel electrode 92 in the y direction in the figure is improved, thereby improving the flatness of the area between the pixel electrode 92 and the scanning line 31, so that the array substrate 100 provided in the present application has the advantage of a flat surface. On the other hand, the fourth connecting portion 72 is made on the protruding portion 11 to avoid the fourth connecting portion 72 affecting the common electrode line 10 and the scanning line 31.

[0071] In one embodiment, Figure 1 As shown, the protruding portion 11 and the fifth connecting portion 51 are both located on the same side of the scanning line 31 or the common electrode line 10 .

[0072] In application, the protrusion 11 and the second connecting portion 52 are both located in the spacing area between the pixel electrode 92 and the scanning line 31 in the y direction in the figure, that is, the first connecting portion 71, the second connecting portion 52, the third connecting portion 91, the protrusion 11, the fourth connecting portion 72, the source 54, the thin film semiconductor and the drain 53 are all located on the same side of the pixel electrode 92 facing the scanning line 31 in the y direction in the figure.

[0073] Therefore, on the one hand, the basic internal wiring space of the FFS array is further reduced, and the aperture ratio of the array substrate 100 provided by the present application is improved. On the other hand, the distribution uniformity of the ITO material and the metal material in the array substrate 100 provided by the present application in the x direction and the y direction in the figure is improved, so that the array substrate 100 provided by the present application has the advantage of a flat surface.

[0074] In one embodiment, Figure 3 As shown, the fourth connecting portion 72 is overlapped with the common electrode line 10;

[0075] A third via hole 003 is provided in the first insulating layer 20 , the second insulating layer 40 and the planar layer 60 , and the fourth connecting portion 72 and the common electrode line 10 are connected through the third via hole 003 .

[0076] In applications, such as Figure 3 As shown, the third via hole 003 passes through the first insulating layer 20, the second insulating layer 40 and the flat layer 60 in sequence along the z direction in the figure, so that the side of the flat layer 60 facing away from the substrate 000 is connected to the side of the first insulating layer 20 facing the common electrode line 10, and part of the fourth connecting portion 72 is coated on the hole wall of the third via hole 003, and part of the fourth connecting portion 72 is coated on the common electrode line 10 at the hole mouth of the third via hole 003.

[0077] Thus, the common electrode line 10 and the fourth connection portion 72 are connected through the third via hole 003 , and the fourth connection portion 72 is connected to the common electrode 73 , thereby connecting the common electrode line 10 and the common electrode 73 .

[0078] In another embodiment, Figure 4 、 Figure 5 and Figure 6 As shown, the fourth connecting portion 72 is overlapped with the common electrode line 10;

[0079] The second metal layer 50 is further formed with a data line 55 and a fifth connecting portion 51. A fourth via hole 004 is provided in the first insulating layer 20 and the second insulating layer 40, and the common electrode line 10 and the fifth connecting portion 51 are connected through the fourth via hole 004.

[0080] The pixel electrode layer 90 is formed with a sixth connecting portion 93 spaced apart from the pixel electrode 92 , and the third insulating layer 80 is provided with a fifth via hole 005 , and the fifth connecting portion 51 and the sixth connecting portion 93 are connected through the fifth via hole 005 ;

[0081] A sixth via hole 006 is provided in the planar layer 60 and the third insulating layer 80 , and the sixth connecting portion 93 and the fifth connecting portion 51 are connected through the sixth via hole 006 .

[0082] In applications, such as Figure 4 、 Figure 5 and Figure 6As shown, the fourth connection portion 72 extends to the side of the portion of the common electrode line 10 facing away from the substrate 000, that is, the projection of the fourth connection portion 72 in the thickness direction coincides with the projection of the portion of the common electrode line 10 in the thickness direction, and a fifth connection portion 51 and a sixth connection portion 93 are provided between the fourth connection portion 72 and the common electrode line 10, and the fifth connection portion 51 is connected to the common electrode line 10 through the fourth via 004, and the sixth connection portion 93 is connected to the fifth connection portion 51 through the sixth via 006, and the fourth connection portion 72 is adjacent to the sixth connection portion 93 through the fifth via 005, so that the fourth connection portion 72 and the common electrode line 10 are connected through the fifth connection portion 51 and the sixth connection portion 93, thereby realizing electrical connection between the fourth connection portion 72 and the common electrode line 10.

[0083] Thus, the fourth connection portion 72 and the common electrode line 10 are connected through the fifth connection portion 51 and the sixth connection portion 93, thereby electrically connecting the fourth connection portion 72 and the common electrode line 10, so that the common electrode line 10 can supply power to the common electrode 73. Figure 4 As shown, in the area between the scanning line 31 and the pixel electrode 92, the material of the pixel electrode layer 90 and the material of the second metal layer 50 are distributed in the x direction in the figure, which increases the distribution uniformity of the ITO material between the common electrode 73 and the common electrode line 10, thereby improving the flatness of the spacing area between the pixel electrode 92 and the scanning line 31 in the x direction and y direction in the figure, thereby making the array substrate 100 provided in the present application have the advantage of a flat surface.

[0084] In addition, the common electrode line 10, the first metal layer 30 and the second metal layer 50 of the array substrate 100 provided by the present application are manufactured before the planar layer 60 and the third insulating layer 80, thereby reducing the influence of the common electrode line 10, the first metal layer 30 and the second metal layer 50 on the surface flatness of the array substrate 100, further making the array substrate 100 provided by the present application have the advantage of a flat surface.

[0085] In one embodiment, Figure 2 and Figure 3 As shown, the flat layer 60 includes a self-leveling insulating layer 61. In application, the flat layer 60 includes the self-leveling insulating layer 61 and a fourth insulating layer 62. The fourth insulating layer 62 is located between the self-leveling insulating layer 61 and the second metal layer 50. The self-leveling insulating layer 61 is made of acrylic self-leveling material.

[0086] Therefore, on the one hand, the self-leveling insulating layer 61 in the flat layer 60 has good self-leveling performance, so that after the flat layer 60 is prepared, the surface flatness of the array substrate 100 provided by the present application is high. On the other hand, the common electrode line 10, the first metal layer 30 and the second metal layer 50 of the array substrate 100 provided by the present application are manufactured before the flat layer 60. After the third insulating layer 80 is manufactured by self-leveling, the influence of the common electrode line 10, the first metal layer 30 and the second metal layer 50 on the surface flatness of the array substrate 100 is significantly reduced, so that the array substrate 100 provided by the present application has the advantage of a flat surface.

[0087] Example 2

[0088] The display panel provided in the embodiments of the present application is described below.

[0089] The present application provides a display panel, including the array substrate 100 described in any one of the above embodiments.

[0090] The display panel provided by the present application has the following beneficial effects: compared with the prior art, on the one hand, the array substrate 100 provided by the present application has the advantage of a high aperture ratio, thereby making the display panel provided by the present application have the advantage of high brightness; on the other hand, the array substrate 100 provided by the present application has the advantage of a flat surface, thereby preventing the display panel provided by the present application from generating debris on the PS side after the array substrate 100 and the PS side are aligned, thereby making the display panel provided by the present application have the advantage of a low failure rate.

[0091] Example 3

[0092] The present application provides a method for manufacturing an array substrate 000, comprising:

[0093] Common electrode lines 10 , a first insulating layer 20 and a first metal layer 30 are sequentially formed on one surface of the substrate 000 . The first metal layer 30 includes scan lines 31 . At least part of the scan lines 31 is stacked with part of the common electrode lines 10 .

[0094] In application, the scanning lines 31 and the common electrode lines 10 both extend along the x direction in the figure, and as shown in the figure, part of the scanning lines 31 and part of the common electrode lines 10 overlap in the z direction in the figure. On the one hand, this saves routing space in the array substrate 100, thereby improving the aperture ratio of the array substrate 100. On the other hand, the process of the common electrode lines 10, the first metal layer 30 and the second metal layer 50 is before the third insulating layer 80 and the fourth insulating layer 62, thereby reducing the influence of the common electrode lines 10, the first metal layer 30 and the second metal layer 50 on the surface flatness of the array substrate 100, further making the array substrate 100 provided by the present application have the advantage of a flat surface.

[0095] The beneficial effect of the array substrate 000 manufacturing method provided in the present application is that: compared with the existing technology, the array substrate 000 manufacturing method of the present application stacks the scanning line 31 and the common electrode line 10 in the thickness direction of the array substrate 100, reducing the routing space occupied by the common electrode line 10, so that the array substrate 100 manufactured by the array substrate 000 manufacturing method has the advantage of a large pixel aperture ratio.

[0096] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: It includes a substrate, a common electrode line, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a planar layer, a common electrode layer, a third insulating layer and a pixel electrode layer which are stacked in sequence; The first metal layer is formed with scan lines, and at least part of the common electrode lines and at least part of the scan lines are stacked; The common electrode layer is formed with a common electrode and a first connecting portion that are spaced apart from each other, the second metal layer is formed with a drain electrode and a second connecting portion connected to the drain electrode, the pixel electrode layer is formed with a pixel electrode and a third connecting portion connected to the pixel electrode, and the first connecting portion is stacked between the second connecting portion and the third connecting portion; The common electrode layer is further formed with a fourth connection portion connected to the common electrode, and the fourth connection portion is electrically connected to the common electrode line; The fourth connecting portion is arranged to overlap with the common electrode line; The second metal layer is further formed with a data line and a fifth connecting portion, and the first insulating layer and the second insulating layer are provided with a fourth via hole, and the common electrode line and the fifth connecting portion are connected through the fourth via hole; The pixel electrode layer is formed with a sixth connecting portion spaced apart from the pixel electrode, the third insulating layer is provided with a fifth via hole, and the fourth connecting portion and the sixth connecting portion are connected through the fifth via hole; A sixth via hole is provided in the planar layer and the third insulating layer, and the sixth connecting portion and the fifth connecting portion are connected through the sixth via hole.

2. The array substrate according to claim 1, wherein: A first via hole is provided in the planar layer, and the first connecting portion is connected to the second connecting portion through the first via hole; A second via hole is provided in the third insulating layer, and the third connecting portion is connected to the second connecting portion through the second via hole.

3. The array substrate according to claim 2, wherein: A projection of the second via hole toward the second connecting portion is located within a projection of the first via hole toward the second connecting portion.

4. The array substrate according to claim 1, wherein: The common electrode line is provided with a protruding portion, and the fourth connecting portion is arranged to overlap with the protruding portion.

5. The array substrate according to claim 4, wherein: The protruding portion and the second connecting portion are both located on the same side of the scan line or the common electrode line.

6. The array substrate according to any one of claims 1 to 5, wherein: The flat layer includes a self-leveling insulating layer.

7. A display panel, characterized in that: The invention comprises an array substrate as claimed in any one of claims 1 to 6.

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