Integrated circuit memory and construction method thereof

Abstract

The present invention provides an integrated circuit memory and a construction method thereof. A dynamic storage area integration unit is used to integrate multiple dynamic storage areas in a storage module inside a synchronous dynamic random access memory unit; a termination resistor pin integration unit is used to transplant and integrate the termination resistor into the interior of a memory chip to form an internal integrated termination resistor; a region qualifier pin module is integrated in the synchronous dynamic random access memory unit; an on-chip calibration reflection control unit is used to integrate a high-precision reference resistor into the region qualifier pin module; an on-chip calibration engine is used to automatically calibrate the internal integrated termination resistor and control signal reflection to control signal integrity and control voltage and signal quality; a multi-purpose register architecture unit is used to intelligently control multiple register modes by integrating multi-purpose registers to construct a high-density memory and a high-bandwidth integrated circuit memory.

Description

Technical Field

[0001] The present invention relates to the field of chip architecture integrated intelligent storage control technology, and more specifically, to an integrated circuit memory and a construction method thereof. Background Art

[0002] As electronic devices develop towards high performance and low energy consumption, the performance requirements for integrated circuit memories are also becoming increasingly higher. Traditional memory technologies face many challenges in terms of storage density, read and write speeds, and power consumption. Specific issues include: how to integrate the dynamic storage area in the internal storage module of the memory cell, how to transfer the external termination resistor to the inside of the memory chip, how to limit the pins of the random storage cell integration area, how to automatically calibrate the internal integrated termination resistor and control signal reflection, how to control multiple register modes and improve the memory storage density and data operation bandwidth, and other issues remain to be resolved. Therefore, it is necessary to propose an integrated circuit memory and a construction method to at least partially solve the problems existing in the prior art. Summary of the Invention

[0003] A series of simplified concepts are introduced in the summary of the invention, which will be further explained in detail in the specific implementation method. The summary of the invention does not mean to attempt to limit the key features and necessary technical features of the technical solution for protection, nor does it mean to attempt to determine the scope of protection of the technical solution for protection.

[0004] To at least partially solve the above problems, the present invention provides an integrated circuit memory, comprising:

[0005] A dynamic storage area integration unit integrates multiple dynamic storage areas in a storage module inside a synchronous dynamic random access memory unit;

[0006] The termination resistor pin integrated unit transplants and integrates the termination resistor into the memory chip to form an internal integrated termination resistor; the region qualifier pin module is integrated into the synchronous dynamic random access memory unit;

[0007] On-chip calibration reflection control unit, the regional qualifier pin module integrates high-precision reference resistors; through the on-chip calibration engine, automatic calibration of the internal integrated termination resistors and signal reflection control are performed to control signal integrity and control voltage signal quality;

[0008] The multi-purpose register architecture unit integrates multi-purpose registers and intelligently controls multiple register modes to build high-density memory and high-bandwidth integrated circuit memory.

[0009] Preferably, the dynamic storage area integrated unit includes:

[0010] The storage array integration sub-unit forms a storage array module by combining the logical storage array of the memory; in the internal storage module, multiple storage array modules are integrated into the storage module;

[0011] High-density line-end arrangement sub-units, setting diamond-shaped staggered arrangement line-end contact blocks, constructing a high-density line-to-line arrangement; setting the address lines of the storage array module; performing storage array logic encoding, setting the system data bit width, and performing high-speed reading and writing of data units.

[0012] Preferably, the terminating resistor pin integrated unit includes:

[0013] The termination resistor integrated sub-unit transplants and integrates the termination resistor into the memory chip to form an internal integrated termination resistor;

[0014] A qualifier pin subunit is provided, wherein the qualifier pin module is integrated in the synchronous dynamic random access memory unit;

[0015] The calibration command data storage subunit and the region qualifier pin module set the calibration command set; the calibration command set sets the long-cycle calibration command and the short-cycle calibration command;

[0016] Long-cycle calibration instructions include: power-on initialization instructions and memory reset instructions; short-cycle calibration instructions include: voltage following instructions and temperature following instructions;

[0017] The power-on initialization instruction and the memory reset instruction are executed to set the first long-cycle calibration clock, the second long-cycle calibration clock and the nth long-cycle calibration clock respectively; the clock period of the second long-cycle calibration clock and the nth long-cycle calibration clock is less than the first long-cycle calibration clock; the short-cycle calibration instruction is executed to set the first short-cycle calibration clock to execute the voltage following instruction and the temperature following instruction; the temperature following instruction includes: the first automatic refresh frequency corresponds to the first temperature range of self-refresh, the second automatic refresh frequency corresponds to the second temperature range of self-refresh, and the self-refresh reference standard temperature is set between the first temperature range of self-refresh and the second temperature range of self-refresh; and low-power state data is saved.

[0018] Preferably, the on-chip calibration reflection control unit comprises:

[0019] Reference resistor integrated sub-unit, regional qualifier pin module integrates high-precision reference resistor; internal integrated termination resistor is calibrated by high-precision reference resistor;

[0020] The calibration engine reflection control subunit performs automatic calibration of the internal integrated termination resistors and signal reflection control through the on-chip calibration engine, controlling signal integrity and controlling voltage and signal quality;

[0021] Dual calibration subunit, dual calibration of the gate resistor and the internal integrated termination resistor;

[0022] The internal integrated termination resistors include: data output drive on-resistance, terminal matching termination resistor, internal series resistor and internal read-write matching resistor; the internal read-write matching resistors include: internal read matching resistor and internal write matching resistor.

[0023] Preferably, the multi-purpose hosting architecture unit comprises:

[0024] The multi-purpose register sub-unit integrates multi-purpose registers, sets and stores data in multiple modes, and performs programming control of operation modes, intelligently controlling multiple register modes;

[0025] The target register subunit enables multiple target registers according to multiple register modes, adapting to the storage of various data characteristics; building high-density memory and high-bandwidth integrated circuit memory.

[0026] The present invention provides a method for constructing an integrated circuit memory, comprising:

[0027] S100, integrating multiple dynamic storage areas in a storage module inside a synchronous dynamic random access memory unit;

[0028] S200, transplanting and integrating the termination resistor into the memory chip to form an internal integrated termination resistor; integrating a region qualifier pin module into the synchronous dynamic random access memory cell;

[0029] S300, the regional qualifier pin module integrates high-precision reference resistors; through the on-chip calibration engine, automatic calibration of the internal integrated termination resistors and signal reflection control are performed to control signal integrity and control voltage signal quality;

[0030] S400, by integrating multi-purpose registers and intelligently controlling multiple register modes, builds high-density memory and high-bandwidth integrated circuit memory.

[0031] Preferably, S100 includes:

[0032] S101, forming a storage array module from a logical storage array of a memory; integrating multiple storage array modules into the storage module in an internal storage module;

[0033] S102, arrange diamond-shaped staggered line end contact blocks to build a high-density line-to-line arrangement; set address lines of the storage array module; perform storage array logic encoding, set system data bit width, and perform high-speed reading and writing of data units.

[0034] Preferably, S200 includes:

[0035] S201, transplanting and integrating the termination resistor into the memory chip to form an internal integrated termination resistor;

[0036] S202, integrating a region qualifier pin module in a synchronous dynamic random access memory unit;

[0037] S203, the region qualifier pin module sets a calibration command set; the calibration command set sets a long-cycle calibration instruction and a short-cycle calibration instruction;

[0038] Long-cycle calibration instructions include: power-on initialization instructions and memory reset instructions; short-cycle calibration instructions include: voltage following instructions and temperature following instructions;

[0039] The power-on initialization instruction and the memory reset instruction are executed to set the first long-cycle calibration clock, the second long-cycle calibration clock and the nth long-cycle calibration clock respectively; the clock period of the second long-cycle calibration clock and the nth long-cycle calibration clock is less than the first long-cycle calibration clock; the short-cycle calibration instruction is executed to set the first short-cycle calibration clock to execute the voltage following instruction and the temperature following instruction; the temperature following instruction includes: the first automatic refresh frequency corresponds to the first temperature range of self-refresh, the second automatic refresh frequency corresponds to the second temperature range of self-refresh, and the self-refresh reference standard temperature is set between the first temperature range of self-refresh and the second temperature range of self-refresh; and low-power state data is saved.

[0040] Preferably, S300 includes:

[0041] S301, the region qualifier pin module integrates a high-precision reference resistor; the internal integrated termination resistor is calibrated by the high-precision reference resistor;

[0042] S302, through the on-chip calibration engine, automatically calibrates the internal integrated termination resistor and controls signal reflection, controls signal integrity and controls voltage and signal quality;

[0043] S303, double calibration of the gate resistor and the internal integrated termination resistor;

[0044] The internal integrated termination resistors include: data output drive on-resistance, terminal matching termination resistor, internal series resistor and internal read-write matching resistor; the internal read-write matching resistors include: internal read matching resistor and internal write matching resistor.

[0045] Preferably, S400 includes:

[0046] S401, by integrating multi-purpose registers, sets and stores multiple mode data, and performs operation mode programming control, intelligently controlling multiple register modes;

[0047] S402, based on multiple register modes, multiple target registers are enabled to adapt to the storage of multiple data characteristics; and high-density memory and high-bandwidth integrated circuit memory are constructed.

[0048] Compared with the prior art, the present invention has at least the following beneficial effects:

[0049] The present invention discloses an integrated circuit memory and a construction method thereof. The invention integrates a plurality of dynamic storage areas in a storage module inside a synchronous dynamic random access memory unit through a dynamic storage area integration unit; a termination resistor pin integration unit transplants and integrates the termination resistor into the memory chip to form an internal integrated termination resistor; a region qualifier pin module is integrated in the synchronous dynamic random access memory unit; an on-chip calibration reflection control unit is used, and a high-precision reference resistor is integrated in the region qualifier pin module; an on-chip calibration engine is used to automatically calibrate the internal integrated termination resistor and control signal reflection to control signal integrity and control voltage and signal quality; a multi-purpose register architecture unit is used to realize automatic calibration of the internal integrated termination resistor and signal reflection control to control signal integrity and control voltage and signal quality. It integrates multi-purpose registers, intelligently controls multiple register modes, and constructs high-density memory and high-bandwidth integrated circuit memory; it can quickly adapt to the rapid development of high-performance and low-energy consumption electronic equipment, and the performance of integrated circuit memory is higher; the present invention significantly improves storage density, read and write speed and power consumption; it can integrate the dynamic storage area in the storage module inside the storage unit; it can transfer the external termination resistor to the inside of the memory chip; it can randomly limit the pins of the storage unit integration area; it can automatically calibrate the internal integrated termination resistor and control the signal reflection; it can control multiple register modes and significantly improve the memory storage density and data operation bandwidth.

[0050] The integrated circuit memory and its construction method described in the present invention, as well as other advantages, objectives and features of the present invention will be reflected in part through the following description, and will also be understood by those skilled in the art through research and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0052] Figure 1 This is a diagram of an embodiment of an integrated circuit memory according to the present invention.

[0053] Figure 2 FIG2 is a diagram of another embodiment of an integrated circuit memory according to the present invention.

[0054] Figure 3 This is a partial embodiment diagram of an integrated circuit memory and its construction method described in the present invention. DETAILED DESCRIPTION

[0055] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments so that those skilled in the art can implement the invention with reference to the description. Figure 1-Figure 3 As shown, the present invention provides an integrated circuit memory, comprising:

[0056] A dynamic storage area integration unit integrates multiple dynamic storage areas in a storage module inside a synchronous dynamic random access memory unit;

[0057] The termination resistor pin integrated unit transplants and integrates the termination resistor into the memory chip to form an internal integrated termination resistor; the region qualifier pin module is integrated into the synchronous dynamic random access memory unit;

[0058] On-chip calibration reflection control unit, the regional qualifier pin module integrates high-precision reference resistors; through the on-chip calibration engine, automatic calibration of the internal integrated termination resistors and signal reflection control are performed to control signal integrity and control voltage signal quality;

[0059] The multi-purpose register architecture unit integrates multi-purpose registers and intelligently controls multiple register modes to build high-density memory and high-bandwidth integrated circuit memory.

[0060] The principle and effect of the above technical solution are as follows: the present invention provides an integrated circuit memory, comprising: a dynamic storage area integration unit, which integrates multiple dynamic storage areas in a synchronous dynamic random access memory unit internal storage module; a termination resistor pin integration unit, which transplants and integrates the termination resistor into the memory chip to form an internal integrated termination resistor; an integrated region qualifier pin module in the synchronous dynamic random access memory unit; an on-chip calibration reflection control unit, in which the region qualifier pin module integrates a high-precision reference resistor; an on-chip calibration engine is used to automatically calibrate the internal integrated termination resistor and control signal reflection, thereby controlling signal integrity and controlling voltage and signal quality; a multi-purpose register rack The present invention can integrate multi-purpose registers, intelligently control multiple register modes, and construct high-density memory and high-bandwidth integrated circuit memory; it can quickly adapt to the rapid development of high-performance and low-energy consumption electronic equipment, and the performance of integrated circuit memory is higher; the present invention significantly improves storage density, read and write speed and power consumption; it can integrate the dynamic storage area in the storage module inside the storage unit; it can transfer the external termination resistor to the inside of the memory chip; it can randomly limit the pins of the storage unit integration area; it can automatically calibrate the internal integrated termination resistor and control the signal reflection; it can control multiple register modes and significantly improve the memory storage density and data operation bandwidth.

[0061] In one embodiment, the dynamic storage area integrated unit includes:

[0062] The storage array integration sub-unit forms a storage array module by combining the logical storage array of the memory; in the internal storage module, multiple storage array modules are integrated into the storage module;

[0063] High-density line-end arrangement sub-units, setting diamond-shaped staggered arrangement line-end contact blocks, constructing a high-density line-to-line arrangement; setting the address lines of the storage array module; performing storage array logic encoding, setting the system data bit width, and performing high-speed reading and writing of data units.

[0064] The principle and effect of the above technical solution are as follows: the dynamic storage area integrated unit includes: a storage array integrated sub-unit, which forms a storage array module with the logical storage array of the memory; in the internal storage module, multiple storage array modules are integrated into the storage module; a high-density line end arrangement sub-unit, which sets a diamond-shaped staggered arrangement of line end contact blocks to construct a high-density line-to-line arrangement; sets the address line of the storage array module; performs storage array logic encoding, sets the system data bit width, and performs high-speed reading and writing of data units; the diamond-shaped staggered arrangement of line end contact blocks includes: setting the line end contact block 1011 to a diamond-shaped staggered arrangement, setting a first separation spacing 1013 in the first spacing direction 1012 between the diamond edge and the adjacent diamond edge; setting a second separation spacing 1014 in the second spacing direction between the diamond edge and the adjacent diamond edge, the first separation spacing and the second separation spacing forming a staggered arrangement; partially overlapping the staggered arrangement in the spacing direction to form a bevel contact column 1015, and the line end contact blocks of the same area construct a high-density line-to-line arrangement.

[0065] In one embodiment, the terminating resistor pin integrated unit includes:

[0066] The termination resistor integrated sub-unit transplants and integrates the termination resistor into the memory chip to form an internal integrated termination resistor;

[0067] A qualifier pin subunit is provided, wherein the qualifier pin module is integrated in the synchronous dynamic random access memory unit;

[0068] The calibration command data storage subunit and the region qualifier pin module set the calibration command set; the calibration command set sets the long-cycle calibration command and the short-cycle calibration command;

[0069] Long-cycle calibration instructions include: power-on initialization instructions and memory reset instructions; short-cycle calibration instructions include: voltage following instructions and temperature following instructions;

[0070] The power-on initialization instruction and the memory reset instruction are executed to set the first long-cycle calibration clock, the second long-cycle calibration clock and the nth long-cycle calibration clock respectively; the clock period of the second long-cycle calibration clock and the nth long-cycle calibration clock is less than the first long-cycle calibration clock; the short-cycle calibration instruction is executed to set the first short-cycle calibration clock to execute the voltage following instruction and the temperature following instruction; the temperature following instruction includes: the first automatic refresh frequency corresponds to the first temperature range of self-refresh, the second automatic refresh frequency corresponds to the second temperature range of self-refresh, and the self-refresh reference standard temperature is set between the first temperature range of self-refresh and the second temperature range of self-refresh; and low-power state data is saved.

[0071] The principle and effect of the above technical solution are as follows: the termination resistor pin integrated unit includes: a termination resistor integrated sub-unit, which transplants and integrates the termination resistor into the memory chip to form an internal integrated termination resistor; a qualifier pin sub-unit, which qualifies the pin module in the synchronous dynamic random access memory unit integration area;

[0072] The calibration command data storage subunit and the region qualifier pin module set the calibration command set; the calibration command set sets long-cycle calibration instructions and short-cycle calibration instructions; the long-cycle calibration instructions include: power-on initialization instructions and memory reset instructions; the short-cycle calibration instructions include: voltage follow instructions and temperature follow instructions;

[0073] The power-on initialization instruction and the memory reset instruction are executed to set the first long-cycle calibration clock, the second long-cycle calibration clock and the nth long-cycle calibration clock respectively; the clock period of the second long-cycle calibration clock and the nth long-cycle calibration clock is less than the first long-cycle calibration clock; the short-cycle calibration instruction is executed to set the first short-cycle calibration clock to execute the voltage following instruction and the temperature following instruction; the temperature following instruction includes: the first automatic refresh frequency corresponds to the first temperature range of self-refresh, the second automatic refresh frequency corresponds to the second temperature range of self-refresh, and the self-refresh reference standard temperature is set between the first temperature range of self-refresh and the second temperature range of self-refresh; and low-power state data is saved.

[0074] In one embodiment, an on-chip calibration reflection control unit includes:

[0075] Reference resistor integrated sub-unit, regional qualifier pin module integrates high-precision reference resistor; internal integrated termination resistor is calibrated by high-precision reference resistor;

[0076] The calibration engine reflection control subunit performs automatic calibration of the internal integrated termination resistors and signal reflection control through the on-chip calibration engine, controlling signal integrity and controlling voltage and signal quality;

[0077] Dual calibration subunit, dual calibration of the gate resistor and the internal integrated termination resistor;

[0078] The internal integrated termination resistors include: data output drive on-resistance, terminal matching termination resistor, internal series resistor and internal read-write matching resistor; the internal read-write matching resistors include: internal read matching resistor and internal write matching resistor.

[0079] The principle and effect of the above technical solution are: on-chip calibration reflection control unit, including: reference resistor integration sub-unit, regional qualifier pin module integrated with high-precision reference resistor; internal integrated termination resistor is calibrated by high-precision reference resistor; calibration engine reflection control sub-unit, through the on-chip calibration engine, automatic calibration of internal integrated termination resistor and signal reflection control, control signal integrity and control voltage control signal quality; dual calibration sub-unit, dual calibration of the selection resistor and internal integrated termination resistor; internal integrated termination resistor includes: data output drive on-resistance, terminal matching termination resistor, internal serial resistor and internal read-write matching resistor; internal read-write matching resistor includes: internal read matching resistor and internal write matching resistor; automatic calibration and signal reflection control of internal integrated termination resistor through on-chip calibration engine includes: triggering the on-chip calibration engine, controlling the long calibration module through power-on initialization instruction, and powering on the system Initialization calibration, power-on calibration value reflects the data output driver on-resistance and terminal matching termination resistance; memory reset is controlled by memory reset instruction; internal serial resistance changes and internal read-write matching resistance changes following voltage changes and temperature changes are changed by short-cycle calibration instruction; during the calibration process, control signal integrity and control voltage control signal quality are detected; during the calibration process, control signal integrity and control voltage control signal quality are detected, including: detecting data flash high level and data strobe high level, as well as data flash low level and data strobe low level; analyzing whether the level matching synchronization status of data flash high level and data strobe high level, as well as data flash low level and data strobe low level meet the set level synchronization status; if the set level synchronization status is not met, the burst address line is selected to perform pull-up resistance level or pull-down resistance level rise and fall transmission until the level matching synchronization status meets the set level synchronization status, control signal integrity and control voltage control signal quality.

[0080] In one embodiment, a multi-purpose hosting architecture unit comprises:

[0081] The multi-purpose register sub-unit integrates multi-purpose registers, sets and stores data in multiple modes, and performs programming control of operation modes, intelligently controlling multiple register modes;

[0082] The target register subunit enables multiple target registers according to multiple register modes, adapting to the storage of various data characteristics; building high-density memory and high-bandwidth integrated circuit memory.

[0083] The principle and effect of the above technical solution are as follows: a multi-purpose register architecture unit, including: a multi-purpose register sub-unit, which integrates multi-purpose registers to set up and store multiple mode data, and performs programming control of operation modes, and intelligently controls multiple register modes; a target register sub-unit, which enables multiple target registers according to multiple register modes, and adapts to the storage of multiple data characteristics; constructs high-density memory and high-bandwidth integrated circuit memory; by integrating multi-purpose registers, it sets up and stores multiple mode data, and performs programming control of operation modes, and intelligently controls multiple register modes including: generating a first mode resistance value by configuring a first mode register as a serial resistance inside the memory, and performing internal serial control of the memory; generating a second mode resistance by configuring a second mode register The integrated circuit memory comprises: an internal read matching resistor, a third mode resistor, a third mode resistor value, a third mode resistor value, a third mode resistor value, a fourth ...

[0084] The present invention provides a method for constructing an integrated circuit memory, comprising:

[0085] S100, integrating multiple dynamic storage areas in a storage module inside a synchronous dynamic random access memory unit;

[0086] S200, transplanting and integrating the termination resistor into the memory chip to form an internal integrated termination resistor; integrating a region qualifier pin module into the synchronous dynamic random access memory cell;

[0087] S300, the regional qualifier pin module integrates high-precision reference resistors; through the on-chip calibration engine, automatic calibration of the internal integrated termination resistors and signal reflection control are performed to control signal integrity and control voltage signal quality;

[0088] S400, by integrating multi-purpose registers and intelligently controlling multiple register modes, builds high-density memory and high-bandwidth integrated circuit memory.

[0089] The principle and effect of the above technical solution are as follows: The present invention provides an integrated circuit memory construction method, comprising: integrating multiple dynamic storage areas in a storage module within a synchronous dynamic random access memory cell; transplanting and integrating termination resistors into a memory chip to form internally integrated termination resistors; integrating a region qualifier pin module within the synchronous dynamic random access memory cell; integrating a high-precision reference resistor into the region qualifier pin module; automatically calibrating and controlling signal reflection of the internally integrated termination resistors through an on-chip calibration engine to control signal integrity and control voltage and signal quality; integrating multi-purpose registers to intelligently control multiple register modes to construct high-density memory and high-bandwidth integrated circuit memory; being able to quickly adapt to the rapid development of high-performance and low-energy electronic devices, and achieving higher performance of integrated circuit memory; the present invention significantly improves storage density, read / write speed, and power consumption; can integrate dynamic storage areas in a storage module within a storage cell; can transfer external termination resistors to the interior of a memory chip; can integrate region limit pins in random access memory cells; can automatically calibrate and control signal reflection of the internally integrated termination resistors; can control multiple register modes and significantly improve memory storage density and data operation bandwidth.

[0090] In one embodiment, S100 includes:

[0091] S101, forming a storage array module from a logical storage array of a memory; integrating multiple storage array modules into the storage module in an internal storage module;

[0092] S102, arrange diamond-shaped staggered line end contact blocks to build a high-density line-to-line arrangement; set address lines of the storage array module; perform storage array logic encoding, set system data bit width, and perform high-speed reading and writing of data units.

[0093] The principle and effect of the above technical solution are as follows: the logical storage array of the memory is constituted into a storage array module; in the internal storage module, multiple storage array modules are integrated into the storage module; line end contact blocks are arranged in a diamond staggered arrangement to construct a high-density line-to-line arrangement; address lines of the storage array module are set; storage array logic encoding is performed, the system data bit width is set, and data units are read and written at high speed; the diamond staggered arrangement of line end contact blocks includes: arranging the line end contact blocks in a diamond staggered arrangement, setting a first separation spacing in the first spacing direction between the diamond side and the adjacent diamond side; setting a second separation spacing in the second spacing direction between the diamond side and the adjacent diamond side, the first separation spacing and the second separation spacing forming a staggered arrangement; partially overlapping the staggered arrangement in the spacing direction to form a diagonal contact column, and the line end contact blocks of the same area construct a high-density line-to-line arrangement.

[0094] In one embodiment, S200 includes:

[0095] S201, transplanting and integrating the termination resistor into the memory chip to form an internal integrated termination resistor;

[0096] S202, integrating a region qualifier pin module in a synchronous dynamic random access memory unit;

[0097] S203, the region qualifier pin module sets a calibration command set; the calibration command set sets a long-cycle calibration instruction and a short-cycle calibration instruction;

[0098] Long-cycle calibration instructions include: power-on initialization instructions and memory reset instructions; short-cycle calibration instructions include: voltage following instructions and temperature following instructions;

[0099] The power-on initialization instruction and the memory reset instruction are executed to set the first long-cycle calibration clock, the second long-cycle calibration clock and the nth long-cycle calibration clock respectively; the clock period of the second long-cycle calibration clock and the nth long-cycle calibration clock is less than the first long-cycle calibration clock; the short-cycle calibration instruction is executed to set the first short-cycle calibration clock to execute the voltage following instruction and the temperature following instruction; the temperature following instruction includes: the first automatic refresh frequency corresponds to the first temperature range of self-refresh, the second automatic refresh frequency corresponds to the second temperature range of self-refresh, and the self-refresh reference standard temperature is set between the first temperature range of self-refresh and the second temperature range of self-refresh; and low-power state data is saved.

[0100] The principle and effect of the above technical solution are: transplanting and integrating the termination resistor into the memory chip to form an internal integrated termination resistor; integrating the region qualifier pin module in the synchronous dynamic random access memory unit; setting the calibration command set in the region qualifier pin module; setting the long-cycle calibration instruction and the short-cycle calibration instruction in the calibration command set; the long-cycle calibration instruction includes: power-on initialization instruction and memory reset instruction; the short-cycle calibration instruction includes: voltage following instruction and temperature following instruction; the power-on initialization instruction and the memory reset instruction are executed to set the first long-cycle calibration clock, the second long-cycle calibration clock and the nth long-cycle calibration clock respectively; the clock period of the second long-cycle calibration clock and the nth long-cycle calibration clock is less than the first long-cycle calibration clock; the short-cycle calibration instruction is executed to set the first short-cycle calibration clock to execute the voltage following instruction and the temperature following instruction; the temperature following instruction includes: corresponding to the first automatic refresh frequency through the self-refresh first temperature range, corresponding to the second automatic refresh frequency through the self-refresh second temperature range, and setting the self-refresh reference standard temperature between the self-refresh first temperature range and the self-refresh second temperature range; and performing low-power state data storage.

[0101] In one embodiment, S300 includes:

[0102] S301, the region qualifier pin module integrates a high-precision reference resistor; the internal integrated termination resistor is calibrated by the high-precision reference resistor;

[0103] S302, through the on-chip calibration engine, automatically calibrates the internal integrated termination resistor and controls signal reflection, controls signal integrity and controls voltage and signal quality;

[0104] S303, double calibration of the gate resistor and the internal integrated termination resistor;

[0105] The internal integrated termination resistors include: data output drive on-resistance, terminal matching termination resistor, internal series resistor and internal read-write matching resistor; the internal read-write matching resistors include: internal read matching resistor and internal write matching resistor.

[0106] The principle and effect of the above technical solution are as follows: the regional qualifier pin module integrates high-precision reference resistors; the internal integrated termination resistors are calibrated by high-precision reference resistors; the internal integrated termination resistors are automatically calibrated and the signal reflection is controlled by the on-chip calibration engine to control the signal integrity and control the voltage and signal quality; the selection resistor and the internal integrated termination resistor are double calibrated; the internal integrated termination resistors include: data output drive on-resistance, terminal matching termination resistor, internal serial resistor and internal read-write matching resistor; the internal read-write matching resistors include: internal read matching resistor and internal write matching resistor; the internal integrated termination resistors are automatically calibrated and the signal reflection control is performed by the on-chip calibration engine, including: triggering the on-chip calibration engine, controlling the long calibration module through the power-on initialization instruction, and performing system power-on initialization calibration, and the power-on calibration value reflects the data output drive on-state Resistance and terminal matching termination resistance; memory reset is controlled by memory reset instruction; internal serial resistance changes and internal read-write matching resistance changes with voltage changes and temperature changes through short-cycle calibration instructions; during the calibration process, the control signal integrity and control voltage control signal quality are detected; during the calibration process, the control signal integrity and control voltage control signal quality are detected, including: detecting the data flash high level and data strobe high level, as well as the data flash low level and data strobe low level; analyzing whether the level matching synchronization status of the data flash high level and data strobe high level, as well as the data flash low level and data strobe low level meet the set level synchronization status; if the set level synchronization status is not met, the burst address line is selected to perform pull-up resistance level or pull-down resistance level increase and decrease transmission until the level matching synchronization status meets the set level synchronization state, control signal integrity and control voltage control signal quality.

[0107] In one embodiment, S400 includes:

[0108] S401, by integrating multi-purpose registers, sets and stores multiple mode data, and performs operation mode programming control, intelligently controlling multiple register modes;

[0109] S402, based on multiple register modes, multiple target registers are enabled to adapt to the storage of multiple data characteristics; and high-density memory and high-bandwidth integrated circuit memory are constructed.

[0110] The principle and effect of the above technical solution are: by integrating multi-purpose registers, setting up storage of multiple mode data, and performing programming control of operation modes, intelligently controlling multiple register modes; enabling multiple target registers according to multiple register modes to adapt to the storage of multiple data characteristics; building high-density memory and high-bandwidth integrated circuit memory; by integrating multi-purpose registers, setting up storage of multiple mode data, and performing programming control of operation modes, intelligently controlling multiple register modes including: generating a first mode resistance value by configuring a first mode register as an internal serial resistance of the memory, and performing internal serial control of the memory; generating a second mode resistance value by configuring a second mode register as an internal read matching resistance, in Matching internal impedance when reading data, and performing memory reading data control; generating a third mode resistance value by configuring a third mode register as an internal write matching resistor, matching internal impedance when writing data, and performing memory writing data control; enabling multiple target registers by configuring a fourth mode register; performing intelligent control of multiple register modes; enabling multiple target registers according to multiple register modes, and setting an integrated circuit memory with multiple data characteristics include: enabling multiple target registers by configuring a fourth mode register according to multiple register modes, reading a preset system timing calibration bit sequence through the multiple target registers, and adapting to the storage of multiple data characteristics; constructing a high-density memory and a high-bandwidth integrated circuit memory.

[0111] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the description and implementation methods. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. An integrated circuit memory, characterized in that: include: A dynamic storage area integration unit integrates multiple dynamic storage areas in a storage module inside a synchronous dynamic random access memory unit; The termination resistor pin integrated unit transplants and integrates the termination resistor into the memory chip to form an internal integrated termination resistor; the region qualifier pin module is integrated into the synchronous dynamic random access memory unit; On-chip calibration reflection control unit, regional qualifier pin module integrates high-precision reference resistor; Through the on-chip calibration engine, the internal integrated termination resistor is automatically calibrated and the signal reflection is controlled to control the signal integrity and control the voltage and signal quality; Multi-purpose register architecture unit, which integrates multi-purpose registers and intelligently controls multiple register modes to build high-density memory and high-bandwidth integrated circuit memory; Termination resistor pin integrated unit, including: The termination resistor integrated sub-unit transplants and integrates the termination resistor into the memory chip to form an internal integrated termination resistor; A qualifier pin subunit is provided, wherein the qualifier pin module is integrated in the synchronous dynamic random access memory unit; The calibration command data storage subunit and the region qualifier pin module set the calibration command set; the calibration command set sets the long-cycle calibration command and the short-cycle calibration command; Long-cycle calibration instructions include: power-on initialization instructions and memory reset instructions; short-cycle calibration instructions include: voltage following instructions and temperature following instructions; The power-on initialization instruction and the memory reset instruction are executed to set the first long-cycle calibration clock, the second long-cycle calibration clock and the nth long-cycle calibration clock respectively; the clock period of the second long-cycle calibration clock and the nth long-cycle calibration clock is less than the first long-cycle calibration clock; the short-cycle calibration instruction is executed to set the first short-cycle calibration clock to execute the voltage following instruction and the temperature following instruction; the temperature following instruction includes: the first automatic refresh frequency corresponds to the first temperature range of self-refresh, the second automatic refresh frequency corresponds to the second temperature range of self-refresh, and the self-refresh reference standard temperature is set between the first temperature range of self-refresh and the second temperature range of self-refresh; and low-power state data is saved.

2. The integrated circuit memory according to claim 1, wherein: Dynamic storage area integrated unit, including: The storage array integration sub-unit forms a storage array module by combining the logical storage array of the memory; in the internal storage module, multiple storage array modules are integrated into the storage module; High-density line-end arrangement sub-units, setting diamond-shaped staggered arrangement line-end contact blocks, constructing a high-density line-to-line arrangement; setting the address lines of the storage array module; performing storage array logic encoding, setting the system data bit width, and performing high-speed reading and writing of data units.

3. The integrated circuit memory according to claim 1, wherein: On-chip calibrated reflectance control unit, including: Reference resistor integrated sub-unit, regional qualifier pin module integrates high-precision reference resistor; internal integrated termination resistor is calibrated by high-precision reference resistor; The calibration engine reflection control subunit performs automatic calibration of the internal integrated termination resistors and signal reflection control through the on-chip calibration engine, controlling signal integrity and controlling voltage and signal quality; Dual calibration subunit, dual calibration of the gate resistor and internal integrated termination resistor; The internal integrated termination resistors include: data output drive on-resistance, terminal matching termination resistor, internal series resistor and internal read-write matching resistor; the internal read-write matching resistors include: internal read matching resistor and internal write matching resistor.

4. The integrated circuit memory according to claim 1, wherein: Multi-purpose hosting infrastructure unit, including: The multi-purpose register sub-unit integrates multi-purpose registers, sets and stores data in multiple modes, and performs programming control of operation modes, intelligently controlling multiple register modes; The target register subunit enables multiple target registers according to multiple register modes, adapting to the storage of various data characteristics; building high-density memory and high-bandwidth integrated circuit memory.

5. A method for constructing an integrated circuit memory, characterized in that: include: S100, integrating multiple dynamic storage areas in a storage module inside a synchronous dynamic random access memory unit; S200, transplanting and integrating the termination resistor into the memory chip to form an internal integrated termination resistor; integrating a region qualifier pin module into the synchronous dynamic random access memory cell; S300, regional qualifier pin module with integrated high-precision reference resistor; Through the on-chip calibration engine, the internal integrated termination resistor is automatically calibrated and the signal reflection is controlled to control the signal integrity and control the voltage and signal quality; S400, by integrating multi-purpose registers and intelligently controlling multiple register modes, builds high-density memory and high-bandwidth integrated circuit memory; S200 includes: S201, transplanting and integrating the termination resistor into the memory chip to form an internal integrated termination resistor; S202, integrating a region qualifier pin module in a synchronous dynamic random access memory unit; S203, the region qualifier pin module sets a calibration command set; the calibration command set sets a long-cycle calibration instruction and a short-cycle calibration instruction; Long-cycle calibration instructions include: power-on initialization instructions and memory reset instructions; short-cycle calibration instructions include: voltage following instructions and temperature following instructions; The power-on initialization instruction and the memory reset instruction are executed to set the first long-cycle calibration clock, the second long-cycle calibration clock and the nth long-cycle calibration clock respectively; the clock period of the second long-cycle calibration clock and the nth long-cycle calibration clock is less than the first long-cycle calibration clock; the short-cycle calibration instruction is executed to set the first short-cycle calibration clock to execute the voltage following instruction and the temperature following instruction; the temperature following instruction includes: the first automatic refresh frequency corresponds to the first temperature range of self-refresh, the second automatic refresh frequency corresponds to the second temperature range of self-refresh, and the self-refresh reference standard temperature is set between the first temperature range of self-refresh and the second temperature range of self-refresh; and low-power state data is saved.

6. The method for constructing an integrated circuit memory according to claim 5, wherein: S100 includes: S101, forming a storage array module from a logical storage array of a memory; integrating multiple storage array modules into the storage module in an internal storage module; S102, arrange diamond-shaped staggered line end contact blocks to build a high-density line-to-line arrangement; set address lines of the storage array module; perform storage array logic encoding, set system data bit width, and perform high-speed reading and writing of data units.

7. The method for constructing an integrated circuit memory according to claim 5, wherein: S300 includes: S301, the region qualifier pin module integrates a high-precision reference resistor; the internal integrated termination resistor is calibrated by the high-precision reference resistor; S302, through the on-chip calibration engine, automatically calibrates the internal integrated termination resistor and controls signal reflection, controls signal integrity and controls voltage and signal quality; S303, double calibration of the gate resistor and the internal integrated termination resistor; The internal integrated termination resistors include: data output drive on-resistance, terminal matching termination resistor, internal series resistor and internal read-write matching resistor; the internal read-write matching resistors include: internal read matching resistor and internal write matching resistor.

8. The method for constructing an integrated circuit memory according to claim 5, wherein: S400 includes: S401, by integrating multi-purpose registers, sets and stores multiple mode data, and performs operation mode programming control, intelligently controlling multiple register modes; S402, based on multiple register modes, multiple target registers are enabled to adapt to the storage of multiple data characteristics; and high-density memory and high-bandwidth integrated circuit memory are constructed.

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