Semiconductor structure and method for manufacturing the same

Abstract

The disclosed embodiments relate to the field of semiconductor technology and provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate and a plurality of semiconductor pillars disposed on the substrate, the plurality of semiconductor pillars being spaced apart along a first direction; a plurality of gate structures spaced apart along the first direction, each gate structure surrounding a sidewall of the semiconductor pillar, and each gate structure corresponding one-to-one to a semiconductor pillar spaced apart along the first direction; a plurality of mutually spaced first conductive layers, a first space being defined between two adjacent gate structures along the first direction, a first conductive layer being disposed within a first space, and the potential of each first conductive layer being adjustable; and a dielectric layer being disposed at least between the gate structure and the first conductive layer. The disclosed embodiments at least contribute to improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] As the integration density of semiconductor structures develops towards a higher level, while studying the arrangement of transistors in semiconductor structures and how to reduce the size of single functional devices in dynamic semiconductor structures, it is also necessary to improve the electrical performance of small-sized functional devices.

[0003] When a vertical gate-all-around (GAA) transistor structure is used as the access transistor of a semiconductor structure, the area occupied by it can reach 4F. 2 (F: the minimum pattern size obtainable under given process conditions). In principle, higher density efficiency can be achieved. However, due to the individual differences between transistors and the small spacing between adjacent transistors, interference can easily occur, making the overall electrical performance of the semiconductor structure unstable. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the electrical performance of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on one hand, the embodiments of the present disclosure provide a semiconductor structure, including: a substrate and a plurality of semiconductor pillars located on the substrate, the plurality of semiconductor pillars being arranged at intervals along a first direction; a plurality of gate structures arranged at intervals along the first direction, each of the gate structures surrounding the sidewalls of the semiconductor pillars, and the gate structures corresponding one-to-one to the semiconductor pillars arranged at intervals along the first direction; a plurality of mutually spaced first conductive layers, a first interval being provided between two adjacent gate structures along the first direction, a first conductive layer being located in a first interval, and the potential of each first conductive layer being adjustable; a dielectric layer, at least located between the gate structure and the first conductive layer.

[0006] In some embodiments, the plurality of semiconductor pillars are further spaced apart and arranged along a second direction, the gate structure and the first conductive layer both extend along the second direction, and the first direction and the second direction intersect.

[0007] In some embodiments, the semiconductor structure further includes: a plurality of second conductive layers corresponding one-to-one to the semiconductor pillars and spaced apart from each other, a partial area of ​​a second conductive layer is located in a semiconductor pillar, the semiconductor pillar exposes a remaining area of ​​the second conductive layer, and the second conductive layer is spaced apart from the gate structure, and the potential of each second conductive layer can be adjusted.

[0008] In some embodiments, along a third direction, the semiconductor column includes a first part, a second part, and a third part arranged in sequence, the gate structure surrounds the side wall of the second part, and the third direction is the direction in which the substrate points to the semiconductor column; the second conductive layer is located in a partial area of ​​the second part and a partial area of ​​the first part, and there is a distance between the second conductive layer close to the bottom surface of the substrate and the first part close to the bottom surface of the substrate.

[0009] In some embodiments, the second conductive layer includes: a second sub-conductive layer and a second lead-out layer in contact with the second sub-conductive layer, the second sub-conductive layer is located in the first part and the second part, the second sub-conductive layer extends along the third direction, and a partial area of ​​the second lead-out layer is located in the first part.

[0010] In some embodiments, along the third direction, the semiconductor column includes a first part, a second part and a third part arranged in sequence, the gate structure surrounds the side wall of the second part, and the third direction is the direction in which the substrate points to the semiconductor column; along the third direction, the height of the gate structure is a first height, the height of the first conductive layer is a second height, and the ratio of the second height to the first height is in the range of 1.5-2.5.

[0011] In some embodiments, the first conductive layer includes: a first sub-conductive layer and a first lead-out layer in contact with the first sub-conductive layer, the first sub-conductive layer extends along the third direction, and the first lead-out layer is located on a side of the dielectric layer away from the substrate.

[0012] In some embodiments, the second direction and the third direction constitute a reference plane, the orthographic projection of the gate structure on the reference plane is a first orthographic projection, the orthographic projection of the first sub-conductive layer on the reference plane is a second orthographic projection, and the first orthographic projection is located in the second orthographic projection.

[0013] In some embodiments, the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer. The first sub-dielectric layer is located on the sidewall and bottom of the first conductive layer, and the second sub-dielectric layer is located on a side of the first sub-dielectric layer away from the first conductive layer.

[0014] In some embodiments, a material of the first conductive layer includes at least one of molybdenum and titanium nitride, and a material of the second conductive layer includes at least one of molybdenum and titanium nitride.

[0015] In some embodiments, the base includes: a substrate; a bit line located on the substrate and extending along the first direction, wherein the bit line is in contact with and connected to bottom surfaces of a plurality of the semiconductor pillars arranged at intervals along the first direction.

[0016] In some embodiments, the material of the bit line includes a metal particle-containing compound.

[0017] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, including: forming a plurality of semiconductor pillars arranged at intervals along a first direction on a substrate; forming a plurality of gate structures, wherein the plurality of gate structures are arranged at intervals along the first direction, each of the gate structures surrounds the sidewalls of the semiconductor pillars, and the gate structures correspond one-to-one to the semiconductor pillars arranged at intervals along the first direction; a first interval is provided between two adjacent gate structures along the first direction, and a first conductive layer and a dielectric layer are formed in each of the first intervals, wherein the potential of each of the first conductive layers can be adjusted, and the dielectric layer is at least located between the gate structure and the first conductive layer.

[0018] In some embodiments, the steps of forming the semiconductor pillar include: providing an initial substrate; performing patterning on the initial substrate to form a plurality of initial semiconductor pillars spaced apart along the first direction; etching the initial semiconductor pillar to form a first gap spaced apart from the gate structure, wherein along a third direction, the bottom surface of the first gap is closer to the bottom surface of the initial semiconductor pillar than the bottom surface of the gate structure, and the third direction is the direction in which the substrate points to the semiconductor pillar; forming a second conductive layer in the first gap, wherein along the third direction, the top surface of the second conductive layer is closer to the bottom surface of the initial semiconductor pillar than the top surface of the gate structure, wherein the potential of the second conductive layer is adjustable; forming a semiconductor layer in the remaining first gap, and the semiconductor layer and the remaining initial semiconductor pillar constitute the semiconductor pillar.

[0019] In some embodiments, the steps of forming the semiconductor column include: providing an initial substrate; performing patterning on the initial substrate to form a plurality of initial second sub-conductive layers spaced apart along the first direction; performing metallization on a portion of the initial second sub-conductive layer to form a second sub-conductive layer, with the remaining initial second sub-conductive layer located between the second sub-conductive layer and the remaining initial substrate; forming an initial semiconductor column wrapping the second sub-conductive layer; etching the initial semiconductor column to form a second gap exposing a portion of the surface of the second sub-conductive layer; forming a second lead-out layer filling the second gap, the second lead-out layer and the second sub-conductive layer constituting a second conductive layer, and the remaining initial second sub-conductive layer and the remaining initial semiconductor column constituting the semiconductor column.

[0020] In some embodiments, the plurality of semiconductor pillars are further arranged at intervals along a second direction, and the first direction and the second direction intersect; before forming the gate structure, forming the first conductive layer includes: forming a third sub-dielectric layer, the third sub-dielectric layer covering the sidewalls of the plurality of semiconductor pillars, and the third sub-dielectric layer filling the gaps between the semiconductor pillars adjacent along the second direction, and the third sub-dielectric layers between the semiconductor pillars adjacent along the first direction have a third gap; forming a fourth sub-dielectric layer, the fourth sub-dielectric layer conformally covering the third gap, and the fourth sub-dielectric layer having a fourth gap; forming a first conductive layer, the first conductive layer filling the fourth gap.

[0021] In some embodiments, the plurality of semiconductor pillars are further arranged at intervals along a second direction, and the first direction and the second direction intersect; before forming the gate structure, forming the first conductive layer includes: forming a third sub-dielectric layer, the third sub-dielectric layer covering the sidewalls of the plurality of semiconductor pillars, and the third sub-dielectric layer filling the intervals between the semiconductor pillars adjacent along the second direction, and a third interval between the third sub-dielectric layers located between the semiconductor pillars adjacent along the first direction; forming a fourth sub-dielectric layer, the fourth sub-dielectric layer filling the third interval; patterning the fourth sub-dielectric layer to form a fourth interval, and any two semiconductor pillars adjacent along the first direction have a fourth interval; forming a first conductive layer, the first conductive layer filling the fourth interval.

[0022] In some embodiments, in the step of patterning the initial substrate, an initial transition layer extending along the first direction is also formed; after forming the initial semiconductor pillar and before forming the first conductive layer, the step further includes: forming a fifth sub-dielectric layer, wherein the fifth sub-dielectric layer conformally covers the surface of the initial semiconductor pillar and the fifth sub-dielectric layer partially exposes the initial transition layer; and metallizing the exposed initial transition layer to form a bit line, wherein the material of the bit line includes a metal particle-containing compound.

[0023] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0024] A semiconductor pillar and a surrounding gate structure form a GAA transistor. A first spacing is defined between two adjacent gate structures along a first direction, i.e., a first spacing is defined between two adjacent GAA transistors along the first direction. Thus, a first conductive layer is located within the first spacing, and the potential of each first conductive layer is adjustable, i.e., the potential of each first conductive layer can be independently adjusted. This facilitates adjusting the threshold voltage of the adjacent GAA transistor via any first conductive layer, thereby reducing the difference in threshold voltages between adjacent GAA transistors along the first direction, for example, ensuring that the threshold voltages of adjacent GAA transistors along the first direction are equal. It will be appreciated that different gate structures control the on / off state of different GAA transistors, and the on / off state of a GAA transistor is related to its threshold voltage. Reducing the difference in threshold voltages between adjacent GAA transistors along the first direction facilitates reducing the difference in potential between different gate structures. This facilitates controlling the on / off state of multiple GAA transistors in the entire semiconductor structure via gate structures with minimal potential difference, such as equal potential, thereby improving the electrical performance of the semiconductor structure. In addition, a first conductive layer located in a first spacer is also advantageous in reducing the coupling effect between any first conductive layer and an adjacent gate structure, thereby further improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1A schematic top view of a semiconductor structure provided by an embodiment of the present disclosure;

[0027] Figure 2 for Figure 1 A schematic partial cross-sectional view of the semiconductor structure shown along a first cross-sectional direction AA1;

[0028] Figure 3 for Figure 1 Another partial cross-sectional schematic diagram of the semiconductor structure along the first cross-sectional direction AA1;

[0029] Figure 4 for Figure 1 A schematic partial cross-sectional view of the semiconductor structure shown along a second cross-sectional direction BB1;

[0030] Figure 5 for Figure 1 A schematic partial cross-sectional view of the semiconductor structure shown along a third cross-sectional direction CC1;

[0031] Figure 6 for Figure 1 A schematic partial cross-sectional view of the semiconductor structure shown along a fourth cross-sectional direction DD1;

[0032] Figures 7 to 9 for Figure 1 Three more partial cross-sectional schematic diagrams of the semiconductor structure along the first cross-sectional direction AA1 are shown;

[0033] Figures 10 to 26 A schematic cross-sectional structural diagram corresponding to each step in a method for manufacturing a semiconductor structure provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0034] As known from the background art, the electrical performance of semiconductor structures needs to be improved.

[0035] Analysis has revealed that during the steps of remanufacturing a vertical gate-all-around (GAA) transistor structure, the semiconductor pillar in the transistor needs to be implanted with dopant ions to achieve its function. Specifically, along a certain direction, the semiconductor pillar includes a first portion, a second portion, and a third portion arranged in sequence, wherein the second portion serves as the channel region in the GAA transistor structure, one of the first portion and the third portion serves as the portion of the GAA transistor structure that is electrically connected to the drain, and the other of the first portion and the third portion serves as the portion of the GAA transistor structure that is electrically connected to the source. The doping concentrations of the dopant ions in the first portion, the second portion, and the third portion are different, placing very high demands on the doping process.

[0036] On the one hand, due to the limitations of the doping process itself, the doping concentration of dopant ions in the same portion of different semiconductor pillars can easily vary, resulting in different threshold voltages for different GAA transistor structures. On the other hand, the increased integration density of semiconductor structures increases the electrical interference between adjacent GAA transistor structures. Both of these factors can reduce the stability of the semiconductor structure's electrical performance. For example, they hinder the ability of different gate structures to control multiple GAA transistor structures using the same potential, making it easy for some GAA transistor structures to fail to turn on or off properly under the influence of the gate structures. Consequently, further improvements in the electrical performance of GAA transistor structures and dynamic memory devices are difficult to achieve.

[0037] The present disclosure provides a semiconductor structure and a method for manufacturing the same. In the semiconductor structure, a semiconductor pillar and a surrounding gate structure form a GAA transistor. A first spacing is defined between two adjacent gate structures along a first direction, i.e., a first spacing is defined between two adjacent GAA transistors along the first direction. Thus, a first conductive layer is located within the first spacing, and the potential of each first conductive layer is adjustable, i.e., the potential of each first conductive layer can be independently adjusted. This facilitates adjusting the threshold voltage of the adjacent GAA transistors via any first conductive layer, thereby reducing the difference between the threshold voltages of adjacent GAA transistors along the first direction. For example, this allows the threshold voltages of adjacent GAA transistors along the first direction to be equal, thereby facilitating reducing the difference in potential between different gate structures. Gate structures with minimal potential difference, such as equal potential, can be used to control the on / off switching of multiple GAA transistors throughout the semiconductor structure, thereby improving the electrical performance of the semiconductor structure. Furthermore, the first conductive layer located within the first spacing further facilitates reducing the coupling effect between any first conductive layer and the adjacent gate structure, thereby further improving the electrical performance of the semiconductor structure.

[0038] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0039] An embodiment of the present disclosure provides a semiconductor structure, which will be described in detail below with reference to the accompanying drawings. Figure 1 A schematic top view of a semiconductor structure provided by an embodiment of the present disclosure; Figure 2 for Figure 1 A schematic partial cross-sectional view of the semiconductor structure shown along a first cross-sectional direction AA1; Figure 3 for Figure 1Another partial cross-sectional schematic diagram of the semiconductor structure along the first cross-sectional direction AA1; Figure 4 for Figure 1 A schematic partial cross-sectional view of the semiconductor structure shown along a second cross-sectional direction BB1; Figure 5 for Figure 1 A schematic partial cross-sectional view of the semiconductor structure shown along a third cross-sectional direction CC1; Figure 6 for Figure 1 A schematic partial cross-sectional view of the semiconductor structure shown along a fourth cross-sectional direction DD1; Figures 7 to 9 for Figure 1 Three more schematic partial cross-sectional views of the semiconductor structure along the first cross-sectional direction AA1 are shown.

[0040] refer to Figures 1 to 9 The semiconductor structure includes: a substrate 100 and a plurality of semiconductor pillars 101 located on the substrate 100, wherein the plurality of semiconductor pillars 101 are arranged at intervals along a first direction X; a plurality of gate structures 102 are arranged at intervals along the first direction X, wherein each gate structure 102 surrounds a sidewall of the semiconductor pillar 101, and each gate structure 102 corresponds to a semiconductor pillar 101 arranged at intervals along the first direction X; a plurality of mutually spaced first conductive layers 103, wherein a first interval is defined between two adjacent gate structures 102 along the first direction X, a first conductive layer 103 is located in a first interval, and the potential of each first conductive layer 103 is adjustable; and a dielectric layer 104 is located at least between the gate structure 102 and the first conductive layer 103.

[0041] It can be understood that a semiconductor pillar 101 and the gate structure 102 surrounding it constitute a GAA transistor. When the potential of the first conductive layer 103 is controlled, an electric field is formed between the first conductive layer 103 and the GAA transistor, and this electric field can adjust the threshold voltage of the GAA transistor. When the potential of all first conductive layers 103 is not controlled, that is, no voltage is applied to all first conductive layers 103, the threshold voltage of each GAA transistor is tested, and then each first conductive layer 103 is adjusted separately so that the difference in threshold voltage of the GAA transistors adjacent to the first conductive layer 103 is small, for example, equal, to improve the electrical performance of the semiconductor structure. In addition, the first conductive layer 103 located in the first gap is also beneficial to reduce the coupling effect between it and the adjacent gate structure 102, so as to further improve the electrical performance of the semiconductor structure.

[0042] In practical applications, the first conductive layer 103 can make the ratio of the threshold voltages of two GAA transistors adjacent to the first conductive layer 103 be 0.95-1.05.

[0043] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0044] In some embodiments, continue to refer to Figure 1 , multiple semiconductor pillars 101 can also be arranged at intervals along the second direction Y, the gate structure 102 and the first conductive layer 103 both extend along the second direction Y, and the first direction X intersects the second direction Y. In this way, a gate structure 102 can control the multiple semiconductor pillars 101 arranged at intervals along the second direction Y, that is, a gate structure 102 can control the conduction or shutdown of multiple GAA transistors arranged at intervals along the second direction Y, and a first conductive layer 103 can adjust the threshold voltage of the multiple GAA transistors arranged at intervals along the second direction Y.

[0045] It should be noted that Figure 1 In the example, four semiconductor pillars 101 are arranged at intervals along the first direction X and four semiconductor pillars 101 are arranged at intervals along the second direction Y. In actual applications, there is no limit on the number of semiconductor pillars 101 arranged at intervals along the first direction X, and there is no limit on the number of semiconductor pillars 101 arranged at intervals along the second direction Y.

[0046] In some embodiments, reference Figures 2 to 9 Along the third direction Z, the semiconductor pillar 101 includes a first portion 111, a second portion 121 and a third portion 131 arranged in sequence, and the gate structure 102 surrounds the sidewall of the second portion 121. The third direction Z is the direction from the substrate 100 to the semiconductor pillar 101.

[0047] It can be understood that the second part 121 serves as the channel region in the GAA transistor, one of the first part 111 and the third part 131 serves as the part of the GAA transistor that is electrically connected to the drain contact, and the other of the first part 111 and the third part 131 serves as the part of the GAA transistor that is electrically connected to the source contact.

[0048] In some embodiments, due to the influence of the manufacturing process, the side walls of the first part 111, the side walls of the second part 121, and the side walls of the third part 131 are all inclined slopes, that is, along the third direction Z, the cross-sectional area of ​​the first part 111, the cross-sectional area of ​​the second part 121, and the cross-sectional area of ​​the third part 131 gradually decrease.

[0049] It should be noted that Figure 2 、 Figure 3 、 Figure 5 as well as Figures 7 to 9The first portion 111, the second portion 121, and the third portion 131 of the semiconductor pillar 103 are schematically illustrated by dotted lines. It will be appreciated that in some embodiments, the first portion 111, the second portion 121, and the third portion 131 may comprise the same semiconductor element, i.e., the first portion 111, the second portion 121, and the third portion 131 may be an integrally formed structure, which facilitates reducing interface state defects between the first portion 111, the second portion 121, and the third portion 131, thereby facilitating improved electrical performance of the semiconductor pillar 103 as a whole. In practical applications, dopant ions are implanted into the semiconductor pillar 103, and the dopant ions have different doping concentrations in the first portion 111, the second portion 121, and the third portion 131.

[0050] In some embodiments, the semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium.

[0051] In some embodiments, the orthographic projection of the second portion 121 on the substrate 100 is smaller than the orthographic projection of the first portion 111 on the substrate 100. This facilitates forming a second portion 121 with a smaller cross-sectional area in a cross section perpendicular to the third direction Z. This improves the ability of the gate structure 102 surrounding the sidewalls of the second portion 121 to control the channel region of the GAA transistor, thereby making it easier to control the on / off state of the GAA transistor. In practical applications, the orthographic projections of the first, second, and third portions on the substrate may be equal or unequal.

[0052] In some embodiments, reference Figure 4 Along the third direction Z, the height of the gate structure 102 is a first height H1, the height of the first conductive layer 103 is a second height H2, and the ratio of the second height H2 to the first height H1 is in the range of 1.5-2.5.

[0053] It can be understood that the first interval is the interval between two gate structures 102 adjacent to each other along the first direction X, the first conductive layer 103 is located in the first interval, and the ratio of the second height H2 to the first height H1 is in the range of 1.5-2.5. Taking the plane formed by the second direction Y and the third direction Z as the reference plane, the orthographic projection of the gate structure 102 on the reference plane is located in the orthographic projection of the first conductive layer 103 on the reference plane, and the first conductive layer 103 at least separates the two gate structures 102 adjacent to each other along the first direction X.

[0054] It should be noted that Figures 2 to 9In the example, the first conductive layer 103 not only separates two gate structures 102 adjacent to each other along the first direction X, but also separates two third portions 131 adjacent to each other along the first direction X, and the first conductive layer 103 is located in a portion of the gap between the two first portions 111 adjacent to each other along the first direction X. In practical applications, the first conductive layer 103 may be located only in the first gap, i.e., the ratio of the second height H2 to the first height H1 is 1; or, in addition to being located in the first gap, the first conductive layer 103 may be located only in at least a portion of the gap between the two third portions 131 adjacent to each other along the first direction X; or, in addition to being located in the first gap, the first conductive layer 103 may be located only in at least a portion of the gap between the two first portions 111 adjacent to each other along the first direction X.

[0055] In some embodiments, the gate structure 102 may include: a gate dielectric layer 112 covering the sidewall surface of the second portion 121 ; and a gate 122 covering the sidewall surface of the gate dielectric layer 112 away from the second portion 121 .

[0056] In some embodiments, reference Figure 2 、 Figure 3 、 Figure 5 as well as Figures 7 to 9 , along the direction perpendicular to the third direction Z, a portion of the gate dielectric layer 112 is embedded in the semiconductor pillar 101. In this way, when the gate 122 covers the sidewall surface of the gate dielectric layer 112 away from the second portion 121, along the direction perpendicular to the third direction Z, the thickness of the gate dielectric layer 112 and the thickness of the gate 122 are constant, which is conducive to reducing the distance between adjacent gates 122.

[0057] In some embodiments, reference Figures 3 to 6 The first conductive layer 103 is only located in the dielectric layer 104, and the top surface of the first conductive layer 103 away from the substrate 100 is flush with the top surface of the dielectric layer 104 away from the substrate 100. Subsequently, corresponding voltages can be applied to the exposed top surfaces of different first conductive layers 103 through different conductive layers.

[0058] In other embodiments, reference Figure 7 The first conductive layer 103 may include: a first sub-conductive layer 113 and a first lead layer 123 in contact with the first sub-conductive layer 113 , the first sub-conductive layer 113 extends along the third direction Z, and the first lead layer 123 is located on a side of the dielectric layer 104 away from the substrate 100 .

[0059] It should be noted that Figure 7In the example, the first lead layers 123 all extend along the first direction X and are located on the same layer. In actual applications, in order to facilitate the control of the potential of each first conductive layer 103, when laying out multiple first lead layers 123, the extension directions of different first lead layers 123 can be different, and different first lead layers 123 can be located on different layers, that is, the distances between different first lead layers 123 and the substrate 100 can be different. In addition, Figure 7 In the figure, the first sub-conductive layer 113 and the first lead-out layer 123 are taken as an example of a layered structure. In actual applications, depending on actual needs or different preparation methods, the first sub-conductive layer 113 and the first lead-out layer 123 can also be an integrally formed structure, which is beneficial to reducing the interface state defects at the contact point between the first sub-conductive layer 113 and the first lead-out layer 123, thereby reducing the contact resistance between the first sub-conductive layer 113 and the first lead-out layer 123, thereby helping to improve the overall conductivity of the first conductive layer 103.

[0060] In some embodiments, the material of the first sub-conductive layer 113 and the material of the first lead-out layer 123 may be the same conductive material; in other embodiments, the material of the first sub-conductive layer 113 and the material of the first lead-out layer 123 may be different conductive materials.

[0061] In some embodiments, the second direction Y and the third direction Z constitute a reference plane, the orthographic projection of the gate structure 102 on the reference plane is a first orthographic projection, the orthographic projection of the first sub-conductive layer 113 on the reference plane is a second orthographic projection, and the first orthographic projection is located within the second orthographic projection. This helps ensure that the gate structure 102 and the first sub-conductive layer 113 are directly aligned in the first direction X, avoiding partial misalignment between the gate structure 102 and the first sub-conductive layer 113 in the third direction Z. This helps ensure that the first conductive layer 103 has a high shielding effect on electrical interference between two adjacent gate structures 102, thereby further reducing the coupling effect between adjacent gate structures 102.

[0062] In some embodiments, reference Figure 8 and Figure 9 The semiconductor structure may further include: a plurality of second conductive layers 105 corresponding one-to-one to the semiconductor pillars 101 and spaced apart from each other, a partial area of ​​a second conductive layer 105 is located in a semiconductor pillar 101, the semiconductor pillar 101 exposes the remaining area of ​​a second conductive layer 105, and the second conductive layer 105 is spaced apart from the gate structure 102, and the potential of each second conductive layer 105 can be adjusted.

[0063] It can be understood that a GAA transistor includes a semiconductor column 101, and the second conductive layer 105 corresponds to the semiconductor column 101 one-to-one, so the second conductive layer 105 corresponds to the GAA transistor one-to-one. Moreover, since the semiconductor column 101 in the relatively insulated state of the GAA transistor forms a charge accumulation effect, it has an adverse effect on the electrical performance of the GAA transistor, that is, the floating body effect of the GAA transistor. In this way, providing the second conductive layer 105 in the semiconductor column 101 is conducive to releasing unnecessary charges accumulated in the corresponding GAA transistor through the second conductive layer 105, so as to reduce the floating body effect of the GAA transistor, thereby achieving the adjustment of the threshold voltage of the GAA transistor. Moreover, the second conductive layer 105 corresponds to the GAA transistor one-to-one, and the potential of each second conductive layer 105 can be adjusted, so the threshold voltage of any GAA transistor can be adjusted through different second conductive layers 105, that is, the threshold voltage of a single GAA transistor can be controlled through the second conductive layer 105.

[0064] In some embodiments, continue to refer to Figure 8 and Figure 9 Along the third direction Z, the semiconductor pillar 101 includes a first portion 111, a second portion 121 and a third portion 131 arranged in sequence, and the gate structure 102 surrounds the side wall of the second portion 121. The third direction Z is the direction from the substrate 100 to the semiconductor pillar 101; the second conductive layer 105 is located in a partial area of ​​the second portion 121 and a partial area of ​​the first portion 111. There is a gap between the bottom surface of the second conductive layer 105 close to the substrate 100 and the bottom surface of the first portion 111 close to the substrate 100, that is, there is a gap between the second conductive layer 105 and the substrate 100.

[0065] It is understandable that in actual applications, the floating body effect is prone to occur in the middle area of ​​the first portion 111. The second conductive layer 105 is located in a portion of the second portion 121 and a portion of the first portion 111, which means that the second conductive layer 105 is located in a region of the first portion 111 and the second portion 121 where the concentration of majority carriers is very low. This is beneficial for reducing the floating body effect of the GAA transistor through the second conductive layer 105, thereby adjusting the threshold voltage of the GAA transistor.

[0066] In addition, a first conductive layer 103 can adjust the threshold voltages of multiple GAA transistors arranged at intervals along the second direction Y, and a second conductive layer 105 can adjust the threshold voltage of a corresponding GAA transistor. In this way, after the threshold voltages of multiple GAA transistors arranged at intervals along the second direction Y are uniformly and preliminarily adjusted through the first conductive layer 103, the threshold voltages of multiple GAA transistors arranged at intervals along the second direction Y are adjusted separately through different second conductive layers 105. This is conducive to fully adjusting the threshold voltage of any GAA transistor through the joint action of the first conductive layer 103 and the second conductive layer 105, so as to further ensure that the differences in the threshold voltages of all GAA transistors in the semiconductor structure are reduced, for example, the threshold voltages of all GAA transistors are consistent.

[0067] In some embodiments, reference Figure 9 The second conductive layer 105 may include: a second sub-conductive layer 115 and a second lead-out layer 125 that is in contact with the second sub-conductive layer 115, the second sub-conductive layer 115 is located in the first part 111 and the second part 121, the second sub-conductive layer 115 extends along the third direction Z, and a partial area of ​​the second lead-out layer 125 is located in the first part 111.

[0068] It should be noted that Figure 9 In the figure, a part of the second lead-out layers 125 extending along the first direction X and being located in the same layer is taken as an example. In actual applications, in order to facilitate the control of the potential of each second conductive layer 105 separately, when laying out multiple second lead-out layers 125, the extension directions of different second lead-out layers 125 can be different, and different second lead-out layers 125 can be located in different layers, that is, the distances between different second lead-out layers 125 and the substrate 100 can be different.

[0069] also, Figure 9 In the figure, the second sub-conductive layer 115 and the second lead-out layer 125 are taken as an example of a layered structure. In actual applications, depending on actual needs or different preparation methods, the second sub-conductive layer 115 and the second lead-out layer 125 can also be an integrally formed structure, which is beneficial to reducing interface state defects at the contact point between the second sub-conductive layer 115 and the second lead-out layer 125, thereby reducing the contact resistance between the second sub-conductive layer 115 and the second lead-out layer 125, thereby helping to improve the overall conductivity of the second conductive layer 105.

[0070] also, Figure 8 The second lead layer cannot be cut out in the cross-sectional view shown in FIG. Figure 8 The second lead-out layer is not shown.

[0071] In some embodiments, the material of the second sub-conductive layer 115 and the material of the second lead-out layer 125 may be the same conductive material; in other embodiments, the material of the second sub-conductive layer 115 and the material of the second lead-out layer 125 may be different conductive materials.

[0072] In some embodiments, the material of the first conductive layer may include at least one of molybdenum and titanium nitride, and the material of the second conductive layer 105 may also include at least one of molybdenum and titanium nitride.

[0073] In some embodiments, reference Figures 3 to 9 The dielectric layer 104 includes a first sub-dielectric layer 114 and a second sub-dielectric layer 124 . The first sub-dielectric layer 114 is located on the sidewall and bottom of the first conductive layer 103 , and the second sub-dielectric layer 124 is located on a side of the first sub-dielectric layer 114 away from the first conductive layer 103 .

[0074] In some embodiments, continue to refer to Figures 2 to 9 The second sub-dielectric layer 124 covers the sidewalls of the first portion 111 and forms a groove. The second sub-dielectric layer 124 is located in the groove and in the gaps between adjacent gate structures 102 and between adjacent third portions 131. It will be appreciated that the first conductive layer 103 is located in the second sub-dielectric layer 124. The second sub-dielectric layer 124 is used to achieve electrical insulation between the gate structure 102 and the first conductive layer 103, as well as between adjacent third portions 131. The first sub-dielectric layer 114 is used to achieve electrical insulation between adjacent first portions 111.

[0075] It should be noted that Figures 2 to 9 The figure only illustrates a dual-layer structure of dielectric layer 104. In practical applications, depending on actual needs or different preparation methods, dielectric layer 104 can be a single-layer structure or a multi-layer structure. This embodiment of the present disclosure does not limit the specific structure of dielectric layer 104, as long as dielectric layer 104 provides electrical insulation between the various conductive structures described above. In addition, first sub-dielectric layer 114 can be a multi-layer structure made of the same material, and second sub-dielectric layer 124 can also be a multi-layer structure made of the same material.

[0076] In one example, the material of the first sub-dielectric layer 114 may be silicon nitride, and the material of the second sub-dielectric layer 124 may be silicon oxide.

[0077] In some embodiments, reference Figures 2 to 9The base 100 may include: a substrate 110; a bit line 106 located on the substrate 110 and extending along a first direction X, wherein each bit line 106 is in contact with and connected to the bottom surfaces of a plurality of semiconductor pillars 101 spaced apart along the first direction X. It is understood that the dielectric layer 104 is also used to achieve electrical insulation between adjacent bit lines 106.

[0078] In some embodiments, continue to refer to Figures 2 to 9 The substrate 100 may further include a transition layer 120, wherein the type of doping ions in the transition layer 120 is different from the type of doping ions in the substrate 110. This is beneficial for reducing leakage of the GAA transistor and improving the electrical performance of the semiconductor structure.

[0079] In one example, the doping ions in the transition layer 120 may be N-type doping ions, and the doping ions in the substrate 110 may be P-type doping ions.

[0080] Along the third direction Z, the height of the bit line 106 directly below the semiconductor pillar 101 first gradually decreases and then gradually increases. That is, at the point where the semiconductor pillar 101 contacts the bit line 106, the semiconductor pillar 101 has a portion that protrudes toward the substrate 100, while the bit line 106 has a portion that is recessed toward the transition layer 120. At the point where the bit line 106 directly below the semiconductor pillar 101 contacts the transition layer 120, the transition layer 120 has a portion that protrudes toward the bit line 106, while the bit line 106 has a portion that is recessed toward the semiconductor pillar 101. This helps increase the contact area between the transition layer 120 and the bit line 106, thereby increasing the contact resistance between the transition layer 120 and the bit line 106, preventing leakage between the transition layer 120 and the bit line 106, and improving the electrical performance of the semiconductor structure.

[0081] In some embodiments, the bit line 106 is further doped with metal elements, that is, the material of the bit line 106 includes a compound containing metal particles. Compared with unmetallized semiconductor materials, the bit line 106 doped with metal elements has a relatively small resistivity. Therefore, it is beneficial to further reduce the conductivity of the bit line 106 itself, thereby further reducing the contact resistance between the bit line 106 and the first part 111, and further improving the electrical performance of the semiconductor structure.

[0082] In some embodiments, the metal element may include at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0083] It can be understood that the base 100 includes a substrate 110, a transition layer 120 and a bit line 106, and the substrate 110, the transition layer 120 and the bit line 106 can have the same semiconductor element, and the substrate 110, the transition layer 120 and the bit line 106 can be formed using the same film layer structure, which is composed of semiconductor elements, so that the substrate 110, the transition layer 120 and the bit line 106 are an integrated structure, thereby improving the interface state defects between the substrate 110 and the transition layer 120, and between the transition layer 120 and the bit line 106, so as to improve the performance of the semiconductor structure.

[0084] In summary, a first conductive layer 103 is located in a first gap, and the potential of each first conductive layer 103 is adjustable. This facilitates adjusting the threshold voltage of the adjacent GAA transistor via any first conductive layer 103, thereby reducing the difference in threshold voltages between adjacent GAA transistors along the first direction X. For example, the threshold voltages of adjacent GAA transistors along the first direction X are equal, thereby facilitating reducing the difference in potential between different gate structures 102. Gate structures 102 with very small potential differences, such as equal potentials, can be used to control the on / off state of multiple GAA transistors in the entire semiconductor structure, thereby facilitating improving the electrical performance of the semiconductor structure. Furthermore, a first conductive layer 103 located in a first gap further facilitates reducing the coupling effect between any first conductive layer 103 and its adjacent gate structure 102, thereby further improving the electrical performance of the semiconductor structure.

[0085] Another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which can be used to form the semiconductor structure provided by an embodiment of the present disclosure. The method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0086] Figures 1 to 26 A schematic diagram of the cross-sectional structures corresponding to each step in the method for manufacturing a semiconductor structure provided in another embodiment of the present invention is provided. The method for manufacturing the semiconductor structure provided in this embodiment will be described in detail below in conjunction with the accompanying drawings, and the parts that are the same as or corresponding to the above embodiment will not be described in detail below.

[0087] refer to Figures 1 to 26The method for manufacturing a semiconductor structure includes: forming a plurality of semiconductor pillars 101 arranged at intervals along a first direction X on a substrate 100; forming a plurality of gate structures 102, wherein the plurality of gate structures 102 are arranged at intervals along the first direction X, each gate structure 102 surrounds a sidewall of the semiconductor pillar 101, and the gate structures 102 correspond one-to-one to the semiconductor pillars 101 arranged at intervals along the first direction X; a first gap is defined between two adjacent gate structures 102 along the first direction X, and a first conductive layer 103 and a dielectric layer 104 are formed in each first gap, wherein the potential of each first conductive layer 103 is adjustable, and the dielectric layer 104 is located at least between the gate structure 102 and the first conductive layer 103.

[0088] A method for manufacturing a semiconductor structure provided by another embodiment of the present invention is described in detail below with reference to the accompanying drawings.

[0089] In some embodiments, the plurality of semiconductor pillars 101 are further arranged at intervals along the second direction Y, and the first direction X intersects the second direction Y. The following description will be made using the arrangement of the plurality of semiconductor pillars 101 at intervals along the first direction X and the second direction Y as an example.

[0090] In some embodiments, reference Figure 9 In addition to the first conductive layer 103, the semiconductor structure may further include a second conductive layer 105. The manufacturing method for forming the semiconductor pillar 101 and the second conductive layer 105 includes but is not limited to the following two embodiments:

[0091] In some embodiments, forming the semiconductor pillar 101 may include the following steps:

[0092] refer to Figure 10 and Figure 11 , providing an initial substrate (not shown); and patterning the initial substrate to form a plurality of initial semiconductor pillars 141 arranged at intervals along a first direction X.

[0093] In some embodiments, the step of patterning the initial substrate includes: forming a first mask layer (not shown) on the initial substrate, the first mask layer having a plurality of mutually discrete first openings; etching the initial substrate using the first mask layer as a mask to form a plurality of first trenches corresponding to the first openings in the initial substrate; forming an initial first isolation layer (not shown) in the first trenches; forming a second mask layer (not shown) on the top surface jointly formed by the initial first isolation layer and the remaining initial substrate, the second mask layer having a plurality of mutually discrete second openings, the extension direction of the first openings intersecting with the extension direction of the second openings; etching the initial first isolation layer and the remaining initial substrate using the second mask layer as a mask to form a plurality of second trenches (not shown), initial semiconductor pillars 141, an initial transition layer 130 and a substrate 110, and along the third direction Z, the depth of the second trenches is less than that of the first trenches, which is conducive to forming a plurality of mutually discrete initial semiconductor pillars 141 on the side of the initial transition layer 130 away from the substrate 110 while forming the initial transition layer 130. Furthermore, in order to achieve electrical insulation between adjacent initial transition layers 130 and adjacent initial semiconductor pillars 141, after etching the initial first isolation layer and the remaining initial substrate using the second mask layer as a mask, the remaining initial first isolation layer is also located in the gap between the adjacent initial transition layers 130 along the second direction Y, and in the gap between the adjacent initial semiconductor pillars 141 along the second direction Y as the first isolation layer 107; the remaining second mask layer can be located as the second isolation layer 117 on the top surface of the initial semiconductor pillar 141 and part of the first isolation layer 107, and the second isolation layer 117 extends along the second direction Y.

[0094] It should be noted that the initial semiconductor pillar 141 and the initial transition layer 130 are subsequently used to form a semiconductor pillar, a bit line and a transition layer.

[0095] In some embodiments, continue to refer to Figure 10 and Figure 11 After forming the initial semiconductor column 141, the manufacturing method of the semiconductor structure may further include the following steps: performing a first ion implantation process on the substrate 110, and performing a second ion implantation process on the initial transition layer 130 and the initial semiconductor column 141, wherein the doping ions implanted in one of the first ion implantation process and the second ion implantation process are N-type doping ions, and the doping ions implanted in the other of the first ion implantation process and the second ion implantation process are P-type doping ions.

[0096] Combined with reference Figure 10 and Figure 12 , the initial semiconductor column 141 is etched to form a first gap 108 in the remaining initial semiconductor column 141, the first gap 108 and the subsequently formed gate structure 102 (refer to Figure 9) are spaced apart from each other, and along the third direction Z, the bottom surface of the first gap 108 is closer to the bottom surface of the initial semiconductor column 141 than the bottom surface of the gate structure 102 formed subsequently, and the third direction Z is the direction from the substrate 100 to the semiconductor column 101.

[0097] Understandably, the reference Figure 12 The cross-sectional shape of the first gap 108 in a certain cross-section parallel to the third direction Z can be L-shaped, which is used for the subsequent formation of the second conductive layer 105 (refer to Figure 9 ). It should be noted that Figure 12 Only two first gaps 108 are shown in FIG. 1 in which the cross-sections perpendicular to the second direction Y are L-shaped, and the cross-sections of the other first gaps 108 in other cross-sections parallel to the third direction Z are L-shaped.

[0098] Combined with reference Figure 12 and Figure 13 A second conductive layer 105 is formed in the first gap 108. Along the third direction Z, the top surface of the second conductive layer 105 is closer to the bottom surface of the initial semiconductor column 141 than the top surface of the subsequently formed gate structure 102, wherein the potential of the second conductive layer 105 is adjustable.

[0099] Combined with reference Figure 13 and Figure 9 A semiconductor layer (not shown) is formed in the remaining first gap 108. The semiconductor layer and the remaining initial semiconductor column 141 constitute the semiconductor column 101. It should be noted that the material of the semiconductor layer is the same as that of the remaining initial semiconductor column 141. Figure 9 The semiconductor layer and the remaining initial semiconductor columns 141 are not divided and are uniformly drawn as semiconductor columns 101 .

[0100] In addition, in actual applications, the second sub-conductive layer 115 (refer to Figure 9 ) and the second lead-out layer 125 (reference Figure 9 ) can also be formed by etching and filling the initial semiconductor column 141 twice.

[0101] In some other embodiments, forming the semiconductor pillar 101 may include the following steps:

[0102] refer to Figure 14 In step 14a, an initial substrate (not shown) is provided; the initial substrate is patterned to form a plurality of initial second sub-conductive layers 135 spaced apart along the first direction X. It will be appreciated that during the step of forming the initial second sub-conductive layers 135, an initial transition layer 130 and a substrate 110 are also formed. The formation of the initial transition layer 130 and the substrate 110 is the same as in the previous embodiment and will not be further described here.

[0103] Combined with reference Figure 14 14a and 14b, a portion of the initial second sub-conductive layer 135 is metallized to form a second sub-conductive layer 115, and the remaining initial second sub-conductive layer 135 is located between the second sub-conductive layer 115 and the remaining initial substrate; continue to refer to Figure 14 , forming an initial semiconductor column 141 that wraps the first sub-conductive layer 115 ; etching the initial semiconductor column 141 to form a second gap 118 that exposes a portion of the surface of the first sub-conductive layer 115 .

[0104] Combined with reference Figure 14 14b and Figure 9 , forming a second lead-out layer 125 that fills the second gap 118, the second lead-out layer 125 and the second sub-conductive layer 115 constitute the second conductive layer 105, and the remaining initial second sub-conductive layer 135 and the remaining initial semiconductor column 141 constitute the semiconductor column 101. It should be noted that the material of the remaining initial second sub-conductive layer 135 is the same as that of the remaining initial semiconductor column 141. Figure 9 The remaining initial second sub-conductive layer 135 and the remaining initial semiconductor pillars 141 are not divided and are uniformly drawn as semiconductor pillars 101 .

[0105] It is understood that there are many methods for forming the second conductive layer 105 and the semiconductor pillar 101, so that the formed semiconductor pillar 101 can be a layered structure in different forms. Figure 9 In the figure, the layering of the semiconductor pillar 101 is not distinguished, and the semiconductor pillar 101 is drawn as a whole.

[0106] In other embodiments, the semiconductor structure may include only the first conductive layer 103 but not the second conductive layer 105. The method for preparing the semiconductor structure will be described in detail below using a semiconductor structure without the second conductive layer as an example.

[0107] In some embodiments, reference Figure 10 and Figure 11 In the step of patterning the initial substrate 130, an initial transition layer 130 extending along the first direction X is also formed. After forming the initial semiconductor pillar 141, the first conductive layer 103 (refer to Figure 3 ), the method for manufacturing the semiconductor structure may further include the following steps:

[0108] refer to Figure 15, forming a fifth sub-dielectric layer 154. The fifth sub-dielectric layer 154 conformally covers the surface of the initial semiconductor pillar 141 and exposes a portion of the initial transition layer 130. It will be understood that in the aforementioned description, the remaining second mask layer serves as the second isolation layer 117 and is located on the top surface of the initial semiconductor pillar 141 and a portion of the first isolation layer 107. On this basis, the step of forming the fifth sub-dielectric layer 154 includes forming a sixth sub-dielectric layer 164 that covers the sidewalls of the initial semiconductor pillar 141 not covered by the first isolation layer 107. The sixth sub-dielectric layer 164 also covers the exposed sidewalls of the first isolation layer 107. The second isolation layer 117 and the sixth sub-dielectric layer 164 together constitute the fifth sub-dielectric layer 154.

[0109] It should be noted that in actual applications, during the step of using the second mask layer, the remaining second mask layer is also removed. That is, no second isolation layer is formed on the top surface of the initial semiconductor pillar 141 and a portion of the top surface of the first isolation layer 107. In the subsequent step of forming the fifth sub-dielectric layer 154, the fifth sub-dielectric layer 154 located on the top surface and sidewalls of the initial semiconductor pillar 141 can be integrally formed. This helps reduce the defect state density within the fifth sub-dielectric layer 154, thereby improving the insulation performance of the fifth sub-dielectric layer 154.

[0110] Combined with reference Figures 15 to 18 , metallizing the exposed initial transition layer 130 to form a bit line 106, wherein the material of the bit line 106 includes a compound containing metal particles. In some embodiments, before metallizing the exposed initial transition layer 130, the method for preparing the semiconductor structure may further include: Figure 15 and Figure 16 , the exposed initial transition layer 130 is etched using the fifth sub-dielectric layer 154 as a mask to form grooves 128. A plurality of grooves 128 are formed in the initial transition layer 130 extending along the first direction X, and the distance between the bottom surface of the groove 128 and the substrate 110 is greater than the distance between the bottom surface of the remaining initial transition layer 130 and the substrate 110; Figures 16 to 18 A metal layer (not shown) is formed on the surface exposed by the groove 128, and the semiconductor structure is annealed so that the metal layer reacts with the initial transition layer 130 in contact with the metal layer to form a semiconductor structure. Figure 17 and Figure 18 Bit line 106 is shown.

[0111] It should be noted that, in the step of forming the bit line 106, the remaining unmetallized initial transition layer 130 located closer to the substrate 110 than the bit line 106 serves as the transition layer 120; the remaining unmetallized initial transition layer 130 located farther from the substrate 110 than the bit line 106 can serve as a portion of the semiconductor pillar 101, that is, the initial semiconductor pillar 141 and this portion of the initial transition layer 130 together constitute the semiconductor pillar 101. Figure 17 and Figure 18 The semiconductor column 101 is drawn as a whole.

[0112] Furthermore, in practical applications, after the semiconductor structure is annealed to form the bit line 106 , a portion of the metal layer may remain without reacting with the initial transition layer 130 , and the remaining metal layer is removed.

[0113] The following describes in detail the formation of the first conductive layer 103 through two embodiments.

[0114] In some embodiments, before forming the gate structure 102 , forming the first conductive layer 103 may include the following steps:

[0115] Combined with reference Figures 17 to 20 A third sub-dielectric layer 134 is formed. The third sub-dielectric layer 134 covers the sidewalls of the plurality of semiconductor pillars 101 and fills the spaces between the semiconductor pillars 101 adjacent to each other along the second direction Y. Third spaces 138 are formed between the third sub-dielectric layers 134 between the semiconductor pillars 101 adjacent to each other along the first direction X.

[0116] It can be understood that in the foregoing description, the first isolation layer 107, the second isolation layer 117, and the sixth sub-dielectric layer 164 have been formed on the surfaces of various regions of the semiconductor pillar 101. On this basis, the seventh sub-dielectric layer 174 is formed. The seventh dielectric layer 174 covers the sidewalls of the sixth sub-dielectric layer 164 and the top surface of the bit line 106. The seventh sub-dielectric layer 174 located between the semiconductor pillars 101 adjacent to each other along the first direction X forms a third spacer 138. The first isolation layer 107, the second isolation layer 117, the sixth sub-dielectric layer 164, and the seventh sub-dielectric layer 174 together constitute the third sub-dielectric layer 134.

[0117] It should be noted that, in actual applications, during the step of forming the third sub-dielectric layer 134, the first isolation layer 107, the second isolation layer 117, and the sixth sub-dielectric layer 164 formed in the aforementioned steps can be removed to expose the sidewalls of the plurality of semiconductor pillars 101, thereby forming an integrally formed third sub-dielectric layer 134. This helps reduce the defect state density within the third sub-dielectric layer 134, thereby improving the insulation performance of the third sub-dielectric layer 134.

[0118] refer to Figures 19 to 22 , a fourth sub-dielectric layer 144 is formed. The fourth sub-dielectric layer 144 conformally covers the third spacer 138 , and the fourth sub-dielectric layer 144 has a fourth spacer 148 .

[0119] Continue to refer Figures 19 to 22 , forming a first conductive layer 103 , and the first conductive layer 103 fills the fourth space 148 .

[0120] In some other embodiments, before forming the gate structure 102 , forming the first conductive layer 103 may include the following steps:

[0121] Combined with reference Figures 17 to 20 A third sub-dielectric layer 134 is formed. The third sub-dielectric layer 134 covers the sidewalls of the plurality of semiconductor pillars 101 and completely fills the spaces between adjacent semiconductor pillars 101 along the second direction Y. Third spaces 138 are formed between the third sub-dielectric layers 134 between adjacent semiconductor pillars 101 along the first direction X. This step is the same as in the previous embodiment and is not further described here.

[0122] A fourth sub-dielectric layer (not shown) is formed, and the fourth sub-dielectric layer fills the third space 138; the fourth sub-dielectric layer is patterned to form a fourth space 148, and there is a fourth space 148 between any two semiconductor pillars 101 adjacent along the first direction X; Figure 21 and Figure 22 , forming the first conductive layer 103, which fills the fourth spacer 148. In this way, it is advantageous to control the size of the fourth spacer 148 by etching the fourth dielectric layer, thereby facilitating the formation of the first conductive layer 103 with more precise size.

[0123] The following describes in detail how to form the gate structure 102 by taking the formation of the third sub-dielectric layer 134 and the fourth sub-dielectric layer 144 as an example.

[0124] Combined with reference Figures 21 to 24 The formed third sub-dielectric layer 134 , the fourth sub-dielectric layer 144 and the first conductive layer 103 are planarized until the top surface of the semiconductor pillar 101 is exposed.

[0125] Continue to refer Figures 21 to 24 Along the third direction Z, the semiconductor pillar 101 includes a first portion 111, a second portion 121 and a third portion 131 arranged in sequence, and a portion of the third sub-dielectric layer 134 is etched until the sidewall of the third portion 131 is exposed.

[0126] Continue to refer Figures 21 to 24An eighth sub-dielectric layer 184 is formed. The eighth sub-dielectric layer 184 surrounds the sidewall of the third portion 131. The eighth sub-dielectric layer 184 located on the sidewall of the third portion 131 forms a through hole 158. The bottom of the through hole 158 exposes a portion of the remaining surface of the third sub-dielectric layer 134. The material of the eighth sub-dielectric layer 184 is different from that of the third sub-dielectric layer 134.

[0127] It should be noted that Figure 23 and Figure 24 The eighth sub-dielectric layer 184 and the fourth sub-dielectric layer 144 are filled in the same filling manner. The material of the eighth sub-dielectric layer 184 and the material of the fourth sub-dielectric layer 144 can be the same or different, and the material of the fourth sub-dielectric layer 144 and the material of the third sub-dielectric layer 134 are also different.

[0128] refer to Figure 23 and Figure 24 , remove the third sub-dielectric layer 134 on the side wall of the second portion 121 exposed by the through hole 158, and the remaining third sub-dielectric layer 134 serves as the second sub-dielectric layer 124 (refer to Figure 3 ).

[0129] In some embodiments, since the through hole 158 exposes a portion of the top surface of the remaining third sub-dielectric layer 134, and the material of the third sub-dielectric layer 134 is different from the materials of the eighth sub-dielectric layer 184 and the fourth sub-dielectric layer 144, an etching solution can be injected into the through hole 158 to remove the third sub-dielectric layer 134 located on the sidewall of the second portion 121 through a wet etching process.

[0130] Furthermore, the eighth sub-dielectric layer 184 and the fourth sub-dielectric layer 144 together form a support framework, which is in contact with and connected to the third portion 131, and partially embedded in the third sub-dielectric layer 134. During the wet etching process, the support framework supports and secures the semiconductor pillars 101. When the etching solution flows, it exerts a compressive force on the semiconductor pillars 101, which helps prevent the semiconductor pillars 101 from tilting or deflecting due to the compression, thereby improving the stability of the semiconductor structure. Furthermore, the support framework wraps around the sidewalls of the third portion 131, helping to prevent damage to the third portion 131 caused by the etching solution.

[0131] After the third sub-dielectric layer 134 located on the sidewall of the second portion 121 is removed, a fifth spacer 168 is formed between the second portion 121 and the fourth sub-dielectric layer 144 . The through hole 158 and the fifth spacer 168 together form a cave structure.

[0132] Combined with reference Figures 23 to 26 A gate dielectric layer 112 is formed on the sidewall surface of the second portion 121 , and the gate dielectric layer 112 covers the sidewall surface of the second portion 121 .

[0133] Taking the material of the semiconductor pillar 101 as silicon as an example, the sidewall of the exposed second portion 121 is thermally oxidized to form a gate dielectric layer 112, and the gate dielectric layer 112 covers the sidewall surface of the remaining second portion 121, and a sixth gap (not marked in the figure) is provided between the gate dielectric layer 112 and the fourth sub-dielectric layer 144.

[0134] refer to Figure 25 and Figure 26 , forming a gate 122 covering the sidewall surface of the gate dielectric layer 112 away from the second portion 121, and the gate 122 fills the sixth gap. It should be noted that, Figure 25 In the example, a gate 122 surrounds four semiconductor pillars 101 . In practical applications, there is no limit on the number of semiconductor pillars surrounded by a gate 122 .

[0135] In some embodiments, the material of the gate 122 includes at least one of polysilicon, titanium nitride, tantalum nitride, copper, or tungsten.

[0136] It can be understood that the gate 122 self-aligns to fill the sixth gap, which is conducive to the self-alignment formation of a gate 122 with precise dimensions. There is no need to design the size of the gate 122 through an etching process, which is conducive to simplifying the steps of forming the gate 122. By adjusting the size of the sixth gap, a small-sized gate 122 can be obtained.

[0137] Continue to refer Figure 25 and Figure 26 , forming a ninth sub-dielectric layer 194, which is filled with the through hole 158. It should be noted that, Figure 25 and Figure 26 The ninth sub-dielectric layer 194 and the eighth sub-dielectric layer 184 are filled in the same filling manner. The material of the ninth sub-dielectric layer 194 and the material of the eighth sub-dielectric layer 184 can be the same or different.

[0138] It is understood that there are many methods for forming the first conductive layer 103, so that in the step of forming the first conductive layer 103 and the subsequent step of forming the gate structure 102, the various dielectric layers formed have different forms. Figure 9 The dielectric layer 104 formed in each step is uniformly divided into a first sub-dielectric layer 114 and a second sub-dielectric layer 124, wherein the first sub-dielectric layer 114 includes Figure 25 and Figure 26 The fourth sub-dielectric layer 144, the eighth sub-dielectric layer 184 and the ninth sub-dielectric layer 194 in the second sub-dielectric layer 124 include Figure 25 and Figure 26 The third sub-dielectric layer 134 in the embodiment of the present invention is shown in FIG.

[0139] In summary, in a semiconductor structure formed by a manufacturing method provided by another embodiment of the present disclosure, a first conductive layer 103 is located in a first gap, and the potential of each first conductive layer 103 is adjustable. This facilitates adjusting the threshold voltage of an adjacent GAA transistor via any first conductive layer 103, thereby reducing the difference between the threshold voltages of adjacent GAA transistors along a first direction X. For example, the threshold voltages of adjacent GAA transistors along the first direction X are equal, thereby facilitating reducing the difference in potential between different gate structures 102. Gate structures 102 with very small potential differences, such as equal potentials, can be used to control the on / off state of multiple GAA transistors in the entire semiconductor structure, thereby facilitating improving the electrical performance of the semiconductor structure. Furthermore, the location of a first conductive layer 103 in a first gap further facilitates reducing the coupling effect between any first conductive layer 103 and its adjacent gate structure 102, thereby further improving the electrical performance of the semiconductor structure.

[0140] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate and a plurality of semiconductor pillars located on the substrate, wherein the plurality of semiconductor pillars are arranged at intervals along a first direction; a plurality of gate structures arranged at intervals along the first direction, each gate structure surrounding a sidewall of the semiconductor pillar, and the gate structures corresponding one-to-one to the semiconductor pillars arranged at intervals along the first direction; a plurality of mutually spaced first conductive layers, wherein a first space is provided between two adjacent gate structures along the first direction, a first conductive layer is located in a first space, and the potential of each first conductive layer is adjustable; a dielectric layer, located at least between the gate structure and the first conductive layer; Multiple second conductive layers correspond one-to-one to the semiconductor pillars and are spaced apart from each other, a partial area of ​​a second conductive layer is located in a semiconductor pillar, the semiconductor pillar exposes a remaining area of ​​the second conductive layer, and the second conductive layer is spaced apart from the gate structure, and the potential of each second conductive layer can be adjusted.

2. The semiconductor structure according to claim 1, wherein The plurality of semiconductor pillars are further arranged at intervals along a second direction, the gate structure and the first conductive layer both extend along the second direction, and the first direction and the second direction intersect.

3. The semiconductor structure according to claim 1, wherein: Along a third direction, the semiconductor pillar includes a first portion, a second portion, and a third portion arranged in sequence, the gate structure surrounds a sidewall of the second portion, and the third direction is a direction from the substrate to the semiconductor pillar; The second conductive layer is located in a partial area of ​​the second portion and a partial area of ​​the first portion, and there is a distance between the second conductive layer close to the bottom surface of the substrate and the first portion close to the bottom surface of the substrate.

4. The semiconductor structure according to claim 3, wherein: The second conductive layer includes: a second sub-conductive layer and a second lead-out layer in contact with the second sub-conductive layer, the second sub-conductive layer is located in the first part and the second part, the second sub-conductive layer extends along the third direction, and a partial area of ​​the second lead-out layer is located in the first part.

5. The semiconductor structure according to claim 2, wherein: Along a third direction, the semiconductor pillar includes a first portion, a second portion, and a third portion arranged in sequence, the gate structure surrounds a sidewall of the second portion, and the third direction is a direction from the substrate to the semiconductor pillar; Along the third direction, the height of the gate structure is a first height, the height of the first conductive layer is a second height, and the ratio of the second height to the first height is in a range of 1.5-2.

5.

6. The semiconductor structure according to claim 5, wherein: The first conductive layer includes a first sub-conductive layer and a first lead-out layer in contact with the first sub-conductive layer. The first sub-conductive layer extends along the third direction. The first lead-out layer is located on a side of the dielectric layer away from the substrate.

7. The semiconductor structure according to claim 6, wherein: The second direction and the third direction constitute a reference plane, the orthographic projection of the gate structure on the reference plane is a first orthographic projection, the orthographic projection of the first sub-conductive layer on the reference plane is a second orthographic projection, and the first orthographic projection is located in the second orthographic projection.

8. The semiconductor structure according to claim 1, wherein: The dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer. The first sub-dielectric layer is located on the sidewall and bottom surface of the first conductive layer, and the second sub-dielectric layer is located on a side of the first sub-dielectric layer away from the first conductive layer.

9. The semiconductor structure according to claim 1, wherein: The material of the first conductive layer includes at least one of molybdenum and titanium nitride, and the material of the second conductive layer includes at least one of molybdenum and titanium nitride.

10. The semiconductor structure according to claim 1, wherein: The substrate comprises: substrate; A bit line is located on the substrate and extends along the first direction, and the bit line is in contact with and connected to the bottom surfaces of the plurality of semiconductor pillars arranged at intervals along the first direction.

11. The semiconductor structure according to claim 10, wherein: The material of the bit line includes a compound containing metal particles.

12. A method for manufacturing a semiconductor structure, characterized in that: include: forming a plurality of semiconductor pillars spaced apart along a first direction on a substrate; forming a plurality of gate structures, the plurality of gate structures being arranged at intervals along the first direction, each gate structure surrounding a sidewall of the semiconductor pillar, and the gate structures corresponding one to one with the semiconductor pillars arranged at intervals along the first direction; A first gap is formed between two adjacent gate structures along the first direction, and a first conductive layer and a dielectric layer are formed in each of the first gaps, wherein the potential of each first conductive layer is adjustable, and the dielectric layer is at least located between the gate structure and the first conductive layer; The step of forming the semiconductor column includes: providing an initial substrate; Performing patterning on the initial substrate to form a plurality of initial semiconductor pillars spaced apart along the first direction; Etching the initial semiconductor pillar to form a first gap spaced apart from the gate structure, wherein a bottom surface of the first gap is closer to a bottom surface of the initial semiconductor pillar than a bottom surface of the gate structure in a third direction, wherein the third direction is a direction from the substrate to the semiconductor pillar; forming a second conductive layer in the first gap, wherein along the third direction, a top surface of the second conductive layer is closer to a bottom surface of the initial semiconductor pillar than a top surface of the gate structure, wherein the potential of the second conductive layer is adjustable; A semiconductor layer is formed in the remaining first gap, and the semiconductor layer and the remaining initial semiconductor column constitute the semiconductor column.

13. The manufacturing method according to claim 12, wherein: The plurality of semiconductor pillars are further arranged at intervals along a second direction, and the first direction and the second direction intersect; Before forming the gate structure, forming the first conductive layer includes: forming a third sub-dielectric layer, wherein the third sub-dielectric layer covers sidewalls of the plurality of semiconductor pillars and fills the spaces between the semiconductor pillars adjacent to each other along the second direction, and a third space is formed between the third sub-dielectric layers located between the semiconductor pillars adjacent to each other along the first direction; forming a fourth sub-dielectric layer, wherein the fourth sub-dielectric layer conformally covers the third gap and has a fourth gap; A first conductive layer is formed, wherein the first conductive layer completely fills the fourth space.

14. The manufacturing method according to claim 12, wherein: The plurality of semiconductor pillars are further arranged at intervals along a second direction, and the first direction and the second direction intersect; Before forming the gate structure, forming the first conductive layer includes: forming a third sub-dielectric layer, wherein the third sub-dielectric layer covers sidewalls of the plurality of semiconductor pillars and fills the spaces between the semiconductor pillars adjacent to each other along the second direction, and a third space is formed between the third sub-dielectric layers located between the semiconductor pillars adjacent to each other along the first direction; forming a fourth sub-dielectric layer, wherein the fourth sub-dielectric layer completely fills the third gap; Performing patterning on the fourth sub-dielectric layer to form a fourth spacer, wherein any two semiconductor pillars adjacent to each other along the first direction have the fourth spacer; A first conductive layer is formed, wherein the first conductive layer completely fills the fourth space.

15. The manufacturing method according to claim 12, wherein: In the step of patterning the initial substrate, an initial transition layer extending along the first direction is also formed; After forming the initial semiconductor pillar and before forming the first conductive layer, the method further includes: forming a fifth sub-dielectric layer, wherein the fifth sub-dielectric layer conformally covers the surface of the initial semiconductor pillar and the fifth sub-dielectric layer partially exposes the initial transition layer; The exposed initial transition layer is metallized to form a bit line, wherein the material of the bit line includes a compound containing metal particles.

16. A method for manufacturing a semiconductor structure, characterized in that: include: forming a plurality of semiconductor pillars spaced apart along a first direction on a substrate; forming a plurality of gate structures, the plurality of gate structures being arranged at intervals along the first direction, each gate structure surrounding a sidewall of the semiconductor pillar, and the gate structures corresponding one to one with the semiconductor pillars arranged at intervals along the first direction; A first gap is formed between two adjacent gate structures along the first direction, and a first conductive layer and a dielectric layer are formed in each of the first gaps, wherein the potential of each first conductive layer is adjustable, and the dielectric layer is at least located between the gate structure and the first conductive layer; The step of forming the semiconductor column includes: providing an initial substrate; Performing a patterning process on the initial substrate to form a plurality of initial second sub-conductive layers spaced apart along the first direction; performing a metallization process on a portion of the initial second sub-conductive layer to form a second sub-conductive layer, with the remaining initial second sub-conductive layer being located between the second sub-conductive layer and the remaining initial substrate; forming an initial semiconductor column encapsulating the second sub-conductive layer; Etching the initial semiconductor pillar to form a second gap exposing a portion of the surface of the second sub-conductive layer; A second lead-out layer filling the second gap is formed, the second lead-out layer and the second sub-conductive layer constitute a second conductive layer, and the remaining initial second sub-conductive layer and the remaining initial semiconductor column constitute the semiconductor column.

17. The manufacturing method according to claim 16, wherein: The plurality of semiconductor pillars are further arranged at intervals along a second direction, and the first direction and the second direction intersect; Before forming the gate structure, forming the first conductive layer includes: forming a third sub-dielectric layer, wherein the third sub-dielectric layer covers sidewalls of the plurality of semiconductor pillars and fills the spaces between the semiconductor pillars adjacent to each other along the second direction, and a third space is formed between the third sub-dielectric layers located between the semiconductor pillars adjacent to each other along the first direction; forming a fourth sub-dielectric layer, wherein the fourth sub-dielectric layer conformally covers the third gap and has a fourth gap; A first conductive layer is formed, wherein the first conductive layer completely fills the fourth space.

18. The manufacturing method according to claim 16, wherein: The plurality of semiconductor pillars are further arranged at intervals along a second direction, and the first direction and the second direction intersect; Before forming the gate structure, forming the first conductive layer includes: forming a third sub-dielectric layer, wherein the third sub-dielectric layer covers sidewalls of the plurality of semiconductor pillars and fills the spaces between the semiconductor pillars adjacent to each other along the second direction, and a third space is formed between the third sub-dielectric layers located between the semiconductor pillars adjacent to each other along the first direction; forming a fourth sub-dielectric layer, wherein the fourth sub-dielectric layer completely fills the third gap; Performing patterning on the fourth sub-dielectric layer to form a fourth spacer, wherein any two semiconductor pillars adjacent to each other along the first direction have the fourth spacer; A first conductive layer is formed, wherein the first conductive layer completely fills the fourth space.

19. The manufacturing method according to claim 16, wherein: In the step of patterning the initial substrate, an initial transition layer extending along the first direction is also formed; After forming the initial semiconductor pillar and before forming the first conductive layer, the method further includes: forming a fifth sub-dielectric layer, wherein the fifth sub-dielectric layer conformally covers the surface of the initial semiconductor pillar and the fifth sub-dielectric layer partially exposes the initial transition layer; The exposed initial transition layer is metallized to form a bit line, wherein the material of the bit line includes a compound containing metal particles.

Images