A method for preparing an air gap structure of a resistive memory array

Abstract

The present invention discloses a method for fabricating an air gap structure for a resistive memory array, belonging to the field of semiconductor and CMOS hybrid integrated circuit technology. During the back-end resistive memory array fabrication process, the present invention utilizes a high-aspect-ratio groove structure design to form periodic air gaps between adjacent resistive memory cells. This method effectively alleviates signal delay issues caused by capacitive coupling and is of great significance for improving the performance of new memory technologies in large-scale integration and production.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors and CMOS hybrid integrated circuits, and in particular relates to a method for preparing an air gap structure between resistive switching memory cells. Background Art

[0002] With the advent of the intelligent era, Moore's Law is gradually failing. The limitations of the traditional von Neumann architecture in separating data storage and processing have prompted research into novel non-volatile memory technologies. To achieve compatibility with existing CMOS platforms, emerging memory technologies such as resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), and phase-change random access memory (PCRAM) typically employ back-end integration to ensure interoperability with traditional metal interconnect layers.

[0003] With the development of ultra-large-scale integrated circuit technology, the continuous reduction in feature size has led to a significant increase in the capacitive coupling effect between interconnects. Faced with this challenge, although traditional methods have used low-dielectric constant materials such as silicon dioxide (SiO2) to reduce parasitic capacitance between interconnects, the effectiveness of these methods has been limited. Therefore, the introduction of air gap technology with an extremely low dielectric constant (about 1) is considered to be an effective strategy to reduce RC delay and improve performance. However, how to integrate air gap technology into existing production processes while ensuring process stability and reliability remains a challenge.

[0004] In the development of 3D flash memory technology, the introduction of air gaps through self-aligned, double patterning processes and wet etching techniques, combined with the sacrificial use of specific layers of material, has demonstrated potential strategies for optimizing back-end interconnect issues. Similarly, the use of XeF2 dry etching to introduce air gaps has also been explored. While these approaches have been successful in reducing coupling capacitance and increasing speed, the additional process steps and the resulting thermal and mechanical stability issues associated with multiple process cycles remain key limitations for widespread adoption.

[0005] In summary, while existing air gap technology provides an effective solution for reducing RC delay in integrated circuits, particularly in back-end metal interconnects, the complex process flow and thermal and mechanical stability issues of the new structure remain unresolved. Therefore, effectively introducing air gaps within a minimal area during CMOS back-end integration without incurring additional costs is of crucial theoretical and practical significance for promoting the development of new memory technologies and CMOS hybrid integration. Summary of the Invention

[0006] To address these technical challenges, this paper proposes a method for fabricating air gap structures in resistive memory arrays. This method innovates upon conventional CMOS processes by optimizing the etching and deposition steps in the back-end manufacturing process. This method achieves the periodic introduction of air gaps within high-density memory structures, effectively reducing capacitive coupling and providing a technical foundation for the commercialization of new high-density memory devices.

[0007] The technical solutions provided by the present invention are as follows:

[0008] A method for preparing an air gap structure of a resistive switching memory array, comprising the following steps:

[0009] 1) Based on a CMOS process, after the front-end process is completed, a first insulating dielectric layer is deposited, a plurality of first interconnect metal layers are provided in the first insulating dielectric layer, the first interconnect metal layers corresponding to the resistive switching memory cells of the resistive switching memory array, and a first barrier layer is deposited above the first interconnect metal layers and the first insulating dielectric layer;

[0010] 2) etching a first through hole in the first barrier layer and depositing an interconnect metal in the first through hole to form a connection end of the first interconnect metal layer;

[0011] 3) depositing a bottom electrode layer, a resistive material layer, a top electrode layer, and a protective layer in sequence above the connection end of the first barrier layer and the first interconnect metal layer by physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD) technology to form a stacked structure;

[0012] 4) etching the stacked structure to form a resistive switching memory cell;

[0013] 5) depositing a second barrier layer on the resistive memory cell, and etching a periodic groove structure between adjacent resistive memory cells, wherein the sidewalls of the grooves are perpendicular to the bottom, and the aspect ratio of the grooves is 10:1 to 10:1000;

[0014] 6) Then, a second insulating dielectric layer is deposited to form an air gap structure in the groove structure;

[0015] 7) Etching a second through hole in the second insulating dielectric layer, the second barrier layer, and the protective layer. The second through hole is located above the top electrode of the resistive memory cell. A second interconnect metal layer is deposited in the second through hole to complete the preparation of the resistive memory array.

[0016] Through the above steps, the present invention not only optimizes the back-end process flow, but also significantly improves the performance of the integrated circuit by periodically self-forming an air gap structure, providing strong technical support for the commercialization of high-density new memory.

[0017] Furthermore, the material of the resistive layer is selected from AlOx, HfOx, TaOx, ZrOx, SiOx, VO x , MnOx, TiOx, CuOx, ZnOx, WOx, AgOx, SrTiOx, CaTiOx or one or more combinations of organic materials.

[0018] Furthermore, the first insulating dielectric layer and the second insulating dielectric layer include but are not limited to SiCOH, SiO2, SiLK, FOx, MSQ, porous materials, Nanoglass, HOSP, organic polymers and porous materials, carbon nanotubes and graphene, etc.

[0019] Furthermore, the first interconnection metal and the second interconnection metal are made of copper or aluminum.

[0020] Furthermore, the first barrier layer and the second barrier layer are made of silicon carbide thin films, and the protective layer is made of metal, metal nitride or conductive metal oxide.

[0021] The bottom electrode and the top electrode are made of metal, metal nitride or conductive metal oxide.

[0022] Furthermore, the first through hole is etched using photolithography technology, and the second through hole is formed using a dual damascene process.

[0023] Beneficial effects of the present invention:

[0024] During the deposition process of the back-end resistive memory array, this invention adheres to specific design principles (such as precisely defining device dimensions and inter-cell spacing) and fine-tunes the lateral and vertical etch aspect ratios and etch rates. By utilizing a groove structure with a high aspect ratio and sharp edges (where the sidewalls meet the horizontal surface), this technology creates periodic air gaps within the dielectric layer. This technology effectively mitigates signal delays caused by capacitive coupling and is of great significance for improving the performance of new memory technologies in large-scale integration and production. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of an air gap structure of a resistive switching memory array prepared using the present invention;

[0026] Figure 2-10 Corresponding to the implementation steps of each embodiment.

[0027] Figure 11 for Figure 1-10 Legend for . DETAILED DESCRIPTION

[0028] In order to make the above features and advantages of the present invention more clearly understood, the following specifically provides embodiments and detailed descriptions with reference to the accompanying drawings.

[0029] The present invention provides a method for preparing an air gap structure of a resistive memory array, wherein the resistive memory cell in the resistive memory array adopts TiN as the bottom electrode material and TaO x (or other chemically matched oxides) as the resistive switching layer material, and TiN as the top electrode material. The specific preparation method is as follows:

[0030] S1: Based on the CMOS process, the front-end process is completed, a first insulating dielectric layer is deposited, and a plurality of first interconnect metal layers are set in the insulating dielectric layer, each first interconnect metal layer corresponds to a resistive switching memory cell, and a first barrier layer is deposited on the first interconnect metal and the first insulating dielectric layer. Figure 2 shown.

[0031] The interconnect metal layer may be made of copper or aluminum, the first insulating dielectric layer may be made of silicon oxide, and the barrier layer may be made of silicon carbide film.

[0032] S2: Etching a first through hole in the first barrier layer and depositing interconnection metal in the first through hole to form a connection end of the first interconnection metal layer, such as Figure 3 shown.

[0033] The through-holes are etched using photolithography technology, and the interconnection metal deposited in the through-holes is made of copper using a PVD process.

[0034] S3: By physical vapor deposition (PVD), atomic layer deposition (ALD) or chemical vapor deposition (CVD) technology, a bottom electrode layer, a resistive material layer, a top electrode layer and a protective layer are sequentially deposited on the connection end of the first insulating dielectric layer and the first interconnect metal layer to form a stacked structure, such as Figure 4 shown.

[0035] The bottom electrode layer and the top electrode layer can be made of TiN, the protective layer can be made of TaN, the resistive material layer can be made of TaOx or HfOx, and each layer is deposited by PVD method, with a thickness of 1 to 300 nm. The stacked structure is patterned by photolithography technology.

[0036] The resistive material layer can be a single layer or two or more layers of material, and the materials used are AlOx, HfOx, TaOx, ZrOx, SiOx, VO x , MnOx, TiOx, CuOx, ZnOx, WOx, AgOx, SrTiOx, CaTiOx or organic materials or a combination of multiple materials.

[0037] The material of the protective layer can also be metal (W, Cu, Al, Ta, Hf, Ti, Pt, Ir, Ru, Pd, etc.) or metal nitride (TiN, TaN, AlN) or conductive metal oxide (IrO, RuO, SrTiO).

[0038] S4: Etching the stacked structure to form a resistive switching memory cell, thereby forming a resistive switching memory array, such as Figure 5 As shown;

[0039] S5: depositing a second barrier layer on the resistive memory array; Figure 6 As shown, the second barrier layer is then etched to form a periodic groove structure between adjacent resistive memory cells, wherein the sidewall of the groove is perpendicular to the bottom, and the aspect ratio of the groove is 10:1 to 10:1000.

[0040] The second barrier layer may include a silicon carbide film with a thickness of 1 to 100 nm, which is mainly used to protect the resistive memory array; after depositing the second barrier layer, the lateral and longitudinal etching aspect ratios and etching rates are adjusted to form a groove with a higher aspect ratio and a steep area (the sidewall of the groove is perpendicular to the bottom), such as Figure 7 shown.

[0041] S6: Deposit a second insulating dielectric layer to form a periodic air gap, such as Figure 8 shown.

[0042] The groove has a high aspect ratio and a steep area structure, which results in different deposition rates at the bottom and sidewalls of the groove during the PVD dielectric layer process, thereby forming periodic air gaps in the dielectric layer, alleviating the speed drop caused by capacitive coupling.

[0043] S7: Etching a second through hole in the second insulating dielectric layer, the second barrier layer and the protective layer, wherein the second through hole is located above the top electrode of the resistive memory cell. Figure 9 As shown, by depositing the second interconnect metal, the preparation of the resistive switching memory array is completed, as shown in FIG. Figure 10 shown.

[0044] The second through hole is etched using a dual damascene process and filled with metal copper or aluminum as interconnection metal.

[0045] In this embodiment, after each layer is deposited, a CMP (Chemical Mechanical Polishing) process is used to perform a planarization process.

[0046] The resistive random access memory and its manufacturing method according to the present invention are described above by way of example with reference to the accompanying drawings. However, those skilled in the art will appreciate that various improvements may be made to the resistive random access memory and its manufacturing method proposed above without departing from the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the contents of the appended claims.

Claims

1. A method for preparing an air gap structure of a resistive switching memory array, characterized in that: The specific steps include: 1) Based on a CMOS process, after the front-end process is completed, a first insulating dielectric layer is deposited, a plurality of first interconnect metal layers are provided in the first insulating dielectric layer, the first interconnect metal layers corresponding to the resistive switching memory cells of the resistive switching memory array, and a first barrier layer is deposited above the first interconnect metal layers and the first insulating dielectric layer; 2) etching a first through hole in the first barrier layer and depositing an interconnect metal in the first through hole to form a connection end of the first interconnect metal layer; 3) depositing a bottom electrode layer, a resistive material layer, a top electrode layer, and a protective layer in sequence above the connection end of the first barrier layer and the first interconnect metal layer by physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD) technology to form a stacked structure; 4) etching the stacked structure to form a resistive switching memory cell; 5) depositing a second barrier layer on the resistive memory cell, and etching a periodic groove structure between adjacent resistive memory cells, wherein the sidewalls of the grooves are perpendicular to the bottom, and the aspect ratio of the grooves is 10:1 to 10:1000; 6) Then, a second insulating dielectric layer is deposited to form an air gap structure in the groove structure; 7) Etching a second through hole in the second insulating dielectric layer, the second barrier layer, and the protective layer. The second through hole is located above the top electrode of the resistive memory cell. A second interconnect metal layer is deposited in the second through hole to complete the preparation of the resistive memory array.

2. The preparation method according to claim 1, wherein The resistive material layer is selected from AlOx, HfOx, TaOx, ZrOx, SiOx, VO x , MnOx, TiOx, CuOx, ZnOx, WOx, AgOx, SrTiOx, CaTiOx or a combination of one or more organic materials.

3. The preparation method according to claim 1, wherein The first insulating dielectric layer and the second insulating dielectric layer are made of SiCOH, SiO2, SiLK, Fox, MSQ, or porous materials, Nanoglass, HOSP, organic polymers or pore materials, and carbon nanotubes or graphene.

4. The preparation method according to claim 1, wherein The first interconnection metal or the second interconnection metal is made of copper or aluminum.

5. The preparation method according to claim 1, wherein The first barrier layer or the second barrier layer is made of a silicon carbide film.

6. The preparation method according to claim 1, wherein The protective layer is made of metal, metal nitride or conductive metal oxide.

7. The preparation method according to claim 1, wherein The bottom electrode or the top electrode is made of metal, metal nitride or conductive metal oxide.

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