Security cloud platform memory allocation method, device, equipment and storage medium

Abstract

The present invention provides a method, device, equipment and storage medium for allocating memory of a secure cloud platform, which is applied to the field of computer technology. The method includes: obtaining the operation requirement parameters of each first CPU in a first system; determining the target memory configuration scheme corresponding to each first CPU from a plurality of preset memory configuration schemes according to the operation requirement parameters of each first CPU; the target memory configuration scheme includes the address of at least one memory slice divided for the corresponding first CPU, the addresses of the memory slices included in each set of memory configuration schemes are not continuous, and different memory configuration schemes correspond to different operation requirement parameters; dividing the preset memory area according to the addresses of the memory slices in the target memory configuration schemes of each first CPU, determining the plurality of memory slices corresponding to the memory area, and allocating them to the corresponding first CPU; wherein the addresses of the memory slices allocated by each first CPU are not continuous. The technical solution of the present invention can improve the operation security of the computer system.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a secure cloud platform memory allocation method, device, equipment and storage medium. Background Art

[0002] In a multi-core two-by-two secure computer system architecture, a single CPU (Central Processing Unit) usually runs a secure BSP (Board Support Package), operating system, security protocol stack, platform core processing layer software, secure application software, etc. To support the operation of the above content, the same SRAM (Static Random-Access Memory) is required. Therefore, it is particularly important to allocate SRAM to each CPU.

[0003] In the related art, when allocating SRAM, a fixed area is usually used for different CPUs, that is, a continuous area is allocated in the memory to the corresponding CPU for use, and the memory allocated to each CPU is generally allocated continuously.

[0004] However, with such a highly coupled memory allocation method, during the memory power-on self-test and periodic self-test, it is easy for a failure in one memory area to cause failure in all memory areas, thereby reducing the operational security of the entire computer system. Summary of the invention

[0005] The present invention provides a secure cloud platform memory allocation method, device, equipment and storage medium, which are used to solve the defect in the prior art that during the memory power-on self-test and periodic self-test process, a failure of one memory area easily leads to failure of all memory areas, thereby reducing the operating security of the entire computer system, thereby achieving the technical effect of improving the operating security of the computer system.

[0006] The present invention provides a secure cloud platform memory allocation method, comprising the following steps.

[0007] Obtaining the operation requirement parameters of each first central processing unit CPU in the first system;

[0008] According to the operation requirement parameters of each first CPU, a target memory configuration scheme corresponding to each first CPU is determined from a plurality of preset memory configuration schemes; the target memory configuration scheme includes the address of at least one memory slice allocated for the corresponding first CPU, the addresses of the memory slices included in each memory configuration scheme are not continuous, and different memory configuration schemes correspond to different operation requirement parameters;

[0009] The preset memory area is divided according to the addresses of the memory slices in the target memory configuration scheme of each first CPU, and multiple memory slices corresponding to the memory area are determined and allocated to the corresponding first CPUs; wherein the addresses of the memory slices allocated to each first CPU are not continuous.

[0010] According to a secure cloud platform memory allocation method provided by the present invention, the target memory configuration scheme of the first CPU includes a partitioning method of each sub-area in the memory slice, and the preset memory area is divided according to the address of the memory slice in the target memory configuration scheme of each first CPU, and multiple memory slices corresponding to the memory area are determined and allocated to the corresponding first CPU, including:

[0011] Dividing a preset memory area according to the addresses of the memory slices in the target memory configuration scheme of each first CPU, and determining a plurality of memory slices corresponding to the memory area;

[0012] For each first CPU, the memory slice corresponding to the first CPU is partitioned according to the partitioning method of each sub-area in the target memory configuration scheme, the partitioned memory slices are obtained, and the partitioned memory slices are allocated to the corresponding first CPU; wherein the partitioning methods in the memory slices of each first CPU are not exactly the same.

[0013] According to a secure cloud platform memory allocation method provided by the present invention, the partitioning method includes the divided sub-area identifiers and the arrangement order between the sub-areas. The memory slices corresponding to the first CPU are partitioned according to the partitioning method of each sub-area in the target memory configuration scheme to obtain the partitioned memory slices, including:

[0014] According to the sub-area identifiers of each sub-area in the target memory configuration scheme, the memory slice corresponding to the first CPU is divided into a plurality of sub-areas having the same number as the sub-area identifiers;

[0015] The multiple sub-areas corresponding to the memory slice are sorted according to the arrangement order between the sub-areas to obtain the partitioned memory slice.

[0016] According to a secure cloud platform memory allocation method provided by the present invention, each sub-area of ​​the first CPU includes a partition memory management header, the partition memory management header includes memory management areas of different formats, the memory management area includes memory blocks, and the memory blocks in each memory management area are respectively used to store data of different byte sizes;

[0017] Each memory management area also includes a next memory block link pointer and a previous memory block link pointer. The next memory block link pointer is used to point to the next memory block of the current memory block, and the previous memory block link pointer is used to point to the previous memory block of the current memory block.

[0018] According to a secure cloud platform memory allocation method provided by the present invention, the discontinuity between the addresses of the memory slices allocated by the above-mentioned first CPUs includes at least one of the following: the addresses of the memory slices allocated by all the first CPUs are discontinuous, the addresses of the memory slices allocated by some of the first CPUs are discontinuous, and the addresses of multiple memory slices allocated by any first CPU are discontinuous.

[0019] According to a secure cloud platform memory allocation method provided by the present invention, the method further includes:

[0020] Acquire the operation requirement parameters of each second CPU in the second system, and determine the memory slice allocated to each second CPU according to the operation requirement parameters of each second CPU;

[0021] Among them, the above-mentioned second system and the first system are redundant systems, the addresses of the memory slices corresponding to the CPUs with the same identification in the first system and the second system are different, and / or the partitioning methods of the memory slices corresponding to the CPUs with the same identification in the first system and the second system are different.

[0022] According to a secure cloud platform memory allocation method provided by the present invention, the above-mentioned operation requirement parameters include the memory size required for operation, and the above-mentioned target memory configuration scheme corresponding to each first CPU is determined from multiple preset memory configuration schemes according to the operation requirement parameters of each first CPU, including:

[0023] According to the memory size required for the operation of each first CPU, determine a target memory configuration scheme matching the memory size required for the operation of each first CPU from multiple sets of memory configuration schemes;

[0024] Each set of memory configuration schemes includes a corresponding memory size, and the target memory configuration schemes corresponding to the first CPUs are not completely the same.

[0025] The present invention also provides a secure cloud platform memory allocation device, comprising the following modules:

[0026] An acquisition module, used for acquiring operation requirement parameters of each first central processing unit CPU in the first system;

[0027] A determination module, configured to determine a target memory configuration scheme corresponding to each first CPU from a plurality of preset memory configuration schemes according to the operation requirement parameters of each first CPU; the target memory configuration scheme includes the address of at least one memory slice allocated for the corresponding first CPU, the addresses of the memory slices included in each set of memory configuration schemes are not continuous, and different memory configuration schemes correspond to different operation requirement parameters;

[0028] The first memory allocation module is used to divide the preset memory area according to the addresses of the memory slices in the target memory configuration scheme of each first CPU, determine multiple memory slices corresponding to the memory area, and allocate them to the corresponding first CPU; wherein the addresses of the memory slices allocated to each first CPU are not continuous.

[0029] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, a secure cloud platform memory allocation method as described in any one of the above is implemented.

[0030] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the secure cloud platform memory allocation method as described in any one of the above.

[0031] The present invention also provides a computer program product, including a computer program, which, when executed by a processor, implements the secure cloud platform memory allocation method as described in any one of the above.

[0032] The memory allocation method, device, equipment and storage medium of the secure cloud platform provided by the present invention obtain the operation requirement parameters of each first CPU in the first system, and determine the target memory configuration scheme corresponding to each first CPU from multiple preset memory configuration schemes according to the operation requirement parameters of each first CPU, and then divide the preset memory area according to the address of the memory slice in the target memory configuration scheme of each first CPU, determine the multiple memory slices corresponding to the memory area and allocate them to the corresponding first CPU; wherein, the target memory configuration scheme includes the address of the memory slice divided for the corresponding first CPU and the address of the memory slice allocated to each first CPU is not continuous. In the technical scheme of the present invention, since the memory slices with discontinuous addresses can be allocated to each CPU through the target memory configuration scheme of each CPU, that is, the memory slices allocated to each CPU are discontinuous, the coupling degree between the memory slices of each CPU can be reduced, so that in the process of power-on self-test and periodic self-test of the memory, the problem of failure of one memory area leading to failure of all memory areas can be avoided, thereby improving the operation safety and reliability of the entire computer system. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 It is a schematic diagram of the architecture of a multi-core two-by-two secure computer system.

[0035] Figure 2 It is a schematic diagram of the hardware architecture of the logic computing module of the two-by-two secure computer platform.

[0036] Figure 3 It is a schematic diagram of the hardware architecture of the logic computing module of the multi-core two-by-two secure computer platform.

[0037] Figure 4 It is a schematic diagram of the logical operations running on the CPU.

[0038] Figure 5 This is a schematic diagram of the traditional multi-core CPU using SRAM.

[0039] Figure 6 It is a flowchart of a secure cloud platform memory allocation method provided in an embodiment of the present invention.

[0040] Figure 7 It is a schematic diagram of allocating and using memory chips by multi-core CPUs in a two-by-two-take-two computer system provided by an embodiment of the present invention.

[0041] Figure 8 It is a schematic diagram of the internal structure of each sub-area in the memory chip provided by an embodiment of the present invention.

[0042] Fig. 9 It is a structural diagram of a secure cloud platform memory allocation device provided in an embodiment of the present invention.

[0043] Fig.10 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] In order to facilitate understanding of the technical solution of the present invention, the relevant technical background of the embodiments of the present invention is first described below.

[0046] For a multi-core 2x2 secure computer system architecture, where the 2x2 secure computer system consists of two independent 2x2 architecture computer systems, see Figure 1The schematic diagram of the multi-core two-by-two-out-of-two secure computer system architecture shown in the figure shows that the two systems are redundant with each other. Two independent modules (including communication module, logic calculation module, security check module and synchronization verification and voting module) are integrated on each system. The two modules run synchronously and perform real-time comparison. Only when the two modules are consistent will the calculation results be output or transmitted to the outside. The two-out-of-two architecture can quickly detect system failures and ensure the system's safe output orientation (for example, the two systems can be switched through the inter-system switching module when a failure occurs). The two-by-two-out-of-two architecture combines the advantages of the two-out-of-two and dual-machine hot standby structures, including both the high security of the two-out-of-two and the high reliability of the dual-machine hot standby.

[0047] As a complex function control system, the safety platform mainly includes input, processing and output parts, and its characteristics are as follows: 1. It has extremely high security and availability. Even if a fault occurs, redundancy and other measures must be used to make the system work normally. 2. Failures can only occur in a predictable and safe way. 3. It has internal diagnostic functions, combining hardware and software to detect abnormal operations of the system itself; a series of special technologies are used to ensure the reliability of the software; redundant configuration, even if a component fails, it must maintain normal operation; any read and write operations through the digital communication port have very high security and reliability guarantees. Based on this, the safety platform can currently be built using a two-by-two safety computer system architecture.

[0048] The following is an explanation of a security platform (i.e., a security cloud platform) based on a two-by-two secure computer system.

[0049] 1. Hardware architecture of the logic computing module of the two-by-two secure computer platform.

[0050] See also Figure 2The hardware architecture diagram of the logic computing module of the two-by-two secure computer platform shown in the figure, the hardware architecture of the logic computing module of the typical secure computer platform may include: CPU (Central Processing Unit), SRAM (Static Random-Access Memory), NOR FLASH (Non-volatile Flash), FPGA (Field Programmable Gate Array), I / 0 processing, etc., which can realize the two-by-two design of a single logic computing module. Among them, CPU1 and CPU2 execute exactly the same program, and perform task synchronization periodically to keep the running pace consistent; SRAM is the main random access memory for logic operation data, and the data stored in it can be kept constant as long as it is powered on; NOR FLASH is a non-volatile flash memory technology used to store configuration files, data files, etc., for system initialization after power-on; FPGA performs periodic comparison of core status data (consistency of system operation data) and self-check and check of key information (such as self-check calculation data of memory); I / 0 processing performs input and output consistency control. At the same time, CPU1 and CPU2 and their ancillary equipment need to maintain physical independence, which is mainly achieved by electrical isolation in hardware design, including but not limited to the isolation voltage defined according to the requirements of EN 50124.1 between the following functional modules: ① between the safety function module and the non-safety function module; ② between two-out-of-two channels; ③ between different communication interfaces; ④ between the strong current and the internal circuit of the board; ⑤ between the chassis ground and the internal circuit of the board.

[0051] 2. Hardware architecture of logical computing module based on multi-core CPU computing core device.

[0052] See also Figure 3 The hardware architecture diagram of the logic computing module of the multi-core two-by-two secure computer platform is shown, where each system includes a 4-core CPU, namely physical CPU1-CPU4. Based on the multi-core CPU, there are multiple physical CPUs using the same SRAM, NOR FLASH, FPGA and I / O processing.

[0053] See also Figure 4 The schematic diagram of the logical operation content running on the CPU shown in the figure. Usually, a single CPU will run logical operation content such as security hardware, security firmware, security BSP (Board Support Package), security operating system, security protocol stack, security core processing layer software, and security application software.

[0054] To support the operation of the above logical operations, the same SRAM (for example, 4G) needs to be used. The traditional memory allocation mechanism is that multiple physical cores in a multi-core CPU use a complete and continuous SRAM memory chip, and a fixed and continuous address area can be allocated to a certain CPU. Figure 5 The schematic diagram of the traditional multi-core CPU using SRAM is shown. Generally, when allocating SRAM, a fixed area is usually used for different CPUs, that is, a continuous area is allocated in the memory for the corresponding CPU to use, and the memory allocated to each CPU is generally allocated continuously. This will lead to the following problems: 1. Key defects such as high coupling, low reliability, and low security; since multiple physical CPUs use the same SRAM, their inherent characteristics are consistent in the SRAM. If a continuous use method is used, during the power-on self-test and periodic self-test of the memory, the reliability will be reduced due to excessive coupling, which is not conducive to the overall security of the system. 2. The consistent use of a continuous section of SRAM by a single CPU (heap area, data area, code area, stack area, and other reserved areas) is not conducive to the principle of differentiated use and reduces the security of the entire system. 3. Two independent multi-core CPUs in a two-out-of-two mode use the same method of using memory slices, and there is a reduction in security due to the use of the same allocation method in both physical independence and software function independence. Based on this, an embodiment of the present invention provides a secure cloud platform memory allocation method, device, equipment and storage medium, which can solve this technical problem.

[0055] It should be noted that the executor of the embodiments of the present invention may be a secure cloud platform memory allocation device, or may be an electronic device including a secure cloud platform memory allocation device, or may be a two-by-two-out-of-two computer system or a two-by-two-out-of-two secure cloud platform including a secure cloud platform memory allocation device or an electronic device, or may be other systems or devices or platforms. The following embodiments will be described using electronic devices as examples.

[0056] Combine the following Figure 6-Figure 8 The present invention describes a method for allocating memory on a secure cloud platform according to an embodiment of the present invention.

[0057] Figure 6 It is a flowchart of the secure cloud platform memory allocation method provided by the present invention, such as Figure 6 As shown, the method comprises the following steps:

[0058] S102, obtaining operation requirement parameters of each first central processing unit CPU in the first system.

[0059] The first system may be any computer system in a two-by-two secure computer platform, and the computer system may be a multi-core system, that is, it may include multiple CPUs (Central Processing Units), all of which are referred to as first CPUs.

[0060] Specifically, each first CPU in the first system can be configured with tasks to be performed in advance, and corresponding operation requirement parameters can be set for each first CPU based on the tasks to be performed by each first CPU (for example, if the task amount of the task to be performed by the first CPU is small, a smaller memory size required for operation can be allocated; for example, if the task amount of the task to be performed by the first CPU is large, a larger memory size required for operation can be allocated). In this way, when the first system is powered on, multiple first CPUs in the first system simultaneously obtain power support, and multiple first CPUs are powered on, and then the operation requirement parameters of each first CPU can be obtained. Among them, the operation requirement parameters of the first CPU refer to the parameters and parameter values ​​required during the operation of the first CPU, and the operation requirement parameters may include the memory size required for operation, the bus type required for operation, etc., or may also include other operation requirement parameters, etc., which are not specifically limited here.

[0061] S104, determining a target memory configuration scheme corresponding to each first CPU from a plurality of preset memory configuration schemes according to the operation requirement parameters of each first CPU; the target memory configuration scheme includes the address of at least one memory slice allocated for the corresponding first CPU, the addresses of the memory slices included in each set of memory configuration schemes are not continuous, and different memory configuration schemes correspond to different operation requirement parameters.

[0062] In this step, multiple sets of different memory configuration schemes can be pre-set, and each set of memory configuration schemes can be set with a slicing method for the memory area (i.e., a method for dividing the memory area into memory slices), a partitioning method for the memory slice after slicing (i.e., a method for dividing the memory slice into various sub-areas), etc. The memory area refers to a preset memory area, for example, it can be a memory area corresponding to the SRAM of the first system. Optionally, the slicing method may include the address / address segment of the divided memory slice, the size of the divided memory slice, the number of divided memory slices, etc. The partitioning method may include the address / address segment of the divided sub-area, the size of the divided sub-area, the number of divided sub-areas, etc.; the sub-area here refers to the sub-area in the memory slice, for example, if a certain sub-area / sub-area is a data area, then the data running by the CPU can be stored in the data area.

[0063] Here, each set of memory configuration schemes may be associated with the operating requirement parameters of each CPU, or each set of memory configuration schemes may be associated with the operating requirement parameters of each CPU and the identification of each CPU, etc., that is, the operating requirement parameters corresponding to different memory configuration schemes may be different. In addition, the addresses of the memory slices included in each set of memory configuration schemes pre-set here are not continuous, which may include that the memory slices included in each set of memory configuration schemes are not continuous as a whole, or may also include that the addresses of multiple memory slices included in each set of memory configuration schemes are not continuous, or may also include other situations. The discontinuity between the addresses of the memory slices here refers to the fact that the end address of the previous memory slice and the beginning address of the next memory slice are not adjacent addresses, so that different memory configuration schemes can be set differently.

[0064] After obtaining the operation requirement parameters of each first CPU as described above, the memory configuration schemes that match the operation requirement parameters of each first CPU can be matched from each set of memory configuration schemes through the correlation between each set of memory configuration schemes and the operation requirement parameters of each CPU, or the memory configuration schemes that match both the operation requirement parameters and the identification of each first CPU can be matched from each set of memory configuration schemes through the correlation between each set of memory configuration schemes and the operation requirement parameters of each CPU and the identification of each CPU, or other methods can be used to obtain the memory configuration scheme corresponding to each first CPU. The memory configuration scheme obtained by matching each first CPU can be recorded as the target memory configuration scheme.

[0065] After determining the target memory configuration scheme of each first CPU, the address / address segment of the memory slice included in each target memory configuration scheme can also be obtained. It can be understood that the address / address segment of the memory slice included in each target memory configuration scheme is different, that is, the memory slice allocated to each first CPU is a different address area of ​​the memory area SRAM.

[0066] S106, dividing the preset memory area according to the addresses of the memory slices in the target memory configuration scheme of each first CPU, determining multiple memory slices corresponding to the memory area, and allocating them to the corresponding first CPUs; wherein the addresses of the memory slices allocated to each first CPU are not continuous.

[0067] In this step, after obtaining the target memory configuration scheme corresponding to each first CPU, the address / address segment of the memory slice allocated to each first CPU can be obtained, where the address / address segment of the memory slice is the address / address segment on the memory area, and then the corresponding memory slices can be divided on the memory area according to the address / address segment of these memory slices to obtain a plurality of divided memory slices. Then, the memory slices divided according to the address / address segment of the memory slice of each first CPU are correspondingly allocated to the corresponding first CPU.

[0068] It is understandable that each first CPU corresponds to at least one memory slice. If a first CPU corresponds to multiple memory slices, the target memory configuration scheme corresponding to the first CPU may include addresses / address segments of the multiple memory slices corresponding to the first CPU.

[0069] In addition, when allocating memory slices to each first CPU, the addresses / address segments of the memory slices allocated by each first CPU are discontinuous, that is, the memory slices are allocated to each first CPU in a discontinuous manner. Optionally, the discontinuity between the addresses of the memory slices allocated by each first CPU includes at least one of the following: the addresses of the memory slices allocated by all the first CPUs are discontinuous, the addresses of the memory slices allocated by some of the first CPUs are discontinuous, and the addresses of multiple memory slices allocated by any first CPU are discontinuous. That is to say, the discontinuity between the addresses / address segments of the memory slices allocated by each first CPU here may be that the addresses / address segments of the memory slices allocated by all the first CPUs are discontinuous, or the addresses / address segments of the memory slices allocated by some of the first CPUs are discontinuous (for example, the addresses / address segments of the memory slices allocated by two adjacent first CPUs are discontinuous), or the addresses / address segments of multiple memory slices allocated by a certain first CPU are discontinuous.

[0070] For example, see Figure 7 The schematic diagram of multi-core CPU allocation and use of memory chips in a two-by-two-take-two computer system is shown in FIG. Figure 7In the multi-core computer system above, after CPU1 is powered on, memory slice 3 is allocated to CPU1 for use, after CPU2 is powered on, memory slice 1 is allocated to CPU2 for use, after CPU3 is powered on, memory slice 5 and memory slice 6 are allocated to CPU3 for use, and after CPU4 is powered on, memory slice 2 and memory slice 4 are allocated to CPU4 for use. It can be seen that the two memory slices of CPU4 are discontinuous, and the address / address segment of the memory slice between CPU1 and CPU2 is discontinuous, the address / address segment of the memory slice between CPU2 and CPU3 is discontinuous, the address / address segment of the memory slice between CPU3 and CPU4 is discontinuous, and the address / address segment of the memory slice between CPU4 and CPU1 is discontinuous.

[0071] against Figure 7 In the multi-core computer system shown below, after CPU1 is powered on, memory slice 1 is allocated for use by CPU1, after CPU2 is powered on, memory slice 2 and memory slice 4 are allocated for use by CPU2, after CPU3 is powered on, memory slice 3 is allocated for use by CPU3, and after CPU4 is powered on, memory slice 5 and memory slice 6 are allocated for use by CPU4. It can be seen that the two memory slices of CPU2 are discontinuous, and the addresses / address segments of the memory slices between CPU2 and CPU3 are discontinuous, and the addresses / address segments of the memory slices between CPU3 and CPU4 are discontinuous.

[0072] It can be seen from the above example that by allocating memory slices to each first CPU in a non-continuous manner, the problem of continuous allocation of memory slices causing one memory slice to fail and causing all other memory slices to fail, resulting in reduced security of the entire computer system, can be avoided. This allows differentiated allocation of memory slices to each first CPU, thereby improving the security and reliability of the entire computer system.

[0073] In this embodiment, by obtaining the operation requirement parameters of each first CPU in the first system, and determining the target memory configuration scheme corresponding to each first CPU from the preset multiple memory configuration schemes according to the operation requirement parameters of each first CPU, the preset memory area is divided according to the address of the memory slice in the target memory configuration scheme of each first CPU, and multiple memory slices corresponding to the memory area are determined and allocated to the corresponding first CPU; wherein, the target memory configuration scheme includes the address of the memory slice divided for the corresponding first CPU and the address of the memory slice allocated to each first CPU is not continuous. In the technical scheme of the present invention, since the memory slices with discontinuous addresses can be allocated to each CPU through the target memory configuration scheme of each CPU, that is, the memory slices allocated to each CPU are not continuous, the coupling degree between the memory slices of each CPU can be reduced, so that during the memory power-on self-test and periodic self-test process, the problem of a memory area failure causing all memory areas to fail can be avoided, thereby improving the operation safety and reliability of the entire computer system.

[0074] The following embodiment describes the specific process of dividing the memory area SRAM.

[0075] In one embodiment, the target memory configuration scheme of the first CPU includes a partitioning method of each sub-area in the memory slice, and the S106 may include the following steps:

[0076] Step A1, dividing a preset memory area according to the addresses of the memory slices in the target memory configuration scheme of each first CPU, and determining a plurality of memory slices corresponding to the memory area.

[0077] In this step, after obtaining the addresses / address segments of the memory slices corresponding to each first CPU, corresponding memory slices can be divided according to these addresses / address segments on the memory area SRAM to obtain multiple memory slices divided on the memory area.

[0078] Here, each first CPU may correspond to one memory slice, or one CPU may correspond to multiple memory slices.

[0079] After the memory slices corresponding to the first CPUs are divided in the memory area SRAM, the memory slices of each first CPU may be further divided into sub-areas. The process of dividing the memory slices into sub-areas is described below.

[0080] Step A2, for each first CPU, partition the memory slice corresponding to the first CPU according to the partitioning method of each sub-area in the target memory configuration scheme, obtain the partitioned memory slices, and allocate the partitioned memory slices to the corresponding first CPU; wherein the partitioning methods in the memory slices of each first CPU are not exactly the same.

[0081] The partitioning method of each sub-area in the memory slice may include the identifier of the memory slice, the number of divided sub-areas, the identifier of the divided sub-areas, the sub-area size corresponding to each sub-area (i.e., the memory size corresponding to the sub-area), the arrangement order between the sub-areas, etc. The identifier of the memory slice is used to distinguish which memory slice it is, such as memory slice 1, memory slice 2, etc. The identifier of the memory slice may be the address of the corresponding memory slice, or may also be the number of the corresponding memory slice, etc. The identifier of the divided sub-area may be the name of the divided sub-area in the memory slice (such as the data area, the stack area, etc.) or the address of the divided sub-area, etc.

[0082] The partitioning method of the memory slice of each first CPU can be pre-set in its corresponding target memory configuration scheme. In addition, the partitioning method in the memory slices of each first CPU is not completely the same, and at least one of the following contents of the memory slices of each first CPU is not completely the same: the number of divided sub-areas, the sub-area identifier, the memory size of each sub-area, and the arrangement order between each sub-area. For example, the sub-areas include heap area, data area, code area, stack area and reserved area. Assuming that the memory slice of CPU1 and the memory slice of CPU2 both include three sub-areas, that is, the number of sub-areas divided into these two memory slices is the same, wherein the memory slice of CPU1 can include heap area, data area and code area, and the memory slice of CPU2 can include code area, stack area and reserved area. It can be seen that the sub-area identifiers included in the memory slices of the two CPUs are not completely the same.

[0083] In the case where the same first CPU has multiple memory slices, the partitioning modes among the multiple memory slices corresponding to the first CPU may be the same, may not be completely the same, or may be completely different.

[0084] Specifically, the corresponding memory slices can be partitioned according to the partitioning method in the target memory configuration scheme of each first CPU. After the memory slices of each first CPU are partitioned, the partitioned memory slices of each first CPU can be allocated to the corresponding first CPU. Subsequently, each first CPU can use each partition or memory slice according to the partitioning method in its memory slice.

[0085] For example, see Figure 7 The schematic diagram shown in FIG. Figure 7In the multi-core computer system located above, CPU1 divides the address of memory chip 3 into: reserved area, stack area, code area, data area, heap area; CPU2 divides the address of memory chip 1 into: heap area, data area, code area, stack area, reserved area; CPU3 divides the addresses of memory chips 5 and 6 into: heap area (memory chip 5), data area (memory chip 5), code area (memory chip 6), stack area (memory chip 6), reserved area (memory chip 6); CPU4 divides the addresses of memory chips 2 and 4 into: heap area (memory chip 2), data area (memory chip 2), code area (memory chip 4), stack area (memory chip 4), reserved area (memory chip 4).

[0086] against Figure 7 In the multi-core computer system located below, CPU1 divides the address of memory chip 1 into: heap area, data area, code area, stack area, reserved area; CPU2 divides the address of memory chips 2 and 4 into: heap area (memory chip 2), data area (memory chip 2), code area (memory chip 4), stack area (memory chip 4), reserved area (memory chip 4); CPU3 divides the address of memory chip 3 into: reserved area, stack area, code area, data area, heap area; CPU4 divides the address of memory chips 5 and 6 into: heap area (memory chip 5), data area (memory chip 5), code area (memory chip 6), stack area (memory chip 6), reserved area (memory chip 6).

[0087] Through the above-mentioned partitioning and allocation of memory slices, it can be known that for different first CPUs, the partitioning methods corresponding to their memory slices are not exactly the same, so the subsequent usage methods of each first CPU when using each memory slice are also not exactly the same. This can avoid the problem of reduced security of the entire computer system caused by a single CPU using a continuous segment of memory slices (also called a segment of SRAM) in the same way (for example, using them in the same way as heap area, data area, code area, stack area, and reserved area), thereby further improving the security and reliability of the computer system.

[0088] In this embodiment, the memory area is first divided into memory slices, and then the divided memory slices are divided into sub-areas according to different partitioning methods and allocated to each first CPU for use. In this way, the subsequent usage of each memory slice by each first CPU is not exactly the same, thereby avoiding the problem of reduced security of the entire computer system caused by a single CPU using a continuous section of memory slices in a consistent manner, thereby further improving the security and reliability of the computer system.

[0089] Furthermore, the following embodiments illustrate a specific process of dividing the internal part of the divided memory slice into sub-partitions according to different partitioning methods.

[0090] In one embodiment, as mentioned above, the partitioning method includes the identification of the divided sub-areas and the arrangement order between the sub-areas. The step of "partitioning the memory slice corresponding to the first CPU according to the partitioning method of each sub-area in the target memory configuration scheme to obtain the partitioned memory slice" in the above step A2 may include the following steps:

[0091] Step A21, according to the sub-area identifier of each sub-area in the target memory configuration scheme, divide the memory slice corresponding to the first CPU into a plurality of sub-areas having the same number as the sub-area identifier.

[0092] In this step, for the memory slice of each first CPU, after obtaining the sub-region identifier of each sub-region in the memory slice of each first CPU, the sub-region size of each sub-region in the memory slice of each first CPU can also be obtained, and then according to the number of sub-region identifiers and the sub-region sizes corresponding to the sub-region identifiers, the memory slice of the first CPU can be divided into multiple sub-regions whose number is equal to the sub-region identifiers and matches the sub-region sizes.

[0093] Step A22, sorting the multiple sub-areas corresponding to the memory slice according to the arrangement order between the sub-areas to obtain the partitioned memory slice.

[0094] In this step, for each memory slice of the first CPU, after obtaining a plurality of sub-areas divided into the memory slice of the first CPU, the sub-areas can be arranged in order according to the arrangement order of the sub-areas in the memory slice to obtain the partitioned memory slice.

[0095] Further, after the memory slice of each first CPU is divided into sub-areas, a partition memory management header for each sub-area can be established, see Figure 8 The schematic diagram of the internal structure of each sub-area in the memory slice shown, optionally, each sub-area of ​​the above-mentioned first CPU includes a partition memory management header, and the partition memory management header includes memory management areas of different formats, for example, it can include 32, 64, 128, 256 and other 2-power memory management areas, and these memory management areas can store data of different formats. The above-mentioned memory management area includes memory blocks, and the memory blocks in each memory management area are respectively used to store data of different byte sizes; each memory management area also includes a next memory block link pointer and a previous memory link pointer, the next memory block link pointer is used to point to the next memory block of the current memory block, and the previous memory block link pointer is used to point to the previous memory block of the current memory block. Of course, the above-mentioned memory management area can also include a memory block information pointer, which is used to point to the information in the memory block.

[0096] Specifically, different storage areas in the above-mentioned memory management area can point to the memory block management header, and each memory block management header can include the number of used blocks, the used memory block link pointer, the number of free memory blocks, the free memory block link pointer, the number of memory blocks that have undergone periodic self-checking, the memory block link pointer that has undergone periodic self-checking, and the mutex lock, etc. Among them, the number of used blocks refers to the number of memory blocks currently used by the corresponding first CPU; the used memory block link pointer points to the first used memory block information; the number of free memory blocks refers to the number of memory blocks currently free of the corresponding first CPU; the free memory block link pointer points to the first free memory block information in the current partition memory management header; the memory block link pointer that has undergone periodic self-checking points to the last memory block information that has completed periodic self-checking.

[0097] Afterwards, a memory block information header can be established for each memory block, which may include: a next memory link pointer and a previous memory block link pointer, a memory block usage status, a memory block size information, a memory block self-test status, and a memory block physical pointer. Among them, the next memory block link pointer is used to point to the next memory block of the current memory block, and the previous memory block link pointer is used to point to the previous memory block of the current memory block. In this way, a memory block bidirectional search linked list can be established, which is convenient for implementing searches in different directions or bidirectional searches according to the needs of different users; the memory block usage status indicates whether the memory block has been used; the memory block size information indicates that the memory block information header is a certain type of memory management partition (for example: 32, 64, 128, etc.); the memory block self-test status indicates whether the memory block has completed self-test; the memory block physical pointer points to the starting address of a certain memory segment in the actual memory area.

[0098] By dividing the memory area into memory slices, then dividing the memory slices into sub-areas, and establishing partition memory management headers and memory block information headers for the sub-areas, the memory allocation in the entire target memory configuration scheme for each first CPU can be completed, that is, the corresponding memory is divided and allocated in the SRAM for each first CPU according to the target memory configuration scheme.

[0099] In this embodiment, by dividing each memory slice into multiple sub-areas according to the sub-area identifier and the arrangement order of each sub-area, the process is simple and intuitive, so the efficiency and accuracy of partitioning each memory slice can be improved, thereby improving the efficiency and accuracy of the entire memory allocation. In addition, each sub-area of ​​each memory slice includes a link pointer with a two-way search function, which can facilitate the implementation of searches in different directions or two-way searches according to the needs of different users, thereby improving the flexibility of memory allocation or memory configuration.

[0100] The following embodiment describes the process of determining memory slices allocated to different systems according to system operation requirement parameters.

[0101] In one embodiment, the above method may further include the following steps:

[0102] Step B: acquiring the operation requirement parameters of each second CPU in the second system, and determining the memory slice allocated to each second CPU according to the operation requirement parameters of each second CPU.

[0103] The second system and the first system are mutually redundant systems, that is, the architectures of the first system and the second system are exactly the same. When a failure occurs in either the first system or the second system, the system can be switched to the other system in time to ensure normal execution of the business.

[0104] The second system may also include multiple CPUs, all of which are recorded as second CPUs. The number of second CPUs included in the second system is the same as the number of first CPUs included in the first system. The operation requirement parameters of the second CPU refer to the parameters and parameter values ​​required during the operation of the second CPU. The operation requirement parameters may include the memory size required for operation, the bus type required for operation, etc., or may include other operation requirement parameters, etc., which are not specifically limited here.

[0105] The method for obtaining the operation requirement parameters of each second CPU may be the same as the method for obtaining the operation requirement parameters of each first CPU, and will not be described in detail here.

[0106] In addition, after obtaining the operating requirement parameters of each second CPU, a matching target memory configuration scheme can also be determined for each second CPU from multiple preset memory configuration schemes, and corresponding memory slices can be divided for each second CPU based on the addresses of the memory slices in the target memory configuration scheme of each second CPU, and the divided memory slices can be partitioned according to the partitioning method in the target memory configuration scheme of each second CPU. The specific process of dividing the memory slices and partitioning the memory slices can be referred to the above-mentioned process of dividing the memory slices and partitioning the memory slices for the first CPU, which will not be repeated here.

[0107] As a further optional embodiment, the addresses of the memory slices corresponding to the CPUs with the same identification in the first system and the second system are different, and / or the partitioning methods of the memory slices corresponding to the CPUs with the same identification in the first system and the second system are different.

[0108] That is to say, when the second system and the first system are divided into memory slices, the addresses / address segments of the memory slices divided by the CPUs with the same identification in the two systems are different, and the difference here can be that the addresses / address segments of the divided memory slices are completely different or partially different. In addition, when the CPUs with the same identification in the first system and the second system are divided into sub-areas, the partitioning methods corresponding to the two CPUs with the same identification are also different, and the difference in the partitioning methods here can be that at least one of the following contents of the memory slices of the two CPUs with the same identification is not completely the same: the number of divided sub-areas, the sub-area identification, the memory size of each sub-area, and the arrangement order between the sub-areas.

[0109] For example, see Figure 7 The schematic diagram of memory slice allocation and use shown in the figure shows that for CPUs with the same identification in two systems, for example, for CPU1, the two CPU1s can use different slicing and partitioning methods (i.e., partitioning methods). The memory slice corresponding to the CPU1 in the upper computer system is memory slice 3, and its address of the memory slice is divided into: reserved area, stack area, code area, data area, and heap area. The memory slice corresponding to the CPU1 in the lower computer system is memory slice 1, and its address of the memory slice is divided into: heap area, data area, code area, stack area, and reserved area. It can be seen that the addresses of the memory slices corresponding to the CPU1 of the two systems are different (different memory slice numbers correspond to memory slices with different addresses), and the partitioning methods of each sub-area in the two CPU1s are also different. The situation is similar for other CPUs with the same identification.

[0110] It can be seen that for the two systems constituting a single logical operation system, the addresses of the memory slices in the CPUs with the same identification of the two systems and the partitioning methods in the memory slices are different, that is, there are differences in memory slicing and differences in address division (or sub-division) within the memory slices in the two CPUs with the same identification. This can solve the problem of reduced security in both physical independence and software functional independence of the two systems due to the use of the same memory allocation method, thereby further improving the operating security and reliability of the computer system.

[0111] In this embodiment, for CPUs with the same identification in two systems, different memory slices can be allocated or different partitioning methods can be used in the memory slices. In this way, there are differences in memory slices and address divisions within the memory slices in the two CPUs with the same identification, so that differentiated use of memory by the two CPUs with the same identification can be achieved, so that when one CPU fails, the CPU with the corresponding identification in the other system will not fail, thereby further improving the operating safety and reliability of the computer system.

[0112] The following embodiment describes a specific process of determining a target memory configuration solution corresponding to a CPU through CPU operation requirement parameters.

[0113] In one embodiment, the operation requirement parameters of the first CPU include the memory size required for operation, and the S104 may include the following steps:

[0114] Step C: according to the memory size required for the operation of each first CPU, determine a target memory configuration scheme that matches the memory size required for the operation of each first CPU from multiple sets of memory configuration schemes.

[0115] Each set of memory configuration schemes includes a corresponding memory size, and the target memory configuration schemes corresponding to the first CPUs are not completely the same.

[0116] In this step, when setting multiple sets of memory configuration schemes in advance, different memory configuration schemes can be set according to different memory sizes, that is, the size of the memory allocated corresponding to each set of memory configuration schemes can be different; at the same time, different partitioning methods can be set in each set of memory schemes, so that the sub-areas within the memory chip can be divided into different partitioning methods for the corresponding CPU in the subsequent partitioning.

[0117] Specifically, after obtaining the memory size required for the operation of each first CPU, a target memory configuration scheme that matches the memory size required for the operation can be found in the preset multiple memory configuration schemes. The target memory configuration schemes of each first CPU are not completely the same. The inconsistency here can be that the addresses / address segments of the divided memory slices are different, or the partitioning methods of dividing sub-areas in the memory slices are not completely the same. For example, CPU1 and CPU3 can adopt the same partitioning method, while CPU1 and CPU2 or CPU4 adopt different partitioning methods.

[0118] The method for each second CPU in the second system to determine the target memory configuration scheme can also be the same as the method for each first CPU in the first system to determine the target memory configuration scheme, that is, it is determined according to the memory size required for the operation of each second CPU, and the specific process will not be repeated here. Similarly, the target memory configuration schemes corresponding to each second CPU are not completely the same.

[0119] In this embodiment, a target memory configuration scheme that matches the memory size required for the operation of each CPU is determined. The target memory configuration scheme determined in this way and the memory size therein can meet the actual operation requirements of the corresponding CPU, thereby ensuring the normal operation of each CPU and further improving the security of the operation of the computer system.

[0120] Furthermore, the memory allocation method of the secure cloud platform of the embodiment of the present invention can be applied to any scenario that requires memory allocation. The following takes the real-time fault detection scenario or the SRAM failure detection scenario as an example to illustrate the specific memory allocation and use process in the two-by-two secure computer platform. Real-time fault detection is also called online self-test, and its purpose is to detect random hardware failures in a timely manner. SRAM failure detection is also an important detection part of the secure computer platform.

[0121] The following is a specific memory allocation and usage process in the two-by-two secure computer platform, which may include the following steps:

[0122] Step 1: The system is powered on. The two physically isolated multi-core CPUs that form a two-out-of-two configuration obtain power support at the same time, and the system is powered on.

[0123] Step 2: (1) Memory configuration, optimized according to the TLSF (Two-Level Segregated Fit memory allocator) algorithm to achieve differentiated memory allocation. First, set up the local link script, set up eight sets of configuration scripts for different segments (heap area, stack area, data area, code area, reserved area), corresponding to the different configuration schemes in the two 4-core CPUs, and complete the layout of each part of the program's executable file in the memory address space. Secondly, according to the linker provided by the real-time operating system, use the above link script to merge the configuration schemes and output them into a loadable executable file.

[0124] (2) Memory allocation. The first step is to divide the memory into heap area, data area, code area, stack area and reserved area according to the memory configuration plan. The second step is to establish a partition memory management header based on the divided memory area to store 32, 64, 128, 256 and other 2n-power memory management areas. The third step is that different storage areas of the memory management area point to the memory block management header. Each memory block management header includes the number of used blocks, the used memory block link pointer, the number of free memory blocks, the free memory block link pointer, the number of cycled self-checked memory blocks, the cycled self-checked memory block link pointer and the mutex lock. The used memory block link pointer points to the first used memory block information, and the free memory block link pointer points to the first free memory block in the current partition memory management. Information, the cycle self-checked memory block link pointer points to the last memory block information that has completed the cycle self-check; the fourth step is to establish each memory block information header, including: the next memory link pointer and the previous memory block link, memory block usage status, memory block size information, memory block self-check status identification, memory block physical pointer, including the next memory link pointer and the previous memory block link pointer are used to establish a memory block bidirectional search linked list, the memory block usage status indicates whether the memory block has been used, the memory block size information indicates that the information header block is a certain type of memory management partition (for example: 32, 64, 128, etc.), the memory block self-check status identifies whether the memory block has been prepared for self-checking, and the memory block physical pointer points to the starting address of a certain memory segment in the actual memory area. Through the above four steps, the memory allocation of the entire memory configuration scheme is completed.

[0125] Step 3: System self-check: After memory allocation, all CPUs and memory chips in the two-out-of-two physically isolated multi-core CPU are self-checked. After the self-check passes, the system starts running. If the self-check fails, the system crashes.

[0126] Step 4: System initialization: Initialize the system by loading the configuration file and data file in NOR FLASH.

[0127] Step 5: Cyclic operation,After the initialization is completed, the system enters the cyclic operation state, and a single system consisting of two-out-of-two pairs (consisting of CPU1 and CPU1 in the two multi-core CPUs) performs logical operations.

[0128] Step 6: Periodic voting: a single system that forms a two-out-of-two structure (such as CPU1 and CPU1 in two multi-core CPUs) performs periodic voting on input data, operation status data, and output data. The output data of the periodic operation is transmitted to the FPGA (Field Programmable Gate Array). The two FPGAs that form the two-out-of-two structure exchange data and compare the consistency of the data received by the two CPUs in the two-out-of-two structure, the logical operation data, and the output data. If the comparison results are inconsistent, the system will be shut down.

[0129] Step 7: Periodic self-check: The system periodically performs self-check on all CPUs and memory chips in the two-out-of-two physically isolated multi-core CPU. The system can continue to run only after the self-check passes. If the self-check fails, the system crashes.

[0130] It can be seen from the above description that in the embodiment of the present invention, by allocating different memory slice addresses to different CPUs in the same system and using different partitioning methods in each memory slice, the problem of reduced security caused by continuous allocation of memory slices to each CPU and the same use method is avoided, and differentiated configuration, allocation and use of memory areas in SRAM are achieved; at the same time, by designing different memory slice addresses and / or different partitioning methods within memory slices for CPUs with the same identification in different systems, the physical independence principle and software function independence principle of a two-by-two-out-of-two secure computer system are effectively achieved. In short, the above-mentioned differentiated memory slicing and memory area (i.e., sub-area) division method within the slicing address improves the reliability and security of the overall system and enhances the robustness of the system.

[0131] The secure cloud platform memory allocation device provided by the present invention is described below. The secure cloud platform memory allocation device described below and the secure cloud platform memory allocation method described above can be referenced to each other.

[0132] Fig. 9 is a schematic diagram of the structure of a secure cloud platform memory allocation device provided by an embodiment of the present invention, see Fig. 9 As shown, the device may include the following modules:

[0133] An acquisition module 210 is used to acquire the operation requirement parameters of each first central processing unit CPU in the first system;

[0134] The determination module 220 is used to determine a target memory configuration scheme corresponding to each first CPU from a plurality of preset memory configuration schemes according to the operation requirement parameters of each first CPU; the target memory configuration scheme includes the address of at least one memory slice allocated for the corresponding first CPU, the addresses of the memory slices included in each set of memory configuration schemes are not continuous, and different memory configuration schemes correspond to different operation requirement parameters;

[0135] The first memory allocation module 230 is used to divide the preset memory area according to the addresses of the memory slices in the target memory configuration scheme of each first CPU, determine multiple memory slices corresponding to the memory area, and allocate them to the corresponding first CPU; wherein the addresses of the memory slices allocated to each first CPU are not continuous.

[0136] In one embodiment, the target memory configuration scheme of the first CPU includes a partitioning method of each sub-area in the memory slice. The first memory allocation module 230 is specifically used to divide the preset memory area according to the address of the memory slice in the target memory configuration scheme of each first CPU, and determine multiple memory slices corresponding to the memory area; for each first CPU, the memory slice corresponding to the first CPU is partitioned according to the partitioning method of each sub-area in the target memory configuration scheme, the partitioned memory slice is obtained, and the partitioned memory slice is allocated to the corresponding first CPU; wherein the partitioning method in the memory slice of each first CPU is not exactly the same.

[0137] In one embodiment, the partitioning method includes the identification of the divided sub-regions and the arrangement order between the sub-regions. The first memory allocation module 230 is specifically used to divide the memory slice corresponding to the first CPU into a plurality of sub-regions with the same number of sub-region identifications according to the sub-region identifications of each sub-region in the target memory configuration scheme; sort the plurality of sub-regions corresponding to the memory slice according to the arrangement order between the sub-regions to obtain the partitioned memory slices.

[0138] In one embodiment, each sub-area of ​​the first CPU includes a partition memory management header, the partition memory management header includes memory management areas of different formats, the memory management areas include memory blocks, and the memory blocks in each memory management area are respectively used to store data of different byte sizes; each memory management area also includes a next memory block link pointer and a previous memory link pointer, the next memory block link pointer is used to point to the next memory block of the current memory block, and the previous memory block link pointer is used to point to the previous memory block of the current memory block.

[0139] In one embodiment, the discontinuity between the addresses of the memory slices allocated by the above-mentioned first CPUs includes at least one of the following: the addresses of the memory slices allocated by all the first CPUs are discontinuous, the addresses of the memory slices allocated by some of the first CPUs are discontinuous, and the addresses of multiple memory slices allocated by any first CPU are discontinuous.

[0140] In one embodiment, the above-mentioned device also includes: a second memory allocation module, which is used to obtain the operating requirement parameters of each second CPU in the second system, and determine the memory slices allocated to each second CPU according to the operating requirement parameters of each second CPU; wherein the above-mentioned second system and the first system are redundant systems, and the addresses of the memory slices corresponding to the CPUs with the same identification in the first system and the second system are different, and / or the partitioning methods of the memory slices corresponding to the CPUs with the same identification in the first system and the second system are different.

[0141] In one embodiment, the above-mentioned operation requirement parameters include the memory size required for operation, and the above-mentioned determination module 220 is specifically used to determine, according to the memory size required for operation of each first CPU, a target memory configuration scheme that matches the respective memory size required for operation from multiple sets of memory configuration schemes; wherein each set of memory configuration schemes includes a corresponding memory size, and the target memory configuration schemes corresponding to the first CPUs are not exactly the same.

[0142] It should be noted here that the above-mentioned device provided in the embodiment of the present invention can implement all the method steps implemented in the above-mentioned method embodiment, and can achieve the same technical effect. The parts and beneficial effects that are the same as the method embodiment in this embodiment will not be described in detail here.

[0143] Fig.10 An example of a physical structure diagram of an electronic device is shown in FIG. Fig.10As shown, the electronic device may include: a processor 310, a communication interface 320, a memory 330 and a communication bus 340, wherein the processor 310, the communication interface 320 and the memory 330 communicate with each other through the communication bus 340. The processor 310 may call the logic instructions in the memory 330 to execute the memory allocation method of the security cloud platform, the method comprising: obtaining the operation requirement parameters of each first central processing unit CPU in the first system; determining the target memory configuration scheme corresponding to each first CPU from a plurality of preset memory configuration schemes according to the operation requirement parameters of each first CPU; the target memory configuration scheme includes the address of at least one memory slice divided for the corresponding first CPU, the addresses of the memory slices included in each set of memory configuration schemes are not continuous, and different memory configuration schemes correspond to different operation requirement parameters; dividing the preset memory area according to the addresses of the memory slices in the target memory configuration schemes of each first CPU, determining a plurality of memory slices corresponding to the memory area, and allocating them to the corresponding first CPU; wherein the addresses of the memory slices allocated to each first CPU are not continuous.

[0144] In addition, the logic instructions in the above-mentioned memory 330 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0145] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the security cloud platform memory allocation method provided by the above methods, and the method includes: obtaining the operating requirement parameters of each first central processing unit CPU in the first system; determining the target memory configuration scheme corresponding to each first CPU from a preset multiple sets of memory configuration schemes according to the operating requirement parameters of each first CPU; the above target memory configuration scheme includes the address of at least one memory slice allocated for the corresponding first CPU, the addresses of the memory slices included in each set of memory configuration schemes are not continuous, and different memory configuration schemes correspond to different operating requirement parameters; the preset memory area is divided according to the addresses of the memory slices in the target memory configuration scheme of each first CPU, and multiple memory slices corresponding to the memory area are determined, and allocated to the corresponding first CPU; wherein the addresses of the memory slices allocated to each first CPU are not continuous.

[0146] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the security cloud platform memory allocation method provided by the above-mentioned methods, the method comprising: obtaining operation requirement parameters of each first central processing unit CPU in the first system; determining a target memory configuration scheme corresponding to each first CPU from a preset plurality of memory configuration schemes according to the operation requirement parameters of each first CPU; the above-mentioned target memory configuration scheme includes the address of at least one memory slice allocated for the corresponding first CPU, the addresses of the memory slices included in each set of memory configuration schemes are not continuous, and different memory configuration schemes correspond to different operation requirement parameters; the preset memory area is divided according to the addresses of the memory slices in the target memory configuration scheme of each first CPU, a plurality of memory slices corresponding to the memory area are determined, and allocated to the corresponding first CPU; wherein the addresses of the memory slices allocated to each first CPU are not continuous.

[0147] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0148] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0149] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A secure cloud platform memory allocation method, characterized in that: include: Obtaining the operation requirement parameters of each first central processing unit CPU in the first system; Determining a target memory configuration scheme corresponding to each of the first CPUs from a plurality of preset memory configuration schemes according to the operation requirement parameters of each of the first CPUs; The target memory configuration scheme includes the address of at least one memory slice allocated for the corresponding first CPU, the addresses of the memory slices included in each set of memory configuration schemes are not continuous, and different memory configuration schemes correspond to different operation requirement parameters; wherein the addresses of the memory slices allocated to each first CPU are not continuous, and the target memory configuration scheme of the first CPU includes the partitioning method of each sub-area in the memory slice, and the partitioning method includes the identification of the divided sub-area and the arrangement order between the sub-areas; Dividing a preset memory area according to the addresses of the memory slices in the target memory configuration scheme of each of the first CPUs, and determining a plurality of memory slices corresponding to the memory area; For each of the first CPUs, according to the sub-area identifiers of each sub-area in the target memory configuration scheme, the memory slice corresponding to the first CPU is divided into a plurality of sub-areas whose number is the same as the sub-area identifiers; the plurality of sub-areas corresponding to the memory slice are sorted according to the arrangement order between the sub-areas to obtain the partitioned memory slices, and the partitioned memory slices are allocated to the corresponding first CPU; wherein the partitioning methods in the memory slices of the first CPUs are not exactly the same; at least one of the following contents of the memory slices of the first CPUs is not exactly the same: the number of divided sub-areas, the sub-area identifiers, the memory size of each sub-area, and the arrangement order between the sub-areas.

2. The secure cloud platform memory allocation method according to claim 1, characterized in that: Each sub-area of ​​the first CPU includes a partition memory management header, the partition memory management header includes memory management areas of different formats, the memory management areas include memory blocks, and the memory blocks in each memory management area are respectively used to store data of different byte sizes; Each of the memory management areas also includes a next memory block link pointer and a previous memory block link pointer. The next memory block link pointer is used to point to the next memory block of the current memory block, and the previous memory block link pointer is used to point to the previous memory block of the current memory block.

3. The secure cloud platform memory allocation method according to claim 1, characterized in that: The addresses of the memory slices allocated by the first CPUs are not continuous, which includes at least one of the following: the addresses of the memory slices allocated by all the first CPUs are not continuous, and the addresses of the memory slices allocated by some of the first CPUs are not continuous; The addresses of the memory slices allocated by the first CPUs are not continuous, which further includes: the addresses of the multiple memory slices allocated by any one of the first CPUs are not continuous.

4. The secure cloud platform memory allocation method according to claim 1, characterized in that: The method further comprises: Acquire the operation requirement parameters of each second CPU in the second system, and determine the memory slice allocated to each second CPU according to the operation requirement parameters of each second CPU; Among them, the second system and the first system are redundant systems, the addresses of the memory slices corresponding to the CPUs with the same identification in the first system and the second system are different, and / or the partitioning methods of the memory slices corresponding to the CPUs with the same identification in the first system and the second system are different.

5. The secure cloud platform memory allocation method according to claim 1, characterized in that: The operation requirement parameters include the memory size required for operation, and determining the target memory configuration scheme corresponding to each of the first CPUs from a plurality of preset memory configuration schemes according to the operation requirement parameters of each of the first CPUs includes: According to the memory size required for the operation of each of the first CPUs, determining a target memory configuration scheme that matches the memory size required for the operation of each of the first CPUs from the multiple sets of memory configuration schemes; Each set of the memory configuration schemes includes a corresponding memory size, and the target memory configuration schemes corresponding to the first CPUs are not completely the same.

6. A secure cloud platform memory allocation device, characterized in that: include: An acquisition module, used for acquiring operation requirement parameters of each first central processing unit CPU in the first system; A determination module, configured to determine a target memory configuration scheme corresponding to each of the first CPUs from a plurality of preset memory configuration schemes according to an operation requirement parameter of each of the first CPUs; The target memory configuration scheme includes the address of at least one memory slice allocated for the corresponding first CPU, the addresses of the memory slices included in each set of memory configuration schemes are not continuous, and different memory configuration schemes correspond to different operation requirement parameters; wherein the addresses of the memory slices allocated to each first CPU are not continuous, and the target memory configuration scheme of the first CPU includes the partitioning method of each sub-area in the memory slice, and the partitioning method includes the identification of the divided sub-area and the arrangement order between the sub-areas; The first memory allocation module is used to divide the preset memory area according to the addresses of the memory slices in the target memory configuration scheme of each of the first CPUs, and determine the multiple memory slices corresponding to the memory area; for each of the first CPUs, according to the sub-area identifiers of each sub-area in the target memory configuration scheme, divide the memory slice corresponding to the first CPU into a plurality of sub-areas with the same number as the sub-area identifiers; sort the multiple sub-areas corresponding to the memory slices according to the arrangement order between the sub-areas, obtain the partitioned memory slices, and allocate the partitioned memory slices to the corresponding first CPU; wherein the partitioning methods in the memory slices of each of the first CPUs are not exactly the same; at least one of the following contents of the memory slices of each of the first CPUs is not exactly the same: the number of divided sub-areas, the sub-area identifiers, the memory size of each sub-area, and the arrangement order between the sub-areas.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the secure cloud platform memory allocation method as described in any one of claims 1 to 5 is implemented.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the secure cloud platform memory allocation method as described in any one of claims 1 to 5 is implemented.

9. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the secure cloud platform memory allocation method as described in any one of claims 1 to 5 is implemented.

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