Semiconductor structure and method for manufacturing the same

Abstract

An embodiment of the present disclosure provides a semiconductor structure and a preparation method thereof, the manufacturing method of the semiconductor structure comprising: sequentially forming a second stacked structure and a first stacked structure on a substrate; wherein the first stacked structure comprises a first sacrificial layer and a first supporting layer stacked in sequence; forming a first initial hole penetrating the first supporting layer and the first sacrificial layer; laterally etching the first sacrificial layer along the first initial hole to enlarge the aperture of a portion of the first initial hole; wherein the first initial hole after the aperture is enlarged constitutes a first through hole; forming a first conductive layer on the surface of the first through hole; etching the first conductive layer and the second stacked structure on the bottom surface of the first through hole in sequence along the first through hole to form a second through hole penetrating the second stacked structure and exposing the substrate; and forming a second conductive layer on the surface of the remaining first conductive layer and the surface of the second through hole.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a common memory device. It features high integration, fast read / write speeds, and low cost, making it widely used in various consumer electronic products such as computers, mobile phones, and set-top boxes. Each memory cell in DRAM can consist of a transistor and a capacitor. As devices become smaller and more integrated, the height of capacitors continues to increase, increasing the risk of capacitor bending. This bending can easily cause short circuits between adjacent capacitors, reducing the memory's yield. Summary of the Invention

[0003] According to a first aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device structure, comprising:

[0004] forming a second stacked structure and a first stacked structure in sequence on the substrate; wherein the first stacked structure comprises a first sacrificial layer and a first supporting layer stacked in sequence;

[0005] forming a first initial hole penetrating the first supporting layer and the first sacrificial layer;

[0006] Etching the first sacrificial layer laterally along the first initial hole to enlarge the aperture of a portion of the first initial hole; wherein the first initial hole after the aperture is enlarged constitutes a first through hole;

[0007] forming a first conductive layer on a surface of the first through hole;

[0008] Sequentially etching the first conductive layer and the second stacked structure on the bottom surface of the first through hole along the first through hole to form a second through hole penetrating the second stacked structure and exposing the substrate;

[0009] A second conductive layer is formed on the surface of the remaining first conductive layer and the surface of the second through hole.

[0010] In some embodiments, laterally etching the first sacrificial layer along the first initial hole includes:

[0011] An etching solution is introduced into the first initial hole, and the etching solution etches the first sacrificial layer along a radial direction of the first initial hole.

[0012] In some embodiments, the first through hole includes a first hole segment located in the first supporting layer and a second hole segment located in the first sacrificial layer;

[0013] wherein the second aperture of the second hole segment is larger than the first aperture of the first hole segment;

[0014] The thickness of the first conductive layer is substantially equal to half of the difference between the first aperture and the second aperture.

[0015] In some embodiments, in the step of forming the first initial hole penetrating the first supporting layer and the first sacrificial layer, the second stacked structure is used as an etch stop layer, and the bottom of the first initial hole is flush with the top surface of the second stacked structure.

[0016] In some embodiments, the second through hole has a third aperture, and the third aperture is equal to the first aperture;

[0017] The step of sequentially etching the first conductive layer and the second stacked structure on the bottom surface of the first through hole along the first through hole further comprises:

[0018] The first conductive layer on the sidewall of the first supporting layer in the first through hole is removed.

[0019] In some embodiments, in the step of forming the first conductive layer, the first conductive layer also covers the top surface of the first supporting layer;

[0020] The manufacturing method further comprises:

[0021] In the etching process of sequentially etching the first conductive layer on the bottom surface of the first through hole and the second stacked structure along the first through hole, the first conductive layer on the top surface of the first supporting layer is removed simultaneously.

[0022] In some embodiments, the second stacked structure includes a bottom supporting layer, a second sacrificial layer, and a second supporting layer stacked in sequence;

[0023] After forming the second conductive layer, the manufacturing method further includes:

[0024] forming a first opening penetrating the first supporting layer, and removing the first sacrificial layer based on the first opening; wherein the first opening is located between adjacent first through holes;

[0025] The second supporting layer is etched along the first opening to form a second opening penetrating the second supporting layer, and the second sacrificial layer is removed based on the second opening.

[0026] In some embodiments, during the step of removing the first sacrificial layer and the second sacrificial layer, the first conductive layer is partially etched and thinned; the manufacturing method further comprises: depositing a dielectric layer on the exposed surfaces of the remaining first conductive layer and the second conductive layer, and depositing a second electrode layer on the surface of the dielectric layer; wherein the remaining first conductive layer and the second conductive layer constitute a first electrode layer, and the first electrode layer, the dielectric layer, and the second electrode layer constitute a capacitor;

[0027] Alternatively, in the step of removing the first sacrificial layer and the second sacrificial layer, the first conductive layer is removed; the manufacturing method also includes: depositing a dielectric layer on the exposed surface of the second conductive layer, and depositing a second electrode layer on the surface of the dielectric layer; wherein the second conductive layer, the dielectric layer and the second electrode layer constitute a capacitor.

[0028] According to a second aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate, a bottom supporting layer, a second supporting layer, and a first supporting layer sequentially arranged parallel to the substrate, and a capacitor; the capacitor comprising:

[0029] a first electrode layer, the first electrode layer comprising a first conductive layer and a second conductive layer, the second conductive layer penetrating the first supporting layer, the second supporting layer, and the bottom supporting layer and contacting the substrate; the first conductive layer being located between the first supporting layer and the second supporting layer and covering an outer surface of the second conductive layer, and / or the first conductive layer being located between a sidewall of the first supporting layer and the second conductive layer;

[0030] a dielectric layer covering surfaces of the first electrode layer, the first supporting layer, the second supporting layer and the bottom supporting layer;

[0031] The second electrode layer covers the surface of the dielectric layer.

[0032] In some embodiments, the first electrode layer includes a first electrode portion located between the first supporting layer and the second supporting layer, and a second electrode portion located between the second supporting layer and the bottom supporting layer;

[0033] The thickness of the first electrode portion is greater than the thickness of the second electrode portion.

[0034] In some embodiments, the number of the capacitor is plural; and the substrate comprises:

[0035] A transistor array, comprising a plurality of transistors arranged in an array, each of the transistors comprising a source region and a drain region;

[0036] a capacitor contact plug array, located on the transistor array, wherein the bottom of each capacitor contact plug in the capacitor contact plug array contacts the source region or the drain region of one of the transistors;

[0037] A plurality of landing pads are located on the capacitor contact plug array, wherein the bottom of each landing pad contacts one of the capacitor contact plugs, and the top of each landing pad contacts the bottom of the second conductive layer of one of the capacitors.

[0038] The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is as follows: first, a first conductive layer and a second conductive layer are deposited successively in the hole section of the first through hole corresponding to the first sacrificial layer, and the thickness of the conductive layer is increased by the two-deposition method. In this way, in the subsequent process of removing the first sacrificial layer and the second sacrificial layer in the second stacked structure, although the conductive layer corresponding to the first sacrificial layer is consumed more than the conductive layer corresponding to the second sacrificial layer, the first conductive layer can offset the excess consumption, so that the film thickness of the conductive layer located in the first through hole and the part located in the second through hole are relatively uniform, thereby improving the bending resistance of the first electrode layer, reducing the risk of short circuit between capacitors due to bending of the first electrode layer, and improving the yield and reliability of the chip.

[0039] Second, the side etching of the first sacrificial layer causes the side wall of the first sacrificial layer to retract a distance, and the first conductive layer is located in the retracted area. Therefore, when etching the second stacked structure to form the second through hole, it is easy to reduce or even avoid etching the first conductive layer on the side wall of the first sacrificial layer. In this way, it is easy to accurately control the thickness of the first conductive layer after the second through hole is formed, and it is less likely that the second conductive layer will be etched due to insufficient thickness of the first conductive layer, thereby making it easier to ultimately obtain a uniform conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1a and Figure 1b A schematic diagram of the structure of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0041] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure;

[0042] Figures 3a to 3j A schematic structural diagram of another semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0043] Figures 4a to 4b A schematic structural diagram of another semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0044] Figures 5a to 5cA schematic structural diagram of another semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0045] Figures 6a to 6g A schematic structural diagram of another semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0046] Figures 7a to 7d A schematic structural diagram of another semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0047] Figure 8 A schematic structural diagram of a substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0049] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0050] It should be understood that spatial relational terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relational terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "beneath" or "beneath" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0051] The terminology used herein is intended only to describe specific embodiments and is not intended to limit the present disclosure. The terms "comprising" and / or "including," when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0052] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0053] Figure 1a and Figure 1b This is a schematic diagram of the structure of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure. Figure 1a As shown, the semiconductor structure includes a substrate 10, which includes a plurality of conductive structures 11 and an isolation layer 12 located between adjacent conductive structures 11. The isolation layer 12 is used to electrically isolate adjacent conductive structures 11.

[0054] In some embodiments, substrate 10 further includes a plurality of transistors (not shown), each of which has a source (or drain) connected to a bit line and a drain (or source) connected to a capacitor. For example, the transistors are located below conductive structure 11. Conductive structure 11 is used to electrically connect the transistors and the capacitors.

[0055] Figure 1a and Figure 1b The process of forming the first electrode layer (also called the lower electrode plate) of the capacitor is shown. Figure 1a As shown, a bottom supporting layer 21, a second sacrificial layer 22, a second supporting layer 23, a first sacrificial layer 24 and a first supporting layer 25 are formed on the surface of the substrate 10 from bottom to top; then, a capacitor hole 30 is formed that passes through the first supporting layer 25, the first sacrificial layer 24, the second supporting layer 23, the second sacrificial layer 22 and the bottom supporting layer 21; then, a conductive material is deposited on the bottom and sidewalls of the capacitor hole 30 to form a first electrode layer 40.

[0056] Continue to see Figure 1a and Figure 1b , the first sacrificial layer 24 and the second sacrificial layer 22 are removed by etching to expose the outer surface of the first electrode layer 40 .

[0057] For example, the first electrode layer 40 is arranged in a U-shape, which can also be understood as a cup-shaped arrangement. The sidewall of the U-shaped first electrode layer 40 is arranged in a ring shape, and the first electrode layer 40 has an inner surface located inside the ring and an outer surface located outside the ring.

[0058] In some embodiments, during the removal of the first sacrificial layer 24 and the second sacrificial layer 22, the first sacrificial layer 24 is removed first, exposing the first region 41 of the first electrode layer 40 (referring to the portion of the first electrode layer 40 located between the first supporting layer 25 and the second supporting layer 23). During the subsequent etching process to remove the second sacrificial layer 22, the first region 41 of the first electrode layer 40 is also etched, causing the first region 41 to undergo more etching and acid washing than the second region 42 (referring to the portion of the first electrode layer 40 located between the second supporting layer 23 and the bottom supporting layer 21). As a result, more material in the first region 41 is consumed than that in the second region 42, resulting in the first region 41 being thinner than the second region 42.

[0059] If the first region 41 of the first electrode layer 40 is too thin, the first region 41 is more likely to bend, which may cause contact with adjacent capacitors, resulting in a short circuit between adjacent capacitors, thereby reducing the production yield of the memory and the reliability of the memory.

[0060] In view of this, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which is used to solve the problem of reduced bending resistance of the first electrode layer due to uneven thickness of the upper and lower layers. Figure 2 A schematic diagram of a process for manufacturing a semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the method for manufacturing the semiconductor structure includes the following steps:

[0061] S100: forming a second stacked structure and a first stacked structure in sequence on a substrate; wherein the first stacked structure includes a first sacrificial layer and a first supporting layer stacked in sequence;

[0062] S200: forming a first initial hole penetrating the first supporting layer and the first sacrificial layer;

[0063] S300: etching the first sacrificial layer laterally along the first initial hole to enlarge the aperture of a portion of the first initial hole; wherein the first initial hole after the aperture is enlarged constitutes a first through hole;

[0064] S400: forming a first conductive layer on a surface of the first through hole;

[0065] S500: etching the first conductive layer and the second stacked structure on the bottom surface of the first through hole in sequence along the first through hole to form a second through hole penetrating the second stacked structure and exposing the substrate;

[0066] S600 : forming a second conductive layer on the surface of the remaining first conductive layer and the surface of the second through hole.

[0067] Figures 3a to 3jA schematic diagram of the structure of another semiconductor structure in the manufacturing process provided by the embodiment of the present disclosure is shown below in conjunction with Figure 2 、 Figures 3a to 3j The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is introduced in detail.

[0068] See also Figure 3a A substrate 100 is provided, and the substrate 100 includes a plurality of conductive structures 110 and an isolation layer 120 located between adjacent conductive structures 110. The isolation layer 120 is used to electrically isolate adjacent conductive structures 110.

[0069] In some embodiments, the material of conductive structure 110 may include at least one of silicon, metal nitride, and metal. Silicon may include single crystal silicon, polycrystalline silicon, or doped polycrystalline silicon. Metal nitrides may include titanium nitride, tungsten nitride, tantalum nitride, etc. Metals may include tungsten, titanium, copper, gold, cobalt, nickel, etc. In some embodiments, conductive structure 110 may be a landing pad for electrically connecting a capacitor.

[0070] In some embodiments, the material of the isolation layer 120 includes, but is not limited to, silicon nitride, silicon oxide, and silicon oxynitride.

[0071] Continue to see Figure 3a , step S100 is performed to form a second stacked structure 200 and a first stacked structure 300 stacked sequentially on a substrate 100. The second stacked structure 200 includes a bottom support layer 210, a second sacrificial layer 220, and a second support layer 230 stacked sequentially from bottom to top. The first stacked structure 300 is located on the second stacked structure 200, and the first stacked structure 300 includes a first sacrificial layer 310 and a first support layer 320 stacked sequentially from bottom to top.

[0072] In some embodiments, the materials of the bottom supporting layer 210 , the second supporting layer 230 , and the first supporting layer 320 include insulating materials, including but not limited to silicon nitride, silicon oxide, silicon oxynitride, and the like.

[0073] The materials of the bottom supporting layer 210 , the second supporting layer 230 and the first supporting layer 320 may all be the same, or may not all be the same or may be different from each other.

[0074] Under certain conditions, the materials of the first sacrificial layer 310 and the second sacrificial layer 220 have a high etching selectivity with the materials of the supporting layers (including the bottom supporting layer 210, the second supporting layer 230, and the first supporting layer 320). This allows the supporting layers to be etched with minimal or no etching loss during the removal of the sacrificial layers. The materials of the first sacrificial layer 310 and the second sacrificial layer 220 may be the same or different.

[0075] In this embodiment, the bottom supporting layer 210, the second supporting layer 230, and the first supporting layer 320 are all made of silicon nitride. The second sacrificial layer 220 and the first sacrificial layer 310 are all made of silicon oxide.

[0076] See also Figure 3b , step S200 is performed to form a plurality of first initial holes 410 penetrating the first support layer 320 and the first sacrificial layer 310. For example, the first initial holes 410 may be formed by etching the first support layer 320 and the first sacrificial layer 310 using a dry etching process.

[0077] In some embodiments, as Figure 3b As shown, during the etching process to form the first initial hole 410, the second stacked structure 200 serves as an etch stop layer, so that the etching stops at the top surface of the second stacked structure 200, thereby making the bottom of the first initial hole 410 flush with the top surface of the second stacked structure 200. This configuration is because if the first initial hole 410 extends into the second supporting layer 230, the contact area between the second supporting layer 230 and the subsequently formed second conductive layer will be reduced. When removing the sacrificial layer, if the first conductive layer is removed, leaving only the second supporting layer 230 supporting the second conductive layer, the support for the second conductive layer will be weakened.

[0078] For example, the material of the second supporting layer 230 may be different from the materials of the first sacrificial layer 310 and the first supporting layer 320 , so that the second supporting layer 230 has a larger etching selectivity to the first sacrificial layer 310 and the first supporting layer 320 .

[0079] As another example, the second stacked structure 200 may also include an etch stop layer, which is located on the second supporting layer 230 and serves as an etch stop layer in the etching process of the first initial hole 410 .

[0080] See also Figure 3c , step S300 is performed to etch the first sacrificial layer 310 along the side of the first initial hole 410 within the first initial hole 410 to enlarge the aperture of a portion of the first initial hole 410; wherein the enlarged first initial hole 410 forms a first through hole 400. The first through hole 400 includes a first hole section 401 located in the first supporting layer 320 and a second hole section 402 located in the first sacrificial layer 310. The first hole section 401 has a first aperture A1, and the second hole section 402 has a second aperture A2, which is larger than the first aperture A1.

[0081] The first aperture A1 is equal to the aperture of the first preliminary hole 410. This is because the first supporting layer 320 is substantially not etched during the process from the first preliminary hole 410 to the formation of the first through hole 400.

[0082] The sidewall of the first sacrificial layer 310 is laterally etched and retracted, so that the second aperture A2 is larger than the aperture of the first initial hole 410 , and thus also larger than the first aperture A1 .

[0083] In some embodiments, the first sacrificial layer 310 shrinks by 3 nm to 5 nm in this step. That is, half of the difference between the second aperture A2 and the first aperture A1 is in the range of 3 nm to 5 nm.

[0084] In some embodiments, a wet etching process may be used to etch the first sacrificial layer 310. Specifically, step S300 may include:

[0085] An etching solution is introduced into the first initial hole 410 , and the etching solution etches the first sacrificial layer 310 along the radial direction of the first initial hole 410 .

[0086] The etching process of the etching liquid on the first sacrificial layer 310 is isotropic, so the hole section of the first initial hole 410 located in the first sacrificial layer 310 expands uniformly in the radial direction, thereby causing the sidewall of the first sacrificial layer 310 to retract uniformly. Figure 3c As shown, the sidewall of the second hole section 402 extends substantially in the up-down direction and is perpendicular to the plane where the base is located.

[0087] In some embodiments, the components of the etching solution include, but are not limited to, hydrofluoric acid and ammonium fluoride. The desired second aperture A2 can be obtained by controlling the etching time, the components of the etching solution, and the like.

[0088] In other embodiments, a dry etching process may be used to etch the first sacrificial layer, thereby imparting a slightly curved profile to the sidewalls of the second hole segment, similar to the shape of a waist drum with smaller ends and a larger center. In still other embodiments, the dry etching process may be used to impart a diameter to the second hole segment that is larger at the top and smaller at the bottom.

[0089] In some embodiments, when dry etching is employed, the plasma used for etching may be directed toward the first sacrificial layer at a predetermined angle relative to the axis of the first initial hole, and the plasma may be rotated about the axis of the first initial hole during the etching process. The predetermined angle may also be adjusted during the etching process based on the desired shape of the second hole segment.

[0090] See also Figure 3d , step S400 is performed to deposit a first conductive material on the surface of the first through hole 400 to form a first conductive layer 510. The first conductive layer 510 covers the sidewalls and bottom of the first through hole 400 and the top surface of the first supporting layer 320.

[0091] In some embodiments, the material of the first conductive layer 510 may include at least one of silicon, metal nitride, and metal. Silicon may include single crystal silicon, polycrystalline silicon, or doped polycrystalline silicon. Metal nitrides may include titanium nitride, tungsten nitride, tantalum nitride, etc. Metals may include tungsten, titanium, copper, gold, cobalt, nickel, etc. In this embodiment, the material of the first conductive layer is titanium nitride.

[0092] In some embodiments, as Figure 3d As shown, the thickness of the first conductive layer 510 may be substantially equal to the retracted thickness of the first sacrificial layer 310. That is, the thickness of the first conductive layer 510 is substantially equal to half of the difference between the second aperture A2 and the first aperture A1.

[0093] In some embodiments, the thickness of the first conductive layer 510 is in a range of 1 nm to 5 nm.

[0094] See also Figure 3e , perform step S500, and etch the first conductive layer 510 and the second stacked structure 200 on the bottom surface of the first through hole 400 in sequence along the first through hole 400 to form a second through hole 600 that penetrates the second stacked structure 200 and exposes the substrate 100.

[0095] In some embodiments, as Figure 3e As shown, etching the second stacked structure 200 includes etching the second supporting layer 230 , the second sacrificial layer 220 and the bottom supporting layer 210 in sequence from top to bottom until the conductive structure 110 is exposed, thereby forming a second through hole 600 .

[0096] In this step, the second through hole 600 may be formed by using a dry etching process and / or a wet etching process.

[0097] The second through hole 600 has a third aperture A3. In some embodiments, if the third aperture A3 of the second through hole 600 is required to be equal to the first aperture A1, step S500 may specifically include:

[0098] removing the first conductive layer 510 from the sidewall of the first supporting layer 320 in the first through hole 400;

[0099] Using the first supporting layer 320 as a mask, the first conductive layer 510 and the second stacked structure 200 at the bottom of the first through hole 400 are sequentially etched to form a second through hole 600 , wherein the third aperture A3 of the second through hole 600 is equal to the first aperture A1 .

[0100] In some embodiments, the so-called removal of the first conductive layer 510 on the sidewalls of the first supporting layer 320 within the first through-hole 400 may involve etching the first conductive layer 510 along the sidewalls of the first supporting layer 320 until the first conductive layer 510 on the sidewalls of the first supporting layer 320 is completely removed. During this process, the first conductive layer 510 at the bottom of the first through-hole 400 may also be partially or completely etched away. Subsequently, using the first supporting layer 320 as a mask, the first conductive layer 510 and the second stacked structure 200 at the bottom of the first through-hole 400 are further etched to form the second through-hole 600.

[0101] like Figure 3e As shown, only the first conductive layer 510 on the sidewalls of the first sacrificial layer 310 is retained. For example, if the thickness of the first conductive layer 510 is substantially equal to half the difference between the second aperture diameter A2 and the first aperture diameter A1, the aperture of the second hole segment 402 after the first conductive layer 510 is formed can be equal to the first aperture diameter A1. Furthermore, the third aperture diameter A3 is equal to the first aperture diameter A1. This allows the sidewalls of the subsequently formed second conductive layer to extend straight in the vertical direction, and the thickness of the second conductive layer to be uniform throughout, thereby providing good support stability for the second conductive layer.

[0102] In some embodiments, step S500 further includes:

[0103] In the etching process of sequentially etching the first conductive layer 510 on the bottom surface of the first through hole 400 and the second stacked structure 200 along the first through hole 400 , the first conductive layer 510 on the top surface of the first supporting layer 320 is simultaneously etched.

[0104] In this step, the first conductive layer 510 protects the top surface of the first supporting layer 320, which can reduce or prevent the top surface of the first supporting layer 320 from being etched and thinned, thereby maintaining a certain thickness of the first supporting layer 320, which is beneficial to improving the support of the first supporting layer 320 for the capacitor.

[0105] In some embodiments, in this step, the first conductive layer 510 on the top surface of the first supporting layer 320 may be completely removed.

[0106] The first conductive layer 510 on the top surface of the first supporting layer 320 may cause a short circuit in the first electrode layer of the subsequently formed capacitor. Therefore, the first conductive layer 510 on the top surface of the first supporting layer 320 is removed in this step to eliminate this risk.

[0107] See also Figure 3f , performing step S600 , depositing a second conductive material on the surface of the remaining first conductive layer 510 and the surface of the second through hole 600 to form a second conductive layer 520 .

[0108] For example, a second conductive material is deposited on the sidewalls of the first supporting layer 320 , the surface of the first conductive layer 510 in the second hole segment, and the sidewalls and bottom of the second through hole 600 to form the second conductive layer 520 .

[0109] In some embodiments, the thickness of the second conductive layer 520 may be in the range of 5 nm to 8 nm.

[0110] In some embodiments, the second conductive material may also cover the top surface of the first supporting layer 320; the manufacturing method further includes:

[0111] The second conductive material on the top surface of the first supporting layer 320 is removed.

[0112] For example, a dry etching process may be used to remove the second conductive material on the top surface of the first supporting layer 320 .

[0113] See also Figure 3g 、 Figure 3h and Figure 3i ,in, Figure 3g is a top view of the semiconductor structure of this embodiment, Figure 3h yes Figure 3g A cross-sectional view along line AA. The manufacturing method further comprises:

[0114] forming a first opening 330 penetrating the first supporting layer 320 and removing the first sacrificial layer 310 based on the first opening 330 ; wherein the first opening 330 is located between adjacent first through holes 400 ;

[0115] The second supporting layer 230 is etched along the first opening 330 to form a second opening (not shown) penetrating the second supporting layer 230 , and the second sacrificial layer 220 is removed based on the second opening.

[0116] like Figure 3g As shown, in some embodiments, a first opening 330 is defined in the first supporting layer 320 region between every three adjacent first through holes 400 (or second conductive layer 520). The first opening 330 can have a relatively large opening area, exposing the sidewall of the conductive layer (the first conductive layer or the second conductive layer). Alternatively, the first opening 330 can have a relatively small opening area, without exposing the sidewall of the conductive layer.

[0117] In some embodiments, the first opening 330 may be formed by a dry etching process or a wet etching process, and the second opening in the first support layer 320 region between every three adjacent first through holes 400 (or second conductive layer 520) may be formed by dry etching. The opening area of ​​the second opening may be equal to the opening area of ​​the first opening 330.

[0118] In some embodiments, a wet etching process may be used to remove the first sacrificial layer 310 and the second sacrificial layer 220 .

[0119] Combine Figure 1b 、 Figure 3h and Figure 3i It can be seen that, by adopting the manufacturing method disclosed in the present invention, the first conductive layer 510 and the second conductive layer 520 are successively deposited in the second hole section 402, and the thickness of the first region 41 of the first electrode layer is increased by the method of two depositions. In this way, in the process of removing the first sacrificial layer 310 and the second sacrificial layer 220, although the material of the first region 41 is consumed more than the material of the second region 42, due to the presence of the first conductive layer 510, the first conductive layer 510 has sufficient thickness to offset the thickness consumed more in the first region than in the second region, so that the thickness of the first region and the second region of the first electrode layer finally formed are not much different, thereby improving the uniformity of the film thickness of the first electrode layer, thereby improving the support stability and anti-bending ability of the first electrode layer, reducing the risk of short circuit between capacitors due to bending of the first electrode layer, and improving the yield and reliability of the chip. In summary, in the present disclosure, the process flow is changed to increase the film thickness of the first region material alone, thereby reducing the risk of bending of the first electrode layer due to excessive loss in the first region.

[0120] Further, if Figures 3c to 3f As shown, in the present disclosure, the side etching of the first sacrificial layer 310 causes the side wall of the first sacrificial layer 310 to retract a certain distance, and then the first conductive layer 510 is located in the retracted area. Therefore, when etching the second stacked structure 200 to form the second through hole, it is easy to reduce or even avoid etching the first conductive layer on the side wall of the first sacrificial layer 310. In this way, it is easy to accurately control the thickness of the first conductive layer after the second through hole is formed, and it is not easy for the second conductive layer to be etched due to insufficient thickness of the first conductive layer, and it is easier to finally obtain a uniform conductive layer.

[0121] In some embodiments, during the process of removing the first sacrificial layer 310, the first conductive layer 510 may also be partially etched and become thinner. Figure 1b In the process of removing the first sacrificial layer 310 and the second sacrificial layer 220 , the thickness of the first conductive layer 510 is adaptively adjusted by etching the first electrode layer 40 .

[0122] In some embodiments, as Figure 3i As shown, in the step of removing the first sacrificial layer and the second sacrificial layer, the first conductive layer 510 is partially etched and thinned. After removing the second sacrificial layer, the first conductive layer 510 still remains on the outer surface of the second conductive layer 520.

[0123] like Figure 3j As shown, the manufacturing method also includes:

[0124] A dielectric layer 710 is deposited on the exposed surfaces of the remaining first conductive layer 510 and the second conductive layer 520, and a second electrode layer 720 is deposited on the surface of the dielectric layer 710; wherein the remaining first conductive layer 510 and the second conductive layer 520 constitute the first electrode layer 500, and the first electrode layer 500, the dielectric layer 710 and the second electrode layer 720 constitute a capacitor.

[0125] like Figure 3j As shown, the first electrode layer 500 includes a first electrode portion 501 located between the first support layer 320 and the second support layer 230, and a second electrode portion 502 located between the second support layer 230 and the bottom support layer 210. The first electrode portion 501 includes a portion of the second conductive layer 520 located between the first support layer 320 and the second support layer 230, and the first conductive layer 510, wherein the first conductive layer 510 is located on the outer surface of the portion of the second conductive layer 520. The second electrode portion 502 includes a portion of the second conductive layer 520 located between the second support layer and the bottom support layer 210. The thickness of the second electrode portion 502 is greater than that of the first electrode portion 501, which helps improve the capacitor's bending resistance, that is, helps improve the capacitor's structural strength.

[0126] In other embodiments, Figure 4a As shown, in the step of removing the first sacrificial layer and the second sacrificial layer, the first conductive layer may be completely removed to expose the outer side of the second conductive layer 520 .

[0127] like Figure 4b As shown, the manufacturing method also includes:

[0128] A dielectric layer 710 is deposited on the exposed surface of the second conductive layer 520 , and a second electrode layer 720 is deposited on the surface of the dielectric layer 710 ; wherein the second conductive layer 520 , the dielectric layer 710 and the second electrode layer 720 constitute a capacitor, and the second conductive layer 520 serves as the first electrode layer of the capacitor.

[0129] like Figure 4b As shown, the thickness of the first electrode portion 501 can be equal to the thickness of the second electrode portion 502, the sidewalls of the first electrode layer extend straight up and down, and the film thickness of the first electrode layer is basically the same at all locations, which is beneficial to improving the support stability and bending resistance of the capacitor.

[0130] In some embodiments, as Figure 3j and 4b As shown, the semiconductor structure further includes a filling layer 730 covering the second electrode layer 720 and filling the remaining space between adjacent capacitors. The remaining space includes the remaining space of the first through hole and the second through hole, and the remaining space released after removing the first sacrificial layer and the second sacrificial layer.

[0131] In some other embodiments, the second electrode layer 720 may cover the surface of the dielectric layer 710 and fill the remaining space between adjacent capacitors.

[0132] In some implementations, such as Figure 5a As shown, in step S500, the first conductive layer 510 and the second stacked structure 200 on the bottom surface of the first through hole 400 are sequentially etched along the first through hole 400 to form the second through hole 600. The first conductive layer 510 on the side wall of the first supporting layer 320 can also be retained.

[0133] That is, using the first supporting layer 320 and the first conductive layer 510 located on the sidewalls of the first supporting layer 320 as masks, the first conductive layer 510 at the bottom of the first through hole 400 and the second stacked structure 200 are sequentially etched to form the second through hole 600. Therefore, the third aperture A3 of the second through hole 600 is smaller than the first aperture A1.

[0134] See also Figure 5b In step S600, a second conductive layer 520 is deposited on the surface of the remaining first conductive layer 510 in the first through hole 400 and on the sidewalls and bottom surface of the second through hole 600. The so-called remaining first conductive layer 510 includes the first conductive layer 510 located on the sidewalls of the first supporting layer 320 and the sidewalls of the first sacrificial layer 310.

[0135] See also Figure 5b and 5c , the first sacrificial layer 310 and the second sacrificial layer 220 are removed.

[0136] In some implementations, such as Figure 5c As shown, the first conductive layer 510 of the second hole segment 402 can be partially etched and thinned, so that the remaining first conductive layer 510 is located between the first supporting layer 320 and the second supporting layer 230 and covers the outer surface of the second conductive layer 520, and is located between the first supporting layer 320 and the second conductive layer 520. The thickness of the first electrode portion 501 is greater than the thickness of the second electrode portion 502.

[0137] In some other embodiments, the first conductive layer 510 of the second hole segment 402 may be completely removed, and the remaining first conductive layer 510 is located between the first supporting layer 320 and the second supporting layer 230 .

[0138] In some embodiments, as Figure 5a As shown, the thickness of the first conductive layer 510 may also be less than half of the difference between the second aperture A2 and the first aperture A1.

[0139] In some embodiments, the semiconductor structure may include multiple stacked structures, for example, three or four. As the desired capacitor height increases, the number of stacked structures may increase. The following describes the technical solution of the present disclosure in further detail, assuming the number of stacked structures is three.

[0140] Figures 6a to 6f This is a schematic diagram of the structure of another semiconductor structure during the manufacturing process provided by the embodiment of the present disclosure. Figure 6a , the manufacturing method further comprises:

[0141] A third stacked structure 800 is formed on the second stacked structure 200 . The third stacked structure 800 is located between the second stacked structure 200 and the first stacked structure 300 . The third stacked structure 800 includes a third sacrificial layer 810 and a third supporting layer 820 stacked sequentially from bottom to top.

[0142] For example, the material of the third sacrificial layer 810 may include silicon oxide, and the material of the third supporting layer 820 may include silicon nitride.

[0143] Continue to see Figure 6a , performing the above steps S200 , S300 and S400 , forming a first conductive layer 510 on the surface of the first through hole 400 .

[0144] See also Figure 6b After removing the first conductive layer 510 on the bottom surface of the first through hole 400 along the first through hole 400, the manufacturing method further includes:

[0145] The third supporting layer 820 and the third sacrificial layer 810 are etched to form a second initial hole 910 penetrating the third stacked structure 800 .

[0146] In some embodiments, in the steps of removing the first conductive layer 510 on the bottom surface of the first through hole 400 and etching the third stacked structure 800, the first conductive layer 510 on the side wall of the first support layer 320 can also be removed. In this way, the first support layer 320 can be used as a mask to etch the third stacked structure 800, so that the aperture of the second initial hole 910 is equal to the first aperture A1.

[0147] In some embodiments, during the step of etching the third stacked structure 800 , the second stacked structure 200 is used as an etching stop layer, and the bottom of the second initial hole 910 is flush with the top surface of the second stacked structure 200 .

[0148] See also Figure 6c , in the second initial hole 910 , the third sacrificial layer 810 is etched along the side of the second initial hole 910 to expand the aperture of a portion of the second initial hole 910 ; wherein the second initial hole 910 after the aperture is expanded forms a third through hole 900 .

[0149] In some embodiments, an etchant can be introduced into the third through-hole 900 to uniformly etch the third sacrificial layer 810 along the radial direction of the second initial hole 910, so that the sidewalls of the hole section of the third through-hole 900 located in the third sacrificial layer 810 extend straight in the vertical direction. In this step, because the third sacrificial layer 810, the support layer (including the first support layer, the second support layer, and the third support layer 820), and the first conductive layer 510 are made of different materials, a high etching selectivity can be achieved under certain conditions. Therefore, this lateral etching process does not affect the structure within the first through-hole 400.

[0150] The third through hole 900 includes a third hole section 901 located in the third supporting layer 820 and a fourth hole section 902 located in the third sacrificial layer 810. The fourth aperture A4 of the third hole section 901 is equal to the first aperture A1.

[0151] In some embodiments, the fifth aperture A5 of the fourth aperture section 902 may be equal to or smaller than the second aperture A2.

[0152] See also Figure 6d , a third conductive material is deposited on the surface of the remaining first conductive layer 510 and the surface of the third through hole 900 to form a third conductive layer 530 .

[0153] For example, a third conductive material is deposited on the sidewalls of the first supporting layer 320 , the surface of the remaining first conductive layer 510 , and the sidewalls and bottom surface of the third through hole 900 to form the third conductive layer 530 .

[0154] See also Figure 6e The third conductive layer 530 at the bottom of the third through hole 900 is removed by etching along the first through hole 400 and the third through hole 900. Next, step S400 is performed to continue etching the second stacked structure 200 along the first through hole 400 to form a second through hole 600 penetrating the second stacked structure 200.

[0155] In some embodiments, the third conductive layer 530 on the sidewalls of the first supporting layer 320 and the third supporting layer 820 may be removed, and the third conductive layer 530 and the second stacked structure 200 at the bottom of the third through hole 900 may be further etched using the first supporting layer 320 as a mask to form a second through hole 600 penetrating the second stacked structure 200. The first aperture A1, the fourth aperture A4, and the third aperture A3 are equal to each other.

[0156] See also Figure 6f A second conductive material is deposited on the surface of the remaining first conductive layer 510 , the surface of the remaining third conductive layer 530 , and the surface of the second through hole 600 to form a second conductive layer 520 .

[0157] In some embodiments, the thickness of the first conductive layer can be equal to half the difference between the second aperture and the first aperture. The thickness of the third conductive layer can be equal to half the difference between the fifth aperture and the fourth aperture. This ensures that the outer diameter of the second conductive layer is uniform throughout, meaning that the second conductive layer extends straight vertically, thereby improving the support stability of the capacitor.

[0158] In some embodiments, when the sacrificial layer is subsequently removed, the first conductive layer may be consumed more than the third conductive layer. Therefore, in this step, the thickness of the first conductive layer may be greater than that of the third conductive layer. Of course, the thickness of the first conductive layer and the thickness of the third conductive layer may also be equal.

[0159] In some embodiments, the first conductive layer, the second conductive layer, and the third conductive layer are made of the same material. For example, the materials of the three layers are all titanium nitride.

[0160] See also Figure 6g , the first sacrificial layer 310 , the third sacrificial layer 810 and the second sacrificial layer 220 are removed in sequence.

[0161] For example, the first conductive layer 510 may be completely or partially removed. The third conductive layer 530 may be completely or partially removed.

[0162] In the manufacturing method provided in this embodiment, the hole section corresponding to the first sacrificial layer is expanded so that the sidewall of the first sacrificial layer is retracted by a distance relative to the sidewall of the support layer, and then the first conductive layer is arranged in the retracted area. When forming the second initial hole, under the premise of not affecting the first conductive layer on the surface of the first sacrificial layer, this embodiment can obtain a second initial hole with a larger aperture. For example, the aperture of the second initial hole is equal to the first aperture. This can avoid the situation where the first electrode layer is smaller at the bottom and larger at the top, thereby improving the support stability of the first electrode layer. It can be understood that no matter how many stacked structures there are, the sidewalls of the second conductive layer can be made to extend straight in the vertical direction, thereby improving the uniformity of the film thickness of the first electrode layer, which is beneficial to improving the support stability and anti-bending ability of the capacitor.

[0163] In some embodiments, in the process of removing the first sacrificial layer and the second sacrificial layer, the higher in the first region (that is, the closer to the first supporting layer), the more material of the first electrode layer may be consumed. Therefore, the thickness of the first conductive layer 510 on the side wall of the first sacrificial layer 310 can gradually increase from bottom to top.

[0164] Figures 7a to 7d A schematic structural diagram of another semiconductor structure during the preparation process provided by an embodiment of the present disclosure.

[0165] like Figure 7aAs shown, in step S300 , a first initial hole 410 is formed, and the diameter of the first initial hole 410 gradually decreases with increasing depth (ie, from top to bottom).

[0166] like Figure 7b As shown, in step S400, the first sacrificial layer 310 is uniformly etched in all directions along the radial direction of the first initial hole 410, so that the sidewalls of the first sacrificial layer 310 are etched by the same distance everywhere, thereby gradually reducing the second aperture A2 of the second hole section 402 of the first through hole 400 from top to bottom.

[0167] Here, in some other embodiments, it is also possible to form Figure 3b After the first initial hole 410 is formed, a dry etching process is used to inject the etching plasma into the hole section corresponding to the first sacrificial layer 310 at a preset angle to the axial direction of the first initial hole 410. By adjusting the preset angle, the Figure 7b The first through hole 400 is shown.

[0168] like Figure 7c As shown, a first conductive layer 510 is deposited in the first through hole 400. The thickness of the first conductive layer 510 is greater than or equal to half the difference between the second aperture A2 and the first aperture A1. For example, the thickness of the first conductive layer 510 is substantially the same everywhere.

[0169] like Figure 7d As shown, the first conductive layer 510 on the sidewalls of the first supporting layer 320 is removed. Using the first supporting layer 320 as a mask, the first conductive layer 510 is etched to remove a portion of the first conductive layer 510 on the sidewalls of the first through-hole. The thickness of the remaining first conductive layer 510 gradually increases from bottom to top. Next, using the first supporting layer 320 as a mask, the first conductive layer and the second stacked structure 200 at the bottom of the first through-hole 400 are etched sequentially to form a second through-hole 600.

[0170] It should be understood that the formation Figure 7d The manner of the first conductive layer 510 shown is not limited to the manner provided in this embodiment. In other embodiments, it may also be Figure 3c The first conductive layer 510 is formed in the first through hole 400 by controlling the deposition process.

[0171] In this embodiment, according to the situation that the first electrode layer 500 is consumed when the sacrificial layer is removed, the thickness of the first conductive layer 510 on the side wall of the first sacrificial layer 310 is adaptively set to gradually increase from bottom to top, which can avoid the situation where the second conductive layer 520 is locally consumed.

[0172] In some embodiments, the first sacrificial layer 310 may include an alternating stack of a first sub-sacrificial layer and a second sub-sacrificial layer, and the etching selectivity ratios of the first sub-sacrificial layer and the second sub-sacrificial layer are different, so that the first sub-sacrificial layer and the second sub-sacrificial layer retract different distances after lateral etching, thereby enabling the sidewalls of the finally formed first electrode layer 500 to have an outward protrusion, thereby increasing the area of ​​the first electrode layer 500 and increasing the capacity of the capacitor.

[0173] Figure 8 Schematic diagram of a substrate provided in an embodiment of the present disclosure. Figure 8 As shown, the base 100 includes a substrate 101, which includes a plurality of active areas 102 arranged in an array, and a shallow trench isolation structure 103 located between adjacent active areas 102. The shallow trench isolation structure 103 is used to electrically isolate adjacent active areas 102. The word line passes through the active area 102 and extends along the X direction. The active area 102 is provided with a drain region and a source region in the area on both sides of the word line. The bit line 104 is located on the substrate and extends along the Y direction. The bottom of the bit line 104 is in contact with the drain region. A bit line insulating layer 105 is also provided on the top of the bit line 104, and the sidewalls of the bit line 104 are covered with a bit line isolation layer 106. By way of example, the bit line isolation layer 106 includes a first silicon nitride layer, a silicon oxide layer, and a second silicon nitride layer arranged in sequence along the X direction.

[0174] Furthermore, the substrate 100 further includes a capacitor contact plug 107 and a landing pad 108. The capacitor contact plug 107 is located on the substrate 101, and the bottom of the capacitor contact plug 107 extends into the source region. The capacitor contact plug 107 and the bit line 104 are electrically isolated by a bit line isolation layer 106.

[0175] Landing pads 108 are located on top of capacitor contact plugs 107 and bitline insulation layer 105. Adjacent landing pads 108 are electrically isolated by isolation layer 109 and bitline insulation layer 105. Capacitors are located on top of landing pads 108. Landing pads 108 can adjust the arrangement of the capacitor array, making it different from the arrangement of capacitor contact plugs 107. For example, the distance between adjacent capacitors can be made larger than the distance between adjacent capacitor contact plugs, thereby increasing the storage area of ​​the capacitors.

[0176] Figure 3a The conductive structure 110 shown may be the landing pad 108 in this embodiment, with an isolation layer 109 / 120 provided between adjacent landing pads.

[0177] The present disclosure also provides a semiconductor structure, such as Figure 3jAs shown, the semiconductor structure includes: a substrate 100, a bottom support layer 210, a second support layer 230 and a first support layer 320 arranged in parallel to the substrate 100, and a capacitor; the capacitor includes:

[0178] The first electrode layer 500 includes a first conductive layer 510 and a second conductive layer 520. The second conductive layer 520 penetrates the first supporting layer 320, the second supporting layer 230, and the bottom supporting layer 210 and contacts the substrate 100. The first conductive layer 510 is located between the first supporting layer 320 and the second supporting layer 230 and covers the outer surface of the second conductive layer 520, and / or the first conductive layer 510 is located between the first supporting layer 320 and the second conductive layer 520.

[0179] The dielectric layer 710 covers the surfaces of the first electrode layer 500 , the first supporting layer 320 , the second supporting layer 230 and the bottom supporting layer 210 ;

[0180] The second electrode layer 720 covers the surface of the dielectric layer 710 .

[0181] In some embodiments, the first electrode layer 500 includes a first electrode portion 501 located between the first supporting layer 320 and the second supporting layer 230, and a second electrode portion 502 located between the second supporting layer 230 and the bottom supporting layer 210. The first electrode portion 501 includes the portion of the second electrode layer 720 located between the first supporting layer 320 and the second supporting layer 230, and the portion of the first electrode layer 500 located between the first supporting layer 320 and the second supporting layer 230. The second electrode portion 502 includes the portion of the second electrode layer 720 located between the second supporting layer 230 and the bottom supporting layer 210. The thickness of the first electrode portion 501 is greater than that of the second electrode portion 502. This can improve the structural strength of the capacitor.

[0182] In some embodiments, the outer diameter of the second electrode portion 502 is smaller than the outer diameter of the first electrode portion 501 .

[0183] In some embodiments, the sidewalls of the second conductive layer 520 extend in the up-down direction, and the thickness of the second conductive layer 520 is uniform everywhere.

[0184] In some embodiments, the bottom of the first conductive layer 510 is flush with the top surface of the second supporting layer 230 .

[0185] In some embodiments, the first conductive layer 510 is further located between the sidewall of the first supporting layer 320 and the second conductive layer 520 .

[0186] The present disclosure also provides a semiconductor structure, wherein the capacitor includes:

[0187] The first electrode layer 500 includes a first conductive layer 510 and a second conductive layer 520. The second conductive layer 520 penetrates the first supporting layer 320, the second supporting layer 230, and the bottom supporting layer 210 and contacts the substrate 100. The first conductive layer 510 is located between the sidewall of the first supporting layer 320 and the second conductive layer 520.

[0188] The dielectric layer 710 covers the surfaces of the first electrode layer 500 , the first supporting layer 320 , the second supporting layer 230 and the bottom supporting layer 210 ;

[0189] The second electrode layer 720 covers the surface of the dielectric layer 710 .

[0190] The present disclosure also provides a semiconductor structure, such as Figure 4b As shown, in the semiconductor structure, the capacitor includes:

[0191] A first electrode layer 500 , which penetrates the first supporting layer 320 , the second supporting layer 230 , and the bottom supporting layer 210 and contacts the substrate 100 ;

[0192] The dielectric layer 710 covers the surfaces of the first electrode layer 500 , the first supporting layer 320 , the second supporting layer 230 and the bottom supporting layer 210 ;

[0193] The second electrode layer 720 covers the surface of the dielectric layer 710 .

[0194] In some embodiments, the thickness of the first electrode portion 501 is equal to the thickness of the second electrode portion 502 .

[0195] In some embodiments, the outer diameter of the first electrode portion 501 is equal to the outer diameter of the second electrode portion 502 .

[0196] In some embodiments, the number of capacitors is multiple; the substrate 100 includes:

[0197] A transistor array, comprising a plurality of transistors arranged in an array, each transistor comprising a source region and a drain region;

[0198] A capacitor contact plug array is located on the transistor array, wherein the bottom of each capacitor contact plug 107 in the capacitor contact plug array contacts the source region or the drain region of a transistor;

[0199] A plurality of landing pads 108 are located on the capacitor contact plug array. The bottom of each landing pad 108 contacts a capacitor contact plug 107 , and the top of each landing pad 108 contacts the bottom of the second conductive layer 520 of a capacitor.

[0200] Figure 8 Each active area 102 is shown to include one or two transistors.

[0201] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed herein shall be covered by the claims of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a second stacked structure and a first stacked structure in sequence on the substrate; wherein the first stacked structure comprises a first sacrificial layer and a first supporting layer stacked in sequence; forming a first initial hole penetrating the first supporting layer and the first sacrificial layer; Etching the first sacrificial layer laterally along the first initial hole to enlarge the aperture of a portion of the first initial hole; wherein the first initial hole after the aperture is enlarged constitutes a first through hole; forming a first conductive layer on a surface of the first through hole; Sequentially etching the first conductive layer and the second stacked structure on the bottom surface of the first through hole along the first through hole to form a second through hole penetrating the second stacked structure and exposing the substrate; A second conductive layer is formed on the surface of the remaining first conductive layer and the surface of the second through hole.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: Laterally etching the first sacrificial layer along the first initial hole, comprising: An etching solution is introduced into the first initial hole, and the etching solution etches the first sacrificial layer along a radial direction of the first initial hole.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: The first through hole includes a first hole section located in the first supporting layer and a second hole section located in the first sacrificial layer; The second aperture of the second hole segment is larger than the first aperture of the first hole segment; and the thickness of the first conductive layer is substantially equal to half of the difference between the second aperture and the first aperture.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: In the step of forming the first initial hole penetrating the first supporting layer and the first sacrificial layer, the second stacked structure is used as an etching stop layer, and the bottom of the first initial hole is flush with the top surface of the second stacked structure.

5. The method for manufacturing a semiconductor structure according to claim 3, wherein: The second through hole has a third aperture, and the third aperture is equal to the first aperture; The step of sequentially etching the first conductive layer and the second stacked structure on the bottom surface of the first through hole along the first through hole further comprises: The first conductive layer on the sidewall of the first supporting layer in the first through hole is removed.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: In the step of forming the first conductive layer, the first conductive layer also covers the top surface of the first supporting layer; The manufacturing method further comprises: In the etching process of sequentially etching the first conductive layer on the bottom surface of the first through hole and the second stacked structure along the first through hole, the first conductive layer on the top surface of the first supporting layer is removed simultaneously.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: The second stacked structure includes a bottom support layer, a second sacrificial layer and a second support layer stacked in sequence; After forming the second conductive layer, the manufacturing method further includes: forming a first opening penetrating the first supporting layer, and removing the first sacrificial layer based on the first opening; wherein the first opening is located between adjacent first through holes; The second supporting layer is etched along the first opening to form a second opening penetrating the second supporting layer, and the second sacrificial layer is removed based on the second opening.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein: In the step of removing the first sacrificial layer and the second sacrificial layer, the first conductive layer is partially etched and thinned; The manufacturing method further includes: depositing a dielectric layer on the exposed surfaces of the remaining first conductive layer and the second conductive layer, and depositing a second electrode layer on the surface of the dielectric layer; wherein the remaining first conductive layer and the second conductive layer constitute a first electrode layer, and the first electrode layer, the dielectric layer, and the second electrode layer constitute a capacitor; Alternatively, in the step of removing the first sacrificial layer and the second sacrificial layer, the first conductive layer is removed; the manufacturing method also includes: depositing a dielectric layer on the exposed surface of the second conductive layer, and depositing a second electrode layer on the surface of the dielectric layer; wherein the second conductive layer, the dielectric layer and the second electrode layer constitute a capacitor.

9. A semiconductor structure, characterized in that include: a substrate, a bottom supporting layer, a second supporting layer, and a first supporting layer sequentially arranged parallel to the substrate, and a capacitor; The capacitor comprises: a first electrode layer, the first electrode layer comprising a first conductive layer and a second conductive layer, the second conductive layer penetrating the first supporting layer, the second supporting layer, and the bottom supporting layer and contacting the substrate; the first conductive layer being located between the first supporting layer and the second supporting layer and covering an outer surface of the second conductive layer, and / or the first conductive layer being located between a sidewall of the first supporting layer and the second conductive layer; a dielectric layer covering surfaces of the first electrode layer, the first supporting layer, the second supporting layer and the bottom supporting layer; The second electrode layer covers the surface of the dielectric layer.

10. The semiconductor structure according to claim 9, wherein: The first electrode layer includes a first electrode portion located between the first supporting layer and the second supporting layer, and a second electrode portion located between the second supporting layer and the bottom supporting layer; The thickness of the first electrode portion is greater than the thickness of the second electrode portion.

11. The semiconductor structure according to claim 9, wherein: The number of the capacitors is multiple; the substrate comprises: A transistor array, comprising a plurality of transistors arranged in an array, each of the transistors comprising a source region and a drain region; a capacitor contact plug array, located on the transistor array, wherein the bottom of each capacitor contact plug in the capacitor contact plug array contacts the source region or the drain region of one of the transistors; A plurality of landing pads are located on the capacitor contact plug array, wherein the bottom of each landing pad contacts one of the capacitor contact plugs, and the top of each landing pad contacts the bottom of the second conductive layer of one of the capacitors.

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