AlGaInP-based reverse polarity vertical light-emitting diode chip and preparation method thereof

Abstract

The present invention provides an AlGaInP-based reverse polarity vertical light-emitting diode chip and a preparation method thereof. The chip comprises a substrate, an intermediate layer, a P-type semiconductor layer, an active layer and an N-type semiconductor layer arranged in sequence from bottom to top. The P-type semiconductor layer comprises a P-type window layer. The P-type window layer comprises AlGaInP-based reverse polarity vertical light-emitting diode chips ... x Ga 0.5‑ x In 0.5 P sublayer and Al α Ga 0.5‑α In 0.5 P sublayer, Al x Ga 0.5‑ x In 0.5 P sublayer and Al α Ga 0.5‑α In 0.5 The P sublayers are doped with Mg or Zn, Al α Ga 0.5‑α In 0.5 The bandgap of the P sublayer is larger than that of the Al x Ga 0.5‑x In 0.5 The bandgap width of the P sublayer, Al α Ga 0.5‑α In 0.5 The doping concentration of Mg or Zn in the P sublayer is greater than that of Al x Ga 0.5‑x In 0.5 The doping concentration of the Mg element or the Zn element in the P sublayer can improve the light extraction rate of the LED device and improve the external quantum rate.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to an AlGaInP-based reverse polarity vertical light-emitting diode chip and a preparation method thereof. Background Art

[0002] LED chips have two basic structures: horizontal and vertical. The so-called horizontal structure LED chip refers to the chip with two electrodes on the same side of the epitaxial wafer. Since the electrodes are on the same side, the current flows horizontally in the n-type restriction layer and the p-type restriction layer, which is not conducive to the diffusion of current and the dissipation of heat. On the contrary, the vertical structure LED chip refers to the two electrodes distributed on the opposite sides of the epitaxial wafer, with the patterned electrode and the entire p-type restriction layer as the second electrode, so that the current almost all flows vertically through the LED epitaxial layer, and very little current flows horizontally.

[0003] The common structure of the LED reverse polarity vertical chip of AlGaInP material includes P electrode, substrate, bonding layer, reflective layer, SiO2 layer, P-type ohmic contact layer, P-type window layer, P-type confinement layer, active layer, N-type confinement layer, N-type window layer, N-type ohmic contact layer, and N electrode from bottom to top.

[0004] In the prior art, when light is emitted from the active layer, the light-emitting surface is on the P-type semiconductor side, and most of the light is absorbed by the thicker P-type GaP window layer, so that the light cannot be effectively emitted, resulting in reduced light extraction efficiency and high growth costs; and thinning the current expansion layer will affect the lateral expansion of the current, causing a significant drop in the light extraction rate and poor results. Summary of the invention

[0005] In view of the deficiencies of the prior art, the present invention aims to provide an AlGaInP-based reverse polarity vertical light emitting diode chip, aiming to solve the technical problems mentioned in the background technology.

[0006] In order to achieve the above object, the present invention is implemented by the following technical solutions:

[0007] An AlGaInP-based reverse polarity vertical light-emitting diode chip comprises a substrate, an intermediate layer, a P-type semiconductor layer, an active layer and an N-type semiconductor layer arranged in sequence from bottom to top, wherein the P-type semiconductor layer comprises a P-type window layer, and the P-type window layer comprises AlGaInP-based reverse polarity vertical light-emitting diode chips, comprising ... x Ga 0.5-x In 0.5 P sublayer and Al α Ga 0.5-α In 0.5 P sublayer, the Al x Ga 0.5- x In 0.5The P sublayer and the Al α Ga 0.5-α In 0.5 The P sublayers are doped with Mg or Zn elements. α Ga 0.5-α In 0.5 The bandgap of the P sublayer is larger than that of the Al x Ga 0.5-x In 0.5 The bandgap width of the P sublayer, the Al α Ga 0.5-α In 0.5 The doping concentration of Mg or Zn in the P sublayer is greater than that of the Al x Ga 0.5-x In 0.5 The doping concentration of Mg or Zn in the P sublayer.

[0008] According to one aspect of the above technical solution, the Al α Ga 0.5-α In 0.5 In the P sublayer, 0< a ≤0.5, the Al x Ga 0.5-x In 0.5 In the P sublayer, 0≤x<0.5.

[0009] According to one aspect of the above technical solution, the Al x Ga 0.5-x In 0.5 The P sublayer and the Al α Ga 0.5-α In 0.5 The thickness of the P sublayer is 5nm~50nm. x Ga 0.5-x In 0.5 The P sublayer and the Al α Ga 0.5-α In 0.5 The number of stacking periods of the P sublayer is 2 to 25, and the Al x Ga 0.5-x In 0.5 The P sublayer and the Al α Ga 0.5-α In 0.5 The total thickness of the P sublayer is 25nm~45nm.

[0010] According to one aspect of the above technical solution, the Al x Ga 0.5-x In 0.5 The doping concentration of Mg or Zn in the P sublayer is 1×10 16atoms / cm 3 ~1×10 20 atoms / cm 3 , the Al α Ga 0.5-α In 0.5 The doping concentration of Mg or Zn in the P sublayer is 1×10 17 atoms / cm 3 ~1×10 21 atoms / cm 3 .

[0011] According to one aspect of the above technical solution, the AlGaInP-based reverse polarity vertical light-emitting diode chip further includes a P electrode prepared below the substrate and an N electrode prepared above the N-type semiconductor layer.

[0012] According to one aspect of the above technical solution, the P-type semiconductor layer further includes a P-type ohmic contact layer and a P-type confinement layer arranged from bottom to top, and the P-type window layer is located between the P-type ohmic contact layer and the P-type confinement layer.

[0013] According to one aspect of the above technical solution, the N-type semiconductor layer includes an N-type confinement layer, an N-type window layer and an N-type ohmic contact layer arranged from bottom to top.

[0014] According to one aspect of the above technical solution, the intermediate layer includes a bonding layer, a mirror reflection layer and a SiO2 layer arranged from bottom to top.

[0015] The present invention also provides a method for preparing an AlGaInP-based reverse polarity vertical light-emitting diode chip, comprising the following steps:

[0016] providing a substrate;

[0017] Depositing a transition layer, an N-type semiconductor layer, an active layer, a P-type semiconductor layer and an intermediate layer in sequence on the substrate;

[0018] The P-type semiconductor layer includes a P-type window layer, and the P-type window layer includes Al x Ga 0.5-x In 0.5 P sublayer and Al α Ga 0.5-α In 0.5 P sublayer, the Al α Ga 0.5-α In 0.5 The bandgap of the P sublayer is larger than that of the Al x Ga 0.5-x In 0.5 The bandgap width of the P sublayer, the Al α Ga0.5-α In 0.5 The doping concentration of Mg or Zn in the P sublayer is greater than that of the Al x Ga 0.5-x In 0.5 Doping concentration of Mg or Zn element in the P sublayer;

[0019] The transition layer is peeled off and removed, and the N-type semiconductor layer, the active layer, the P-type semiconductor layer and the intermediate layer are turned over as a whole, so that the intermediate layer contacts the substrate;

[0020] A P electrode is prepared below the substrate, and an N electrode is prepared above the N-type semiconductor layer to form an AlGaInP-based reverse polarity vertical light-emitting diode chip.

[0021] According to one aspect of the above technical solution, the method for preparing the P-type window layer includes:

[0022] S1, set the temperature of the reaction chamber to 650℃~750℃, use TMAl as Al source, TMGa as Ga source, TMIn as In source, PH3 as P source, Mg element or Zn element as dopant, and grow Al with a thickness of 5nm~50nm x Ga 0.5-x In 0.5 P sublayer, 0≤x<0.5, wherein the Al x Ga 0.5-x In 0.5 The doping concentration of Mg or Zn in the P sublayer is 1×10 16 atoms / cm 3 ~1×10 20 atoms / cm 3 ;

[0023] S2, set the reaction chamber temperature to 600℃~700℃, use TMAl as Al source, TMGa as Ga source, TMIn as In source, PH3 as P source, Mg element or Zn element as dopant, and grow Al with a thickness of 5nm~50nm α Ga 0.5-α In 0.5 P sublayer, 0< a ≤0.5, wherein the Al α Ga 0.5-α In 0.5 The doping concentration of Mg or Zn in the P sublayer is 1×10 17 atoms / cm 3 ~1×10 21 atoms / cm 3 ;

[0024] Repeat steps S1 to S2 to periodically prepare n Al x Ga 0.5-x In 0.5 The P sublayer and the Al α Ga 0.5-α In 0.5 A stack of P sublayers, where 2≤n≤25.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The P-type window layer has a superlattice current expansion structure, which is composed of alternately arranged Al2O3 layers with inconsistent bandgap widths. x Ga 0.5-x In 0.5 P sublayer and Al α Ga 0.5-α In 0.5 The P sublayer can make the light emitted by the multi-quantum well layer less absorbed by the epitaxial layer, thereby improving the light extraction efficiency; while the Al x Ga 0.5-x In 0.5 The P sublayer has lower Mg or Zn doping, and relatively high In and Ga components make the Al α Ga 0.5-α In 0.5 The P sublayer has a smaller bandgap, which increases the electron x Ga 0.5-x In 0.5 The migration rate of the P sublayer is larger than that of Al α Ga 0.5-α In 0.5 The P sublayer has a higher Mg or Zn doping and a relatively low In and Ga composition, making the Al α Ga 0.5-α In 0.5 The P sublayer has a larger bandgap and improves the Al x Ga 0.5-x In 0.5 The electron lateral diffusion ability of the P sublayer and the alternating growth structure of the two can significantly improve the lateral current expansion ability of the device and improve the antistatic ability of the device;

[0027] 2. In the P-type window layer, Al x Ga 0.5-x In 0.5 P sublayer and Al α Ga 0.5-α In 0.5The P sublayer forms a superlattice structure with high and low bandgap widths interspersed and grown alternately, which greatly improves the lateral expansion capability and migration data of the current. A thinner growth thickness can be used to achieve a higher electron expansion capability. The current expansion layer is greatly thinned, which reduces the absorption rate of the emitted light, increases the light output rate, increases the external quantum rate, and greatly reduces the cost of raw materials and the cost of growth time. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0029] Figure 1 It is a schematic structural diagram of an AlGaInP-based reverse polarity vertical light-emitting diode chip in the first embodiment of the present invention;

[0030] Figure 2 It is a schematic flow chart of a method for preparing an AlGaInP-based reverse polarity vertical light-emitting diode chip in a second embodiment of the present invention;

[0031] Description of main structural symbols:

[0032] 14, P electrode; 13, substrate; 12, bonding layer; 11, mirror reflection layer; 16, SiO2 layer; 10, P-type ohmic contact layer; 9, P-type window layer; 8, P-type confinement layer; 7, active layer; 6, N-type confinement layer; 5, N-type window layer; 4, N-type ohmic contact layer; 15, N electrode; 91, Al x Ga 0.5-x In 0.5 P sublayer; 92, Al α Ga 0.5-α In 0.5 P sublayer.

[0033] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0034] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0035] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0037] Embodiment 1

[0038] See also Figure 1 , which is an AlGaInP-based reverse polarity vertical light-emitting diode chip in the first embodiment of the present invention, comprises a substrate 13, an intermediate layer, a P-type semiconductor layer, an active layer 7 and an N-type semiconductor layer arranged in sequence from bottom to top, wherein the P-type semiconductor layer comprises a P-type window layer 9, wherein the P-type window layer 9 comprises Al x Ga 0.5- x In 0.5 P sublayer 91 and Al α Ga 0.5-α In 0.5 The P sublayer 92, the Al x Ga 0.5-x In 0.5 The P sublayer 91 and the Al α Ga 0.5-α In 0.5 The P sublayer 92 is doped with Mg or Zn. α Ga 0.5-α In 0.5 The bandgap of the P sublayer 92 is greater than that of the Al x Ga 0.5-x In 0.5 The bandgap width of the P sublayer 91 is α Ga 0.5-α In 0.5 The doping concentration of the Mg element or Zn element in the P sublayer 92 is greater than that of the Al x Ga 0.5-x In 0.5 The doping concentration of the P sublayer 91 is the Mg element or the Zn element.

[0039] It can be understood that the present invention provides the P-type window layer 9 with a superlattice current expansion structure, wherein the superlattice current expansion structure is composed of alternately arranged Al x Ga 0.5-x In 0.5 P sublayer 91 and Al α Ga 0.5-α In 0.5 The P sublayer 92 can make the light emitted by the multi-quantum well layer less absorbed by the epitaxial layer, thereby improving the light extraction efficiency; and the Al x Ga 0.5-x In 0.5 The P sublayer 91 has lower Mg or Zn doping, and relatively high In and Ga components make the Al α Ga 0.5-α In 0.5 The P sublayer 92 has a smaller bandgap, which increases the electron x Ga 0.5-x In 0.5 The migration rate of the P sublayer 91 is greater than that of the Al α Ga 0.5-α In 0.5 The P sublayer 92 has a higher Mg or Zn doping and a relatively low In and Ga composition, making the Al α Ga 0.5-α In 0.5 The P sublayer 92 has a larger bandgap and improves the Al x Ga 0.5-x In 0.5 The electron lateral diffusion capability of the P sublayer 91, the alternating growth structure of the two can significantly improve the lateral current expansion capability of the device and improve the antistatic capability of the device;

[0040] In the P-type window layer 9, Al x Ga 0.5-x In 0.5 P sublayer 91 and Al α Ga 0.5-α In 0.5 The P sublayer 92 forms a superlattice structure with high and low bandgap widths interspersed and grown alternately, which greatly improves the lateral expansion capability and migration data of the current. A thinner growth thickness can be used to achieve a higher electron expansion capability. The current expansion layer is greatly thinned, which reduces the absorption rate of the emitted light, increases the light output rate, increases the external quantum rate, and greatly reduces the cost of raw materials and the cost of growth time.

[0041] Preferably, both the upper and lower sides of the P-type window layer 9 are made of Al x Ga 0.5-x In 0.5 P sublayer 91.

[0042] It can be understood that this design can increase the electron migration rate between interfaces.

[0043] Furthermore, in the Al α Ga 0.5-α In 0.5 In the P sublayer 92, 0 < a ≤0.5, in the Al x Ga 0.5-x In 0.5 In the P sublayer 91, 0≤x<0.5.

[0044] Furthermore, the Al x Ga 0.5-x In 0.5 The P sublayer 91 and the Al α Ga 0.5-α In 0.5 The thickness of the P sublayer 92 is 5nm~50nm. x Ga 0.5-x In 0.5 The P sublayer 91 and the Al α Ga 0.5-α In 0.5 The number of stacking cycles of the P sublayer 92 is 2 to 25, and the Al x Ga 0.5-x In 0.5 The P sublayer 91 and the Al α Ga 0.5-α In 0.5 The total thickness of the P sublayer 92 is 25 nm to 45 nm.

[0045] Furthermore, the Al x Ga 0.5-x In 0.5 The doping concentration of Mg or Zn in the P sublayer 91 is 1×10 16 atoms / cm 3 ~1×10 20 atoms / cm 3 , the Al α Ga 0.5-α In 0.5 The doping concentration of Mg or Zn in the P sublayer 92 is 1×10 17 atoms / cm 3 ~1×10 21 atoms / cm 3 .

[0046] Specifically, the AlGaInP-based reverse polarity vertical light-emitting diode chip also includes a P electrode 14 prepared below the substrate 13 and an N electrode 15 prepared above the N-type semiconductor layer; the P-type semiconductor layer also includes a P-type ohmic contact layer 10 and a P-type confinement layer 8 arranged from bottom to top, and the P-type window layer 9 is located between the P-type ohmic contact layer 10 and the P-type confinement layer 8; the N-type semiconductor layer includes an N-type confinement layer 6, an N-type window layer 5 and an N-type ohmic contact layer 4 arranged from bottom to top; the intermediate layer includes a bonding layer 12, a mirror reflection layer 11 and a SiO2 layer 16 arranged from bottom to top.

[0047] In summary, the AlGaInP-based reverse polarity vertical light-emitting diode chip described above in this embodiment can significantly improve the lateral current expansion capability of the device, improve the anti-static ability of the device, and can use a thinner growth thickness to achieve a higher electron expansion capability. The current expansion layer is greatly thinned, which reduces the absorption of emitted light, improves the light extraction rate, improves the external quantum yield, and greatly reduces the raw material and production costs.

[0048] Embodiment 2

[0049] Please refer to Figure 2 , shown is a method for preparing an AlGaInP-based reverse polarity vertical light-emitting diode chip in a second embodiment of the present invention, comprising the following steps S10 to S40:

[0050] S10, providing a substrate;

[0051] Exemplarily, the substrate is a Si substrate or a sapphire substrate with a thickness of 200 nm to 500 nm. In this embodiment, a Si substrate is selected, and the thickness takes a median value of 350 nm.

[0052] S20, depositing a transition layer, an N-type semiconductor layer, an active layer, a P-type semiconductor layer and an intermediate layer on the substrate in sequence;

[0053] The transition layer comprises an N-type GaAs substrate, a GaAs buffer layer, and a GaInP etching stop layer;

[0054] Specifically, an N-type GaAs substrate is prepared on a Si substrate;

[0055] The temperature of the reaction chamber was controlled at 600℃~700℃, TMGa was used as Ga source, AsH3 as As source, and Si2H6 as dopant to grow a GaAs buffer layer with a thickness of 50nm~300nm on an N-type GaAs substrate, where the Si doping concentration was 1×10 17 atoms / cm 3 ~1×10 19 atoms / cm 3In this embodiment, the values ​​of this step are all intermediate values.

[0056] The temperature of the reaction chamber was controlled at 650℃~750℃, TMGa was used as Ga source, TMIn as In source, PH3 as P source, Si2H6 as dopant, and a GaInP etching stop layer with a thickness of 200nm~800nm ​​was grown on the GaAs buffer layer, where the Si doping concentration was 1×10 17 atoms / cm 3 ~1×10 19 atoms / cm 3 In this embodiment, the values ​​of this step are all intermediate values.

[0057] The N-type semiconductor layer includes an N-type ohmic contact layer, an N-type window layer and an N-type confinement layer.

[0058] Specifically, the temperature of the reaction chamber is controlled at 650°C to 700°C, TMGa is used as the Ga source, AsH3 is used as the As source, and Si2H6 is used as the dopant, and an N-type GaAs ohmic contact layer with a thickness of 50nm to 200nm is grown on the GaInP corrosion cutoff layer, wherein the Si doping concentration is 1×10 18 atoms / cm 3 ~1×10 19 atoms / cm 3 In this embodiment, the values ​​of this step are all intermediate values.

[0059] The temperature of the reaction chamber was controlled at 620℃~720℃, TMAl was used as Al source, TMGa as Ga source, AsH3 as As source, and Si as dopant to grow an N-type GaN window layer with a thickness of 100nm~260nm on the N-type ohmic contact layer, where the Si doping concentration was 1×10 17 atoms / cm 3 ~1×10 19 atoms / cm 3 In this embodiment, the values ​​of this step are all intermediate values.

[0060] The temperature of the reaction chamber was controlled at 650℃~750℃, TMAl was used as Al source, TMIn as In source, PH3 as P source, Si2H6 as dopant, and an N-type AlInP confinement layer with a thickness of 100nm~400nm was grown on the N-type window layer, where the Si doping concentration was 1×10 18 atoms / cm 3 ~1×10 19 atoms / cm 3 In this embodiment, the values ​​of this step are all intermediate values.

[0061] The temperature of the reaction chamber is controlled at 620°C~720°C, TMAl is used as the Al source, TMGa is used as the Ga source, TMIn is used as the In source, and PH3 is used as the P source. An AlGaInP barrier layer with a thickness of 60Å~200Å is grown on the N-type confinement layer, and a GaInP well layer with a thickness of 30Å~80Å is grown. The alternating arrangement period is 8-18. In this embodiment, the values ​​taken in this step are all intermediate values.

[0062] The P-type semiconductor layer includes a P-type confinement layer, a P-type window layer and a P-type ohmic contact layer;

[0063] Specifically, the temperature of the reaction chamber is controlled at 700°C to 800°C, TMAl is used as the Al source, TMIn is used as the In source, PH3 is used as the P source, and Mg or Zn is used as the dopant to grow a P-type AlInP confinement layer with a thickness of 100nm to 400nm on the active layer, wherein the Mg or Zn doping concentration is 1×10 17 atoms / cm 3 ~1×10 19 atoms / cm 3 In this embodiment, the values ​​of this step are all intermediate values, and Mg is used as the doping agent.

[0064] S1, set the temperature of the reaction chamber to 650℃~750℃, use TMAl as Al source, TMGa as Ga source, TMIn as In source, PH3 as P source, Mg element or Zn element as dopant, and grow Al with a thickness of 5nm~50nm on the P-type confinement layer. x Ga 0.5-x In 0.5 P sublayer, 0≤x<0.5, wherein the Al x Ga 0.5-x In 0.5 The doping concentration of Mg or Zn in the P sublayer is 1×10 16 atoms / cm 3 ~1×10 20 atoms / cm 3 In this embodiment, the reaction chamber temperature is 700°C, the growth thickness is 20 nm, x is 0, and Mg doping is selected with a doping concentration of 1×10 18 atoms / cm 3 ;

[0065] S2, set the reaction chamber temperature to 600℃~700℃, use TMAl as Al source, TMGa as Ga source, TMIn as In source, PH3 as P source, Mg element or Zn element as dopant, and grow Al with a thickness of 5nm~50nm α Ga0.5-α In 0.5 P sublayer, 0< a ≤0.5, wherein the Al α Ga 0.5-α In 0.5 The doping concentration of Mg or Zn in the P sublayer is 1×10 17 atoms / cm 3 ~1×10 21 atoms / cm 3 In this embodiment, the reaction chamber temperature is 650°C and the growth thickness is 20nm. a Take 0.05, select Mg doping, and the doping concentration is 1×10 19 atoms / cm 3 ;

[0066] Repeat steps S1 to S2 to periodically prepare n Al x Ga 0.5-x In 0.5 The P sublayer and the Al α Ga 0.5-α In 0.5 A stack of P sublayers, wherein 2≤n≤25, in this embodiment, n=10.

[0067] The temperature of the reaction chamber was controlled at 550℃~700℃, the pressure of the reaction chamber was controlled at 50mbar~90mbar, TMGa was used as the Ga source, PH3 was used as the P source, and a carbon-doped P-type GaP ohmic contact layer with a thickness of 50nm~200nm was grown on the P-type window layer, where the carbon doping concentration was 1×10 20 atoms / cm 3 ~1×10 22 atoms / cm 3 In this embodiment, the values ​​of this step are all intermediate values.

[0068] The intermediate layer includes a SiO2 layer, a mirror reflection layer and a bonding layer;

[0069] Specifically, through chemical vapor deposition (CVD), the reaction chamber is controlled at 150°C~500°C, SiH4 is used as the Si source, O2 is used as the O source, and a SiO2 layer with a thickness of 50nm~300nm is grown on the P-type ohmic contact layer; and conductive holes are punched, the depth of the conductive holes is equal to the thickness of the SiO2 layer, exposing the P-type window layer. In this embodiment, the values ​​of this step are all intermediate values.

[0070] The Au layer evaporated at high temperature is used as the Au reflective mirror, which grows from the bottom of the conductive hole and covers the SiO2 layer to form a mirror reflective layer. The reaction temperature is maintained at 550°C~700°C, and the growth thickness is 100 nm~600nm. In this embodiment, the values ​​of this step are all intermediate values.

[0071] Ti, Pt, and Au alloys are deposited on the mirror reflection layer in a high-temperature, high-pressure, and vacuum environment to bond the Si substrate to form a bonding layer. The reaction temperature is maintained at 550°C to 700°C, and the growth thickness is 150 nm to 800 nm. In this embodiment, the values ​​of this step are all intermediate values.

[0072] S30, removing the transition layer by stripping, and turning over the N-type semiconductor layer, the active layer, the P-type semiconductor layer and the intermediate layer as a whole, so that the intermediate layer contacts the substrate;

[0073] Specifically, in this embodiment, the N-type GaAs substrate, the GaAs buffer layer, and the GaInP etching stop layer are stripped and removed, and the N-type semiconductor layer, the active layer, the P-type semiconductor layer, and the intermediate layer are turned over as a whole, so that the intermediate layer contacts the Si substrate;

[0074] S40, preparing a P electrode under the substrate and an N electrode above the N-type semiconductor layer to form an AlGaInP-based reverse polarity vertical light-emitting diode chip;

[0075] Specifically, a P electrode is prepared under the Si substrate. The P electrode is obtained by evaporating Ti and Au alloy with a growth thickness of 150nm~600nm. Au is used to make an N electrode for the exposed N-type ohmic contact layer with a thickness of 800nm~2550nm. In this embodiment, the values ​​of this step are all intermediate values.

[0076] The AlGaInP-based reverse polarity vertical light emitting diode chip can be obtained through the above steps. Compared with the existing vertical light emitting diode chip, the brightness of the AlGaInP-based reverse polarity vertical light emitting diode chip in the present invention is improved by 0.6%.

[0077] The present invention also provides more groups of experimental data, as shown in the following table:

[0078]

[0079] It can be seen from the above table that in the current experimental process, the AlGaInP-based reverse polarity vertical light-emitting diode chip in the present invention can increase the brightness by at least 0.4% and at most 0.6%. It should be noted that in the above experimental data, except for the parameters in the table that have been adjusted, the other parameters are consistent with the parameters in the second embodiment.

[0080] In summary, the AlGaInP-based reverse polarity vertical light emitting diode chip prepared by the preparation method of the AlGaInP-based reverse polarity vertical light emitting diode chip in this embodiment;

[0081] 1. The light intensity emitted by the multi-quantum wells is improved, the problem of poor light extraction efficiency is solved, and the brightness of the prepared LED device is improved.

[0082] 2. Enhanced the lateral current expansion capability of LED devices, solved the problem of weak anti-static ability of devices, and reduced the operating voltage.

[0083] 3. Reduce production costs such as raw materials and production time.

[0084] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0085] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An AlGaInP-based reverse polarity vertical light-emitting diode chip, characterized in that: The invention comprises a substrate, an intermediate layer, a P-type semiconductor layer, an active layer and an N-type semiconductor layer arranged in sequence from bottom to top, wherein the P-type semiconductor layer comprises a P-type window layer, and the P-type window layer comprises Al x Ga 0.5-x In 0.5 P sublayer and Al α Ga 0.5-α In 0.5 P sublayer, the Al x Ga 0.5-x In 0.5 The P sublayer and the Al α Ga 0.5-α In 0.5 The P sublayers are doped with Mg or Zn elements. α Ga 0.5-α In 0.5 The bandgap of the P sublayer is larger than that of the Al x Ga 0.5-x In 0.5 The bandgap width of the P sublayer, the Al α Ga 0.5-α In 0.5 The doping concentration of Mg or Zn in the P sublayer is greater than that of the Al x Ga 0.5-x In 0.5 The doping concentration of Mg or Zn in the P sublayer.

2. The AlGaInP-based reverse polarity vertical light-emitting diode chip according to claim 1, characterized in that: The Al α Ga 0.5-α In 0.5 In the P sublayer, 0< a ≤0.5, the Al x Ga 0.5-x In 0.5 In the P sublayer, 0≤x<0.

5.

3. The AlGaInP-based reverse polarity vertical light-emitting diode chip according to claim 1, characterized in that: The Al x Ga 0.5-x In 0.5 The P sublayer and the Al α Ga 0.5-α In 0.5 The thickness of the P sublayer is 5nm~50nm. x Ga 0.5-x In 0.5 The P sublayer and the Al α Ga 0.5-α In 0.5 The number of stacking periods of the P sublayer is 2 to 25, and the Al x Ga 0.5-x In 0.5 The P sublayer and the Al α Ga 0.5-α In 0.5 The total thickness of the P sublayer is 25nm~45nm.

4. The AlGaInP-based reverse polarity vertical light-emitting diode chip according to claim 1, characterized in that: The Al x Ga 0.5-x In 0.5 The doping concentration of Mg or Zn in the P sublayer is 1×10 16 atoms / cm 3 ~1×10 20 atoms / cm 3 , the Al α Ga 0.5-α In 0.5 The doping concentration of Mg or Zn in the P sublayer is 1×10 17 atoms / cm 3 ~1×10 21 atoms / cm 3 .

5. The AlGaInP-based reverse polarity vertical light emitting diode chip according to claim 1, characterized in that: The AlGaInP-based reverse polarity vertical light-emitting diode chip further includes a P electrode prepared below the substrate and an N electrode prepared above the N-type semiconductor layer.

6. The AlGaInP-based reverse polarity vertical light-emitting diode chip according to claim 1, characterized in that: The P-type semiconductor layer further includes a P-type ohmic contact layer and a P-type confinement layer arranged from bottom to top, and the P-type window layer is located between the P-type ohmic contact layer and the P-type confinement layer.

7. The AlGaInP-based reverse polarity vertical light emitting diode chip according to claim 1, characterized in that: The N-type semiconductor layer includes an N-type confinement layer, an N-type window layer and an N-type ohmic contact layer arranged from bottom to top.

8. The AlGaInP-based reverse polarity vertical light emitting diode chip according to claim 1, characterized in that: The intermediate layer includes a bonding layer, a mirror reflection layer and a SiO2 layer arranged from bottom to top.

9. A method for preparing an AlGaInP-based reverse polarity vertical light-emitting diode chip, characterized in that: The steps include: providing a substrate; Depositing a transition layer, an N-type semiconductor layer, an active layer, a P-type semiconductor layer and an intermediate layer in sequence on the substrate; The P-type semiconductor layer includes a P-type window layer, and the P-type window layer includes Al x Ga 0.5-x In 0.5 P sublayer and Al α Ga 0.5-α In 0.5 P sublayer, the Al α Ga 0.5-α In 0.5 The bandgap of the P sublayer is larger than that of the Al x Ga 0.5-x In 0.5 The bandgap width of the P sublayer, the Al α Ga 0.5-α In 0.5 The doping concentration of Mg or Zn in the P sublayer is greater than that of the Al x Ga 0.5-x In 0.5 Doping concentration of Mg or Zn element in the P sublayer; The transition layer is peeled off and removed, and the N-type semiconductor layer, the active layer, the P-type semiconductor layer and the intermediate layer are turned over as a whole, so that the intermediate layer contacts the substrate; A P electrode is prepared below the substrate, and an N electrode is prepared above the N-type semiconductor layer to form an AlGaInP-based reverse polarity vertical light emitting diode chip.

10. The method for preparing the AlGaInP-based reverse polarity vertical light emitting diode chip according to claim 9, characterized in that: The preparation method of the P-type window layer comprises: S1, set the temperature of the reaction chamber to 650℃~750℃, use TMAl as Al source, TMGa as Ga source, TMIn as In source, PH3 as P source, Mg element or Zn element as dopant, and grow Al with a thickness of 5nm~50nm x Ga 0.5-x In 0.5 P sublayer, 0≤x<0.5, wherein the Al x Ga 0.5-x In 0.5 The doping concentration of Mg or Zn in the P sublayer is 1×10 16 atoms / cm 3 ~1×10 20 atoms / cm 3 ; S2, set the reaction chamber temperature to 600℃~700℃, use TMAl as Al source, TMGa as Ga source, TMIn as In source, PH3 as P source, Mg element or Zn element as dopant, and grow Al with a thickness of 5nm~50nm α Ga 0.5-α In 0.5 P sublayer, 0< a ≤0.5, wherein the Al α Ga 0.5-α In 0.5 The doping concentration of Mg or Zn in the P sublayer is 1×10 17 atoms / cm 3 ~1×10 21 atoms / cm 3 ; Repeat steps S1 to S2 to periodically prepare n Al x Ga 0.5-x In 0.5 The P sublayer and the Al α Ga 0.5-α In 0.5 A stack of P sublayers, where 2≤n≤25.

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