Routing Path Determination Method and Related Devices

Abstract

An embodiment of the present invention provides a routing path determination method and related device. Among them, the routing path determination method includes: determining an initial identification chip among the multiple chips and using the initial identification chip as the current chip; transmitting an incremented logical identification value from the current chip to the next chip connected thereto; using the next chip that obtains the incremented logical identification value as the current chip, and when the logical identification value of the current chip has been configured, determining the total number of chips in the ring interconnect structure based on the incremented logical identification value; determining the routing paths between the chips in the ring interconnect structure based on the logical identification values of the chips and the total number of chips. The routing path determination method provided by the embodiment of the present invention realizes the determination of the routing paths between the chips based on the logical identification values of the chips after transmission and configuration and the total number of chips in the case where the number of chips in the ring interconnect structure and the logical identification of each chip cannot be determined in advance.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of integrated circuit technology, and particularly to a method for determining a routing path and related devices. Background Art

[0002] In the field of integrated circuits, the ring interconnect structure has been widely used in various high-performance computing and communication systems due to its advantages such as simple structure, compact layout, and easy implementation of synchronous clock distribution.

[0003] Multi-chip ring interconnect can be the interconnect of multiple single-chip packages (Single Chip Module, SCM), or the interconnect of one or more homogeneous multi-chip packages (Multi-Chip Module, MCM), or the interconnect of one or more heterogeneous multi-chip packages (System in Package, SIP). In a multi-chip ring interconnect structure, there are two routing paths between any two chips. To improve communication efficiency, it is necessary to calculate the lengths of these two paths respectively and select the shorter path.

[0004] However, for the ring interconnect structure, the applicability of existing routing path determination methods is insufficient. Summary of the Invention

[0005] The technical problem to be solved by the embodiments of the present invention is the problem that the routing path determination method is not applicable in the scenario where the number of chips and the logical identifiers of each chip in the ring interconnect structure cannot be determined in advance.

[0006] To solve the above technical problem, the embodiments of the present invention provide the following technical solutions.

[0007] In a first aspect, an embodiment of the present invention provides a method for determining a routing path, which is applied to a ring interconnect structure. The ring interconnect structure includes a plurality of chips connected in sequence to form a ring, and the method includes:

[0008] Determine an initial identification chip of the ring interconnect structure among the plurality of chips, configure the logical identifier value of the initial identification chip as an initial value, and use the initial identification chip as the current chip;

[0009] Transmit an incremented logical identifier value from the current chip to the next chip connected thereto, and the incremented logical identifier value corresponding to the next chip is the value after incrementing the logical identifier value corresponding to the current chip by a preset value;

[0010] Take the next chip for obtaining the next incremental logic identification value as the current chip, determine whether the logic identification value of the current chip has been configured, if not, configure the incremental logic identification value to the current chip, and execute the step of transmitting the incremental logic identification value from the current chip to the next chip connected thereto; if so, determine the total number of chips in the ring interconnect structure based on the incremental logic identification value;

[0011] Based on the logic identification values of the chips in the ring interconnect structure and the total number of chips, determine the routing paths between the chips in the ring interconnect structure.

[0012] In a second aspect, an embodiment of the present invention provides a routing path determination device, which is applied to each chip connected in sequence to form a ring in a ring interconnect structure, and includes:

[0013] An initial identification chip determination module, configured to determine the initial identification chip of the ring interconnect structure among the multiple chips, configure the logic identification value of the initial identification chip to an initial value, and use the initial identification chip as the current chip;

[0014] A logical node number transmission module, configured to transmit an incremental logic identification value from the current chip to the next chip connected thereto, and the incremental logic identification value corresponding to the next chip is the value after the logic identification value corresponding to the current chip is incremented by a preset value;

[0015] A logical node number configuration module, configured to take the next chip for obtaining the incremental logic identification value as the current chip, determine whether the logic identification value of the current chip has been configured, if not, configure the incremental logic identification value to the current chip, and execute the step of transmitting the incremental logic identification value from the current chip to the next chip connected thereto; if so, determine the total number of chips in the ring interconnect structure based on the incremental logic identification value;

[0016] A routing path determination module, configured to determine the routing paths between the chips in the ring interconnect structure based on the logic identification values of the chips in the ring interconnect structure and the total number of chips.

[0017] In a third aspect, an embodiment of the present invention provides a computing device, the computing device includes a memory and a processor, the memory stores computer instructions, and the processor calls the computer instructions stored in the memory to execute the routing path determination method as described in the first aspect.

[0018] In a fourth aspect, an embodiment of the present invention provides a storage medium, the storage medium stores computer instructions, and the computer instructions, when executed, implement the routing path determination method as described in the first aspect.

[0019] Fifth aspect, an embodiment of the present invention provides a computer program product, which includes computer instructions that, when executed, implement the routing path determination method as described in the first aspect.

[0020] An embodiment of the present invention provides a routing path determination method. In a scenario where the number of chips and the logical identifiers of the chips in a ring interconnect structure cannot be determined in advance, first, an initial identification chip of the ring interconnect structure is determined among the multiple chips, and starting from the initial identification chip, incrementing logical identifier values are sequentially transmitted to each chip in the ring interconnect structure; when the logical identifier value of the chip that obtains the incrementing logical identifier value has been configured, the total number of chips in the ring interconnect structure is determined based on the incrementing logical identifier value, that is, the logical identifiers of the unknown chips in the ring interconnect structure are determined; the total number of chips in the ring interconnect structure is determined based on the incrementing logical identifier value, that is, the number of unknown chips in the ring interconnect structure is determined; finally, based on the logical identifier values of the chips in the ring interconnect structure and the total number of chips, the routing paths between the chips in the ring interconnect structure are determined, realizing the determination of the routing paths between the chips in the ring interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0022] Figure 1 is a flowchart of a routing path determination method provided by an embodiment of the present invention.

[0023] Figure 2 is another flowchart of a routing path determination method provided by an embodiment of the present invention.

[0024] Figure 3 is a schematic diagram of the initial state of a ring interconnect structure provided by an embodiment of the present invention.

[0025] Figure 4 is a schematic diagram of the process of a routing path determination method provided by an embodiment of the present invention.

[0026] Figure 5 is a schematic diagram of the initial state of a ring interconnect structure composed of multiple single-chip packages provided by an embodiment of the present invention.

[0027] Figure 6 is a schematic diagram of the initial state of a ring interconnect structure composed of a single homogeneous multi-chip package provided by an embodiment of the present invention.

[0028] Figure 7 It is a schematic diagram of the initial state of a ring interconnect structure composed of multiple homogeneous multi-chip packages provided by an embodiment of the present invention.

[0029] Figure 8 It is a schematic diagram of the initial state of a ring interconnect structure composed of multiple heterogeneous multi-chip packages provided by an embodiment of the present invention.

[0030] Figure 9 It is a schematic diagram of a routing path determination device provided by an embodiment of the present invention. Detailed implementation manners

[0031] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0032] In the field of integrated circuits, the ring interconnect structure has been widely used in various high-performance computing and communication systems due to its advantages such as simple structure, compact layout, and easy implementation of synchronous clock distribution. In a multi-chip ring interconnect structure, there are 2 routing paths between any two chips. To improve communication efficiency, it is necessary to calculate the lengths of these 2 paths respectively based on the number of chips and the logical identifiers of each chip, and select the shorter path.

[0033] The production and packaging of chips are two key links in integrated circuit manufacturing, which are respectively responsible for by chip manufacturers and motherboard manufacturers. Chip manufacturers can determine the number of chips integrated inside a single package (Package) during the design and manufacturing process; while the external interconnect structure of the package is determined by the motherboard manufacturer. The motherboard manufacturer needs to consider the interconnect method between packages during design. Among them, the number of packages constituting the ring interconnect structure is a key part of motherboard design, which determines the data transmission efficiency and the expansion ability of the system; but chip manufacturers can only define the lead pins of the package, and the motherboard manufacturer interconnects all the chips in a ring and limits the maximum number of supported interconnects.

[0034] It can be seen that for chip manufacturers, the chips inside the package may not be able to know in advance the total number of chips under the entire ring interconnect structure. When the chip supports expansion, that is, allowing one or more packages to be interconnected in a ring, and the logical IDs of the chips in the ring interconnect structure are not pre-specified, the existing routing path determination method cannot calculate the lengths of two paths in the multi-chip ring interconnect structure, nor can it determine the shorter path based on the lengths of these two paths. That is to say, the existing routing path determination method is not applicable to scenarios where the number of chips and the logical identifiers of each chip cannot be determined in advance. Obviously, the applicability of the existing routing path determination method is insufficient.

[0035] In view of this, the embodiments of the present invention provide a routing path determination method. In a scenario where the number of chips and the logical identifiers of the chips in the ring interconnect structure cannot be determined in advance, first, an initial identification chip of the ring interconnect structure is determined, and starting from the initial identification chip, the incremented logical identifier values are sequentially transmitted to each chip in the ring interconnect structure; when the logical identifier value of the chip that obtains the incremented logical identifier value has been configured, the total number of chips in the ring interconnect structure is determined based on the incremented logical identifier value, that is, the logical identifiers of the unknown chips in the ring interconnect structure are determined; the total number of chips in the ring interconnect structure is determined based on the incremented logical identifier value, that is, the number of unknown chips in the ring interconnect structure is determined; finally, based on the logical identifier values of the chips in the ring interconnect structure and the total number of chips, the routing paths between the chips in the ring interconnect structure are determined, realizing the determination of the routing paths between the chips in the ring interconnect structure, thereby providing a routing path determination method with higher applicability.

[0036] The routing path determination method of the embodiments of the present invention will be described in detail below.

[0037] Figure 1 It is a schematic flowchart of a routing path determination method provided by an embodiment of the present invention. Refer to Figure 1 , the routing path determination method includes the following steps:

[0038] Step S100: Determine the initial identification chip of the ring interconnect structure among the multiple chips, configure the logical identifier value of the initial identification chip as an initial value, and use the initial identification chip as the current chip.

[0039] Since the routing path determination method provided by the embodiments of the present invention is applied to a ring interconnect structure, the ring interconnect structure includes multiple chips connected in sequence to form a ring, but the number of chips in the ring interconnect structure and the logical identifiers of each chip are not pre-determined. Therefore, it is necessary to determine an initial identification chip in the ring interconnect structure to provide a technical basis for the process of configuring the logical identifiers of each chip in the subsequent steps.

[0040] Among them, the initial identification chip is a chip whose logical identification value is configured as an initial value, and the initial identification chip is determined by a pre-set initial definition identification. For example, the initial definition identification can be that a specific GPIO (General Purpose Input / Output) pin on the chip is at a high level. In the ring interconnect structure, the initial identification chip will serve as the starting point for configuring the logical identification of each chip in the subsequent steps.

[0041] The logical identification value is a unique and determined identification value assigned to each chip in the ring interconnect structure, and is used to indicate the interconnection relationship of each chip in the ring interconnect structure. In some specific embodiments, the logical identification value is a logical ID (Logic ID). The logical identification values of the chips in the ring interconnect structure are increasing or decreasing numerical values. In some specific embodiments, the logical identification values of the chips in the ring interconnect structure are consecutive integers. For example, 0, 1, 2, …… 8, 9.

[0042] The initial value is used to mark the initial chip, and also serves as the starting value for incrementing the logical identification value. The initial value is also used to determine the total number of chips in the ring interconnect structure. In some specific embodiments, the initial value can be 0; in some other specific embodiments, the initial value can also be set to 1, 2, 3, 4, etc.

[0043] After determining the initial identification chip of the ring interconnect structure, step S110 is continued to be executed.

[0044] Step S110: Transmit the incremented logical identification value from the current chip to the next chip connected thereto, and the incremented logical identification value corresponding to the next chip is the value obtained by incrementing the logical identification value corresponding to the current chip by a preset value.

[0045] After determining the initial identification chip, taking this chip as the current chip, transmit the incremented logical identification value to the next chip of the current chip, that is, starting from the initial identification chip, start the process of transmitting the logical identification value to each chip in the ring interconnect structure. And, in order to ensure the uniqueness and continuity of the logical identification value, before the current chip sends out the incremented logical identification value, it is necessary to increment the logical identification value corresponding to the current chip by a preset value to obtain the incremented logical identification value.

[0046] Among them, transmitting the incremented logical identification value from the current chip to the next chip connected thereto can ensure that each chip connected in sequence to form a ring in the ring interconnect structure can receive the incremented logical identification value in sequence. Since data transmission in the ring interconnect structure can be in the clockwise or counterclockwise direction, by transmitting the incremented logical identification value from the current chip to the next chip connected thereto, it can be ensured that the incremented logical identification value is transmitted to one side of the chips in the ring interconnect structure.

[0047] The incremented logical identification value is the value after the logical identification value of the current chip is incremented by a preset value. The incremented logical identification value can ensure that the incremented logical identification values received by each chip in the ring interconnect structure are uniquely determined. In some specific embodiments, the preset value can be 1. That is to say, the incremented logical identification value is obtained by adding 1 to the logical identification value of the current chip before being sent by the current chip each time. In some other embodiments, the preset value can also be -1, 2, 3, etc., as long as it is ensured that the preset value is not 0.

[0048] Moreover, the incremented logical identification value is also used as the logical identification value of the next chip. And, in some specific embodiments, the chip further includes a temporary transmission register. The transmitting the incremented logical identification value from the current chip to the next chip connected thereto includes: transmitting the incremented logical identification value from the current chip to the temporary transmission register of the next chip connected thereto.

[0049] Before transmitting the incremented logical identification value from the current chip to the next chip connected thereto, each chip in the ring interconnect structure can agree on a memory for temporary transmission, such as a temporary transmission register, to improve the transmission efficiency of the incremented logical identification value. The temporary transmission register is used to receive the incremented logical identification value during the process of transmitting the incremented logical identification value in the ring interconnect structure.

[0050] After transmitting the incremented logical identification value from the current chip to the next chip connected thereto, step S120 is continued to be executed.

[0051] Step S120: Taking the next chip that obtains the incremented logical identification value as the current chip, determining whether the logical identification value of the current chip has been configured. If so, step S130 is executed; if not, step S121 is executed.

[0052] According to the foregoing step S110, the current chip issues an incremented logical identification value. At this time, the next chip connected to the current chip in the ring interconnect structure obtains the incremented logical identification value. In step S120, the next chip that obtains the incremented logical identification value is taken as the current chip, and it is determined whether the logical identification value of this current chip has been configured; if the logical identification value of the current chip has been configured, since multiple chips in the ring interconnect structure are connected in sequence to form a ring, it means that the incremented logical identification value has been transmitted around the ring interconnect structure and returned to the chip whose logical identification value has been configured. That is to say, all chips in the ring interconnect structure have been configured with unique logical identification values corresponding to the chips; if the logical identification value of the current chip has not been configured, it means that the process of transmitting the incremented logical identification value in the ring interconnect structure has not been completely completed, and there are still chips in the ring interconnect structure whose logical identification values have not been configured. In the above steps, the "current chip" refers to the chip that obtains the incremented logical identification value, and the "next chip" refers to the chip connected to the current chip in the ring interconnect structure, that is, the chip that receives the incremented logical identification value sent from the current chip. That is to say, the "current chip" and the "next chip" change with the above steps.

[0053] In some embodiments, the chip includes a logical identification value register, so the incremented logical identification value can be configured into the logical identification value register; at the same time, the logical identification value register can be configured with a configuration identifier, and it is possible to determine whether the logical identification value has been configured based on this configuration identifier.

[0054] Among them, if the logical identification value of this current chip has not been configured, step S121 is executed.

[0055] Step S121: Configure the incremented logical identification value into the current chip.

[0056] After the current chip obtains the incremented logical identification value, it is necessary to configure the incremented logical identification value into the current chip, indicating that the chip has been configured with a logical identification value, providing a technical basis for the subsequent process of determining the routing paths between chips.

[0057] In some embodiments, to improve the execution efficiency of the routing path determination method, the chip includes a logical identification value register. At this time, configuring the incremented logical identification value into the current chip includes: configuring the incremented logical identification value into the logical identification value register of the current chip. Further, in some specific embodiments, the logical identification value register is a logical ID register, and when the chip obtains the incremented logical identification value, the incremented logical identification value is written into its own logical ID register.

[0058] In some specific embodiments, the chip includes a temporary transfer register. Then, configuring the incremented logical identification value to the current chip includes: configuring the incremented logical identification value in the temporary transfer register of the current chip to the logical identification value register of the current chip, for example, the logical ID register.

[0059] Since a register is a high-speed storage element, by configuring the incremented logical identification value to a logical identification value register, such as a logical ID register, the execution speed and efficiency of the routing path determination method can be effectively improved.

[0060] Moreover, since the process of transmitting the incremented logical identification value in the ring interconnect structure has not been completely completed and there are still chips in the ring interconnect structure whose logical identification values have not been configured, after configuring the incremented logical identification value to the current chip, steps S110 and S120 will continue to be executed until it is determined that the logical identification value of the next chip for obtaining the incremented logical identification value has been configured.

[0061] In step S120, if the logical identification value of the current chip has been configured, step S130 is executed.

[0062] Step S130: Determine the total number of chips in the ring interconnect structure based on the incremented logical identification value.

[0063] If the logical identification value of the current chip has been configured, it indicates that all chips in the ring interconnect structure have been configured with unique logical identification values corresponding to the chips, and each chip has successively received and transmitted the incremented logical identification value, ensuring the uniqueness and continuity of the logical identification values of the chips in the ring interconnect structure. That is to say, the incremented logical identification value effectively identifies and differentiates the chips in the ring interconnect structure. Therefore, the total number of chips in the ring interconnect structure can be determined based on the incremented logical identification value, providing a technical basis for determining the routing paths between the chips in the ring interconnect structure according to the total number of chips and the logical identification values of the chips.

[0064] In some embodiments, for example, when the initial value is 0 and the preset value is 1, if the logical identification value of the chip that obtains the increment logical identification value has been configured, it indicates that the increment logical identification value has passed through all the chips in the ring interconnect structure once at this time. At this time, the increment logical identification value has increased by a value equal to the number of chips in the ring interconnect structure. That is to say, the total number of chips is the increment logical identification value at this time. For example, when the current chip obtains the increment logical identification value "7" and the logical identification value of this chip has been configured, the total number of chips in the ring interconnect structure is 7. In other embodiments, for example, when the initial value is 10 and the preset value is -1, when the current chip obtains the increment logical identification value "4" and the logical identification value of this chip has been configured, the total number of chips in the ring interconnect structure is the result "-6" obtained by subtracting the initial value "10" from the increment logical identification value "4" at this time, and then dividing this result by the preset value "-1", and the total number of chips obtained is 6.

[0065] After determining the total number of chips in the ring interconnect structure, continue to execute step S140.

[0066] Step S140: Based on the logical identification values of the chips in the ring interconnect structure and the total number of chips, determine the routing paths between the chips in the ring interconnect structure.

[0067] In the case where the logical identification values of the chips in the ring interconnect structure and the total number of chips have been determined, that is, it is possible to determine the routing paths between the chips in the ring interconnect structure based on the logical identification values of the chips and the total number of chips.

[0068] In order to accurately determine the initial identification chip of the ring interconnect structure, in some embodiments, the routing path determination method uses the high level of the initial identification definition pin as the mark of the initial identification chip. At this time, the method for determining the initial identification chip of the ring interconnect structure among the multiple chips is specifically as follows: sequentially detect the initial identification definition pins of the chips in the ring interconnect structure, and when detecting that the initial identification definition pin is at a high level, use this chip as the initial identification chip.

[0069] Among them, the initial identification definition pin is one of the pre-defined pins of the chip. For example, an initial identification definition pin GPIO_1 is defined among the GPIO pins (General Purpose Input Output) of the chip. When it is detected that this pin GPIO_1 is at a high level, it is determined that this chip is the initial identification chip.

[0070] Obviously, the hardware method of determining the state of pins by the initial identifier to define the initial identifier chip is more direct and efficient than the software method, which can improve the execution efficiency of the routing path determination method.

[0071] In order to accurately determine the initial identifier chip of the ring interconnect structure, in some other embodiments, the routing path determination method defines an initial identifier definition flag in the memory with the initial identifier as a mark of the initial identifier chip. At this time, determining the initial identifier chip of the ring interconnect structure among the multiple chips specifically includes: sequentially detecting the initial identifier definition memories of the chips in the ring interconnect structure, and when the initial identifier definition flag exists in the detected initial identifier definition memory, using this chip as the initial identifier chip.

[0072] Among them, the initial identifier definition memory is predefined and can be a flash memory, eFUSE (Electrically Programmable Read-Only Memory Fuse), or a register. For example, before the chip leaves the factory, the initial identifier definition flash memory is predefined. Then, when the initial identifier definition flag exists in the detected initial identifier definition flash memory, using this chip as the initial identifier chip. Similarly, the initial identifier definition flag can also be burned into the eFUSE of a specific chip before the chip leaves the factory. When the initial identifier definition flag exists in the detected initial identifier definition eFUSE, using this chip as the initial identifier chip.

[0073] In some embodiments, after determining the total number of chips in the ring interconnect structure based on the incremented logical identifier value, the routing path determination method further includes: transmitting the total number of chips to each chip in the ring interconnect structure.

[0074] After each chip in the ring interconnect structure obtains the total number of chips, for any chip in the ring interconnect structure, when determining the routing path between this chip and other chips, it is not necessary to obtain the total number of chips from other chips to determine the routing path, which improves the execution efficiency of the routing path determination method.

[0075] In some specific embodiments, during the process of transmitting the total number of chips to each chip in the ring interconnect structure, the memory for temporary transmission that has been agreed upon by each chip in the ring interconnect structure can be utilized, for example, a temporary transmission register, to improve the transmission efficiency of the total number of chips. That is to say, the temporary transmission register is also used to receive the total number of chips transmitted by each chip in the ring interconnect structure.

[0076] To further improve the execution efficiency of the routing path determination method, in some further embodiments, the chip further includes a chip total number register. Transmitting the chip total number to each chip in the ring interconnect structure includes: using the chip that determines the chip total number of the ring interconnect structure based on the increasing logic identification value as the current chip, and transmitting the chip total number from the current chip to the next chip connected thereto; using the next chip that obtains the chip total number as the current chip, determining whether the chip total number of the current chip has been configured. If not, configuring the chip total number to the chip total number register of the current chip, and performing the step of transmitting the chip total number from the current chip to the next chip connected thereto; if so, completing the step of transmitting the chip total number to each chip in the ring interconnect structure.

[0077] In the above embodiment, if the chip total number of the current chip has been configured, since multiple chips in the ring interconnect structure are connected in sequence to form a ring, it means that the chip total number has been transmitted in the ring interconnect structure for one circle and returned to the chip whose chip total number has been configured. That is to say, all chips in the ring interconnect structure have been configured with the chip total number corresponding to the chip. At this time, the process of transmitting the chip total number to each chip in the ring interconnect structure can be completed, avoiding repeated configuration of the chip total number; if the chip total number of the current chip has not been configured, it means that the process of transmitting the chip total number in the ring interconnect structure has not been completely completed, and there are still chips in the ring interconnect structure whose chip total numbers have not been configured.

[0078] Moreover, for the same reason as the above logic identification value register, by utilizing the high-speed characteristic of the register, the method of configuring the chip total number to the chip total number register of the current chip can further improve the execution efficiency of the routing path determination method.

[0079] In some embodiments, to reduce the computational amount of the chip to determine the routing path and improve the execution efficiency of the routing path determination method, the chip further includes a loop longest path register. Transmitting the chip total number to each chip in the ring interconnect structure further includes: sequentially detecting whether the chip total number of each chip in the ring interconnect structure has been configured. If so, configuring the ceiling result of dividing the chip total number by 2 into the loop longest path registers of each chip in the ring interconnect structure. In some specific embodiments, when it is detected that the chip total number of the current chip has been configured as 7, the loop longest path, that is, the ceiling result of 7 / 2, which is 4, is written into the loop longest path register of the current chip.

[0080] Since when determining the routing paths between the chips in the ring interconnect structure, it is necessary to compare the lengths of the routing paths and the longest path in the loop to determine the direction of the routing path. And the longest path in the loop is uniquely determined by the total number of chips of each chip in the ring interconnect structure. Therefore, configuring the longest path in the loop, that is, the ceiling result of dividing the total number of chips by 2, into the longest path register in the loop of each chip in the ring interconnect structure can avoid calculating from the total number of chips when comparing the length of the routing path and the longest path in the loop, reduce the calculation amount of the chip to determine the routing path, and improve the execution efficiency of the routing path determination method at the same time.

[0081] Figure 2 is another flowchart of a routing path determination method provided by an embodiment of the present invention. Refer to Figure 2 In the routing path determination method provided by the embodiment of the present invention, determining the routing paths between the chips in the ring interconnect structure includes the following steps:

[0082] Step S210: Determine the starting chip and the target chip of the routing path to be determined in the ring interconnect structure.

[0083] The routing path refers to a series of chips that data passes through from the starting chip to the target chip. The routing algorithm is responsible for determining the best transmission path of the data to ensure the effective and efficient transmission of the data. Therefore, it is necessary to determine the starting chip and the target chip of the routing path. Among them, the starting chip is the starting point of the routing path to be determined, and the target chip is the end point of the routing path to be determined.

[0084] After determining the starting chip and the target chip, step S220 is executed.

[0085] Step S220: Obtain the logical identification value of the starting chip and the logical identification value of the target chip from the logical identification value registers of the starting chip and the target chip respectively.

[0086] To determine the routing path between the starting chip and the target chip, the logical identification value of the starting chip and the logical identification value of the target chip are first required to determine the positions of the two chips in the ring interconnect structure. For example, in some specific embodiments, the logical ID register of the starting chip stores the logical ID "1" of the starting chip, and the logical ID register of the target chip stores the logical ID "4" of the target chip. Then, "1" and "4" are respectively obtained from the logical ID registers of the starting chip and the target chip.

[0087] After obtaining the logical identification value of the starting chip and the logical identification value of the target chip, step S230 is continued to be executed.

[0088] Step S230: Obtain the total number of chips and the longest loop path from the total chip number register and the longest loop path register of the starting chip respectively.

[0089] By utilizing the high-speed feature of the register to directly obtain the total number of chips and the longest loop path from the two registers of the starting chip respectively, it is possible to avoid the starting chip from obtaining data from other chips, reduce the occupancy of the ring interconnect structure, and effectively improve the execution efficiency of the routing path determination method. After obtaining the total number of chips and the longest loop path, continue to execute Step S240.

[0090] Step S240: Calculate the routing path length according to the logical identification values of the starting chip and the target chip and the total number of chips.

[0091] To determine the routing path between the starting chip and the target chip, it is necessary to calculate the length of this routing path. Since the logical identification values of each chip in the ring interconnect structure increase along the transmission direction of the increasing logical identification value, therefore, the length of this routing path is actually the path length for transmitting data along the transmission direction of the increasing logical identification value, and this length may be greater than the longest loop path. For example, in one implementation, the longest loop path is 3, while the path length for transmitting data along the transmission direction of the increasing logical identification value is 4, that is, the routing path length is greater than the longest loop path.

[0092] After obtaining the length of this routing path, continue to execute Step S250.

[0093] Step S250: Determine whether the routing path length is less than or equal to the longest loop path. If so, execute Step S251; if not, execute Step S252.

[0094] In the ring interconnect structure, there must be two routing paths between the starting chip and the target chip. To improve the communication efficiency, it is necessary to calculate the lengths of these two paths respectively and select the shorter path. Also, due to the characteristics of the ring interconnect structure, the length of the shorter path must be less than or equal to the longest loop path. Therefore, it is necessary to determine the relationship between the routing path length and the longest loop path.

[0095] When the routing path length is less than or equal to the longest loop path, execute Step S251.

[0096] Step S251: Determine that the direction of the routing path is the same as the transmission direction of the increasing logical identification value.

[0097] When the length of the routing path is less than or equal to the longest path of the loop, it indicates that the routing path for transmitting data in the same direction as the transmission direction of the increasing logical identification value is a shorter routing path. Thus, it can be determined that the direction of the routing path between the starting chip and the target chip is the same as the transmission direction of the increasing logical identification value. For example, when the transmission direction of the increasing logical identification value is clockwise, the direction of the routing path is also clockwise.

[0098] Conversely, when the length of the routing path is greater than the longest path of the loop, step S252 is executed.

[0099] Step S252: Determine that the direction of the routing path is the opposite of the transmission direction of the increasing logical identification value.

[0100] When the length of the routing path is greater than the longest path of the loop, it indicates that the routing path for transmitting data in the transmission direction of the increasing logical identification value is a longer routing path. Thus, it can be determined that the direction of the routing path between the starting chip and the target chip is the opposite of the transmission direction of the increasing logical identification value. For example, when the transmission direction of the increasing logical identification value is clockwise and the length of the routing path is greater than the longest path of the loop, the direction of the routing path is counterclockwise.

[0101] In some specific embodiments, for a ring interconnect structure where the transmission direction of the increasing logical identification value is clockwise, the length of the routing path is 4, and the longest path of the loop is 6. Since the length of the routing path is less than the longest path of the loop, it is determined that the direction of the routing path is the transmission direction of the increasing logical identification value, i.e., clockwise. In some other specific embodiments, for a ring interconnect structure where the transmission direction of the increasing logical identification value is clockwise, the length of the routing path is 7, and the longest path of the loop is 5. Since the length of the routing path is greater than the longest path of the loop, it is determined that the direction of the routing path is the opposite of the transmission direction of the increasing logical identification value, i.e., counterclockwise.

[0102] In some embodiments, calculating the routing path length according to the logical identification values of the starting chip and the target chip and the total number of chips includes: calculating the remainder obtained by dividing the sum of the result of subtracting the logical identification value of the starting chip from the logical identification value of the target chip and the total number of chips by the total number of chips. In a specific embodiment, the logical ID of the target chip is "7", the result of subtracting the logical ID "2" of the starting chip is 5, the sum with the total number of chips "8" is 13, and the remainder obtained by dividing by the total number of chips "8" is 5, that is, the routing path length is 5. In another specific embodiment, the logical ID of the target chip is "1", the result of subtracting the logical ID "8" of the starting chip is -7, the sum with the total number of chips "10" is 3, and the remainder obtained by dividing by the total number of chips "10" is 3, that is, the routing path length is 3.

[0103] The above calculation method can accurately calculate the routing path length and improve the accuracy of the routing path determination method.

[0104] In some embodiments, in the routing path determination method, the ring interconnect structure is: a ring interconnect structure of multiple single-chip packages, or at least one homogeneous multi-chip package ring interconnect structure, or at least one heterogeneous multi-chip package ring interconnect structure.

[0105] Due to the high flexibility of the ring interconnect structure composed of multiple chips, the routing path determination method provided by the embodiments of the present invention can achieve the effect of determining the routing paths between the chips in the ring interconnect structure for a ring interconnect structure of multiple single-chip packages, or at least one homogeneous multi-chip package ring interconnect structure, or at least one heterogeneous multi-chip package ring interconnect structure.

[0106] When the chips in the ring interconnect structure provided by the embodiments of the present invention need to determine a routing path for data transmission, they only need to read the data in the register and can determine the shortest routing path between any two chips through single-step calculation, which simplifies the routing path determination method and improves the efficiency of the routing path determination method.

[0107] Furthermore, in the routing path determination method provided by the embodiments of the present invention, the steps of determining the routing paths between the chips in the ring interconnect structure can be implemented in a software manner, for example, a program stored in the chip, or can also be implemented in a hardware circuit manner.

[0108] Next, the routing path determination method provided by the embodiments of the present invention will be described in conjunction with a specific ring interconnect structure.

[0109] Figure 3It is a schematic diagram of the initial state of a ring interconnect structure provided by an embodiment of the present invention. As Figure 3 shown, the ring interconnect structure includes two packages, namely Package A and Package B. Each package has 4 chips, for a total of 8 chips. Among them, all chips have not been assigned logical identification values.

[0110] Obviously, for the ring interconnect structure as Figure 3 shown, when the logical IDs of each chip are not pre-specified, the existing routing path determination method cannot determine the routing path in this ring interconnect structure.

[0111] Figure 4 It is a process schematic diagram of a routing path determination method provided by an embodiment of the present invention. Referring to Figure 4 , for the ring interconnect structure as Figure 3 shown, the routing path can be determined as follows.

[0112] First, pull up the level of the initial defined pin GPIO_1 of chip 0 in Package A, that is, Figure 4 in chip 0. When it is detected that the initial defined pin GPIO_1 of chip 0 is at a high level, it is determined as the initial identification chip of the chip 0 ring interconnect structure.

[0113] After that, chip 0 writes "0" into its own logical identification value register, that is, takes chip 0 as the current chip and configures the logical identification value of chip 0 to the initial value "0". Then, after incrementing the logical identification value by 1 (i.e., the preset value is "1"), the incremented logical identification value "1" is transmitted from the counterclockwise direction to the next chip of the current chip, that is, Figure 4 chip 1 in.

[0114] Similarly, chip 1 writes the received incremented logical identification value "1" into its own logical identification value register, that is, takes chip 1 as the current chip. Then, chip 1 takes the incremented logical identification value as its own logical identification value, and then after incrementing the logical identification value of chip 1 at this time by 1 to get the incremented logical identification value "2" to be sent, the incremented logical identification value "2" is transmitted from the counterclockwise direction to the next chip of the current chip, that is, Figure 4 chip 2 in.

[0115] And so on, continue to transmit the incremented logical identification value in the counterclockwise direction until chip 0 receives the incremented logical identification value "8" sent by chip 8. At this time, since the logical identification value of chip 0 has been configured as "0", therefore, based on this incremented logical identification value "8", it is determined that the total number of chips in the ring interconnect structure is 8. Chip 0 writes the total number of chips "8" into its own total number of chips register. And, since it is detected that the total number of chips has been configured, chip 0 writes the ceiling result "4" of dividing the total number of chips "8" by 2 into its own longest path in the loop register, and transmits the total number of chips "8" in the counterclockwise direction to the next chip of the current chip, that is, chip 1.

[0116] After that, chip 1 receives the total number of chips "8" and writes it into its own total number of chips register, that is, taking chip 1 as the current chip. And, since it is detected that the total number of chips has been configured, chip 1 writes the ceiling result "4" of dividing the total number of chips "8" by 2 into its own longest path in the loop register, and transmits the total number of chips "8" in the counterclockwise direction to the next chip of the current chip, that is, chip 2.

[0117] And so on, continue to transmit the total number of chips in the counterclockwise direction until chip 0 receives the total number of chips "8" sent by chip 8, and end the transmission of the total number of chips. At this time Figure 4 In the shown ring interconnect structure, the logical identification values, the total number of chips, and the longest path in the loop of all chips have been configured.

[0118] When it is necessary to determine the routing path for data transmission between two chips. For example, if data is to be transmitted from chip 4 to chip 7, calculate the length of this routing path as: the sum of the result of subtracting the logical identification value "4" of the starting chip from the logical identification value "7" of the target chip and the total number of chips "8", and then the remainder obtained by dividing by the total number of chips "8", that is, (7 - 4 + 8) % 8 = 3. The length of this routing path is less than the longest path in the loop "4", so it is determined that the direction of this routing path is counterclockwise.

[0119] Another example, if data is to be transmitted from chip 7 to chip 4, calculate the length of this routing path as: the sum of the result of subtracting the logical identification value "7" of the starting chip from the logical identification value "4" of the target chip and the total number of chips "8", and then the remainder obtained by dividing by the total number of chips "8", that is, (4 - 7 + 8) % 8 = 5. The length of this routing path is greater than the longest path in the loop "4", so it is determined that the direction of this routing path is clockwise.

[0120] The above routing path determination method is for Figure 3 a shown ring interconnect structure. And for different ring interconnect structures such as Figures 5 - 8 shown, such as Figure 5 a ring interconnect structure composed of multiple SCM packages shown,Figure 6 The ring interconnect structure composed of a single MCM package shown Figure 7 The ring interconnect structure composed of multiple MCM packages shown, and Figure 8 The ring interconnect structure composed of multiple SIP packages shown. The routing path determination method provided by the embodiments of the present invention can also implement the determination of the routing paths between the chips in the ring interconnect structure such as Figures 5 - 8 .

[0121] To implement the routing path determination method provided by the embodiments of the present invention in a chip, the embodiments of the present invention further provide a routing path determination device, and the device is applied to each chip that is sequentially connected to form a ring in the ring interconnect structure.

[0122] Figure 5 It is a schematic diagram of a routing path determination device provided by the embodiments of the present invention.

[0123] Referring to Figure 5 , the routing path determination device 1 includes:[[]]

[0124] An initial identification chip determination module 11, configured to determine the initial identification chip of the ring interconnect structure among the multiple chips, configure the logical identification value of the initial identification chip as an initial value, and use the initial identification chip as the current chip;

[0125] A logical node number transmission module 12, configured to transmit an incremented logical identification value from the current chip to the next chip connected thereto, and the incremented logical identification value corresponding to the next chip is the value after the logical identification value corresponding to the current chip is incremented by a preset value;

[0126] A logical node number configuration module 13, configured to use the next chip that obtains the incremented logical identification value as the current chip, determine whether the logical identification value of the current chip has been configured, if not, configure the incremented logical identification value to the current chip, and execute the step of transmitting the incremented logical identification value from the current chip to the next chip connected thereto; if so, determine the total number of chips in the ring interconnect structure based on the incremented logical identification value;

[0127] A routing path determination module 14, configured to determine the routing paths between the chips in the ring interconnect structure based on the logical identification values of the chips in the ring interconnect structure and the total number of chips.

[0128] It can be seen that in a routing path determination device provided by an embodiment of the present invention, the initial identification chip determination module 11 determines whether the current chip is an initial identification chip. Through the logical node number transmission module 12, the incremented logical identification value is transmitted from the current chip to the next chip connected thereto. Through the logical node number configuration module 13, it is determined whether the logical identification value of the chip that obtains the incremented logical identification value has been configured, and the total number of chips in the ring interconnect structure is determined based on the incremented logical identification value, that is, the logical identifications of the unknown chips in the ring interconnect structure are determined; the total number of chips in the ring interconnect structure is determined based on the incremented logical identification value, that is, the number of unknown chips in the ring interconnect structure is determined; finally, through the routing path determination module 14, based on the logical identification values of the chips in the ring interconnect structure and the total number of chips, the routing paths between the chips in the ring interconnect structure are determined, realizing the determination of the routing paths between the chips in the ring interconnect structure.

[0129] In some embodiments, the routing path determination device 1 uses the initial identification definition pin being at a high level as a mark of the initial identification chip. When the initial identification chip determination module 11 detects that the initial identification definition pin is at a high level, this chip is used as the initial identification chip.

[0130] In some embodiments, the routing path determination device 1 uses the initial identification definition memory containing the initial identification definition flag as a mark of the initial identification chip. When the initial identification chip determination module 11 detects the existence of the initial identification definition flag in the initial identification definition memory, this chip is used as the initial identification chip.

[0131] In some embodiments, when the chip includes a logical identification value register, the configuring the incremented logical identification value to the current chip includes: configuring the incremented logical identification value to the logical identification value register of the current chip.

[0132] In some embodiments, continue to refer to Figure 9 When the chip further includes a total number of chips register, the routing path determination device 1 further includes a loop total number of chips transmission module 15, configured to transmit the total number of chips to each chip in the ring interconnect structure after determining the total number of chips in the ring interconnect structure based on the incremented logical identification value; a loop total number of chips configuration module 16, configured to detect whether the total number of chips of each chip in the ring interconnect structure has been configured after transmitting the total number of chips to each chip in the ring interconnect structure, and if so, configure the ceiling result of dividing the total number of chips by 2 into the loop longest path registers of each chip in the ring interconnect structure.

[0133] In some embodiments, continue to refer toFigure 9 When the chip further includes a loop longest path register, the routing path determination device 1 further includes a loop longest path configuration module 17, configured to, after transmitting the total number of chips to each chip in the ring interconnect structure, detect whether the total number of chips of each chip in the ring interconnect structure has been configured, and if so, configure the ceiling result of dividing the total number of chips by 2 into the loop longest path registers of each chip in the ring interconnect structure.

[0134] In some embodiments, the routing path determination module 14 includes:

[0135] A target chip determination module, configured to determine the target chip of the routing path to be determined and the logical identification value of the target chip in the ring interconnect structure;

[0136] A logical identification value acquisition unit, configured to acquire the logical identification value of the starting chip from the logical identification value register of the current chip, that is, the starting chip of the routing path to be determined;

[0137] A total number of chips acquisition unit, configured to acquire the total number of chips from the total number of chips register of the starting chip;

[0138] A loop longest path acquisition module, configured to acquire the loop longest path from the loop longest path register of the starting chip;

[0139] A routing path calculation module, the routing path calculation module calculates the routing path length according to the logical identification values of the starting chip and the target chip and the total number of chips; when the routing path length is less than or equal to the loop longest path, it is determined that the direction of the routing path is the same as the transmission direction of the increasing logical identification value; when the routing path length is greater than the loop longest path, it is determined that the direction of the routing path is opposite to the transmission direction of the increasing logical identification value.

[0140] In some embodiments, calculating the routing path length according to the logical identification values of the starting chip and the target chip and the total number of chips includes: calculating the remainder obtained by dividing the sum of the result of subtracting the logical identification value of the target chip from the logical identification value of the starting chip and the total number of chips by the total number of chips.

[0141] An embodiment of the present invention further provides a computing device, the computing device includes a memory and a processor, the memory stores computer instructions, and the processor calls the computer instructions stored in the memory to execute the routing path determination method as described in any of the foregoing embodiments.

[0142] An embodiment of the present invention further provides a storage medium storing computer instructions, and when the computer instructions are executed, the routing path determination method described in any of the foregoing embodiments is implemented.

[0143] An embodiment of the present invention further provides a computer program product, which includes computer instructions, and when the computer instructions are executed, the routing path determination method described in any of the foregoing embodiments is implemented.

[0144] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A routing path determination method, characterized in that, Applied to a ring interconnect structure, the ring interconnect structure includes a plurality of chips connected in sequence to form a ring, and the routing path determination method includes: Determine an initial identification chip of the ring interconnect structure among the plurality of chips, configure the logical identification value of the initial identification chip as an initial value, and use the initial identification chip as the current chip. The logical identification value is a unique identification value assigned to each chip in the ring interconnect structure, and is used to indicate the interconnection relationship of each chip in the ring interconnect structure; Transmit an incremented logical identification value from the current chip to the next chip connected thereto, and the incremented logical identification value corresponding to the next chip is the value after the logical identification value corresponding to the current chip is incremented by a preset value; Use the next chip that obtains the incremented logical identification value as the current chip, and determine whether the logical identification value of the current chip has been configured. If not, configure the incremented logical identification value to the current chip, and execute the step of transmitting the incremented logical identification value from the current chip to the next chip connected thereto; if so, determine the total number of chips in the ring interconnect structure based on the incremented logical identification value; Based on the logical identification values corresponding to each chip in the ring interconnect structure and the total number of chips in the ring interconnect structure, determine the routing paths between each chip in the ring interconnect structure, including: Determine the starting chip and the target chip of the routing path to be determined in the ring interconnect structure; calculate the routing path length according to the logical identification values of the starting chip and the target chip and the total number of chips; when the routing path length is less than or equal to the longest path of the loop, determine that the direction of the routing path is the same as the transmission direction of the incremented logical identification value; when the routing path length is greater than the longest path of the loop, determine that the direction of the routing path is the opposite of the transmission direction of the incremented logical identification value, and the longest path of the loop is uniquely determined by the total number of chips in the ring interconnect structure.

2. The routing path determination method according to claim 1, wherein Using the initial identification definition pin being at a high level as the mark of the initial identification chip, the step of determining the initial identification chip of the ring interconnect structure among the plurality of chips is specifically: Sequentially detect the initial identification definition pins of each chip in the ring interconnect structure, and when it is detected that the initial identification definition pin is at a high level, use this chip as the initial identification chip.

3. The routing path determination method according to claim 1, wherein Using the initial identification definition memory containing the initial identification definition flag as the mark of the initial identification chip, the step of determining the initial identification chip of the ring interconnect structure among the plurality of chips is specifically: Sequentially detect the initial identification definition memories of each chip in the ring interconnect structure, and when it is detected that there is an initial identification definition flag in the initial identification definition memory, use this chip as the initial identification chip.

4. The routing path determination method according to claim 1, characterized in that After determining the total number of chips in the ring interconnect structure based on the incremented logical identification value, it further includes: Transmit the total number of chips to each chip in the ring interconnect structure.

5. The routing path determination method according to claim 4, wherein The chip further includes a chip total register, and the step of transmitting the total number of chips to each chip in the ring interconnect structure is specifically: Taking the chip that determines the total number of chips in the ring interconnect structure based on the increasing logic identification value as the current chip, transmitting the total number of chips from the current chip to the next chip connected thereto; Taking the next chip that obtains the total number of chips as the current chip, determining whether the total number of chips of the current chip has been configured, and if not, configuring the total number of chips into the total number of chips register of the current chip, and performing the step of transmitting the total number of chips from the current chip to the next chip connected thereto; If so, completing the step of transmitting the total number of chips to each chip in the ring interconnect structure.

6. The routing path determination method according to claim 5, wherein The chip further includes a loop longest path register. After transmitting the total number of chips to each chip in the ring interconnect structure, the method further includes: Detecting whether the total number of chips of each chip in the ring interconnect structure has been configured, and if so, configuring the ceiling result of dividing the total number of chips by 2 into the loop longest path registers of each chip in the ring interconnect structure.

7. The routing path determination method according to claim 6, wherein The chip further includes a logic identification value register. Configuring the increasing logic identification value to the current chip includes: Configuring the increasing logic identification value to the logic identification value register of the current chip.

8. The routing path determination method according to claim 7, wherein The chip further includes a temporary transfer register; Transmitting the increasing logic identification value from the current chip to the next chip connected thereto includes: transmitting the increasing logic identification value from the current chip to the temporary transfer register of the next chip connected thereto; Configuring the increasing logic identification value to the current chip includes: configuring the increasing logic identification value in the temporary transfer register of the current chip to the logic identification value register of the current chip.

9. The routing path determination method according to claim 7, characterized in that, Determining the routing paths between each chip in the ring interconnect structure based on the logic identification values corresponding to each chip in the ring interconnect structure and the total number of chips in the ring interconnect structure further includes: Respectively obtaining the logic identification value of the starting chip and the logic identification value of the target chip from the logic identification value registers of the starting chip and the target chip; respectively obtaining the total number of chips and the loop longest path from the total number of chips register and the loop longest path register of the starting chip.

10. The routing path determination method according to claim 9, wherein, Calculating the routing path length according to the logic identification values of the starting chip and the target chip and the total number of chips includes: Calculating the remainder obtained by dividing the sum of the result of subtracting the logic identification value of the target chip from the logic identification value of the starting chip and the total number of chips by the total number of chips; Taking the remainder as the routing path length.

11. The routing path determination method according to claim 1, wherein The ring interconnect structure is: a plurality of single-chip packaged ring interconnect structures, or at least one homogeneous multi-chip packaged ring interconnect structure, or at least one heterogeneous multi-chip packaged ring interconnect structure.

12. A routing path determination device, characterized in that, Applied to each chip connected in sequence to form a ring in the ring interconnect structure, including: An initial identification chip determination module, configured to determine an initial identification chip of the ring interconnect structure among multiple chips, configure the logical identification value of the initial identification chip as an initial value, and use the initial identification chip as the current chip. The logical identification value is a unique identification value assigned to each chip in the ring interconnect structure, and is used to indicate the interconnection relationship of each chip in the ring interconnect structure; A logical node number transmission module, configured to transmit an incremented logical identification value from the current chip to the next chip connected thereto. The incremented logical identification value is obtained by incrementing a preset value based on the logical identification value corresponding to the current chip; A logical node number configuration module, configured to use the next chip that obtains the incremented logical identification value as the current chip, determine whether the logical identification value of the current chip has been configured. If not, configure the incremented logical identification value to the current chip, and execute the step of transmitting the incremented logical identification value from the current chip to the next chip connected thereto; if so, determine the total number of chips in the ring interconnect structure based on the incremented logical identification value; A routing path determination module, configured to determine the routing paths between each chip in the ring interconnect structure based on the logical identification values corresponding to each chip in the ring interconnect structure and the total number of chips in the ring interconnect structure. Specifically: determine the starting chip and the target chip of the routing path to be determined in the ring interconnect structure; calculate the routing path length according to the logical identification values of the starting chip and the target chip and the total number of chips; when the routing path length is less than or equal to the longest path of the loop, determine that the direction of the routing path is the same as the transmission direction of the incremented logical identification value; when the routing path length is greater than the longest path of the loop, determine that the direction of the routing path is opposite to the transmission direction of the incremented logical identification value. The longest path of the loop is uniquely determined by the total number of chips in the ring interconnect structure.

13. The routing path determination device according to claim 12, wherein The chip further includes a total number of chips register, and the routing path determination device further includes: A loop total number of chips transmission module, configured to transmit the total number of chips to each chip in the ring interconnect structure after determining the total number of chips in the ring interconnect structure based on the incremented logical identification value; 14. The routing path determination device according to claim 13, characterized in that, The loop total number of chips transmission module is configured to transmit the total number of chips to each chip in the ring interconnect structure, specifically: Use the chip that determines the total number of chips in the ring interconnect structure based on the incremented logical identification value as the current chip, and transmit the total number of chips from the current chip to the next chip connected thereto; Use the next chip that obtains the total number of chips as the current chip, determine whether the total number of chips of the current chip has been configured. If not, configure the total number of chips to the total number of chips register of the current chip, and execute the step of transmitting the total number of chips from the current chip to the next chip connected thereto; If so, complete the step of transmitting the total number of chips to each chip in the ring interconnect structure.

15. The routing path determination device according to claim 14, characterized in that, The chip further includes a longest path of the loop register, and the device further includes: The total number of loop chips configuration module is used to detect whether the total number of chips in the ring interconnect structure has been configured after transmitting the total number of chips to each chip in the ring interconnect structure. If so, configure the ceiling result of dividing the total number of chips by 2 into the loop longest path registers of each chip in the ring interconnect structure.

16. The routing path determination device according to claim 15, wherein The routing path determination module is further configured to respectively obtain the logical identification value of the starting chip and the logical identification value of the target chip from the logical identification value registers of the starting chip and the target chip; and respectively obtain the total number of chips and the loop longest path from the total number of chips register and the loop longest path register of the starting chip.

17. The routing path determination device according to claim 16, wherein The routing path determination module is used to calculate the routing path length according to the logical identification values of the starting chip and the target chip and the total number of chips, including: Calculating the remainder obtained by dividing the sum of the result of subtracting the logical identification value of the target chip from the logical identification value of the starting chip and the total number of chips by the total number of chips; Using the remainder as the routing path length.

18. A computing device, characterized in that, It includes a memory and a processor. The memory stores computer instructions, and the processor calls the computer instructions stored in the memory to execute the routing path determination method according to any one of claims 1-11.

19. A storage medium, characterized in that, The storage medium stores computer instructions, and when the computer instructions are executed, the routing path determination method according to any one of claims 1-11 is implemented.

20. A computer program product, characterized in that, characterized in that, It includes computer instructions, and when the computer instructions are executed, the routing path determination method according to any one of claims 1-11 is implemented.

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