Chip layout method, device, computer equipment, storage medium and computer program product

Abstract

The present application relates to a chip layout method, device, computer equipment, storage medium and computer program product. The method comprises: determining a reference chip to be laid out of a target chip to be laid out from each chip to be laid out according to the similarity between the circuit information vectors of each chip to be laid out; if the layout parameter migration condition is met, migrating each candidate layout parameter of the reference chip to be laid out to the target chip to be laid out, and determining a parameter traversal strategy according to the layout quality index value of the reference chip to be laid out corresponding to each candidate layout parameter; traversing each target candidate layout parameter according to the parameter traversal strategy, obtaining a layout design and a layout quality index value corresponding to the layout design for the target candidate layout parameter currently traversed, and performing chip layout on the target chip to be laid out according to the layout design when the layout quality index value meets the preset index value condition. The use of this method can improve chip layout efficiency.

Description

Technical Field

[0001] The present application relates to the field of chip layout, and in particular to a chip layout method, apparatus, computer equipment, storage medium and computer program product. Background Art

[0002] As the nanometer size of chips becomes smaller and smaller, the number of wafers in the chip increases, and the chip gradually changes from a simple integrated circuit to a very large-scale integrated circuit. The placement and wiring methods of each component in the chip also begin to have an increasingly greater impact on chip performance.

[0003] There are currently some algorithms that can automatically layout chips, such as AutoDMP for macrocell layout (an automated layout algorithm based on DREAMPlace (a deep learning toolkit)). However, due to the different circuit designs of different chips, the layouts generated by these algorithms for specific chips and the parameters used when generating the layouts often cannot be directly migrated to other chips. As a result, when there is a need to layout multiple different chips at the same time, the complete process of using the algorithm to generate the layout must be performed for each chip, resulting in low chip layout generation efficiency. Summary of the invention

[0004] Based on this, it is necessary to provide a chip layout method, apparatus, computer equipment, storage medium and computer program product to address the above technical issues.

[0005] In a first aspect, the present application provides a chip layout method. The method comprises:

[0006] Determining a reference chip to be laid out of a target chip to be laid out from the chips to be laid out according to the similarity between the circuit information vectors of the chips to be laid out; the target chip to be laid out is any one of the chips to be laid out;

[0007] In the case that the reference chip to be laid out meets the layout parameter migration condition, each candidate layout parameter of the reference chip to be laid out is used as the target candidate layout parameter of the target chip to be laid out, and according to the layout quality index value of each candidate layout parameter corresponding to the reference chip to be laid out, a parameter traversal strategy of the target chip to be laid out is determined;

[0008] Each of the target candidate layout parameters is traversed according to the parameter traversal strategy. For the currently traversed target candidate layout parameters, the target candidate layout parameters and the circuit information of the target chip to be laid out are input into the chip layout model to obtain a layout design corresponding to the target candidate layout parameters and a layout quality index value corresponding to the layout design. When the layout quality index value satisfies a preset index value condition, chip layout is performed on the target chip to be laid out according to the layout design.

[0009] In one embodiment, the method further comprises:

[0010] When the reference chip to be placed does not exist for the target chip to be placed, or the reference chip to be placed does not meet the placement parameter migration condition, the target candidate placement parameters of the target chip to be placed are generated, and a parameter traversal strategy of the target chip to be placed is determined according to each of the target candidate placement parameters.

[0011] In one embodiment, generating the target candidate layout parameters of the target chip to be laid out includes:

[0012] Determining initial candidate layout parameters of the target chip to be laid out, and inputting the initial candidate layout parameters into a chip layout model to obtain initial layout quality index values ​​corresponding to the initial candidate layout parameters;

[0013] generating at least one target candidate layout parameter according to the initial candidate layout parameter, and determining a new initial candidate layout parameter from each of the target candidate layout parameters, wherein an expected layout quality index value of each of the target candidate layout parameters is greater than or equal to the initial layout quality index value;

[0014] The steps of inputting the initial candidate layout parameters into a chip layout model, obtaining initial layout quality indicator values ​​corresponding to the initial candidate layout parameters, generating at least one target candidate layout parameter according to the initial candidate layout parameters, and determining new initial candidate layout parameters from each of the target candidate layout parameters are repeatedly performed until the number of each of the target candidate layout parameters reaches a preset number.

[0015] In one embodiment, the method further comprises:

[0016] For any of the chips to be laid out, a first circuit information graph of the chip to be laid out is generated according to each standard cell in the chip to be laid out and the connection relationship between each standard cell, and a second circuit information graph of the chip to be laid out is generated according to each gate circuit in the chip to be laid out and the connection relationship between each gate circuit;

[0017] A circuit information vector of each chip to be laid out is generated according to the first circuit information graph and the second circuit information graph of each chip to be laid out.

[0018] In one embodiment, determining a reference chip to be laid out of a target chip to be laid out from the chips to be laid out according to the similarity between the circuit information vectors of the chips to be laid out comprises:

[0019] Determine an initial chip to be placed from each of the chips to be placed, take the initial chip to be placed as the first chip to be placed, and determine a target second chip to be placed whose circuit information vector has the greatest similarity to the circuit information vector of the first chip to be placed from each of the second chips to be placed; wherein the second chip to be placed is a chip to be placed other than the initial chip to be placed and does not have a reference chip to be placed;

[0020] The first chip to be laid out is used as a reference chip to be laid out for the target second chip to be laid out, the target second chip to be laid out is used as a first chip to be laid out, and the steps of determining, from among the second chips to be laid out, a target second chip to be laid out having a circuit information vector having the greatest similarity to the circuit information vector of the first chip to be laid out, and using the first chip to be laid out as a reference chip to be laid out for the target second chip to be laid out are repeatedly performed until there is no second chip to be laid out.

[0021] In one embodiment, the method further comprises:

[0022] Clustering the chips to be placed according to the circuit information vectors of the chips to be placed, to obtain at least one category of chips to be placed;

[0023] In a case where the category of the chip to be laid out to which the target chip to be laid out belongs is the same as the category of the chip to be laid out to which the reference chip to be laid out belongs, determining that the reference chip to be laid out meets the layout parameter migration condition; or

[0024] When the similarity between the target chip to be placed and the reference chip to be placed is greater than or equal to a similarity threshold, it is determined that the reference chip to be placed meets the placement parameter migration condition.

[0025] In a second aspect, the present application also provides a chip layout device. The device comprises:

[0026] A first determination module is used to determine a reference chip to be placed of a target chip to be placed from the chips to be placed according to the similarity between the circuit information vectors of the chips to be placed; the target chip to be placed is any one of the chips to be placed;

[0027] a migration module, configured to use each candidate layout parameter of the reference chip to be laid out as a target candidate layout parameter of the target chip to be laid out, if the reference chip to be laid out meets the layout parameter migration condition, and determine a parameter traversal strategy of the target chip to be laid out according to the layout quality index value of each candidate layout parameter corresponding to the reference chip to be laid out;

[0028] A layout module is used to traverse each of the target candidate layout parameters according to the parameter traversal strategy, and for the currently traversed target candidate layout parameters, input the target candidate layout parameters and the circuit information of the target chip to be laid out into a chip layout model, obtain a layout design corresponding to the target candidate layout parameters, and a layout quality index value corresponding to the layout design, and when the layout quality index value meets a preset index value condition, perform chip layout on the target chip to be laid out according to the layout design.

[0029] In one embodiment, the device further comprises:

[0030] The first generating module is used to generate the target candidate layout parameters of the target chip to be placed if the reference chip to be placed of the target chip to be placed does not exist or the reference chip to be placed does not meet the layout parameter migration condition, and determine the parameter traversal strategy of the target chip to be placed according to each of the target candidate layout parameters.

[0031] In one embodiment, the first generating module is further used for:

[0032] Determining initial candidate layout parameters of the target chip to be laid out, and inputting the initial candidate layout parameters into a chip layout model to obtain initial layout quality index values ​​corresponding to the initial candidate layout parameters;

[0033] generating at least one target candidate layout parameter according to the initial candidate layout parameter, and determining a new initial candidate layout parameter from each of the target candidate layout parameters, wherein an expected layout quality index value of each of the target candidate layout parameters is greater than or equal to the initial layout quality index value;

[0034] The steps of inputting the initial candidate layout parameters into a chip layout model, obtaining initial layout quality indicator values ​​corresponding to the initial candidate layout parameters, generating at least one target candidate layout parameter according to the initial candidate layout parameters, and determining new initial candidate layout parameters from each of the target candidate layout parameters are repeatedly performed until the number of each of the target candidate layout parameters reaches a preset number.

[0035] In one embodiment, the device further comprises:

[0036] A second generating module is used to generate, for any of the chips to be laid out, a first circuit information graph of the chip to be laid out according to each standard cell in the chip to be laid out and the connection relationship between each standard cell, and to generate a second circuit information graph of the chip to be laid out according to each gate circuit in the chip to be laid out and the connection relationship between each gate circuit;

[0037] The third generating module is used to generate a circuit information vector of each chip to be laid out according to the first circuit information graph and the second circuit information graph of each chip to be laid out.

[0038] In one embodiment, the first determining module is further used to:

[0039] Determine an initial chip to be placed from each of the chips to be placed, take the initial chip to be placed as the first chip to be placed, and determine a target second chip to be placed whose circuit information vector has the greatest similarity to the circuit information vector of the first chip to be placed from each of the second chips to be placed; wherein the second chip to be placed is a chip to be placed other than the initial chip to be placed and does not have a reference chip to be placed;

[0040] The first chip to be laid out is used as a reference chip to be laid out for the target second chip to be laid out, the target second chip to be laid out is used as a first chip to be laid out, and the steps of determining, from among the second chips to be laid out, a target second chip to be laid out having a circuit information vector having the greatest similarity to the circuit information vector of the first chip to be laid out, and using the first chip to be laid out as a reference chip to be laid out for the target second chip to be laid out are repeatedly performed until there is no second chip to be laid out.

[0041] In one embodiment, the device further comprises:

[0042] A clustering module, configured to perform clustering processing on each of the chips to be arranged according to the circuit information vector of each of the chips to be arranged, so as to obtain at least one category of the chips to be arranged;

[0043] The second determination module is used to determine that the reference chip to be placed meets the layout parameter migration condition when the category of the chip to be placed to which the target chip to be placed belongs is the same as the category of the chip to be placed to which the reference chip to be placed belongs; or to determine that the reference chip to be placed meets the layout parameter migration condition when the similarity between the target chip to be placed and the reference chip to be placed is greater than or equal to a similarity threshold.

[0044] In a third aspect, the present application further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, any one of the above methods is implemented.

[0045] In a fourth aspect, the present application further provides a computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, any of the above methods is implemented.

[0046] In a fifth aspect, the present application further provides a computer program product, wherein the computer program product comprises a computer program, and when the computer program is executed by a processor, any of the above methods is implemented.

[0047] The above-mentioned chip layout method, device, computer equipment, storage medium and computer program product, when performing layout design for a variety of different chips to be laid out, determine a reference chip to be laid out that is similar to the target chip to be laid out. If the reference chip to be laid out can perform layout parameter migration, then migrate the candidate layout parameters used by the reference chip to be laid out to the target chip to be laid out, and determine the order in which the target chip to be laid out tries each candidate layout parameter (i.e., parameter traversal strategy) according to the layout quality index value obtained by the reference chip to be laid out using each candidate layout parameter. Try each candidate layout parameter in order according to the parameter traversal strategy, input the candidate layout parameters into the chip layout model to obtain a layout design that meets the candidate layout parameters, and determine the layout quality index value of the layout design. If the layout quality index value meets the requirements, the target chip to be laid out is laid out according to the layout design. When laying out the chip, the embodiment of the present application determines a reference chip to be laid out that can be used for reference, and uses the layout quality index value verified by the reference chip to be laid out for each candidate layout parameter as a reference to determine which candidate layout parameters should be used first for the layout of the target chip to be laid out. Since the reference chip to be laid out is similar to the target chip to be laid out, there is a high probability that the candidate layout parameters that perform well on the reference chip to be laid out can also perform well on the target chip to be laid out, so that the target chip to be laid out can find a layout design that meets the requirements after a small number of candidate layout parameter attempts, thereby improving the efficiency of chip layout generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a schematic flow chart of a chip layout method in one embodiment;

[0049] Figure 2 A schematic diagram of a process for generating target candidate layout parameters in one embodiment;

[0050] Figure 3 A schematic diagram of a process for generating target candidate layout parameters in one embodiment;

[0051] Figure 4 A schematic diagram of a process for generating a circuit information vector in one embodiment;

[0052] Figure 5 A schematic diagram of a partial circuit of a chip to be laid out in one embodiment;

[0053] Figure 6 A local first circuit information graph generated according to a local circuit in one embodiment;

[0054] Figure 7 is a schematic diagram of disassembling a standard cell into gate circuits in one embodiment;

[0055] Figure 8 A local second circuit information graph generated according to a local circuit in one embodiment;

[0056] Fig. 9 is a flow chart of step 102 in one embodiment;

[0057] Fig.10 A schematic diagram of a flow chart for determining layout parameter migration conditions in one embodiment;

[0058] Fig.11 is a structural block diagram of a chip layout device in one embodiment;

[0059] Fig.12 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0061] In one embodiment, Figure 1 As shown, a chip layout method is provided. This embodiment takes the method applied to a server as an example for illustration. It is understandable that the method can also be applied to a terminal, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0062] Step 102 : determining a reference chip to be placed of a target chip to be placed from among the chips to be placed according to the similarity between the circuit information vectors of the chips to be placed; the target chip to be placed is any chip to be placed.

[0063] In the embodiment of the present application, the chip to be laid out is a chip that needs to be laid out, and the circuit information vector is generated based on the circuit information of each chip to be laid out. The circuit information may include but is not limited to the types of components in the chip, the number of components, the connection relationship between components, etc.

[0064] The embodiments of the present application do not specifically limit how to use the circuit information vector to represent the circuit information of the chip to be laid out. In one example, all possible component types in the chip can be determined, and a vector format can be designed, in which each bit in the vector corresponds to a component type, and the value of each bit represents the number of components corresponding to the component type in the chip. The circuit information vector of each chip to be laid out is generated according to the vector format.

[0065] In another example, a graph corresponding to the chip to be laid out can be generated based on the connection relationship between the components in the chip to be laid out, where each vertex in the graph is a component, and a connection edge between two vertices represents that the two components have a connection relationship. Then, an arbitrary graph representation algorithm is used to convert the graph into a vector to obtain the circuit information vector of the chip to be laid out.

[0066] After obtaining the circuit information vector of each chip to be laid out, the similarity between the circuit information vectors of each two chips to be laid out can be obtained by any algorithm for calculating the similarity between two vectors. According to the similarity between the circuit information vectors of each two chips to be laid out, a reference chip to be laid out that may be used to migrate layout parameters to the chip to be laid out can be determined for each chip to be laid out. The embodiment of the present application does not specifically limit how to select the reference chip to be laid out, and it is sufficient to ensure that the similarity between the reference chip to be laid out and the chip to be laid out is relatively high.

[0067] In one example, for each chip to be laid out, the chip with the highest similarity to the chip to be laid out among the remaining chips to be laid out can be used as the reference chip to be laid out for the chip to be laid out. For example, when there are chips to be laid out 1, 2, and 3, and the chip with the highest similarity to chip 1 is chip 2, the chip with the highest similarity to chip 2 is chip 3, and the chip with the highest similarity to chip 3 is chip 2, the reference chip to be laid out for chip 1 is chip 2, the reference chip to be laid out for chip 2 is chip 3, and the reference chip to be laid out for chip 3 is chip 2. Using the chip to be laid out with the highest similarity to each chip to be laid out as the reference chip to be laid out for the chip to be laid out can increase the probability that the candidate layout parameters that perform well for the reference chip to be laid out can also perform well on the target chip to be laid out, further improving the efficiency of chip layout generation.

[0068] In another example, for each chip to be laid out, similar chips whose similarity with the chip to be laid out is greater than a similarity threshold are determined from the remaining chips to be laid out, and the number of times each chip to be laid out becomes a similar chip to another chip to be laid out is counted, and the chip to be laid out with the highest number of similarities is used as the initial chip, and the chips to be laid out that have the initial chip among the similar chips are determined, and the reference chips to be laid out of these chips to be laid out are all used as the initial chips. Since the initial chip needs to be used as the starting point for the migration of layout parameters, the initial chip is a chip to be laid out that has no reference chip to be laid out.

[0069] If after this process, there are still chips to be placed that have no reference to the chip to be placed except the initial chip, the above process starting from determining similar chips is repeated for these chips to be placed until each chip to be placed has a reference chip to be placed, or there are no similar chips to the chips to be placed that have no reference to the chip to be placed.

[0070] For example, when there are chips 1, 2, 3, and 4 to be laid out, and the similar chips of chip 1 to be laid out are 2, 3, and 4, the similar chips of chip 2 are 1 and 3, the similar chips of chip 3 are 1 and 2, and the similar chip of chip 4 is 1, since chip 1 has the highest number of similarities to other chips to be laid out, A is used as the initial chip, and the reference chips to be laid out for chips 2, 3, and 4 are all used as chip 1. Chip 1 has no reference chip to be laid out as the initial chip. In this way, the reference chips to be laid out for as many chips to be laid out as possible can be made the same, so the candidate layout parameters generated for a certain chip to be laid out can be migrated to multiple chips to be laid out, reducing the number of candidate layout parameters that need to be generated and improving the efficiency of chip layout generation.

[0071] It should be noted that the above are only two examples. In fact, other methods of selecting reference chips to be laid out may also be applicable to the embodiments of the present application.

[0072] Step 104, when the reference chip to be placed meets the placement parameter migration condition, each candidate placement parameter of the reference chip to be placed is used as the target candidate placement parameter of the target chip to be placed, and according to the placement quality index value of the reference chip to be placed corresponding to each candidate placement parameter, a parameter traversal strategy of the target chip to be placed is determined.

[0073] In the embodiment of the present application, the layout parameter refers to the input parameter of the chip layout model, such as the expected cell layout density, the operation mode of the model, etc. The chip layout model can be any model that can generate a chip layout design according to the input parameters. The layout parameter migration condition is pre-set to determine whether the candidate layout parameters of the reference chip to be laid out can be migrated to the target chip to be laid out, and if so, whether such migration can be started at present. Exemplarily, the condition for determining whether the candidate layout parameters of the reference chip to be laid out can be that the similarity between the reference chip to be laid out and the target chip to be laid out is greater than the similarity threshold (for example, when the chip with the greatest similarity to the chip to be laid out is selected as the reference chip to be laid out, the similarity between the reference chip to be laid out and the target chip to be laid out is not necessarily greater than the similarity threshold, so this condition needs to be set), the reference chip to be laid out has at least a preset number of components and the target chip to be laid out, etc. The condition for determining whether the migration can be started at present can be that the reference chip to be laid out has candidate layout parameters (which can be migrated from the reference chip to be laid out of the reference chip to be laid out itself, or generated). If the reference chip to be placed meets the placement parameter migration condition, the candidate placement parameters of the reference chip to be placed are migrated to the target chip to be placed as target candidate placement parameters of the target chip to be placed.

[0074] It should be noted that at least one set of candidate layout parameters needs to be generated for each chip to be laid out before the migration process can begin. The set of candidate layout parameters can be pre-set, for example, a set of verified candidate layout parameters with good performance can be prepared in advance, and the candidate layout parameters are used as the target candidate layout parameters of any chip to be laid out, and the migration process of the candidate layout parameters is started. The migration process of the candidate layout parameters can also be started after a set of candidate layout parameters is generated for any chip to be laid out, and the embodiments of the present application do not specifically limit this.

[0075] It should be noted that, in order to avoid the situation where multiple chips to be placed are each other's reference chips to be placed, and each chip to be placed is waiting for the reference chip to be placed to generate candidate placement parameters, resulting in the inability to start parameter migration, a waiting time can be set for each chip to be placed, and the waiting time can be determined according to the number of all chips to be placed, for example, it can be set to the product of the time required to generate candidate placement parameters for each chip to be placed and the number of all chips to be placed. After the waiting time is reached, it is considered that the reference chip to be placed does not meet the placement parameter migration conditions, and the step of generating candidate placement parameters for the target chip to be placed is executed.

[0076] After obtaining its own candidate layout parameters, each chip to be laid out will execute the steps of traversing the candidate layout parameters in order, inputting the candidate layout parameters and the circuit information of the chip to be laid out into the chip layout model to obtain a layout design, and obtaining the layout quality index value of the layout design. Therefore, when the candidate layout parameters are migrated to the target chip to be laid out, at least some of the candidate layout parameters will have a layout quality index value corresponding to the reference chip to be laid out. The layout quality index value is used to evaluate the quality of the layout design, and the higher the layout quality index value, the better the layout design. The layout quality index value can be specifically evaluated based on the total area of ​​the chip, the total length of the routing, the distance between each component, etc. after the chip is laid out using the layout design. The embodiment of the present application does not specifically limit how to determine the layout quality index value.

[0077] The parameter traversal strategy of the target chip to be laid out can be determined based on the layout quality index value of the reference chip to be laid out corresponding to the candidate layout parameters. Since the reference chip to be laid out and the target chip to be laid out are similar, the candidate layout parameters that perform well for the reference chip to be laid out (i.e., have a higher layout quality index value) are more likely to perform well for the target chip to be laid out.

[0078] In one example, each candidate layout parameter may be sorted from high to low according to the layout quality index value (if the reference chip to be laid out has not tried the candidate layout parameter, the layout quality index value of the candidate layout parameter corresponding to the reference chip to be laid out may be set to 0 or a smaller value), and each candidate layout parameter may be traversed in the order as a parameter traversal strategy.

[0079] In another example, the layout quality index value intervals may be divided, and each layout quality index value interval is arranged in descending order according to the corresponding layout quality index value. Each candidate layout parameter is divided into each layout quality index value interval according to the layout quality index value, and then each layout quality index value interval is traversed in the arrangement order of the layout quality index value interval, and all candidate layout parameters of the currently traversed layout quality index value interval are tried as the parameter traversal strategy.

[0080] It should be noted that the above are only two examples. In fact, other methods can also be used to generate parameter traversal strategies.

[0081] Step 106, traverse each target candidate layout parameter according to the parameter traversal strategy, input the target candidate layout parameter and the circuit information of the target chip to be laid out into the chip layout model for the currently traversed target candidate layout parameter, obtain the layout design corresponding to the target candidate layout parameter, and the layout quality index value corresponding to the layout design, and when the layout quality index value meets the preset index value condition, perform chip layout for the target chip to be laid out according to the layout design.

[0082] In an embodiment of the present application, after obtaining the parameter traversal strategy, each target candidate layout parameter is traversed according to the parameter traversal strategy. For the target candidate layout parameters currently traversed, the target candidate layout parameters and the circuit information of the target chip to be laid out are input into the chip layout model, and the layout design of the target chip to be laid out corresponding to the target candidate layout parameters and the layout quality index value corresponding to the layout design can be obtained. If the layout quality index value meets the preset index value condition, the chip layout is performed for the target chip to be laid out according to the layout design. If the layout quality index value does not meet the preset index value condition, the next target candidate layout parameter is continued to be traversed. If all the target candidate layout parameters are traversed and no target candidate layout parameter that meets the preset index value condition is found, then the layout design with the highest corresponding layout quality index value can be selected from the layout designs generated according to each target candidate layout parameter to lay out the target chip to be laid out, or the target candidate layout parameters can be regenerated for the target chip to be laid out, and the embodiment of the present application does not make specific limitations on this.

[0083] The preset indicator value condition can also be set according to actual needs. In one example, the preset indicator value condition is that the layout quality indicator value is greater than or equal to the preset indicator value threshold. That is, when the first target candidate layout parameter that meets the condition is traversed, the traversal of the remaining target candidate layout parameters is stopped, and the target chip to be laid out is laid out according to the layout design generated by the target candidate layout parameter that meets the condition. In another example, if multiple target candidate layout parameters are traversed at the same time each time according to the parameter traversal strategy (for example, the case where all candidate layout parameters in the layout quality indicator value interval are tried each time in the aforementioned example), the preset indicator value condition can be set to the highest layout quality indicator value among the target candidate layout parameters traversed in the same batch. The embodiment of the present application does not specifically limit this.

[0084] The chip layout method provided in the embodiment of the present application determines a reference chip to be laid out that is similar to the target chip to be laid out when performing layout design for a variety of different chips to be laid out. If the reference chip to be laid out can perform layout parameter migration, each candidate layout parameter used by the reference chip to be laid out is migrated to the target chip to be laid out, and the order in which the target chip to be laid out tries each candidate layout parameter (i.e., parameter traversal strategy) is determined based on the layout quality index value obtained by the reference chip to be laid out using each candidate layout parameter. Each candidate layout parameter is tried in order according to the parameter traversal strategy, and the candidate layout parameters are input into the chip layout model to obtain a layout design that meets the candidate layout parameters, and the layout quality index value of the layout design is determined. If the layout quality index value meets the requirements, the target chip to be laid out is laid out according to the layout design. When laying out the chip, the embodiment of the present application determines a reference chip to be laid out that can be used for reference, and uses the layout quality index value verified by the reference chip to be laid out for each candidate layout parameter as a reference to determine which candidate layout parameters should be used first for the layout of the target chip to be laid out. Since the reference chip to be laid out is similar to the target chip to be laid out, there is a high probability that the candidate layout parameters that perform well on the reference chip to be laid out can also perform well on the target chip to be laid out, so that the target chip to be laid out can find a layout design that meets the requirements after a small number of candidate layout parameter attempts, thereby improving the efficiency of chip layout generation.

[0085] In one embodiment, the method further includes:

[0086] When there is no reference chip to be placed for the target chip to be placed, or the reference chip to be placed does not meet the placement parameter migration condition, target candidate placement parameters of the target chip to be placed are generated, and a parameter traversal strategy of the target chip to be placed is determined according to each target candidate placement parameter.

[0087] In the embodiment of the present application, if the target chip to be laid out does not have a reference chip to be laid out, or the candidate layout parameters of the reference chip to be laid out cannot be migrated to the target chip to be laid out, it is necessary to generate target candidate layout parameters for the target chip to be laid out. In this case, a set of pre-generated general candidate layout parameters can be used as the target candidate layout parameters, the target candidate layout parameters can be randomly generated, or any heuristic algorithm can be used to generate the target candidate layout parameters.

[0088] After generating each target candidate layout parameter, the parameter traversal strategy of the target chip to be laid out can be determined according to each target candidate layout parameter. For example, if when generating each target candidate layout parameter, the layout quality index value predicted for each target candidate layout parameter is also generated, then the method of the aforementioned embodiment can be referred to, and the parameter traversal strategy of each target candidate layout parameter can be generated according to the predicted layout quality index value. Alternatively, the parameter traversal strategy can be used as the traversal in the order in which each target candidate layout parameter is generated, and the parameter traversal strategy can be used as the traversal in the order in which a certain parameter in the target candidate layout parameter is traversed from large to small.

[0089] In one embodiment, Figure 2 As shown, the target candidate layout parameters of the target chip to be laid out are generated, including:

[0090] Step 202, determining initial candidate layout parameters of the target chip to be laid out;

[0091] Step 204, inputting the initial candidate layout parameters into the chip layout model to obtain initial layout quality index values ​​corresponding to the initial candidate layout parameters;

[0092] Step 206, generating at least one target candidate layout parameter according to the initial candidate layout parameter, and determining a new initial candidate layout parameter from each target candidate layout parameter, wherein the expected layout quality index value of each target candidate layout parameter is greater than or equal to the initial layout quality index value;

[0093] Step 204 and step 206 are repeatedly performed until the number of target candidate layout parameters reaches a preset number.

[0094] In the embodiment of the present application, a combination of the expected improvement algorithm (EI) and the heuristic algorithm is used to generate target candidate layout parameters. First, the initial candidate layout parameters of the target chip to be laid out can be generated. The initial candidate layout parameters can be a good candidate layout parameter that has been verified before, or can also be a randomly generated candidate layout parameter.

[0095] After obtaining the initial candidate layout parameters, the initial candidate layout parameters are input into the chip layout model to obtain the initial layout quality index values ​​corresponding to the initial candidate layout parameters. Then, at least one target candidate layout parameter is derived based on the initial candidate layout parameters, and the expected layout quality index values ​​of these target candidate layout parameters (that is, the roughly estimated layout quality index values, which can be obtained by fitting the candidate layout parameters, circuit information and layout quality index values, and inputting the expected layout quality index values ​​and the circuit information of the target chip to be laid out into the function) should be greater than the initial layout quality index value. For example, multiple layout parameters can be randomly generated based on the initial candidate layout parameters, and the expected layout quality index value of each layout parameter can be calculated separately, and the layout parameters with expected layout quality index values ​​greater than the initial layout quality index values ​​are used as target candidate layout parameters.

[0096] After obtaining the target candidate layout parameters, one or more are selected as new initial candidate layout parameters (for example, the one with the largest expected layout quality index value is selected as the new initial candidate layout parameter), the steps of obtaining the initial layout quality index value corresponding to the initial candidate layout parameters, generating at least one target candidate layout parameter according to the initial candidate layout parameters, and determining new initial candidate layout parameters from the target candidate layout parameters are repeated until the number of target candidate layout parameters reaches a preset number.

[0097] See also Figure 3 As shown in FIG. 1 , an example of implementing the above method is shown. In this example, a sample set is maintained, which includes a set X of all target candidate layout parameters and a set Y of layout quality indicator values ​​corresponding to the target candidate layout parameters. Figure 3 middle represents any candidate layout parameter, Representatives will After input into the chip layout model, the layout quality index value obtained is represent When generating the target candidate layout parameters, the Kriging belief method is used (the initial layout quality index value obtained for the initial candidate layout parameters is used to estimate the expected layout quality index value, and the estimated The expected layout quality index value of the target candidate layout parameter is obtained by using the constant deception method (using the maximum value, minimum value or average value of the expected layout quality index values ​​of the existing target candidate layout parameters as the expected layout quality index value), and finally obtaining q target candidate layout parameters whose expected layout quality index values ​​are better than the original initial layout quality index values. These target candidate layout parameters are recorded in set X, and the expected layout quality index values ​​are temporarily recorded in set Y.

[0098] This example selects new initial candidate layout parameters by using the actual layout quality index values ​​corresponding to these target candidate layout parameters. These target candidate layout parameters are input into the chip layout model to obtain the layout quality index values ​​corresponding to each target candidate layout parameter, and then these layout quality index values ​​are used to replace the expected layout quality index values ​​in set Y. Using any expected improvement algorithm, a new initial candidate layout parameter with the maximum expected improvement is selected according to set X and set Y, and the above process is repeated until the number of target candidate layout parameters reaches a preset number.

[0099] The chip layout method provided in the embodiment of the present application repeatedly performs the steps of generating target candidate layout parameters that are better than the initial candidate layout parameters and selecting new initial candidate layout parameters from the target candidate layout parameters until the number of each target candidate layout parameter reaches a preset number. Thus, it is possible to generate multiple target candidate layout parameters that are better, increase the probability that the layout quality index value of the target candidate layout parameter meets the preset index value condition, and thus speed up the layout speed.

[0100] In one embodiment, Figure 4 As shown, the above method also includes:

[0101] Step 402, for any chip to be laid out, a first circuit information graph of the chip to be laid out is generated according to each standard cell in the chip to be laid out and the connection relationship between each standard cell, and a second circuit information graph of the chip to be laid out is generated according to each gate circuit in the chip to be laid out and the connection relationship between each gate circuit;

[0102] Step 404 , generating a circuit information vector of each chip to be laid out according to the first circuit information graph and the second circuit information graph of each chip to be laid out.

[0103] In the embodiment of the present application, since the migration of the standard cell layout of the chip is a difficult point, a first circuit information diagram characterizing the structure of each standard cell in the chip can be generated, and a circuit information vector of the chip to be laid out is generated through the first circuit information diagram and the second circuit information diagram capable of characterizing the most detailed gate circuit structure of the chip, so that chips with similar circuit information vectors will have similar gate circuit structures and similar standard cell structures, thereby making the overall performance of the reference chip to be laid out better. Therefore, the candidate layout parameters that perform better in the standard cell layout can also be applied to the standard cell layout of the target chip to be laid out with a high probability.

[0104] Reference Figure 5 As shown, it is a partial circuit diagram of the twisted ring counter of the chip to be laid out. In the figure, D represents input, Q represents output signal, It represents the opposite signal of Q, CLK is the clock signal, and FF is the flip-flop. Figure 6A local first circuit information diagram generated according to the local circuit diagram. Each vertex in the first circuit information diagram can represent a standard cell, or when there is a gate circuit that does not belong to any standard cell in the circuit, it can also represent a gate circuit. The connecting edges between the vertices represent that there is a connection relationship between the standard cells or between the standard cells and the gate circuits. The weight of the edge can be set by a person skilled in the art according to actual needs. For example, in the case of wanting to improve the layout effect of the interconnected standard cells A and standard cells B, the weight of the connecting edge between the vertex of the standard cell A and the vertex of the standard cell B in the first circuit information diagram can be appropriately increased, so that the chips with higher similarity between the circuit information vectors will also be more similar in the connection mode between the standard cell A and the standard cell B. If there is no similar demand, the weights of all connecting edges can be set to 1.

[0105] Similarly, each vertex in the second circuit information graph represents a gate circuit, and a connection relationship between vertices represents a connection relationship between gate circuits. Figure 7 As shown, Figure 5 The gate circuit structure diagram of the trigger in the twisted ring counter, where S represents the set input and R represents the reset input. Figure 8 After each trigger is split into gate circuits, a second circuit information graph at the gate circuit level is generated. The weight setting of each connecting edge in the second circuit information graph can refer to the first circuit information graph, and the embodiment of the present application will not be repeated here.

[0106] The first circuit information graph and the second circuit information graph can be converted into vector form by any graph characterization algorithm. The circuit information vector can be obtained by weighted summing, weighted averaging, splicing, etc. of the two vectors. The weight can be set according to actual needs. If the two chips to be laid out are expected to have a high similarity, the standard unit connection method of the two chips to be laid out can be characterized by a high similarity, and the weight of the first circuit information graph can be increased. If the similarity is expected to be high, the detailed gate circuit structure is characterized by a high similarity, and the weight of the second circuit information graph can be increased.

[0107] The chip layout method provided in the embodiment of the present application generates a first circuit information diagram representing the standard cell connection method and a second circuit information diagram representing the gate circuit connection method. The circuit information vector is generated based on the two information diagrams, so that chips with high circuit information vector similarity can have similar standard cell connection methods and gate circuit connection methods. Therefore, the candidate layout parameters that have better overall performance and better performance in standard cell layout for the reference chip to be laid out can also be applied to the standard cell layout of the target chip to be laid out with a high probability, which can improve the standard cell layout efficiency of the chip.

[0108] In one embodiment, Fig. 9As shown, in step 102, according to the similarity between the circuit information vectors of the chips to be laid out, a reference chip to be laid out of the target chip to be laid out is determined from the chips to be laid out, including:

[0109] Step 902, determining an initial chip to be placed from the chips to be placed, and taking the initial chip to be placed as the first chip to be placed;

[0110] Step 904, determining, from among the second chips to be laid out, a target second chip to be laid out whose circuit information vector has the greatest similarity to the circuit information vector of the first chip to be laid out; wherein the second chip to be laid out is a chip to be laid out other than the initial chip to be laid out and which does not have a reference chip to be laid out;

[0111] Step 906, using the first chip to be laid out as a reference chip to be laid out for the target second chip to be laid out, and using the target second chip to be laid out as the first chip to be laid out;

[0112] Step 904 and step 906 are repeatedly performed until there is no second chip to be laid out.

[0113] In an embodiment of the present application, in order to perform candidate layout parameter migration between various chips to be laid out as much as possible and reduce the number of candidate layout parameters that need to be generated, various chips to be laid out can be connected into a path according to similarity. When performing candidate layout parameter migration, after generating candidate layout parameters once for the chip to be laid out at the starting point of the path, candidate layout parameters can be continuously migrated to the chips to be laid out at the rear of the path.

[0114] First, any chip can be determined from the chips to be placed as the initial chip to be placed, which is the chip at the starting point of the path and has no reference chip to be placed. This chip is used as the first chip to be placed, and then a chip with the largest similarity to the first chip to be placed is selected from the chips to be placed other than the initial chip to be placed and that do not have a reference chip to be placed (the second chip to be placed) as the chip arranged after the first chip to be placed on the path. The reference chip to be placed for this chip is the first chip to be placed. Repeat this process until all chips are on the path and there is no second chip to be placed.

[0115] The above process is explained by taking chips 1, 2, 3, and 4 to be laid out as examples. Assuming that after calculating the similarity of every two chips to be laid out according to the circuit information vectors of each chip to be laid out, it is concluded that the chip with the greatest similarity to chip 1 is chip 4, the chip with the greatest similarity to chip 4 is chip 1, the chip with the greatest similarity to chip 2 is chip 3, and the chip with the greatest similarity to chip 3 is chip 2, then if the method of the embodiment of the present application is not adopted, but the chip with the greatest similarity is used as the reference chip to be laid out for the target chip to be laid out, chip 1 and chip 4, chip 2 and chip 3 will be each other's reference chips to be laid out, so it is necessary to generate candidate layout parameters for chip 1 or chip 4 once, and generate candidate layout parameters for chip 2 or chip 3 once to start the layout parameter migration process.

[0116] In the case of adopting the method of the embodiment of the present application, assuming that chip 1 is first used as the initial chip to be laid out, the target second chip to be laid out is chip 4, and chip 1 is the reference chip to be laid out for chip 4. Chip 4 is used as the first chip to be laid out, and the next target second chip to be laid out is determined from the chips to be laid out that do not have a reference chip to be laid out except the initial chip to be laid out. At this time, chip 1 is the initial chip to be laid out, and chip 4 has a reference chip to be laid out, so the second chips to be laid out at this time are chip 2 and chip 3. Assuming that chip 2 is the target second chip to be laid out with the greatest similarity to chip 4, chip 4 is the reference chip to be laid out for chip 2. Chip 2 is used as the first chip to be laid out, and the remaining second chip to be laid out is only chip 3, so the target second chip to be laid out is chip 3, and chip 2 is the reference chip to be laid out for chip 3. Therefore, a candidate layout parameter migration path of chip 1-chip 4-chip 2-chip 3 can be formed, and the layout parameter migration process can be started by generating candidate layout parameters for chip 1 only once.

[0117] It should be noted that, since the reference chip to be laid out of the chip to be laid out under this method is related to the initial chip to be laid out, in order to improve the similarity between each chip to be laid out and its own reference chip to be laid out and obtain the optimal candidate layout parameter migration path, the above process can be performed with different chips to be laid out as the initial chip to be laid out. After obtaining the reference chip to be laid out of each chip to be laid out each time, the similarities between each chip to be laid out and the reference chip to be laid out are summed as the similarity evaluation value corresponding to the initial chip to be laid out. Then, the reference chip to be laid out of each chip to be laid out obtained based on the initial chip to be laid out with the largest similarity evaluation value is used as the reference chip to be laid out of each chip to be laid out that is finally determined.

[0118] The chip layout method provided in the embodiment of the present application selects the chip with the greatest similarity to the chip to be laid out from the remaining chips to be laid out that do not have reference chips to be laid out, and uses the chip to be laid out as the reference chip to be laid out for the chip with the greatest similarity, and repeats the above process until each chip has a reference chip to be laid out. Therefore, the layout parameter migration process can be started by only generating candidate layout parameters for the initial chip to be laid out once, and at the same time, it can ensure that the similarity between the chip to be laid out and its reference chip to be laid out is high, which can improve the chip layout efficiency.

[0119] In one embodiment, Fig.10 As shown, the above method also includes:

[0120] Clustering the chips to be placed according to the circuit information vectors of the chips to be placed, to obtain at least one category of the chips to be placed;

[0121] When the category of chips to be placed to which the target chip to be placed belongs is the same as the category of chips to be placed to which the reference chip to be placed belongs, it is determined that the reference chip to be placed meets the layout parameter migration condition; or when the similarity between the target chip to be placed and the reference chip to be placed is greater than or equal to a similarity threshold, it is determined that the reference chip to be placed meets the layout parameter migration condition.

[0122] In an embodiment of the present application, the layout parameter migration condition may be that the target chip to be laid out and the reference chip to be laid out belong to the same category of chips to be laid out, or the similarity between the two chips is greater than a threshold. Each chip to be laid out may be clustered according to the circuit information vector of each chip to be laid out to obtain at least one category of chips to be laid out. In order to improve the accuracy of the category division, multiple clustering may be performed, and a different number of preset categories may be specified for each clustering. After clustering according to the preset number of categories is completed, the contour coefficient of the category of chips to be laid out clustered this time is calculated according to any clustering contour coefficient algorithm. Then, each category of chips to be laid out corresponding to the clustering with the best contour coefficient is selected as the final category of chips to be laid out.

[0123] If the target chip to be laid out and the reference chip to be laid out belong to the same category of chips to be laid out, it indicates that the target chip to be laid out and the reference chip to be laid out are relatively similar, so the candidate layout parameter migration of the reference chip to be laid out to the target chip to be laid out can be initiated. Alternatively, if the similarity between the target chip to be laid out and the reference chip to be laid out is high, it also indicates that the target chip to be laid out and the reference chip to be laid out are relatively similar, so the candidate layout parameter migration of the reference chip to be laid out to the target chip to be laid out can be initiated.

[0124] The two conditions are used as layout parameter migration conditions because the reference chip to be laid out for the target chip to be laid out may not be selected based solely on similarity. Therefore, it may happen that chip 1 is similar to chip 2, chip 2 is similar to chip 3, and chip 1 is not very similar to chip 3, but chip 1 is the reference chip to be laid out for chip 3. In this case, theoretically, since the layout parameter migration of chip 1-chip 2-chip 3 can be performed, chip 1 can migrate layout parameters to chip 3. However, if it is determined whether the candidate layout parameter migration can be started based solely on similarity, it will be concluded that chip 1 cannot migrate candidate layout parameters to chip 3, resulting in the need to regenerate the target candidate layout parameters for chip 1, reducing chip layout efficiency. When the above two conditions are used, chip 1, chip 2, and chip 3 will be clustered into the same category of chips to be laid out. Therefore, when the layout parameter migration condition is determined, chip 1 will be determined to be eligible for candidate layout parameter migration to chip 3.

[0125] The chip layout method provided in the embodiment of the present application adopts the condition that the target chip to be laid out and the reference chip to be laid out belong to the same category of chips to be laid out, or that the target chip to be laid out and the reference chip to be laid out have a high similarity as the layout parameter migration condition, thereby enriching the similarity judgment criteria between chips. Therefore, layout parameter migration can be performed even between chips that are not similar based on similarity but are similar based on clustering results, thereby reducing the number of times the target candidate layout parameters are regenerated and improving layout efficiency.

[0126] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0127] Based on the same inventive concept, the embodiment of the present application also provides a chip layout device for implementing the chip layout method involved above. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in one or more chip layout device embodiments provided below can refer to the limitations of the chip layout method above, and will not be repeated here.

[0128] In one embodiment, Fig.11 As shown, a chip layout device 1100 is provided, comprising: a first determination module 1102, a migration module 1104, and a layout module 1106, wherein:

[0129] A first determination module 1102 is configured to determine a reference chip to be placed of a target chip to be placed from among the chips to be placed according to the similarity between the circuit information vectors of the chips to be placed; the target chip to be placed is any one of the chips to be placed;

[0130] The migration module 1104 is used to use each candidate layout parameter of the reference chip to be placed as the target candidate layout parameter of the target chip to be placed if the reference chip to be placed meets the layout parameter migration condition, and determine the parameter traversal strategy of the target chip to be placed according to the layout quality index value of each candidate layout parameter corresponding to the reference chip to be placed;

[0131] The layout module 1106 is used to traverse each of the target candidate layout parameters according to the parameter traversal strategy, and for the currently traversed target candidate layout parameters, input the target candidate layout parameters and the circuit information of the target chip to be laid out into the chip layout model, obtain the layout design corresponding to the target candidate layout parameters, and the layout quality index value corresponding to the layout design, and when the layout quality index value meets the preset index value condition, perform chip layout on the target chip to be laid out according to the layout design.

[0132] The chip layout device provided in the embodiment of the present application determines a reference chip to be laid out that is similar to the target chip to be laid out when performing layout design for a variety of different chips to be laid out. If the reference chip to be laid out can perform layout parameter migration, each candidate layout parameter used by the reference chip to be laid out is migrated to the target chip to be laid out, and the order in which the target chip to be laid out tries each candidate layout parameter (i.e., parameter traversal strategy) is determined based on the layout quality index value obtained by the reference chip to be laid out using each candidate layout parameter. Each candidate layout parameter is tried in the order of the parameter traversal strategy, and the candidate layout parameters are input into the chip layout model to obtain a layout design that meets the candidate layout parameters, and the layout quality index value of the layout design is determined. If the layout quality index value meets the requirements, the target chip to be laid out is laid out according to the layout design. When laying out the chip, the embodiment of the present application determines a reference chip to be laid out that can be used for reference, and uses the layout quality index value verified by the reference chip to be laid out for each candidate layout parameter as a reference to determine which candidate layout parameters should be used first for the layout of the target chip to be laid out. Since the reference chip to be laid out is similar to the target chip to be laid out, there is a high probability that the candidate layout parameters that perform well on the reference chip to be laid out can also perform well on the target chip to be laid out, so that the target chip to be laid out can find a layout design that meets the requirements after a small number of candidate layout parameter attempts, thereby improving the efficiency of chip layout generation.

[0133] In one embodiment, the device further comprises:

[0134] The first generating module is used to generate the target candidate layout parameters of the target chip to be placed if the reference chip to be placed of the target chip to be placed does not exist or the reference chip to be placed does not meet the layout parameter migration condition, and determine the parameter traversal strategy of the target chip to be placed according to each of the target candidate layout parameters.

[0135] In one embodiment, the first generating module is further used for:

[0136] Determining initial candidate layout parameters of the target chip to be laid out, and inputting the initial candidate layout parameters into a chip layout model to obtain initial layout quality index values ​​corresponding to the initial candidate layout parameters;

[0137] generating at least one target candidate layout parameter according to the initial candidate layout parameter, and determining a new initial candidate layout parameter from each of the target candidate layout parameters, wherein an expected layout quality index value of each of the target candidate layout parameters is greater than or equal to the initial layout quality index value;

[0138] The steps of inputting the initial candidate layout parameters into a chip layout model, obtaining initial layout quality indicator values ​​corresponding to the initial candidate layout parameters, generating at least one target candidate layout parameter according to the initial candidate layout parameters, and determining new initial candidate layout parameters from each of the target candidate layout parameters are repeatedly performed until the number of each of the target candidate layout parameters reaches a preset number.

[0139] In one embodiment, the device further comprises:

[0140] A second generating module is used to generate, for any of the chips to be laid out, a first circuit information graph of the chip to be laid out according to each standard cell in the chip to be laid out and the connection relationship between each standard cell, and to generate a second circuit information graph of the chip to be laid out according to each gate circuit in the chip to be laid out and the connection relationship between each gate circuit;

[0141] The third generating module is used to generate a circuit information vector of each chip to be laid out according to the first circuit information graph and the second circuit information graph of each chip to be laid out.

[0142] In one embodiment, the first determining module 1102 is further configured to:

[0143] Determine an initial chip to be placed from each of the chips to be placed, take the initial chip to be placed as the first chip to be placed, and determine a target second chip to be placed whose circuit information vector has the greatest similarity to the circuit information vector of the first chip to be placed from each of the second chips to be placed; wherein the second chip to be placed is a chip to be placed other than the initial chip to be placed and does not have a reference chip to be placed;

[0144] The first chip to be laid out is used as a reference chip to be laid out for the target second chip to be laid out, the target second chip to be laid out is used as a first chip to be laid out, and the steps of determining, from among the second chips to be laid out, a target second chip to be laid out having a circuit information vector having the greatest similarity to the circuit information vector of the first chip to be laid out, and using the first chip to be laid out as a reference chip to be laid out for the target second chip to be laid out are repeatedly performed until there is no second chip to be laid out.

[0145] In one embodiment, the device further comprises:

[0146] A clustering module, configured to perform clustering processing on each of the chips to be arranged according to the circuit information vector of each of the chips to be arranged, so as to obtain at least one category of the chips to be arranged;

[0147] The second determination module is used to determine that the reference chip to be placed meets the layout parameter migration condition when the category of the chip to be placed to which the target chip to be placed belongs is the same as the category of the chip to be placed to which the reference chip to be placed belongs; or to determine that the reference chip to be placed meets the layout parameter migration condition when the similarity between the target chip to be placed and the reference chip to be placed is greater than or equal to a similarity threshold.

[0148] Each module in the above device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module above.

[0149] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Fig.12 As shown. The computer device includes a processor, a memory and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a chip layout method is implemented.

[0150] Those skilled in the art will understand that Fig.12 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0151] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0152] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0153] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0154] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0155] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0156] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0157] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A chip layout method, characterized in that: The method comprises: Determining a reference chip to be laid out of a target chip to be laid out from the chips to be laid out according to the similarity between the circuit information vectors of the chips to be laid out; the target chip to be laid out is any one of the chips to be laid out; In the case that the reference chip to be laid out meets the layout parameter migration condition, each candidate layout parameter of the reference chip to be laid out is used as the target candidate layout parameter of the target chip to be laid out, and according to the layout quality index value of each candidate layout parameter corresponding to the reference chip to be laid out, a parameter traversal strategy of the target chip to be laid out is determined; Each of the target candidate layout parameters is traversed according to the parameter traversal strategy. For the currently traversed target candidate layout parameters, the target candidate layout parameters and the circuit information of the target chip to be laid out are input into the chip layout model to obtain a layout design corresponding to the target candidate layout parameters and a layout quality index value corresponding to the layout design. When the layout quality index value satisfies a preset index value condition, chip layout is performed on the target chip to be laid out according to the layout design.

2. The method according to claim 1, characterized in that The method further comprises: When the reference chip to be placed does not exist for the target chip to be placed, or the reference chip to be placed does not meet the placement parameter migration condition, the target candidate placement parameters of the target chip to be placed are generated, and a parameter traversal strategy of the target chip to be placed is determined according to each of the target candidate placement parameters.

3. The method according to claim 2, characterized in that The generating the target candidate layout parameters of the target chip to be laid out includes: Determining initial candidate layout parameters of the target chip to be laid out, and inputting the initial candidate layout parameters into a chip layout model to obtain initial layout quality index values ​​corresponding to the initial candidate layout parameters; generating at least one target candidate layout parameter according to the initial candidate layout parameter, and determining a new initial candidate layout parameter from each of the target candidate layout parameters, wherein an expected layout quality index value of each of the target candidate layout parameters is greater than or equal to the initial layout quality index value; The steps of inputting the initial candidate layout parameters into a chip layout model, obtaining initial layout quality indicator values ​​corresponding to the initial candidate layout parameters, generating at least one target candidate layout parameter according to the initial candidate layout parameters, and determining new initial candidate layout parameters from each of the target candidate layout parameters are repeatedly performed until the number of each of the target candidate layout parameters reaches a preset number.

4. The method according to claim 1, characterized in that: The method further comprises: For any of the chips to be laid out, a first circuit information graph of the chip to be laid out is generated according to each standard cell in the chip to be laid out and the connection relationship between each standard cell, and a second circuit information graph of the chip to be laid out is generated according to each gate circuit in the chip to be laid out and the connection relationship between each gate circuit; A circuit information vector of each chip to be laid out is generated according to the first circuit information graph and the second circuit information graph of each chip to be laid out.

5. The method according to claim 1 or 4, characterized in that: The step of determining a reference chip to be laid out of a target chip to be laid out from the chips to be laid out according to the similarity between the circuit information vectors of the chips to be laid out comprises: Determine an initial chip to be placed from each of the chips to be placed, take the initial chip to be placed as the first chip to be placed, and determine a target second chip to be placed whose circuit information vector has the greatest similarity to the circuit information vector of the first chip to be placed from each of the second chips to be placed; wherein the second chip to be placed is a chip to be placed other than the initial chip to be placed and does not have a reference chip to be placed; The first chip to be laid out is used as a reference chip to be laid out for the target second chip to be laid out, the target second chip to be laid out is used as a first chip to be laid out, and the steps of determining, from among the second chips to be laid out, a target second chip to be laid out having a circuit information vector having the greatest similarity to the circuit information vector of the first chip to be laid out, and using the first chip to be laid out as a reference chip to be laid out for the target second chip to be laid out are repeatedly performed until there is no second chip to be laid out.

6. The method according to claim 1, characterized in that The method further comprises: Clustering the chips to be placed according to the circuit information vectors of the chips to be placed, to obtain at least one category of chips to be placed; When the category of chips to be placed to which the target chip to be placed belongs is the same as the category of chips to be placed to which the reference chip to be placed belongs, it is determined that the reference chip to be placed meets the layout parameter migration condition; or when the similarity between the target chip to be placed and the reference chip to be placed is greater than or equal to a similarity threshold, it is determined that the reference chip to be placed meets the layout parameter migration condition.

7. A chip layout device, characterized in that: The device comprises: A first determination module is used to determine a reference chip to be placed of a target chip to be placed from the chips to be placed according to the similarity between the circuit information vectors of the chips to be placed; the target chip to be placed is any one of the chips to be placed; a migration module, configured to use each candidate layout parameter of the reference chip to be laid out as a target candidate layout parameter of the target chip to be laid out, if the reference chip to be laid out meets the layout parameter migration condition, and determine a parameter traversal strategy of the target chip to be laid out according to the layout quality index value of each candidate layout parameter corresponding to the reference chip to be laid out; A layout module is used to traverse each of the target candidate layout parameters according to the parameter traversal strategy, and for the currently traversed target candidate layout parameters, input the target candidate layout parameters and the circuit information of the target chip to be laid out into a chip layout model, obtain a layout design corresponding to the target candidate layout parameters, and a layout quality index value corresponding to the layout design, and when the layout quality index value meets a preset index value condition, perform chip layout on the target chip to be laid out according to the layout design.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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