Processing control method, device, equipment, storage medium and product of combined equipment

Abstract

The present application discloses a processing control method, device, equipment, storage medium and product of a combined device, and relates to the field of semiconductor manufacturing technology. In the present application, for any group of parallel target processing modules in a plurality of processing modules, the initial cumulative process times of each target processing module are constructed to obtain each candidate initial cumulative process time set; the candidate initial cumulative process time set with the shortest average wafer processing cycle is selected from each candidate initial cumulative process time set as the target initial cumulative process time set; the initial cumulative process times of each target processing module in the target initial cumulative process time set are converted into the theoretical delayed start time of each target processing module, and based on the theoretical delayed start time of each target processing module, each target processing module is started to process the wafers in the wafer group to be processed, so as to stagger the time when each target processing module enters the cleaning step, thereby avoiding the problem of centralized cleaning of the processing modules.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a processing control method, device, equipment, storage medium and product of a combined device. Background Art

[0002] Wafer manufacturing is a key link in the semiconductor industry, involving the production process from raw materials to finished wafers, mainly including thin film deposition, glue coating, exposure, development, etching, cleaning and other processes, with complex processes and high degree of automation. Cluster tool has the advantages of versatility, space and cost saving, improved production efficiency, reduced production risks, energy saving and environmental protection, and strong adaptability. It is one of the indispensable important equipment in the semiconductor manufacturing industry and is often used in processes such as thin film deposition and etching. Usually, Cluster Tool consists of a vacuum end, an atmospheric end, and a vacuum lock responsible for connecting the two ends. Each end is responsible for loading / unloading wafers by different types of manipulators. According to the differences in the nature of the process area, there are a variety of processing modules (PM, Process Module) responsible for wafer processes, such as: the atmospheric end is responsible for wafer calibration, cooling, etc.; the vacuum end is determined by the use of Cluster Tool to be responsible for thin film deposition, etching and other processes; and the vacuum lock is usually used to provide a safe transfer mechanism between the vacuum end and the atmospheric end to prevent air from suddenly entering the vacuum chamber or a large amount of gas in the vacuum chamber from leaking out, thereby protecting the equipment and process from damage.

[0003] During the process, the PM chamber produces particles and residual chemicals after each wafer processing, and as the number of times increases, it often affects the quality of the subsequent processed wafers. Therefore, in order to maintain the cleanliness of the chamber, the PM needs to perform a chamber cleaning operation after processing n wafers. However, each time the PM performs cleaning, the robot will be idle because it cannot operate the PM. This phenomenon will be aggravated as the chamber process time or cleaning time increases, thereby affecting the production efficiency of the equipment. In this regard, the industry often solves this problem by increasing the number of parallel PMs. However, due to the high cost of the equipment and the spatial scalability, when the ratio of cleaning time, process time, and robot cycle is large, there may be a moment when the PMs of the parallel process are cleaned at the same time, which is called centralized cleaning. At this time, the robot will still be idle due to the cleaning time, thereby affecting the overall production efficiency.

[0004] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The main purpose of this application is to provide a processing control method, device, equipment, storage medium and product for a combined device, aiming to solve the technical problem that centralized PM cleaning of parallel processes affects the overall production efficiency.

[0006] To achieve the above-mentioned purpose, the present application proposes a processing control method of a combined device, wherein a plurality of processing modules are provided in the combined device, wherein the processing module will enter a cleaning step after the cumulative number of wafer processing times exceeds a preset number, and the processing control method of the combined device includes:

[0007] For any group of parallel target processing modules among the multiple processing modules, construct the initial cumulative process times of each target processing module to obtain each candidate initial cumulative process time set, wherein the candidate initial cumulative process time set includes the initial cumulative process times of each target processing module, and the initial cumulative process times of each target processing module in one candidate initial cumulative process time set are different;

[0008] Selecting from the candidate initial cumulative process times sets, a candidate initial cumulative process times set with the shortest average wafer processing cycle as a target initial cumulative process times set;

[0009] Converting the initial cumulative process times of each target processing module in the target initial cumulative process times set into the theoretical delayed start time of each target processing module;

[0010] When a wafer group to be processed is being processed for the first time by each target processing module, based on the theoretical delayed start time of each target processing module, each target processing module is started to start processing the wafers in the wafer group to be processed so as to stagger the time when each target processing module enters the cleaning step, wherein the processing parameters of each wafer in the wafer group to be processed are the same.

[0011] Before the step of selecting, from among the candidate initial cumulative process number sets, a candidate initial cumulative process number set with the shortest average wafer processing cycle as a target initial cumulative process number set, the method includes:

[0012] For any one of the candidate initial cumulative process number sets in the candidate initial cumulative process number sets, configure the initial cumulative process number in the candidate initial cumulative process number set for each target processing module to obtain an initialized processing module group;

[0013] Simulating the processing steps of the initialization processing module group to process the wafer within a preset period to obtain the number of wafers processed in the preset period, wherein the processing steps include wafer process steps and processing module cleaning steps;

[0014] Based on the preset cycle and the wafer processing quantity, the average wafer processing cycle of the candidate initial cumulative process number set is calculated.

[0015] Optionally, the step of converting the initial cumulative process times of each target processing module in the target initial cumulative process times into a theoretical delayed start time of each target processing module includes:

[0016] The simulation obtains the execution time required for each target processing module to complete each initial cumulative number of processes;

[0017] The execution time required to complete each initial cumulative number of processes is used as the theoretical delayed start time of each corresponding target processing module.

[0018] Optionally, the step of starting each target processing module to start processing the wafers in the wafer group to be processed based on the theoretical delayed start time of each target processing module includes:

[0019] For any one of the target processing modules, if the actual accumulated process times of the target processing modules are reset before the wafer group to be processed is processed, then after waiting for the theoretical delayed start time of the target processing module, the target processing module is started to start processing the wafers in the wafer group to be processed.

[0020] Optionally, the step of delaying starting each target processing module to process the wafer based on the theoretical delayed start time of each target processing module further includes:

[0021] If the actual accumulated number of processes of each target processing module is not reset before processing the wafer group to be processed, then determining the idle time of each target processing module when each target processing module enters an idle state;

[0022] Obtaining the intermediate duration of the target processing module based on the sum of the idle duration of the target processing module and the theoretical delayed start duration of the target processing module;

[0023] After subtracting the common delay time from the intermediate time of the target processing module, the actual delayed start time of the target processing module is obtained, wherein the common delay time is the smallest intermediate time among the intermediate times of the target processing modules;

[0024] After waiting for the actual delayed start time of the target processing module, the target processing module is started to start processing the wafers in the wafer group to be processed.

[0025] Optionally, the step of constructing the initial cumulative process times of each target processing module to obtain each candidate initial cumulative process times set includes:

[0026] Based on a preset arithmetic difference rule, the initial cumulative process times of each target processing module are constructed to obtain each candidate initial cumulative process time set, wherein each candidate initial cumulative process time in the candidate initial cumulative process time set constitutes an arithmetic difference array, and the maximum tolerance of the constituted arithmetic difference array is determined based on the number of each target processing module.

[0027] In addition, to achieve the above-mentioned purpose, the present application also proposes a processing control device of a combined device, wherein a plurality of processing modules are arranged in the combined device, wherein the processing module will enter a cleaning step after the cumulative number of wafer processing times exceeds a preset number, and the processing control device of the combined device includes:

[0028] A construction unit is used to construct the initial cumulative process times of each target processing module for any group of parallel target processing modules among the multiple processing modules, and obtain each candidate initial cumulative process time set, wherein the candidate initial cumulative process time set includes the initial cumulative process times of each target processing module, and the initial cumulative process times of each target processing module in one candidate initial cumulative process time set are different;

[0029] A selection unit, configured to select, from the candidate initial cumulative process number sets, a candidate initial cumulative process number set with the shortest average wafer processing cycle as a target initial cumulative process number set;

[0030] A conversion unit, used for converting the initial cumulative process times of each target processing module in the target initial cumulative process times set into a theoretical delayed start time of each target processing module;

[0031] A control unit is used to start each target processing module to start processing the wafers in the wafer group to be processed based on a theoretical delayed start time of each target processing module when a wafer group to be processed is processed for the first time by each target processing module, so as to stagger the time when each target processing module enters a cleaning step, wherein the processing parameters of each wafer in the wafer group to be processed are the same.

[0032] In addition, to achieve the above-mentioned purpose, the present application also proposes an electronic device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the processing control method of the combined device as described above.

[0033] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the processing control method of the combined device as described above are implemented.

[0034] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of the processing control method of the combined device as described above are implemented.

[0035] One or more technical solutions proposed in this application have at least the following technical effects:

[0036] In this embodiment, for any group of parallel target processing modules among the multiple processing modules, the combination device will construct the initial cumulative process times of each target processing module to obtain each candidate initial cumulative process number set, wherein the candidate initial cumulative process number set includes the initial cumulative process times of each target processing module, and the initial cumulative process times of each target processing module in a candidate initial cumulative process number set are different; from the candidate initial cumulative process number sets, the candidate initial cumulative process number set with the shortest average wafer processing cycle is selected as the target initial cumulative process number set; the initial cumulative process times of each target processing module in the target initial cumulative process number set is converted into a theoretical delayed start time of each target processing module; in the case that there is a wafer group to be processed being processed by each target processing module for the first time, based on the theoretical delayed start time of each target processing module, each target processing module is started to start processing the wafers in the wafer group to be processed, so as to stagger the time when each target processing module enters the cleaning step, wherein the processing parameters of each wafer in the wafer group to be processed are the same. It is understandable that, since the initial cumulative process times of each target processing module in the constructed candidate initial cumulative process times set are different, for any candidate initial cumulative process times set, the selected initial cumulative process times set can ensure that any two target processing modules will not enter the cleaning step at the same time, thereby minimizing the possibility of robot idleness. Further, after obtaining each candidate initial cumulative process times set, the candidate initial cumulative process times set with the shortest average wafer processing cycle is selected as the target initial cumulative process times set, so as to ensure the fastest processing efficiency of the wafer as much as possible under the condition of staggered cleaning. In addition, in order to facilitate actual operation control, the initial cumulative process times in the target initial cumulative process times set are converted into the theoretical delayed start time of each target processing module, and when starting to process the wafer group to be processed, according to the theoretical delayed start time of each target processing module, control the start of each target processing module to process the wafers in the wafer group to be processed. Since the processing parameters of each wafer in the wafer group to be processed are the same, it can be ensured that the above-mentioned delayed start-up processing module method can accurately stagger the cleaning steps of each target processing module, avoid centralized cleaning, and cause the robot to be idle, thereby ensuring that the overall production efficiency will not be affected by centralized cleaning. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0039] Figure 1 This is a schematic flow chart of the first embodiment of the processing control method of the combined device of the present application;

[0040] Figure 2 This is a flow chart of a second embodiment of the processing control method of the combined device of the present application;

[0041] Figure 3 This is a flow chart of a third embodiment of the processing control method of the combined device of the present application;

[0042] Figure 4 A schematic diagram of the structure of a processing control device of a combined device in a processing control method of a combined device of the present application;

[0043] Figure 5 This is a schematic diagram of the device structure of the hardware operating environment involved in the processing control method of the combined device in the embodiment of the present application.

[0044] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0045] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0046] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0047] At present, in the wafer processing process, the PM chamber produces particles and residual chemicals after each wafer processing, and as the number of times increases, it often affects the quality of the subsequent processed wafers. Therefore, in order to maintain the cleanliness of the chamber, the PM needs to perform a chamber cleaning operation after processing n wafers. However, each time the PM performs cleaning, the robot will be idle because it cannot operate the PM. This phenomenon will be aggravated as the chamber process time or cleaning time increases, thereby affecting the production efficiency of the equipment. In this regard, the industry often solves this problem by increasing the number of parallel PMs. However, due to the high cost of the equipment and the spatial scalability, when the ratio of cleaning time, process time, and robot cycle is large, there may be a moment when the PMs of the parallel process are cleaned at the same time, which is called centralized cleaning. At this time, the robot will still be idle due to the cleaning time, thereby affecting the overall production efficiency.

[0048] In the embodiment of the present application, a plurality of processing modules are arranged in the combined device, wherein the processing module will enter a cleaning step after the cumulative number of wafer processing times exceeds a preset number of times. The main solution of the corresponding embodiment of the present application is: a plurality of processing modules are arranged in the combined device, wherein the processing module will enter a cleaning step after the cumulative number of wafer processing times exceeds a preset number of times. For any group of parallel target processing modules among the plurality of processing modules, an initial cumulative number of processes of each target processing module is constructed to obtain each candidate initial cumulative number of processes set, wherein the candidate initial cumulative number of processes set includes the initial cumulative number of processes of each target processing module, and each in a candidate initial cumulative number of processes set The target processing modules have different initial cumulative process times; a candidate initial cumulative process time set with the shortest average wafer processing cycle is selected from the candidate initial cumulative process time sets as a target initial cumulative process time set; the initial cumulative process times of each target processing module in the target initial cumulative process time set are converted into a theoretical delayed start time of each target processing module; when there is a wafer group to be processed for the first time by each target processing module, each target processing module is started to process the wafers in the wafer group to be processed based on the theoretical delayed start time of each target processing module, so as to stagger the time when each target processing module enters the cleaning step, wherein the processing parameters of each wafer in the wafer group to be processed are the same.

[0049] It is understandable that, since the initial cumulative process times of each target processing module in the candidate initial cumulative process times set constructed by the present application are different, for any candidate initial cumulative process times set, the selected initial cumulative process times set can ensure that any two target processing modules will not enter the cleaning step at the same time, thereby minimizing the possibility of robot idleness. Further, after obtaining each candidate initial cumulative process times set, the candidate initial cumulative process times set with the shortest average wafer processing cycle is selected as the target initial cumulative process times set, so as to ensure the fastest processing efficiency of the wafer as much as possible under the condition of staggered cleaning. In addition, in order to facilitate actual operation control, the initial cumulative process times in the target initial cumulative process times set are converted into the theoretical delayed start time of each target processing module, and when starting to process the wafer group to be processed, according to the theoretical delayed start time of each target processing module, control the start of each target processing module to process the wafers in the wafer group to be processed. Since the processing parameters of each wafer in the wafer group to be processed are the same, it can be ensured that the above-mentioned delayed start-up processing module method can accurately stagger the cleaning steps of each target processing module, avoid centralized cleaning, and cause the robot to be idle, thereby ensuring that the overall production efficiency will not be affected by centralized cleaning.

[0050] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a vehicle, a car computer, a cloud server, a computer, a mobile phone, etc., or an electronic device that can realize the above functions.

[0051] Based on this, the embodiment of the present application provides a processing control method of a combined device, referring to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the processing control method of the combined equipment of the present application.

[0052] In this embodiment, a plurality of processing modules are provided in the combined device, wherein the cumulative number of wafer process processing performed by the processing module exceeds a preset number of times, and the cleaning step will be entered. It should be noted that the combined device may be a Cluster tool, in which a plurality of processing modules are provided, wherein the functional types of the processing modules may include thin film deposition, etching, etc., and correspondingly, the functional types of different processing modules may be the same or different, and are not limited here, and under normal circumstances, when the cumulative number of wafer process processing performed by a processing module exceeds a preset number of times, the processing module will enter the cleaning step, and after the processing module completes the cleaning, its cumulative number of processes will be reset to 0.

[0053] The processing control method of the combined equipment includes steps S10 to S30:

[0054] Step S10, for any group of parallel target processing modules among the plurality of processing modules, construct an initial cumulative process number of each target processing module to obtain each candidate initial cumulative process number set, wherein the candidate initial cumulative process number set includes the initial cumulative process number of each target processing module, and the initial cumulative process number of each target processing module in one candidate initial cumulative process number set is different;

[0055] It should be noted that the implementation subject of the processing control method of the above-mentioned combined device can be a combined device or a cloud server connected to the combined device. In addition, the target processing modules that can work in parallel refer to that each target processing module can process the wafer at the same time. It is worth noting that since the target processing modules can work in parallel, it means that each target processing module may also enter the cleaning step (centralized cleaning) at the same time, which causes the manipulator to enter an idle state, that is, if the processing modules enter the cleaning step at the same time, it may cause a situation where there is no wafer to be transferred temporarily in the combined device, and accordingly, there is no work for the manipulator to perform, so that the manipulator is idle. Therefore, in order to avoid the situation of centralized cleaning of the processing module, the present application will control the timing of starting each processing module to stagger the cleaning time of each processing module. In addition, in actual applications, the multiple processing modules of the combined device may include multiple groups of parallel target processing modules, and the control method of each group of parallel target processing modules is the same, so in this implementation, one of the parallel processing modules will be used as an example for explanation.

[0056] Exemplarily, for any group of parallel target processing modules among the multiple processing modules, the initial cumulative process times of each target processing module are constructed to obtain multiple candidate initial cumulative process times sets. It should be noted that the initial cumulative process times of a target processing module refers to the number of times the target processing module has performed wafer processing in the initial period. Usually, the initial cumulative process times will not exceed the threshold of the process times for the processing module to trigger cleaning. A candidate initial cumulative process times set will include the initial cumulative process times of each target processing module in this group, and the initial cumulative process times of each target processing module in a candidate initial cumulative process times set are different. It can be understood that the different initial cumulative process times of each target processing module in the candidate initial cumulative process times set can ensure that any two target processing modules in the group will not enter the cleaning step at the same time, thereby minimizing the possibility of robot idleness.

[0057] Step S20, selecting from the candidate initial cumulative process number sets, a candidate initial cumulative process number set with the shortest average wafer processing cycle as a target initial cumulative process number set;

[0058] Exemplarily, after obtaining each candidate initial cumulative process number set, it is possible to simulate the scenario in which each target processing module starts wafer processing when the initial cumulative process number in each candidate initial cumulative process number set is configured for each target processing module, and record the average wafer processing cycle of the group of target processing modules after each target processing module is configured with each candidate initial cumulative process number set. Accordingly, each candidate initial cumulative process number set can obtain an average wafer processing cycle, and then the candidate initial cumulative process number set with the shortest average wafer processing cycle can be used as the target initial cumulative process number set.

[0059] It can be understood that after configuring the initial cumulative process times in the candidate initial cumulative process times set for each target processing module, since the initial cumulative process times of each target processing module are different, it can be ensured that each target processing module will not be centrally cleaned. A candidate initial cumulative process times set is equivalent to a method of staggering the cleaning steps of each target processing module. On this basis, the candidate initial cumulative process times set with the shortest average processing cycle of the wafer is selected as the target initial cumulative process times set, and the target initial cumulative process times set is used in the subsequent actual control steps, so as to ensure the fastest processing efficiency of the wafer as much as possible while achieving staggered cleaning.

[0060] Step S30, converting the initial cumulative process times of each target processing module in the target initial cumulative process times set into a theoretical delayed start time of each target processing module;

[0061] It should be noted that, since the process of obtaining the theoretical delayed start time of each target processing module is basically the same, in this embodiment, one of the target processing modules will be taken as an example for description.

[0062] Exemplarily, for any one of the target processing modules, the initial cumulative process times of the target processing module in the target initial cumulative process times set is converted into the theoretical delayed start time of the target processing module. For example, the time required for the target processing module to perform wafer processing to reach the initial cumulative process times of the target processing module in the target initial cumulative process times set can be obtained by simulation, and the required time is used as the theoretical delayed start time of the target processing module. And through the above method, the theoretical delayed start time of each target processing module can be obtained.

[0063] Step S40, when there is a wafer group to be processed being processed for the first time by each target processing module, based on the theoretical delayed start time of each target processing module, start each target processing module to start processing the wafers in the wafer group to be processed so as to stagger the time for each target processing module to enter the cleaning step, wherein the processing parameters of each wafer in the wafer group to be processed are the same.

[0064] It should be noted that the above-mentioned wafer group to be processed refers to the same batch of wafers that need to be processed, and in the wafer group to be processed, the processing parameters of each wafer are the same, wherein the same processing parameters of the wafers mean that the processing time required for the wafers in the wafer group to be processed by each target processing module is the same, and the cleaning time after processing the wafers in the wafer group to be processed is also the same. This ensures that when each target processing module cyclically processes each wafer in the wafer group to be processed, the effect of staggered cleaning will not be affected by different wafer processing time or cleaning time.

[0065] Exemplarily, when there is a wafer group to be processed that is processed by each target processing module for the first time, that is, when each target processing module starts to process the batch of wafer groups to be processed. If the combined equipment is started, it is necessary to process the wafers in the wafer group to be processed, and the theoretical delayed start time of each target processing module has been determined. For any target processing module, after waiting for the theoretical delayed start time of the target processing module, the target processing module is started to process the wafers in the wafer group to be processed. It is worth noting that the theoretical delayed start time can be 0. Similarly, each target processing module can use the above method to determine the start time (that is, when to start processing the wafer). Since the processing parameters of each wafer in the wafer group to be processed are the same, it can be ensured that the above-mentioned delayed start processing module method can accurately stagger the time for each target processing module to enter the cleaning step, thereby avoiding the occurrence of centralized cleaning.

[0066] In this embodiment, for any group of parallel target processing modules among the multiple processing modules, the combination device will construct the initial cumulative process times of each target processing module to obtain each candidate initial cumulative process number set, wherein the candidate initial cumulative process number set includes the initial cumulative process times of each target processing module, and the initial cumulative process times of each target processing module in a candidate initial cumulative process number set are different; from the candidate initial cumulative process number sets, the candidate initial cumulative process number set with the shortest average wafer processing cycle is selected as the target initial cumulative process number set; the initial cumulative process times of each target processing module in the target initial cumulative process number set is converted into a theoretical delayed start time of each target processing module; in the case that there is a wafer group to be processed being processed by each target processing module for the first time, based on the theoretical delayed start time of each target processing module, each target processing module is started to start processing the wafers in the wafer group to be processed, so as to stagger the time when each target processing module enters the cleaning step, wherein the processing parameters of each wafer in the wafer group to be processed are the same. It is understandable that, since the initial cumulative process times of each target processing module in the constructed candidate initial cumulative process times set are different, for any candidate initial cumulative process times set, the selected initial cumulative process times set can ensure that any two target processing modules will not enter the cleaning step at the same time, thereby minimizing the possibility of robot idleness. Further, after obtaining each candidate initial cumulative process times set, the candidate initial cumulative process times set with the shortest average wafer processing cycle is selected as the target initial cumulative process times set, so as to ensure the fastest processing efficiency of the wafer as much as possible under the condition of staggered cleaning. In addition, in order to facilitate actual operation control, the initial cumulative process times in the target initial cumulative process times set are converted into the theoretical delayed start time of each target processing module, and when starting to process the wafer group to be processed, according to the theoretical delayed start time of each target processing module, control the start of each target processing module to process the wafers in the wafer group to be processed. Since the processing parameters of each wafer in the wafer group to be processed are the same, it can be ensured that the above-mentioned delayed start-up processing module method can accurately stagger the cleaning steps of each target processing module, avoid centralized cleaning, and cause the robot to be idle, thereby ensuring that the overall production efficiency will not be affected by centralized cleaning.

[0067] In a feasible implementation manner, before the step of selecting, from the candidate initial cumulative process number sets, a candidate initial cumulative process number set with the shortest average wafer processing cycle as a target initial cumulative process number set, the method includes steps S21 to S23:

[0068] Step S21, for any one of the candidate initial cumulative process number sets in the candidate initial cumulative process number sets, configuring the initial cumulative process number in the candidate initial cumulative process number set for each target processing module to obtain an initialized processing module group;

[0069] Step S22, simulating the processing steps of the initialization processing module group to process the wafer within a preset period, and obtaining the number of wafers processed in the preset period, wherein the processing steps include wafer process steps and processing module cleaning steps;

[0070] Step S23, based on the preset cycle and the number of wafer processes, calculate the average wafer processing cycle of the candidate initial cumulative process number set.

[0071] It should be noted that in this embodiment, the average wafer processing cycle corresponding to the peak staggering scheme (i.e., the cleaning steps of each target processing module are staggered) of each candidate initial cumulative process data set will be determined. The determination process of the average wafer processing cycle of each candidate initial cumulative process number set is basically the same, so in this embodiment, one of the candidate initial cumulative process number sets will be used as an example for description.

[0072] Exemplarily, for any candidate initial cumulative process number set in the candidate initial cumulative process number set, the initial cumulative process number in the candidate initial cumulative process number set is configured for each target processing module to obtain an initialization processing module module. In actual application, each time the processing module performs a process processing step of the wafer, the process number will be accumulated once. When the process number accumulates to a preset number of times, the processing module will enter the cleaning step, and after completing the processing module cleaning step, the cumulative process number will be reset to 0. In this embodiment, the initialization processing module group is to set each initial cumulative process number in the above-mentioned candidate initial cumulative process number set for each target processing module. Then simulate the processing steps of the initialization processing module group to process the wafer within a preset period (such as one hour), and record the number of wafers processed by the initialization processing module group within the preset period, that is, the number of wafers processed. It is worth noting that in actual applications, since the combination equipment and the robot are usually fixed, the wafer processing time and the execution time required for the robot to complete the wafer transfer are known. Therefore, the processing steps of the initialization processing module group to process the wafer within a preset cycle can be presented through simulation.

[0073] After obtaining the number of wafers processed by the initialization processing module group within the preset period, the preset period is divided by the number of wafers processed to obtain the average wafer processing period of the initial processing module group, that is, the average wafer processing period of the candidate initial cumulative process number set. The average wafer processing period of each candidate initial cumulative process number set can be obtained in the above manner. Then, the candidate initial cumulative process number set with the smallest average wafer processing period is selected as the target initial cumulative process number set.

[0074] In a feasible implementation manner, the step of converting the initial cumulative process times of each target processing module in the target initial cumulative process times into the theoretical delayed start time of each target processing module includes steps S31 and S32:

[0075] Step S31, simulating and obtaining the execution time required for each target processing module to complete each initial cumulative number of processes;

[0076] In step S32, the execution time required to complete each initial accumulated process number is used as the theoretical delayed start time length of each target processing module.

[0077] It should be noted that, since the process of converting the initial accumulated process times of each target processing module is substantially the same, in this embodiment, one of the target processing modules will be taken as an example for description.

[0078] For example, for any one of the target processing modules, the working process of the target processing module to complete the corresponding initial cumulative number of processes can also be simulated, so as to obtain the execution time required to complete the initial cumulative number of processes, and the execution time can be used as the theoretical delayed start duration. Similarly, the theoretical delayed start duration of each target processing module can be obtained by simulation.

[0079] Reference Figure 2 , is a flow chart of the second embodiment of the present application proposed based on the first embodiment of the present application. In this embodiment, the same or similar contents as the above embodiment can refer to the above contents, so they are not repeated here. The step of starting each target processing module to start processing the wafers in the wafer group to be processed based on the theoretical delayed start time of each target processing module includes step S41:

[0080] Step S41, for any one of the target processing modules, if the actual accumulated process times of the target processing modules are reset before the wafer group to be processed is processed, then after waiting for the theoretical delayed start time of the target processing module, the target processing module is started to start processing the wafers in the wafer group to be processed.

[0081] It should be noted that, in practical applications, after determining the theoretical delayed start time of each target processing module, the process of controlling the target processing module is basically the same, so in this embodiment, one of the target processing modules will be used as an example for explanation. It is worth noting that, in practical applications, since the embodiment of the present application is to stagger the cleaning steps of the target processing module, the timing of starting the processing of each target processing module is not the same, and accordingly, this will also cause the end time of each target processing module to be different, which is equivalent to the start of some target processing modules. The delay has been carried out, therefore, when processing two consecutive wafer groups to be processed with different processing parameters, if the theoretical delayed start time is directly used to control the start of the target processing module, the delay that has been made by the above-mentioned part of the target processing module may be wasted, so in this embodiment, under certain circumstances, the delay that has been made by some target processing modules will be considered and controlled.

[0082] Exemplarily, for any one of the target processing modules, if the actual cumulative number of processes of each target processing module is reset before the wafer group to be processed is processed, there is no need to consider the different end times of each target processing module caused by the processing of the previous batch of wafers. If no wafer processing task is received after a preset period of time, each target processing module can be cleaned to reset the actual cumulative number of processes, even if the set number of processes is not reached. Accordingly, in this case, for the above-mentioned target processing module, after waiting for the theoretical delayed start time of the target processing module, the target processing module can be started to start processing the wafers in the wafer group to be processed. Accordingly, other target processing modules can also be started according to the above method.

[0083] In a feasible implementation manner, the step of delaying starting each target processing module to process the wafer based on the theoretical delayed start time of each target processing module further includes steps S42 to S45:

[0084] Step S42, if the actual accumulated number of processes of each target processing module has not been reset before processing the wafer group to be processed, then determining the idle time of each target processing module when each target processing module enters an idle state;

[0085] Step S43, obtaining the intermediate duration of the target processing module based on the sum of the idle duration of the target processing module and the theoretical delayed start duration of the target processing module;

[0086] Step S44, after subtracting the common delay time from the intermediate time of the target processing module, the actual delayed start time of the target processing module is obtained, wherein the common delay time is the minimum intermediate time among the intermediate time of each target processing module;

[0087] Step S45, after waiting for the actual delayed start time of the target processing module, start the target processing module to start processing the wafers in the wafer group to be processed.

[0088] Exemplarily, if the actual cumulative number of processes of each target processing module is not reset, it indicates that the processing of the previous batch of wafer groups will affect the cleaning step of the wafer group to be processed. In this case, the idle time of each target processing module can be considered as the delayed time to control the startup of each target processing module. Similarly, for any target processing module in each target processing module, the idle time of the target processing module is determined when each target processing module enters the idle state, and the sum of the idle time of the target processing module and the theoretical delayed startup time is added as the intermediate time of the target processing module. After subtracting the common delay time from the intermediate time of the target processing module, the actual delayed startup time of the target processing module is obtained. Among them, the common delay time traverses each target processing module, and the minimum intermediate time among the intermediate times of each target processing module is obtained. It can be understood that the common delay time is equivalent to the calculated time that each target processing module needs to be delayed. If all need to be delayed, it is equal to no delay. Therefore, after subtracting the common delay time from the intermediate time, the actual delayed startup time can be obtained. Correspondingly, after waiting for the actual delayed start time of the target processing module, the target processing module can be started to start processing the wafers in the processing wafer group.

[0089] It can be understood that, in this embodiment, the delay caused by processing the target processing module after processing the wafer group to be processed with different processing parameters is taken into consideration. Therefore, when processing the wafer group to be processed with different processing parameters, the delay caused by the target processing module is avoided from being wasted, thereby ensuring the processing efficiency.

[0090] Reference Figure 3 , is a flow chart of the third embodiment of the present application proposed based on the first embodiment and the second embodiment of the present application. In this embodiment, the same or similar contents as the above embodiments can refer to the above contents, so they are not repeated here. The step of constructing the initial cumulative process times of each target processing module and obtaining each candidate initial cumulative process times set includes step S11:

[0091] Step S11, constructing the initial cumulative process times of each target processing module based on a preset arithmetic difference rule to obtain each candidate initial cumulative process time set, wherein each candidate initial cumulative process time in the candidate initial cumulative process time set constitutes an arithmetic difference array, and the maximum tolerance of the constituted arithmetic difference array is determined based on the number of each target processing module.

[0092] It should be noted that in practical applications, the delay effects actually produced by some candidate initial cumulative process times sets are the same or similar. Therefore, in this implementation, the initial cumulative process times of each target processing module will be constructed according to the preset arithmetic difference rule to form each candidate initial cumulative process times set, so as to avoid the excessive number of candidate initial cumulative process times sets with repeated effects, resulting in a waste of computing resources. Among them, the preset arithmetic difference rule is used to calculate the initial cumulative process times of each target processing module, which can be set by technology. For example, the initial cumulative process times of a target processing module are first set to 0, and the tolerance is set to 1, and then 1 is accumulated to form a candidate initial cumulative process times set in which the candidate initial cumulative process times constitute an arithmetic difference array. Among them, the maximum tolerance of the arithmetic difference array composed of the candidate initial cumulative process times can be determined based on the number of each target processing module. For example, the maximum tolerance is S / 2, where S is the number of each target processing module. It can be understood that a representative candidate initial cumulative process times set can be constructed in the above manner, thereby reducing the number of candidate initial cumulative process times sets, thereby reducing the computing resources required to consume the simulation process.

[0093] In addition, in order to clearly explain this solution, the following example will be used for illustration.

[0094] Step 1: Given the initial sequence path information (i.e., the process steps required for processing the wafers in the wafer group to be processed), the robot action time, the PM process time P={pi}, i∈n, the cleaning time C={ci}, i∈n, the cleaning process threshold m, and the initial PM process times Q={qi}, i∈n. Usually, the initial state qi is always 0. The simulator simulates the steady-state processing of the sequence, ignoring the subtle actions of each processing module, such as door opening and closing, and pressure control. According to the step size S (i.e., the tolerance of the candidate initial cumulative process times set), S<=m / 2, by adjusting the possible initial process times Q1 of each PM, the operation sequence of the interaction between the robot and the processing module is deduced, and then the average cycle time of the processed wafers in various typical scenarios is obtained, and the Q1 corresponding to the minimum wafer processing cycle is taken as the initial process times of the PM.

[0095] In the second step, according to the difference between Q1 and Q (when the combined equipment is first started, Q is a set of 0, and when the sequence is switched, that is, when two batches of wafer groups are processed continuously, Q is the idle time of each PM), the sequence enters the initial state of each PM idle time Gap = Px (Q1-Q), and introduces a virtual process Delay to represent the idle state (that is, the time required to reach the initial number of processes is determined by simulation). If the PM needs to switch to a new sequence process (that is, switch to start processing a new wafer group), then extract the release time of each PM in the previous sequence R = {ri} (that is, the idle time of the PM after processing the previous batch of wafer groups), i∈n, transition Gap2 = max(R) - R + Gap, then the new Gap = Gap2 - min(Gap2), where min(Gap2) is the common delay time, that is, the smallest intermediate time in the intermediate time of the target processing module, and the new Gap is the actual delayed startup time.

[0096] In the third step, after the virtual process Delay is completed and the number of PM processing times meets the internal difference condition of Q1, the PM enters the wafer process and binds the pre- and post-action logic between the robot and the PM to solve the specific peak-shifting cleaning cycle scheduling plan;

[0097] The fourth step is to abandon the virtual process and realize the periodic scheduling of the peak-shifting cleaning plan from the system initial state to the steady state through the system's actual operation sequence and the logical relationship between them before and after execution.

[0098] The following examples are given to illustrate the key steps of the algorithm and compare it with the traditional method.

[0099] Assume that Sequence 1 has parallel paths PM1 / PM2 / PM3, P={100,100,100}, C={90, 90,90}, m=6, Q={0,0,0}. Then the maximum value of S=3. In this regard, the simulator deduces the wafer processing cycle time for each Q scenario, where Q={0,0,0} is the centralized cleaning scenario, and the shortest average wafer processing cycle is obtained, Q1={0,2,4}.

[0100] Calculate Gap={0,200,400}. It should be noted that Gap={0,200,400} can be temporarily regarded as the theoretical delayed start time of each target processing module, because Gap={0,200,400} only calculates the process time. In actual applications, it also takes time for the robot to transfer the wafer.

[0101] Each PM performs Delay 200 and 400 respectively according to Gap, PM2 / PM3, and meets the Q1 condition, that is, PM1 is performing the secondary process PM2 feeding the film, and PM2 is performing the fourth process PM3 feeding the film. Therefore, the pre- and post-action logic between the robot and PM can be bound to obtain the system operation sequence.

[0102] Abandon the virtual process, output the system's actual operation sequence and the relationship between them, complete the system's staggered cleaning cycle scheduling, that is, convert the simulated time required for the virtual process execution to reach the initial cumulative number of processes into a theoretical delayed start time.

[0103] If Sequence 1 is about to be completed, the system imports the parallel path PM1 / PM2 / PM3 of Sequence 2 again, P={80,80,80}, C={50, 50,50}, m=6. Then the maximum value of S=3.

[0104] Go back to the first step and find Q1={0,1,2};

[0105] In the second step, Gap = {0,80,160} (theoretical delayed start time). If it is assumed that the time for Sequence1 to release each PM is R = {5000,5200,5300}, which is equivalent to the idle time of each target processing module when each target processing module enters the idle state, R = {300,100,0}, which is added to the above theoretical delayed start time {0,80,160} in sequence, then Gap2 = {300,180,160}, and then the common delay time 160 is subtracted to obtain the new Gap = {140,20,0}, and the third and fourth steps are repeated to complete the scheduling.

[0106] The present application provides a processing control device for a combined device, wherein a plurality of processing modules are arranged in the combined device, wherein the processing module will enter a cleaning step after the cumulative number of wafer processing times exceeds a preset number, referring to Figure 4 , the processing control device of the combined equipment includes:

[0107] A construction unit 10 is used to construct the initial cumulative process times of each target processing module for any group of parallel target processing modules among the plurality of considered cleaning processing modules, and obtain each candidate initial cumulative process time set, wherein the candidate initial cumulative process time set includes the initial cumulative process times of each target processing module, and the initial cumulative process times of each target processing module in one candidate initial cumulative process time set are different;

[0108] A selection unit 20 is used to select, from the candidate initial cumulative process number sets, a candidate initial cumulative process number set with the shortest average wafer processing cycle as a target initial cumulative process number set;

[0109] A conversion unit 30, configured to convert the initial cumulative process times of each target processing module in the target initial cumulative process times set into a theoretical delayed start time length of each target processing module;

[0110] The control unit 40 is used to start each target processing module to start processing the wafers in the wafer group to be processed based on the theoretical delayed start time of each target processing module when the wafer group to be processed is processed for the first time by each target processing module, so as to stagger the time for each target processing module to enter the cleaning step, wherein the processing parameters of each wafer in the wafer group to be processed are the same.

[0111] Optionally, the processing control device of the combined equipment further includes a simulation unit 50, and the simulation unit 50 is further used for:

[0112] For any one of the candidate initial cumulative process number sets in the candidate initial cumulative process number sets, configure the initial cumulative process number in the candidate initial cumulative process number set for each target processing module to obtain an initialized processing module group;

[0113] Simulating the processing steps of the initialization processing module group to process the wafer within a preset period to obtain the number of wafers processed in the preset period, wherein the processing steps include wafer process steps and processing module cleaning steps;

[0114] Based on the preset cycle and the wafer processing quantity, the average wafer processing cycle of the candidate initial cumulative process number set is calculated.

[0115] Optionally, the conversion unit 30 is further configured to:

[0116] The simulation obtains the execution time required for each target processing module to complete each initial cumulative number of processes;

[0117] The execution time required to complete each initial cumulative number of processes is used as the theoretical delayed start time of each corresponding target processing module.

[0118] Optionally, the control unit 40 is further configured to:

[0119] For any one of the target processing modules, if the actual accumulated process times of the target processing modules are reset before the wafer group to be processed is processed, then after waiting for the theoretical delayed start time of the target processing module, the target processing module is started to start processing the wafers in the wafer group to be processed.

[0120] Optionally, the control unit 40 is further configured to:

[0121] If the actual accumulated number of processes of each target processing module is not reset before processing the wafer group to be processed, then determining the idle time of each target processing module when each target processing module enters an idle state;

[0122] Obtaining the intermediate duration of the target processing module based on the sum of the idle duration of the target processing module and the theoretical delayed start duration of the target processing module;

[0123] After subtracting the common delay time from the intermediate time of the target processing module, the actual delayed start time of the target processing module is obtained, wherein the common delay time is the smallest intermediate time among the intermediate times of the target processing modules;

[0124] After waiting for the actual delayed start time of the target processing module, the target processing module is started to start processing the wafers in the wafer group to be processed.

[0125] Optionally, the construction unit 10 is further used for:

[0126] Based on a preset arithmetic difference rule, the initial cumulative process times of each target processing module are constructed to obtain each candidate initial cumulative process time set, wherein each candidate initial cumulative process time in the candidate initial cumulative process time set constitutes an arithmetic difference array, and the maximum tolerance of the constituted arithmetic difference array is determined based on the number of each target processing module.

[0127] The processing control device of the combined equipment provided in the present application adopts the processing control method of the combined equipment in the above embodiment, aiming to solve the technical problem that the PM centralized cleaning of the parallel process affects the overall production efficiency. Compared with the prior art, the beneficial effects of the processing control device of the combined equipment provided in the embodiment of the present application are the same as the beneficial effects of the processing control method of the combined equipment provided in the above embodiment 1, and the other technical features in the processing control device of the combined equipment are the same as the features disclosed in the above embodiment method, which will not be repeated here.

[0128] The present application provides an electronic device, which includes: at least one processor; and a memory that is communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the processing control method of the combined device in the above-mentioned embodiment one.

[0129] Reference below Figure 5, which shows a schematic diagram of the structure of an electronic device suitable for implementing an embodiment of the present application. The electronic device in the embodiment of the present application may include but is not limited to mobile terminals such as laptop computers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions: tablet computers), etc., and fixed terminals such as desktop computers, etc. Figure 5 The electronic device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0130] like Figure 5 As shown, the electronic device may include a processing device 1001 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the electronic device are also stored. The processing device 1001, ROM1002, and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows an electronic device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have alternatively.

[0131] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0132] The electronic device provided by the present application adopts the processing control method of the combined device in the above embodiment, which can solve the technical problem that the longitudinal control algorithm cannot provide a good control effect while being easy to apply to the real-time control of the vehicle. Compared with the prior art, the beneficial effects of the electronic device provided by the present application are the same as the beneficial effects of the processing control method of the combined device provided by the above embodiment, and the other technical features in the electronic device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0133] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0134] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0135] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, wherein the computer-readable program instructions are used to execute the processing control method of the combined device in the above-mentioned embodiment.

[0136] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM: Random Access Memory), a read-only memory (ROM: Read Only Memory), an erasable programmable read-only memory (EPROM: Erasable Programmable Read Only Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM: CD-Read Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency: Radio Frequency), etc., or any suitable combination of the above.

[0137] The computer-readable storage medium may be included in the electronic device, or may exist independently without being installed in the electronic device.

[0138] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device: for any group of parallel target processing modules among the multiple processing modules, construct the initial cumulative process times of each target processing module to obtain each candidate initial cumulative process number set, wherein the candidate initial cumulative process number set includes the initial cumulative process times of each target processing module, and the initial cumulative process times of each target processing module in a candidate initial cumulative process number set are different; select from the candidate initial cumulative process number sets, the candidate initial cumulative process number set with the shortest average wafer processing cycle as the target initial cumulative process number set; convert the initial cumulative process times of each target processing module in the target initial cumulative process number set into the theoretical delayed start time of each target processing module; when there is a wafer group to be processed that is processed by each target processing module for the first time, based on the theoretical delayed start time of each target processing module, start each target processing module to start processing the wafers in the wafer group to be processed, so as to stagger the time when each target processing module enters the cleaning step, wherein the processing parameters of each wafer in the wafer group to be processed are the same.

[0139] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Python, Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0140] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0141] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0142] The readable storage medium provided in the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the processing control method of the above-mentioned combined device, and can solve the technical problem that the existing data display method is difficult to intuitively and clearly complete data visualization. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in the present application are the same as the beneficial effects of the processing control method of the combined device provided in the above-mentioned embodiment, and will not be repeated here.

[0143] The present application also provides a computer program product, including a computer program, which implements the steps of the processing control method of the combined device as described above when the computer program is executed by a processor.

[0144] The computer program product provided by this application can solve the technical problem of processing control of combined equipment. Compared with the prior art, the beneficial effects of the computer program product provided by this application are the same as the beneficial effects of the processing control method of the combined equipment provided by the above embodiment, which will not be repeated here.

[0145] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A processing control method for a combined device, characterized in that: The combined device is provided with a plurality of processing modules, wherein the processing module will enter a cleaning step after the cumulative number of wafer processing times exceeds a preset number, and the processing control method of the combined device includes: For any group of parallel target processing modules among the multiple processing modules, construct an initial cumulative process number of each target processing module to obtain each candidate initial cumulative process number set, wherein the candidate initial cumulative process number set includes the initial cumulative process number of each target processing module, and the initial cumulative process number of each target processing module in one candidate initial cumulative process number set is different; Selecting from the candidate initial cumulative process times sets, a candidate initial cumulative process times set with the shortest average wafer processing cycle as a target initial cumulative process times set; Converting the initial cumulative process times of each target processing module in the target initial cumulative process times set into the theoretical delayed start time of each target processing module; In the case where there is a wafer group to be processed that is processed by each target processing module for the first time, based on the theoretical delayed start time of each target processing module, each target processing module is started to start processing the wafers in the wafer group to be processed, so as to stagger the time when each target processing module enters the cleaning step, wherein the processing parameters of each wafer in the wafer group to be processed are the same; The step of converting the initial cumulative process times of each target processing module in the target initial cumulative process times set into the theoretical delayed start time of each target processing module comprises: The simulation obtains the execution time required for each target processing module to complete each initial cumulative number of processes; The execution time required to complete each initial cumulative number of processes is used as the theoretical delayed start time of each corresponding target processing module.

2. The processing control method of the combined equipment according to claim 1, characterized in that: Before the step of selecting, from among the candidate initial cumulative process number sets, a candidate initial cumulative process number set with the shortest average wafer processing cycle as a target initial cumulative process number set, the method includes: For any one of the candidate initial cumulative process number sets in the candidate initial cumulative process number sets, configure the initial cumulative process number in the candidate initial cumulative process number set for each target processing module to obtain an initialized processing module group; Simulating the processing steps of the initialization processing module group to process the wafer within a preset period to obtain the number of wafers processed in the preset period; Based on the preset cycle and the wafer processing quantity, the average wafer processing cycle of the candidate initial cumulative process number set is calculated.

3. The processing control method of the combined equipment as claimed in claim 1, characterized in that: The step of starting each target processing module to start processing the wafers in the wafer group to be processed based on the theoretical delayed start time of each target processing module includes: For any one of the target processing modules, if the actual accumulated process times of the target processing modules are reset before the wafer group to be processed is processed, then after waiting for the theoretical delayed start time of the target processing module, the target processing module is started to start processing the wafers in the wafer group to be processed.

4. The processing control method of the combined equipment according to claim 3, characterized in that: The step of starting each target processing module to start processing the wafers in the wafer group to be processed based on the theoretical delayed start time of each target processing module also includes: If the actual accumulated number of processes of each target processing module is not reset before processing the wafer group to be processed, then determining the idle time of each target processing module when each target processing module enters an idle state; Obtaining the intermediate duration of the target processing module based on the sum of the idle duration of the target processing module and the theoretical delayed start duration of the target processing module; After subtracting the common delay time from the intermediate time of the target processing module, the actual delayed start time of the target processing module is obtained, wherein the common delay time is the smallest intermediate time among the intermediate times of the target processing modules; After waiting for the actual delayed start time of the target processing module, the target processing module is started to start processing the wafers in the wafer group to be processed.

5. The processing control method of the combined equipment according to claim 1, characterized in that: The step of constructing the initial cumulative process times of each target processing module to obtain each candidate initial cumulative process times set comprises: Based on a preset arithmetic difference rule, the initial cumulative process times of each target processing module are constructed to obtain each candidate initial cumulative process time set, wherein each candidate initial cumulative process time in the candidate initial cumulative process time set constitutes an arithmetic difference array, and the maximum tolerance of the constituted arithmetic difference array is determined based on the number of each target processing module.

6. A processing control device for a combined device, characterized in that: The combined equipment is provided with a plurality of processing modules, wherein the processing module will enter a cleaning step after the cumulative number of wafer processing times exceeds a preset number, and the processing control device of the combined equipment includes: A construction unit is used to construct the initial cumulative process times of each target processing module for any group of parallel target processing modules among the multiple processing modules, and obtain each candidate initial cumulative process time set, wherein the candidate initial cumulative process time set includes the initial cumulative process times of each target processing module, and the initial cumulative process times of each target processing module in one candidate initial cumulative process time set are different; A selection unit, configured to select, from the candidate initial cumulative process number sets, a candidate initial cumulative process number set with the shortest average wafer processing cycle as a target initial cumulative process number set; A conversion unit, used for converting the initial cumulative process times of each target processing module in the target initial cumulative process times set into a theoretical delayed start time of each target processing module; A control unit, for starting each target processing module to start processing the wafers in the wafer group to be processed based on a theoretical delayed start time of each target processing module when there is a wafer group to be processed being processed by each target processing module for the first time, so as to stagger the time when each target processing module enters a cleaning step, wherein the processing parameters of each wafer in the wafer group to be processed are the same; The step of converting the initial cumulative process times of each target processing module in the target initial cumulative process times set into the theoretical delayed start time of each target processing module comprises: The simulation obtains the execution time required for each target processing module to complete each initial cumulative number of processes; The execution time required to complete each initial cumulative number of processes is used as the theoretical delayed start time of each corresponding target processing module.

7. An electronic device, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the processing control method of the combined device according to any one of claims 1 to 5.

8. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the processing control method of the combined device as described in any one of claims 1 to 5 are implemented.

9. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the processing control method of the combined device according to any one of claims 1 to 5 are implemented.

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