Current-sharing synchronization method, device, source-carrying system and equipment for series interleaved circuits

Abstract

The present application discloses a current sharing synchronization method, device, source-carrying system and equipment for a series interleaved circuit. The method includes comparing the magnitudes of the A-phase current and the B-phase current in each buck module, obtaining the max-phase buck circuit and the min-phase buck circuit corresponding to each buck module according to the comparison result; obtaining the average phase current; using the current of all max-phase buck circuits as the feedback value of the first feedback control loop, and using the current of all min-phase buck circuits as the feedback value of the second feedback control loop; controlling the current of all max-phase buck circuits by the first PWM signal output by the first feedback control loop, and controlling the current of all min-phase buck circuits by the second PWM signal output by the second feedback control loop. The method can simultaneously meet the current sharing and synchronization of the series interleaved buck circuit.

Description

Technical Field

[0001] The present application relates to the field of source-carrying systems, and in particular to a current-sharing synchronization method, device, source-carrying system and equipment for a series interleaved circuit. Background Art

[0002] A source-load system is a device that can work as both a source-load system and a load at the same time. It can provide power to external circuits and absorb power from external circuits. It has high flexibility and can adapt to different application scenarios.

[0003] In the source-load system, a multi-phase interleaved buck circuit can be used to increase the output current and reduce the output ripple. A series boost buck circuit can also be used to increase the output voltage level. The multi-phase interleaved buck circuit needs to consider the current sharing between the phases, while the series boost buck circuit needs to consider the switch tube synchronization. If multi-phase interleaving and series boost are used at the same time, current sharing and synchronization cannot be met at the same time. Summary of the invention

[0004] The present application proposes a current sharing and synchronization method, device, source-carrying system and equipment for a series interleaved circuit, which can simultaneously meet the current sharing and synchronization requirements of the series interleaved buck circuit.

[0005] According to the first aspect of the present application, the current sharing synchronization method of the series interleaved circuit is used for the series interleaved buck circuit, the series interleaved buck circuit includes a plurality of buck modules connected in series, each buck module includes an A-phase buck circuit and a B-phase buck circuit arranged in an interleaved manner, and includes the following steps:

[0006] Get the A-phase current and B-phase current of each buck module;

[0007] Compare the magnitudes of the A-phase current and the B-phase current in each buck module, and obtain the max-phase buck circuit and the min-phase buck circuit corresponding to each buck module according to the comparison results, wherein the max-phase buck circuit is a buck circuit with a larger current, and the min-phase buck circuit is a buck circuit with a smaller current;

[0008] Obtaining an average phase current, wherein the average phase current is the sum of all A-phase currents and all B-phase currents divided by two;

[0009] The current of all max-phase buck circuits is used as the feedback value of the first feedback control loop, the current of all min-phase buck circuits is used as the feedback value of the second feedback control loop, and the average phase current is used as the given value of the first feedback control loop and the second feedback control loop; the current of all max-phase buck circuits is controlled by the first PWM signal output by the first feedback control loop, and the current of all min-phase buck circuits is controlled by the second PWM signal output by the second feedback control loop.

[0010] According to some embodiments of the present application, after the first PWM signal outputted by the first feedback control loop controls the current of all max-phase buck circuits, and the second PWM signal outputted by the second feedback control loop controls the current of all min-phase buck circuits, the method further includes:

[0011] The A-phase current and the B-phase current of each buck module are monitored in real time. When the relative magnitudes of the A-phase current and the B-phase current change, the max-phase buck circuit and the min-phase buck circuit corresponding to each buck module are updated, and the buck circuit corresponding to the first feedback control loop and the buck circuit corresponding to the second feedback control loop are switched through switches to keep the first feedback control loop controlling all max-phase buck circuits and the second feedback control loop controlling all min-phase buck circuits.

[0012] According to the second aspect of the present application, a current sharing synchronization device for a series interleaved circuit includes:

[0013] A series interleaved buck circuit includes a plurality of buck modules connected in series, each buck module includes an A-phase buck circuit and a B-phase buck circuit arranged in an interleaved manner;

[0014] A control unit, the control unit comprising a current sampling module, a current selection module, a given value input module, a first feedback control loop and a second feedback control loop;

[0015] The current sampling module is used to obtain the A-phase current and the B-phase current of each buck module, and the output end of the current sampling module is connected to the input end of the current selection module;

[0016] The current selection module is used to compare the magnitudes of the A-phase current and the B-phase current in each buck module, and obtain the max-phase buck circuit and the min-phase buck circuit corresponding to each buck module according to the comparison result, wherein the max-phase buck circuit is a buck circuit with a larger current, and the min-phase buck circuit is a buck circuit with a smaller current;

[0017] The given value input module is used to obtain an average phase current, where the average phase current is the sum of all A-phase currents and all B-phase currents divided by two;

[0018] The output end of the current selection module is connected to the feedback end of the first feedback control loop so as to use the current of all max-phase buck circuits as the feedback value of the first feedback control loop; the output end of the current selection module is connected to the feedback end of the second feedback control loop so as to use the current of all min-phase buck circuits as the feedback value of the second feedback control loop; the given value input module is respectively connected to the given value input ends of the first feedback control loop and the second feedback control loop so as to use the average phase current as the given value of the first feedback control loop and the second feedback control loop; the first feedback control loop is used to output a first PWM signal to control the current of all max-phase buck circuits according to the feedback value and the given value; the second feedback control loop is used to output a second PWM signal to control the current of all min-phase buck circuits according to the feedback value and the given value.

[0019] According to some embodiments of the present application, the control unit also includes a switch switching module, the PWM signal output end of the first feedback control loop and the PWM signal output end of the second feedback control loop are both connected to the input end of the switch switching module, and the multiple output ends of the switch switching module are respectively connected to the control end of each A-phase buck circuit and the B-phase buck circuit for switching the buck circuit corresponding to the first feedback control loop and the buck circuit corresponding to the second feedback control loop.

[0020] According to some embodiments of the present application, the control unit also includes a voltage control loop, the first feedback control loop includes a first current sharing control loop and a first PWM modulation module, the second feedback control loop includes a second current sharing control loop and a second PWM modulation module, the output end of the voltage control loop is respectively connected to the first input end of the first PWM modulation module and the second PWM modulation module, the output end of the first current sharing control loop is connected to the second input end of the first PWM modulation module, the output end of the second current sharing control loop is connected to the second input end of the second PWM modulation module, the first PWM modulation module is used to output a first PWM signal to control the current of all max phase buck circuits; the second PWM modulation module is used to output a second PWM signal to control the current of all min phase buck circuits.

[0021] According to the third aspect of the present application, the source-load system includes the above-mentioned current-sharing synchronization device for the series interleaved circuit.

[0022] An electronic device according to an embodiment of the fourth aspect of the present application includes the above-mentioned current sharing synchronization device for the series interleaved circuit.

[0023] The current sharing synchronization method, device, source-carrying system and equipment of the series interleaved circuit according to the embodiments of the present application have at least the following beneficial effects:

[0024] In the embodiment of the present application, by obtaining the A-phase current and the B-phase current of each buck module; comparing the magnitudes of the A-phase current and the B-phase current in each buck module, the max-phase current and the min-phase current corresponding to each buck module are obtained; the average phase current is obtained, and the average phase current is the sum of all the A-phase currents and all the B-phase currents divided by two; all the max-phase currents are used as the feedback values ​​of the first feedback control loop, all the min-phase currents are used as the feedback values ​​of the second feedback control loop, and the average phase current is used as the given value of the first feedback control loop and the second feedback control loop; the current of the buck circuit corresponding to all the max-phase currents is controlled by the first PWM signal output by the first feedback control loop, and the current of the buck circuit corresponding to all the min-phase currents is controlled by the second PWM signal output by the second feedback control loop. The current sharing and synchronization of the series interleaved buck circuit can be satisfied at the same time.

[0025] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present application is further described below with reference to the accompanying drawings and embodiments, wherein:

[0027] Figure 1 A circuit diagram of a series interleaved buck circuit in an embodiment of the present application;

[0028] Figure 2 This is a flow chart of a current sharing synchronization method for a series interleaved circuit in an embodiment of the present application;

[0029] Figure 3 A circuit schematic diagram of a control unit of a current sharing synchronization device of a series interleaved circuit in an embodiment of the present application;

[0030] Figure 4 1 is a circuit schematic diagram of a switch switching module of a current sharing synchronization device of a series interleaved circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0032] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0034] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0035] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0036] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0037] First, some nouns involved in this application are analyzed:

[0038] Buck module / circuit: Also known as a step-down converter, it is a DC-DC converter used to convert a higher DC input voltage into a lower DC output voltage. It is one of the most common types of switching source load systems and is widely used in various electronic devices. It includes a main MOS tube Q1, which is used to control the switch of the main source load system path. A synchronous rectifier MOS tube Q2 is used to replace the traditional diode to reduce conduction losses. An inductor L is used to store energy and smooth the current during the switching cycle. And an output capacitor C is used to filter the output voltage and provide a stable DC output.

[0039] The series boost circuit in the related art connects two buck modules in series to achieve boost. In the series boost circuit of the buck modules, it is necessary to synchronize the MOS tube Q1A with the MOS tube Q2A, and synchronize the MOS tube Q1B with the MOS tube Q2B.

[0040] A source-load system is a device that can work as both a source-load system and a load at the same time. It can provide power to external circuits and absorb power from external circuits. It has high flexibility and can adapt to different application scenarios.

[0041] In the source-load system, a multi-phase interleaved buck circuit can be used to increase the output current and reduce the output ripple. A series boost buck circuit can also be used to increase the output voltage level. The multi-phase interleaved buck circuit needs to consider the current sharing between the phases, while the series boost buck circuit needs to consider the switch tube synchronization. If multi-phase interleaving and series boost are used at the same time, current sharing and synchronization cannot be met at the same time.

[0042] Based on this, the embodiments of the present application provide a current sharing and synchronization method, device, source-load system and equipment for a series interleaved circuit, aiming to simultaneously meet the current sharing and synchronization requirements of a series interleaved buck circuit.

[0043] The current balancing synchronization method, device, source-carrying system and equipment for the series interleaved circuit provided in the embodiments of the present application are specifically illustrated through the following embodiments. First, the current balancing synchronization method for the series interleaved circuit in the embodiments of the present application is described.

[0044] Reference Figure 1 As shown, a current sharing synchronization method for a series interleaved circuit is used for a series interleaved buck circuit. The series interleaved buck circuit includes a plurality of buck modules connected in series, and each buck module includes an A-phase buck circuit and a B-phase buck circuit that are interleaved.

[0045] First, the specific structure of the series interleaved buck circuit in the embodiment of the present application is introduced. The series interleaved buck circuit in the present application uses three buck modules connected in series, namely buck module 1, buck module 2 and buck module 3. Buck module 1 includes an A1 phase buck circuit and a B1 phase buck circuit, and the A1 phase buck circuit and the B1 phase buck circuit are arranged alternately. Buck module 2 includes an A2 phase buck circuit and a B2 phase buck circuit, and the A2 phase buck circuit and the B2 phase buck circuit are arranged alternately. Buck module 3 includes an A3 phase buck circuit and a B3 phase buck circuit, and the A3 phase buck circuit and the B3 phase buck circuit are arranged alternately. Buck module 1, buck module 2 and buck module 3 are connected in series to achieve boosting.

[0046] Specifically, the A1 phase buck circuit is composed of MOS transistor Q1A_P, MOS transistor Q1A_N and inductor LA1, the B1 phase buck circuit is composed of MOS transistor Q1B_P, MOS transistor Q1B_N and inductor LB1, similarly, the A2 phase buck circuit is composed of MOS transistor Q2A_P, MOS transistor Q2A_N and inductor LA2, the B2 phase buck circuit is composed of MOS transistor Q2B_P, MOS transistor Q2B_N and inductor LB2, the A3 phase buck circuit is composed of MOS transistor Q3A_P, MOS transistor Q3A_N and inductor LA3, and the B3 phase buck circuit is composed of MOS transistor Q3B_P, MOS transistor Q3B_N and inductor LB3. U1 is the source-load system input of buck module 1, U2 is the source-load system input of buck module 2, U3 is the source-load system input of buck module 3, and U0 is the source-load system output of the series interleaved buck circuit.

[0047] It should be noted that in the related art, if the synchronization of the MOS tubes of the three buck modules is given priority, the A1~A3 phase buck circuits can share a set of PWM signals, and the B1~B3 phase buck circuits can share a set of PWM signals. Only two sets of PWM signals are needed to achieve synchronization. However, since the on-resistance of each MOS tube cannot be exactly the same, the difference in the on-resistance of the MOS tubes in each buck circuit will lead to uneven current flow in the inductor, thus causing the current LA1 of the A1 phase buck circuit ≠ the B1 phase buck circuit LB1. Similarly, the current LA2 of the A2 phase buck circuit ≠ the current LB2 of the B2 phase buck circuit, and the current LA3 of the A3 phase buck circuit ≠ the B3 phase buck circuit LB3.

[0048] If current sharing is given priority, the A1 phase buck circuit and the B1 phase buck circuit need to adopt average current control, the A2 phase buck circuit and the B2 phase buck circuit need to adopt average current control, and the A3 phase buck circuit and the B3 phase buck circuit need to sample average current control. Since each buck module is controlled by its own average current control loop, there will be 6 sets of PWM waves, making the drive waveforms of the A1 phase, A2 phase, and A3 phase different, making it difficult to achieve synchronous conduction of the MOS tubes of the A1 phase, A2 phase, and A3 phase.

[0049] In order to solve the above problems, the present application proposes a current sharing synchronization method for a series interleaved circuit, referring to Figure 2 As shown, the specific steps include:

[0050] S101, obtaining the A-phase current and the B-phase current of each buck module;

[0051] S102, comparing the magnitudes of the A-phase current and the B-phase current in each buck module, and obtaining the max-phase buck circuit and the min-phase buck circuit corresponding to each buck module according to the comparison result, wherein the max-phase buck circuit is a buck circuit with a larger current, and the min-phase buck circuit is a buck circuit with a smaller current;

[0052] S103, obtaining an average phase current, where the average phase current is the sum of all A-phase currents and all B-phase currents divided by two;

[0053] S104, using the current of all max-phase buck circuits as the feedback value of the first feedback control loop, using the current of all min-phase buck circuits as the feedback value of the second feedback control loop, and using the average phase current as the given value of the first feedback control loop and the second feedback control loop; controlling the current of all max-phase buck circuits by the first PWM signal output by the first feedback control loop, and controlling the current of all min-phase buck circuits by the second PWM signal output by the second feedback control loop.

[0054] In the embodiment of the present application, by obtaining the A-phase current and the B-phase current of each buck module; comparing the magnitudes of the A-phase current and the B-phase current in each buck module, and obtaining the max-phase buck circuit and the min-phase buck circuit corresponding to each buck module according to the comparison result; obtaining the average phase current; using the current of all the max-phase buck circuits as the feedback value of the first feedback control loop, using the current of all the min-phase buck circuits as the feedback value of the second feedback control loop, and using the average phase current as the given value of the first feedback control loop and the second feedback control loop; controlling the current of all the max-phase buck circuits through the first PWM signal output by the first feedback control loop, and controlling the current of all the min-phase buck circuits through the second PWM signal output by the second feedback control loop. The current sharing and synchronization of the series interleaved buck circuit can be satisfied at the same time.

[0055] Before obtaining the A-phase current and the B-phase current of each buck module in the above step S101, it is necessary to first start the series interleaved buck circuit through the debugging stage. During the debugging stage, the A1-phase buck circuit, the A2-phase buck circuit, and the A3-phase buck circuit can share a set of PWM signals, and the B1-phase buck circuit, the B2-phase buck circuit, and the B3-phase buck circuit can share a set of PWM signals. The PWM signal wave of the B phase lags the PWM signal of the A phase by 180°.

[0056] Acquiring the A-phase current and the B-phase current of each buck module in step S101 refers to sampling the currents of all buck circuits through the current sampling module, that is, sampling the inductor currents ILA1, ILA2, ILA3, ILB1, ILB2, and ILB3, wherein ILA1 is the A-phase current of buck module 1, that is, the inductor current of the A1-phase buck circuit, and ILB1 is the B-phase current of buck module 1, that is, the inductor current of the B1-phase buck circuit; ILA2 is the A-phase current of buck module 2, that is, the inductor current of the A2-phase buck circuit, and ILB2 is the B-phase current of buck module 2, that is, the inductor current of the B2-phase buck circuit; ILA3 is the A-phase current of buck module 3, that is, the inductor current of the A3-phase buck circuit, and ILB3 is the B-phase current of buck module 3, that is, the inductor current of the B3-phase buck circuit.

[0057] It should be noted that since buck module 1, buck module 2 and buck module 3 are connected in series, it can be seen that ILA1+ILB1=ILA2+ILB2=ILA3+ILB3.

[0058] In the above step S102, the magnitudes of the A-phase current and the B-phase current in each buck module are compared, and the max-phase buck circuit and the min-phase buck circuit corresponding to each buck module are obtained according to the comparison result, which refers to comparing the magnitudes of ILA1 and ILB1, ILA2 and ILB2, and ILA3 and ILB3 in the debugging stage, and then grouping is performed according to the comparison result, and the phase with the larger current in each group is used as the max phase, and the phase with the smaller current is used as the min phase, as shown in Table 1:

[0059] Table 1 Comparison results grouping table

[0060]

[0061] In the above step S103, the average phase current is obtained. The average phase current is the sum of all A-phase currents and all B-phase currents divided by two. The purpose of obtaining the average phase current is to use it as the given value Iav of the current balancing loop. The expression of Iav is as follows: Iav=(ILA1+ILA2+ILA3+ILB1+ILB2+ILB3) / 2;

[0062] In the above step S104, the currents of all max phase buck circuits are used as the feedback values ​​of the first feedback control loop, the currents of all min phase buck circuits are used as the feedback values ​​of the second feedback control loop, and the average phase current is used as the given value of the first feedback control loop and the second feedback control loop, which means that the 1max phase inductor current + 2max phase inductor current + 3max phase inductor current are used as the feedback input of the first feedback control loop, and the 1min phase inductor current + 2min phase inductor current + 3min phase inductor current are used as the feedback input of the second feedback control loop. A current balancing loop is provided in both the first feedback control loop and the second feedback control loop. The function of the first feedback control loop is to reduce the currents of the three buck circuits with large currents together, and the function of the second feedback control loop is to increase the currents of the three buck circuits with small currents together. After the current balancing loop takes effect, the PWM duty ratios of the 1max phase, 2max phase, and 3max phase will all decrease, and the corresponding phase currents will decrease; the PWM duty ratios of the 1min phase, 2min phase, and 3min phase will all increase, and the corresponding phase currents will decrease, thereby ultimately achieving current balancing of all phase currents.

[0063] In some implementations of the present application, after step S104, the following may also be included:

[0064] The A-phase current and the B-phase current of each buck module are monitored in real time. When the relative magnitudes of the A-phase current and the B-phase current change, the max-phase buck circuit and the min-phase buck circuit corresponding to each buck module are updated, and the buck circuit corresponding to the first feedback control loop and the buck circuit corresponding to the second feedback control loop are switched through switches to keep the first feedback control loop controlling all max-phase buck circuits and the second feedback control loop controlling all min-phase buck circuits.

[0065] For example, taking buck module 1 as an example, if ILA1>ILB1 at the beginning, then phase A1 is 1max phase and phase B1 is 1min phase; at this time, ILA1 is used as the input of the first feedback control loop, and ILB1 is used as the input of the second feedback control loop. The A1 phase buck circuit is adjusted through the first feedback control loop to reduce the current of the A1 phase buck circuit, and the B1 phase buck circuit is adjusted through the second feedback control loop to increase the current of the B1 phase buck circuit. When ILA1 is less than ILB1, phase A1 is 1min phase and phase B1 is 1max phase. At this time, ILA1 is adjusted as the input of the second feedback control loop, and ILB1 is adjusted as the input of the first feedback control loop. The B1 phase buck circuit is adjusted through the first feedback control loop to reduce the current of the B1 phase buck circuit, and the A1 phase buck circuit is adjusted through the second feedback control loop to increase the current of the A1 phase buck circuit. The dynamic adjustment method of the remaining buck modules is the same as that of buck module 1. Through this dynamic adjustment and switching, current sharing can be maintained at all times.

[0066] The present application groups each phase according to the inductor current when the current is not balanced, and controls it through a feedback control loop according to the grouping result. The two feedback control loops act simultaneously, which ensures the synchronization of the switch tubes of the same phase and the current sharing between different phases.

[0067] refer to Figure 1 and Figure 3 As shown, the present application also relates to a current sharing synchronization device for a series interleaved circuit, comprising: a series interleaved buck circuit and a control unit. The series interleaved buck circuit comprises a plurality of buck modules connected in series, and each buck module comprises an A-phase buck circuit and a B-phase buck circuit arranged in an interleaved manner.

[0068] refer to Figure 1As shown, in this embodiment, the series interleaved buck circuit uses three buck modules connected in series, namely buck module 1, buck module 2 and buck module 3. Buck module 1 includes an A1-phase buck circuit and a B1-phase buck circuit, and the A1-phase buck circuit and the B1-phase buck circuit are interleaved. Buck module 2 includes an A2-phase buck circuit and a B2-phase buck circuit, and the A2-phase buck circuit and the B2-phase buck circuit are interleaved. Buck module 3 includes an A3-phase buck circuit and a B3-phase buck circuit, and the A3-phase buck circuit and the B3-phase buck circuit are interleaved. Buck module 1, buck module 2 and buck module 3 are connected in series to achieve boosting.

[0069] Specifically, the A1 phase buck circuit is composed of MOS transistor Q1A_P, MOS transistor Q1A_N and inductor LA1, the B1 phase buck circuit is composed of MOS transistor Q1B_P, MOS transistor Q1B_N and inductor LB1, similarly, the A2 phase buck circuit is composed of MOS transistor Q2A_P, MOS transistor Q2A_N and inductor LA2, the B2 phase buck circuit is composed of MOS transistor Q2B_P, MOS transistor Q2B_N and inductor LB2, the A3 phase buck circuit is composed of MOS transistor Q3A_P, MOS transistor Q3A_N and inductor LA3, and the B3 phase buck circuit is composed of MOS transistor Q3B_P, MOS transistor Q3B_N and inductor LB3. U1 is the source-load system input of buck module 1, U2 is the source-load system input of buck module 2, U3 is the source-load system input of buck module 3, and U0 is the source-load system output of the series interleaved buck circuit.

[0070] refer to Figure 3 As shown, the control unit includes a current sampling module, a current selection module, a given value input module, a first feedback control loop and a second feedback control loop. The current sampling module is used to obtain the A-phase current and the B-phase current of each buck module. Specifically, in this embodiment, the current sampling module samples the currents of all six buck circuits, that is, the inductor currents ILA1, ILA2, ILA3, ILB1, ILB2, and ILB3 are sampled, and the output end of the current sampling module is connected to the input end of the current selection module; the current selection module is used to compare the magnitude of the A-phase current and the B-phase current in each buck module, and obtain the max-phase buck circuit and the min-phase buck circuit corresponding to each buck module according to the comparison result, wherein the max-phase buck circuit is a buck circuit with a larger current, and the min-phase buck circuit is a buck circuit with a smaller current.

[0071] The given value input module is used to obtain the average phase current, which is the sum of all A-phase currents and all B-phase currents divided by two. The purpose of obtaining the average phase current is to use it as the given value Iav of the current sharing loop. The expression of Iav is as follows: Iav=(ILA1+ILA2+ILA3+ILB1+ILB2+ILB3) / 2.

[0072] The output end of the current selection module is connected to the feedback end of the first feedback control loop so as to use the current of all max-phase buck circuits as the feedback value of the first feedback control loop; the output end of the current selection module is connected to the feedback end of the second feedback control loop so as to use the current of all min-phase buck circuits as the feedback value of the second feedback control loop; the set value input module is respectively connected to the set value input ends of the first feedback control loop and the second feedback control loop so as to use the average phase current as the set value of the first feedback control loop and the second feedback control loop; the first feedback control loop is used to output a first PWM signal to control the current of all max-phase buck circuits according to the feedback value and the set value; the second feedback control loop is used to output a second PWM signal to control the current of all min-phase buck circuits according to the feedback value and the set value.

[0073] In this embodiment, the control unit also includes a voltage control loop, the first feedback control loop includes a first current sharing control loop and a first PWM modulation module A, the second feedback control loop includes a second current sharing control loop and a second PWM modulation module B, the output end of the voltage control loop is connected to the first input end of the first PWM modulation module A and the second PWM modulation module B respectively through an error amplifier 1, the output end of the first current sharing control loop is connected to the second input end of the first PWM modulation module A through an error amplifier 2, the output end of the second current sharing control loop is connected to the second input end of the second PWM modulation module B through an error amplifier 3, the first PWM modulation module A is used to output a first PWM signal to control the buck circuit corresponding to all max phase currents; the second PWM modulation module B is used to output a second PWM signal to control the buck circuit corresponding to all min phase currents.

[0074] The first current sharing control loop and the second current sharing control loop are current sharing control loops implemented by software control, and their control targets are that a given value is equal to a feedback value.

[0075] In this embodiment, the current selection module uses 1max phase inductor current + 2max phase inductor current + 3max phase inductor current as the feedback input of the first current sharing control loop, and uses 1min phase inductor current + 2min phase inductor current + 3min phase inductor current as the feedback input of the second current sharing control loop. The first PWM modulation module A and the second PWM modulation module B are used to produce waveforms staggered by 180°. The first PWM modulation module A outputs a first PWM signal PWMA_P and a first PWM signal PWMA_N, and PWMA_P and PWMA_N are complementary. The second PWM modulation module B outputs a second PWM signal PWMB_P and a second PWM signal PWMB_N, and PWMB_P and PWMB_N are complementary. PWMA_P and PWMB_P are staggered by 180°.

[0076] refer to Figure 4 As shown, in the embodiment of the present application, the control unit also includes a switch switching module, the PWM signal output end of the first feedback control loop and the PWM signal output end of the second feedback control loop are both connected to the input end of the switch switching module, and multiple output ends of the switch switching module are respectively connected to the control end of each A-phase buck circuit and the B-phase buck circuit for switching the buck circuit corresponding to the first feedback control loop and the buck circuit corresponding to the second feedback control loop.

[0077] Specifically, in the embodiment of the present application, the switch switching module includes switches S1 to S6, a total of 6 relay switches, which are used to switch the PWM waveforms of the first PWM modulation module A and the second PWM modulation module B, wherein switch S1 and switch S4 share a switching signal, switch S2 and switch S5 share a switching signal, and switch S3 and switch S6 share a switching signal. Through the switching of switches S1 to S6, the first PWM signal PWMA_P output by the first PWM modulation module A is always input to the gate of the MOS tube in the max phase buck circuit, and the second PWM signal PWMB_P and the second PWM signal PWMB_N output by the second PWM modulation module B are always input to the gate of the MOS tube in the min phase buck circuit.

[0078] The switching process of the switch is described in detail below, as shown in Table 2.

[0079] Table 2 Switching logic table

[0080]

[0081] It should be noted that the above PWMA1_P is the PWM signal of the gate of the MOS tube Q1A_P, and PWMA1_N is the PWM signal of the gate of the MOS tube Q1A_N; PWMB1_P is the PWM signal of the gate of the MOS tube Q1B_P, and PWMB1_N is the PWM signal of the gate of the MOS tube Q1B_N; PWMA2_P is the PWM signal of the gate of the MOS tube Q2A_P, and PWMA2_N is the PWM signal of the gate of the MOS tube Q2A_N; PWMB2_P is the PWM signal of the gate of the MOS tube Q2B_P, and PWMB2_N is the PWM signal of the gate of the MOS tube Q2B_N; PWMA3_P is the PWM signal of the gate of the MOS tube Q3A_P, and PWMA3_N is the PWM signal of the gate of the MOS tube Q3A_N; PWMB3_P is the PWM signal of the gate of the MOS tube Q3B_P, and PWMB3_N is the PWM signal of the gate of the MOS tube Q3B_N.

[0082] Through the above switch switching logic, the first PWM signal PWMA_P output by the first PWM modulation module A can be always input into the gate of the MOS tube in the max phase buck circuit, and the second PWM signal PWMB_P and the second PWM signal PWMB_N output by the second PWM modulation module B can be always input into the gate of the MOS tube in the min phase buck circuit. After the two current sharing control loops take effect, the PWM duty ratios of the 1max phase, the 2max phase, and the 3max phase will all decrease, and the corresponding phase current will decrease. The PWM duty ratios of the 1min phase, the 2min phase, and the 3min phase will all increase, and the corresponding phase current will decrease. Therefore, the series interleaved buck circuit can always maintain current sharing.

[0083] The implementation process of the present invention is described in detail below with specific examples:

[0084] First, in the debugging stage, phases 1A, 2A, and 3A share a drive waveform PWMA, and phases 1B, 2B, and 3B share a drive waveform PWMB. At this time, no current sharing control is performed. The current values ​​of inductors L1A, L2A, and L3A are measured by the current sampling module to be 9.8A, 10.3A, and 9.6A respectively, and the current values ​​of inductors L1B, L2B, and L3B are 10.2A, 9.7A, and 10.4A respectively, as shown in Table 3 below:

[0085] Table 3 Initial current measurement values

[0086]

[0087] Since ILA1 < ILB1, phase 1A is defined as the 1min phase and phase 1B as the 1max phase; similarly, since ILA2 > ILB2, phase 2A is defined as the 2max phase and phase 2B as the 2min phase; similarly, since ILA3 < ILB3, phase 3A is defined as the 3min phase and phase 3B as the 3max phase, as shown in Table 4 below:

[0088] Table 4 Definition Table of max Phase and min Phase

[0089]

[0090] The currents of the 1max phase, 2max phase, and 3max phase are added together for the feedback of current sharing loop 1, i.e., ILB1 + ILA2 + ILB3; the currents of the 1min phase, 2min phase, and 3min phase are added together for the feedback of current sharing loop 2, i.e., ILA1 + ILB2 + ILA3.

[0091] The output of error amplifier 2 and the output of error amplifier 1 are superimposed and then input to the first PWM modulation module A to generate the PWMA signal; the output of error amplifier 3 and the output of error amplifier 1 are superimposed and then input to the second PWM modulation module A to generate the PWMB signal;

[0092] The fundamental waves of the first PWM debugging module A and the second PWM modulation module B lag by 180 degrees, so PWMA and PWMB lag by 180 degrees; the feedback phases corresponding to PWMA are the 1max phase, 2max phase, and 3max phase, i.e., phase B1, phase A2, and phase B3. The switching mode of the three analog switches is that switch S1 is switched down, switch S2 is switched up, and switch S3 is switched down. By means of switch switching, the PWMA wave is switched to phase B1, phase A2, and phase B3. Since switch S1 and switch S4 share a switch signal, switch S2 and switch S5 share a switch signal, and switch S3 and switch S6 share a switch signal, therefore, the PWMB wave is also correspondingly switched to the 1min phase, 2min phase, and 3min phase, i.e., phase A1, phase B2, and phase A3.

[0093] After the current sharing loop takes effect, the PWM duty cycles of phase B1, phase A2, and phase B3 decrease, and the currents become smaller; the PWM duty cycles of phase 1, phase B2, and phase A3 increase, and the currents become larger, thereby achieving current sharing.

[0094] In summary, during the debugging stage of the present application, each phase is grouped according to the inductor current when the series interleaved buck circuit is not current sharing, and the output PWM signals are switched, and the two feedback control loops act simultaneously. This not only ensures the synchronization of the switching tubes of the same phase but also ensures current sharing between different phases.

[0095] The present application also relates to a source-load system, including the current sharing and synchronization device of the series interleaved circuit in the above embodiment.

[0096] The present application also relates to an electronic device, comprising the current sharing synchronization device of the series interleaved circuit of the above embodiment.

[0097] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A current sharing synchronization method for a series interleaved circuit, for a series interleaved buck circuit, wherein the series interleaved buck circuit comprises a plurality of buck modules connected in series, each buck module comprises an A-phase buck circuit and a B-phase buck circuit arranged in an interleaved manner, characterized in that: The following steps are involved: Get the A-phase current and B-phase current of each buck module; Compare the magnitudes of the A-phase current and the B-phase current in each buck module, and obtain the max-phase buck circuit and the min-phase buck circuit corresponding to each buck module according to the comparison results, wherein the max-phase buck circuit is a buck circuit with a larger current, and the min-phase buck circuit is a buck circuit with a smaller current; Obtaining an average phase current, wherein the average phase current is the sum of all A-phase currents and all B-phase currents divided by two; The currents of all the max-phase buck circuits are used as feedback values ​​of the first feedback control loop, the currents of all the min-phase buck circuits are used as feedback values ​​of the second feedback control loop, and the average phase current is used as a given value of the first feedback control loop and the second feedback control loop; The first feedback control loop outputs a first PWM signal to control the current of all max-phase buck circuits according to the feedback value and the given value, and the second feedback control loop outputs a second PWM signal to control the current of all min-phase buck circuits according to the feedback value and the given value.

2. The current sharing synchronization method of the series interleaved circuit according to claim 1, characterized in that: After the first feedback control loop outputs a first PWM signal to control the current of all max-phase buck circuits according to the input feedback value and the given value, and the second feedback control loop outputs a second PWM signal to control the current of all min-phase buck circuits according to the input feedback value and the given value, the method further includes: The A-phase current and the B-phase current of each buck module are monitored in real time. When the relative magnitudes of the A-phase current and the B-phase current change, the max-phase buck circuit and the min-phase buck circuit corresponding to each buck module are updated, and the buck circuit corresponding to the first feedback control loop and the buck circuit corresponding to the second feedback control loop are switched through switches to keep the first feedback control loop controlling all max-phase buck circuits and the second feedback control loop controlling all min-phase buck circuits.

3. A current sharing synchronization device for a series interleaved circuit, characterized in that: include: A series interleaved buck circuit includes a plurality of buck modules connected in series, each buck module includes an A-phase buck circuit and a B-phase buck circuit arranged in an interleaved manner; A control unit, the control unit comprising a current sampling module, a current selection module, a given value input module, a first feedback control loop and a second feedback control loop; The current sampling module is used to obtain the A-phase current and the B-phase current of each buck module, and the output end of the current sampling module is connected to the input end of the current selection module; The current selection module is used to compare the magnitudes of the A-phase current and the B-phase current in each buck module, and obtain the max-phase buck circuit and the min-phase buck circuit corresponding to each buck module according to the comparison result, wherein the max-phase buck circuit is a buck circuit with a larger current, and the min-phase buck circuit is a buck circuit with a smaller current; The given value input module is used to obtain an average phase current, where the average phase current is the sum of all A-phase currents and all B-phase currents divided by two; The output end of the current selection module is connected to the feedback end of the first feedback control loop to use the current of all max-phase buck circuits as the feedback value of the first feedback control loop; the output end of the current selection module is connected to the feedback end of the second feedback control loop to use the current of all min-phase buck circuits as the feedback value of the second feedback control loop; the given value input module is respectively connected to the given value input ends of the first feedback control loop and the second feedback control loop to use the average phase current as the given value of the first feedback control loop and the second feedback control loop; The first feedback control loop is used to output a first PWM signal to control the current of all max-phase buck circuits according to the feedback value and the given value, and the second feedback control loop is used to output a second PWM signal to control the current of all min-phase buck circuits according to the feedback value and the given value.

4. The current sharing synchronization device for the series interleaved circuit according to claim 3, characterized in that: The control unit also includes a switch switching module, wherein the PWM signal output end of the first feedback control loop and the PWM signal output end of the second feedback control loop are both connected to the input end of the switch switching module, and multiple output ends of the switch switching module are respectively connected to the control end of each A-phase buck circuit and the B-phase buck circuit for switching the buck circuit corresponding to the first feedback control loop and the buck circuit corresponding to the second feedback control loop.

5. The current sharing synchronization device for the series interleaved circuit according to claim 3, characterized in that: The control unit also includes a voltage control loop, the first feedback control loop includes a first current sharing control loop and a first PWM modulation module, the second feedback control loop includes a second current sharing control loop and a second PWM modulation module, the output end of the voltage control loop is respectively connected to the first input end of the first PWM modulation module and the second PWM modulation module, the output end of the first current sharing control loop is connected to the second input end of the first PWM modulation module, the output end of the second current sharing control loop is connected to the second input end of the second PWM modulation module, the first PWM modulation module is used to output a first PWM signal to control the current of all max-phase buck circuits; the second PWM modulation module is used to output a second PWM signal to control the current of all min-phase buck circuits.

6. A source-carrying system, characterized in that: A current sharing synchronization device comprising a series interleaved circuit as described in any one of claims 3 to 5.

7. An electronic device, characterized in that: A current sharing synchronization device comprising a series interleaved circuit as described in any one of claims 3 to 5.

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