Pre-voltage regulator circuit

Abstract

Embodiments of this disclosure provide a pre-regulator circuit, including: a reference voltage circuit, a regulator circuit, and a mirror circuit; wherein, the reference voltage circuit is configured to obtain a first current based on a reference voltage feedback loop; the regulator circuit is configured to obtain a second current based on a regulator feedback loop; the mirror circuit is configured to determine a first mirror current based on the first current, determine a second mirror current based on the second current, and adjust the relationship between a first coefficient of the first current and the first mirror current and a second coefficient of the second current and the second mirror current, so that the pre-regulator circuit outputs a power-on reset reference voltage with zero temperature coefficient. While ensuring a high-precision output reference voltage, the static current of the pre-regulator circuit is greatly reduced, thereby reducing the system standby power consumption.

Description

Technical Field

[0001] The embodiments of this disclosure relate to the field of integrated circuit technology and related technical fields, and more specifically, to a pre-regulator circuit. Background Technology

[0002] Pre-regulators are widely used in high-voltage integrated circuits. For example, when a system requires extremely low-power modes, such as memory retention or baseline housekeeping, the circuitry in the system needs to ensure a stable power supply. At the same time, due to area and power consumption considerations, circuits operating in low-power modes typically use low-voltage devices, requiring the pre-regulator to withstand high voltage.

[0003] Traditional pre-regulator circuits have limited output accuracy due to their simple structure. The low output accuracy of the pre-regulator circuit results in a large variation in the power-on-reset (POR) threshold. If it is necessary to improve the output accuracy of the pre-regulator circuit, a low-power voltage reference and several low-power comparators are required. However, the power consumption of the pre-regulator circuit is high after adding the voltage reference circuit and comparators.

[0004] Given the problems with existing technologies, there is an urgent need for a pre-regulator circuit that can reduce power consumption while ensuring the accuracy of the output voltage of the regulator circuit. Summary of the Invention

[0005] The embodiments described herein provide a pre-regulator circuit that addresses the problems existing in the prior art.

[0006] According to the present disclosure, a pre-regulator circuit is provided, including: a reference voltage circuit, a regulator circuit, and a mirror circuit;

[0007] The reference voltage circuit is configured to obtain the first current based on the reference voltage feedback loop;

[0008] The voltage regulator circuit is configured to obtain the second current based on the voltage regulation feedback loop;

[0009] The mirror circuit is configured to determine a first mirror current based on the first current, determine a second mirror current based on the second current, and adjust the relationship between a first coefficient of the first current and the first mirror current and a second coefficient of the second current and the second mirror current, so that the pre-regulator circuit outputs a power-on reset reference voltage with zero temperature coefficient.

[0010] In some embodiments of this disclosure, the reference voltage circuit includes: a first transistor, a second transistor, a first transistor, a second transistor, a third transistor, a first resistor, and a second resistor;

[0011] The bases of the first transistor and the second transistor are electrically connected to the rated voltage node. The collector of the first transistor is electrically connected to the first terminal of the first transistor and the control terminal of the third transistor, respectively. The second terminal of the first transistor is electrically connected to the second terminal of the second transistor, the second terminal of the third transistor, and the precharge voltage threshold node, respectively. The first terminal of the second transistor is electrically connected to the collector of the second transistor, the control terminal of the first transistor, and the control terminal of the second transistor, respectively. The emitter of the second transistor is electrically connected to the first terminal of the first resistor. The second terminal of the first resistor is electrically connected to the first terminal of the second resistor and the emitter of the first transistor, respectively. The second terminal of the second resistor is electrically connected to the ground node.

[0012] In some embodiments of this disclosure, the voltage regulator circuit includes the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the third resistor;

[0013] The first terminal of the third transistor is electrically connected to the first terminal of the fourth transistor, the control terminal of the fourth transistor, and the control terminal of the fifth transistor. The second terminal of the third transistor is electrically connected to the control terminal of the sixth transistor, the second terminal of the seventh transistor, and the precharge voltage threshold node. The second terminals of the fourth transistor and the fifth transistor are electrically connected to the ground node. The first terminal of the fifth transistor is electrically connected to the second terminal of the sixth transistor. The first terminal of the sixth transistor is electrically connected to the first terminal of the third resistor. The second terminal of the third resistor is electrically connected to the first terminal of the seventh transistor and the battery voltage output node.

[0014] In some embodiments of this disclosure, a first capacitor is also included; a first terminal of the first capacitor is electrically connected to the control terminal of the third transistor, the first terminal of the first transistor, and the collector of the first transistor, respectively, and a second terminal of the first capacitor is electrically connected to a ground node.

[0015] In some embodiments of this disclosure, a second capacitor is also included, the first terminal of which is electrically connected to the first terminal of the third resistor, the first terminal of the sixth transistor, and the control terminal of the seventh transistor, respectively, and the second terminal of which is electrically connected to the node node.

[0016] In some embodiments of this disclosure, the mirror circuit includes an eighth transistor and a ninth transistor;

[0017] The first terminal of the eighth transistor is electrically connected to the power-on reset output node and the first terminal of the ninth transistor, respectively. The second terminal of the eighth transistor is electrically connected to the precharge voltage threshold node, and the control terminal of the eighth transistor is electrically connected to the control terminal of the first transistor and the control terminal of the second transistor, respectively.

[0018] The second terminal of the ninth transistor is electrically connected to the ground node, and the control terminal of the ninth transistor is electrically connected to the control terminals of the fifth transistor and the fourth transistor, respectively.

[0019] In some embodiments of this disclosure, a fourth resistor and a fifth resistor are also included, wherein a first end of the fourth resistor is electrically connected to a precharge voltage threshold node, a second end of the fourth resistor is electrically connected to a first end of the fifth resistor and the rated voltage node, and a second end of the fifth resistor is electrically connected to a ground node.

[0020] In some embodiments of this disclosure, the first transistor and the second transistor are NPN transistors.

[0021] In some embodiments of this disclosure, the first transistor, the second transistor, the third transistor, and the eighth transistor are P-type transistors.

[0022] In some embodiments of this disclosure, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the ninth transistor are N-type transistors.

[0023] The pre-regulator circuit provided in this embodiment adjusts the relationship between the first coefficient of the first current and the first mirror current and the second coefficient of the second current and the second mirror current, so that the pre-regulator circuit outputs a power-on reset reference voltage with zero temperature coefficient. In addition, no additional startup circuit is required, reducing circuit power consumption. That is, while ensuring the output of a high-precision power-on reset reference voltage, the static current is greatly reduced, thereby reducing the system standby power consumption. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0025] Figure 1 This is a schematic diagram of the circuit structure of a pre-regulator circuit provided in an embodiment of this disclosure;

[0026] Figure 2 This is a schematic diagram of the simulation results of a pre-regulator circuit provided in an embodiment of this disclosure. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0028] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0029] In all embodiments of this disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current directions between the source and drain (emitter and collector) of N-type and P-type transistors are opposite, the controlled intermediate terminal of the transistor is referred to as the control terminal, and the remaining two terminals of the transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0030] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0031] Based on the problems existing in the prior art, this disclosure provides a pre-voltage regulator circuit, such as... Figure 1As shown, the pre-regulator circuit includes: a reference voltage circuit, a voltage regulator circuit, and a mirror circuit; wherein, the reference voltage circuit is configured to obtain a first current based on the reference voltage feedback loop; the voltage regulator circuit is configured to obtain a second current based on the voltage regulator feedback loop; the mirror circuit is configured to determine a first mirror current based on the first current, determine a second mirror current based on the second current, and adjust the relationship between a first coefficient of the first current and the first mirror current and a second coefficient of the second current and the second mirror current, so that the pre-regulator circuit outputs a power-on reset reference voltage with zero temperature coefficient.

[0032] like Figure 1 As shown, the reference voltage circuit includes: a first transistor Q1, a second transistor Q2, a first transistor Mp1, a second transistor Mp2, a third transistor Mp3, a first resistor R1, and a second resistor R2; the bases of the first transistor Q1 and the second transistor Q2 are electrically connected to the rated voltage node Vbg; the collector of the first transistor Q1 is electrically connected to the first terminal of the first transistor Mp1 and the control terminal of the third transistor Mp3, respectively; the second terminal of the first transistor Mp1 is electrically connected to the second terminal of the second transistor Mp2, the second terminal of the third transistor Mp3, and the precharge voltage threshold node Vpre, respectively; the first terminal of the second transistor Mp2 is electrically connected to the collector of the second transistor Q2, the control terminal of the first transistor Mp1, and the control terminal of the second transistor Mp2, respectively; the emitter of the second transistor Q2 is electrically connected to the first terminal of the first resistor R1; the second terminal of the first resistor R1 is electrically connected to the first terminal of the second resistor R2 and the emitter of the first transistor Q1, respectively; and the second terminal of the second resistor R2 is electrically connected to the ground node.

[0033] The reference voltage circuit consists of a first transistor Q1, a second transistor Q2, a first transistor Mp1, a second transistor Mp2, a third transistor Mp3, a first resistor R1, and a second resistor R2, forming a classic Brokaw bandgap reference voltage circuit. The rated voltage node is Vbg = Vbe(Q2) + ΔVbe*(R1+R2) / R1, where VBE is the voltage difference between the base and emitter of the second transistor.

[0034] Continue to combine Figure 1The voltage regulator circuit includes a third transistor Mp3, a fourth transistor Mn4, a fifth transistor Mn5, a sixth transistor Mn6, a seventh transistor Mn7, and a third resistor R3. The first terminal of the third transistor Mp3 is electrically connected to the first terminal of the fourth transistor Mn4, the control terminal of the fourth transistor Mn4, and the control terminal of the fifth transistor Mn5. The second terminal of the third transistor Mp3 is electrically connected to the control terminal of the sixth transistor Mn6, the second terminal of the seventh transistor Mn7, and the precharge voltage threshold node Vpre. The second terminals of the fourth transistor Mn4 and the fifth transistor Mn5 are electrically connected to the ground node. The first terminal of the fifth transistor Mn5 is electrically connected to the second terminal of the sixth transistor Mn6. The first terminal of the sixth transistor Mn6 is electrically connected to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is electrically connected to the first terminal of the seventh transistor Mn7 and the battery voltage output node VBAT.

[0035] In the voltage regulator circuit, the seventh transistor Mn7 acts as a high-voltage NMOS to provide a precise and stable output power supply voltage, i.e., the battery voltage.

[0036] In a specific embodiment, if the base current of the first transistor Q1 and the second transistor Q2 is not considered, the precharge voltage threshold node Vpre voltage satisfies Vpre=Vbg*(R4+R5) / R5.

[0037] Continue to combine Figure 1 The pre-voltage regulator circuit also includes a first capacitor C1; the first end of the first capacitor C1 is electrically connected to the control terminal of the third transistor Mp3, the first end of the first transistor Mp1, and the collector of the first transistor Q1, respectively, and the second end of the first capacitor C1 is electrically connected to the ground node.

[0038] The first capacitor C1 is used to improve the stability of the reference voltage feedback loop and the voltage regulation feedback loop.

[0039] Continue to combine Figure 1 The pre-voltage regulator circuit also includes a second capacitor C2. The first end of the second capacitor C2 is electrically connected to the first end of the third resistor R3, the first end of the sixth transistor Mn6, and the control end of the seventh transistor Mn7, respectively. The second end of the second capacitor C2 is electrically connected to the ground node.

[0040] The second capacitor C2 is used to improve the stability of the voltage regulation feedback loop.

[0041] Specifically, the mirror circuit includes an eighth transistor Mp8 and a ninth transistor Mn9; the first terminal of the eighth transistor Mp8 is electrically connected to the power-on reset output node VPorb and the first terminal of the ninth transistor Mn9, respectively; the second terminal of the eighth transistor Mp8 is electrically connected to the precharge voltage threshold node Vpre; the control terminal of the eighth transistor Mn8 is electrically connected to the control terminal of the first transistor Mp1 and the control terminal of the second transistor Mp2, respectively; the second terminal of the ninth transistor Mn9 is electrically connected to the ground node; and the control terminal of the ninth transistor Mn9 is electrically connected to the control terminal of the fifth transistor Mn5 and the control terminal of the fourth transistor Mn4, respectively.

[0042] Furthermore, the pre-regulator circuit also includes a fourth resistor R4 and a fifth resistor R5. The first end of the fourth resistor R4 is electrically connected to the pre-charge voltage threshold node Vpre, the second end of the fourth resistor R4 is electrically connected to the first end of the fifth resistor R5 and the rated voltage node Vbg, and the second end of the fifth resistor R5 is electrically connected to the ground node.

[0043] In the specific embodiments described above, the first transistor Q1 and the second transistor Q2 are NPN transistors. The first transistor Mp1, the second transistor Mp2, the third transistor Mp3, and the eighth transistor Mp8 are N-type transistors. The fourth transistor Mn4, the fifth transistor Mn5, the sixth transistor Mn6, the seventh transistor Mn7, and the ninth transistor Mn8 are N-type transistors.

[0044] Combination Figure 1The pre-regulator circuit includes a reference voltage circuit, a regulator circuit, and a mirror circuit. The reference voltage circuit includes a first transistor, a second transistor, a first transistor, a second transistor, a third transistor, a first resistor, and a second resistor. The reference voltage feedback loop of the reference voltage circuit is composed of Q1-Mp1-Mp3-R4-R1-Q1. At this time, the current flowing through the first transistor satisfies ΔVbe / R1, where ΔVbe is the change in the base voltage of the first transistor, that is, the first current I1 satisfies ΔVbe / R1. The regulator circuit includes a third transistor, a fourth transistor, a second transistor, a third transistor, a first resistor, and a second resistor. The voltage regulator circuit consists of a battery transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a third resistor. The voltage regulation feedback loop is composed of Mp3-Mn4-Mn5-Mn6-R3-Mn7-Mp3. At this time, the current flowing through the fourth and fifth transistors satisfies (VBAT-Vgs.mn7-Vpre) / R3, where VBAT is the battery voltage, Vgs.mn7 is the driving voltage of the seventh transistor, and Vpre is the pre-charge voltage threshold voltage. That is, the second current I2 satisfies (VBAT-Vgs.mn7-Vpre) / R3. The mirror circuit includes an eighth transistor and a ninth transistor. According to the working principle of the mirror circuit, the eighth transistor Mp8 is a mirror current source, which replicates the current of the first transistor Mp1 and the second transistor Mp2 and multiplies it by the first coefficient N1, that is, the first mirror current I1' is N1*ΔVbe / R3. The ninth transistor Mp9 is a mirror current source, which replicates the current of the fourth transistor Mp4 and the fifth transistor Mp5 and multiplies it by the second coefficient N2, that is, the second mirror current I2' is N2*(VBAT-Vgs.mn7-Vpre) / R3. According to the working principle of the pre-regulator circuit, when the first mirror current equals the second mirror current, the power-on reset output signal Vporb flips. Therefore, based on the first and second mirror currents, the battery voltage VBAT can be calculated to satisfy VBAT=Vpre+Vgs.mn7+(N1 / N2)*(R3 / R1)*ΔVbe=Vbg*(R4+R5) / R4+Vgs.mn7+(N1 / N2)*(R3 / R1)*ΔVbe. Since the gate-source voltage Vgs.mn7 of the seventh transistor has a negative temperature coefficient (comp... The base voltage ΔVbe of the first transistor has a positive temperature coefficient (PTAT). Therefore, by adjusting the ratio of (N1 / N2)*(R3 / R1), a power-on reset reference voltage that does not change with temperature can be obtained. Once the pre-regulator circuit is configured, i.e., when the resistances of the first and third resistors are fixed, the ratio of the first coefficient to the second coefficient can be adjusted to ensure that the pre-regulator circuit outputs a power-on reset reference voltage with zero temperature coefficient. Figure 2As shown, the Vporb signal flips when VBAT is above a certain voltage threshold (3.8V in this example), after which Vpre and Vbg are stable output voltages independent of the power supply.

[0045] Furthermore, since the current flowing through the sixth transistor Mn6 is determined by VBAT and R5, the embodiments of this disclosure do not require an additional startup circuit, thus reducing circuit power consumption.

[0046] The pre-regulator circuit provided in this embodiment adjusts the relationship between the first coefficient of the first current and the first mirror current and the second coefficient of the second current and the second mirror current, so that the pre-regulator circuit outputs a power-on reset reference voltage with zero temperature coefficient. In addition, no additional startup circuit is required, reducing circuit power consumption. That is, while ensuring the output of a high-precision power-on reset reference voltage, the static current is greatly reduced, thereby reducing the system standby power consumption.

[0047] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0048] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A pre-regulator circuit, characterized in that, include: Reference voltage circuit, voltage regulator circuit, and mirror circuit; The reference voltage circuit is configured to obtain the first current based on the reference voltage feedback loop; The voltage regulator circuit is configured to obtain the second current based on the voltage regulation feedback loop; The mirror circuit is configured to determine a first mirror current based on the first current, determine a second mirror current based on the second current, and adjust the relationship between a first coefficient of the first current and the first mirror current and a second coefficient of the second current and the second mirror current, so that the pre-regulator circuit outputs a power-on reset reference voltage with zero temperature coefficient.

2. The pre-regulator circuit according to claim 1, characterized in that, The reference voltage circuit includes: a first transistor, a second transistor, a first transistor, a second transistor, a third transistor, a first resistor, and a second resistor; The bases of the first transistor and the second transistor are electrically connected to the rated voltage node. The collector of the first transistor is electrically connected to the first terminal of the first transistor and the control terminal of the third transistor, respectively. The second terminal of the first transistor is electrically connected to the second terminal of the second transistor, the second terminal of the third transistor, and the precharge voltage threshold node, respectively. The first terminal of the second transistor is electrically connected to the collector of the second transistor, the control terminal of the first transistor, and the control terminal of the second transistor, respectively. The emitter of the second transistor is electrically connected to the first terminal of the first resistor. The second terminal of the first resistor is electrically connected to the first terminal of the second resistor and the emitter of the first transistor, respectively. The second terminal of the second resistor is electrically connected to the ground node.

3. The pre-regulator circuit according to claim 2, characterized in that, The voltage regulator circuit includes the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the third resistor; The first terminal of the third transistor is electrically connected to the first terminal of the fourth transistor, the control terminal of the fourth transistor, and the control terminal of the fifth transistor. The second terminal of the third transistor is electrically connected to the control terminal of the sixth transistor, the second terminal of the seventh transistor, and the precharge voltage threshold node. The second terminals of the fourth transistor and the fifth transistor are electrically connected to the ground node. The first terminal of the fifth transistor is electrically connected to the second terminal of the sixth transistor. The first terminal of the sixth transistor is electrically connected to the first terminal of the third resistor. The second terminal of the third resistor is electrically connected to the first terminal of the seventh transistor and the battery voltage output node.

4. The pre-regulator circuit according to claim 3, characterized in that, It also includes a first capacitor; the first end of the first capacitor is electrically connected to the control terminal of the third transistor, the first end of the first transistor, and the collector of the first transistor, respectively, and the second end of the first capacitor is electrically connected to the ground node.

5. The pre-regulator circuit according to claim 3, characterized in that, It also includes a second capacitor, the first end of which is electrically connected to the first end of the third resistor, the first end of the sixth transistor, and the control terminal of the seventh transistor, respectively, and the second end of the second capacitor is electrically connected to the node node.

6. The pre-regulator circuit according to claim 3, characterized in that, The mirror circuit includes an eighth transistor and a ninth transistor; The first terminal of the eighth transistor is electrically connected to the power-on reset output node and the first terminal of the ninth transistor, respectively. The second terminal of the eighth transistor is electrically connected to the precharge voltage threshold node, and the control terminal of the eighth transistor is electrically connected to the control terminal of the first transistor and the control terminal of the second transistor, respectively. The second terminal of the ninth transistor is electrically connected to the ground node, and the control terminal of the ninth transistor is electrically connected to the control terminals of the fifth transistor and the fourth transistor, respectively.

7. The pre-regulator circuit according to claim 6, characterized in that, It also includes a fourth resistor and a fifth resistor. The first end of the fourth resistor is electrically connected to the precharge voltage threshold node, the second end of the fourth resistor is electrically connected to the first end of the fifth resistor and the rated voltage node, and the second end of the fifth resistor is electrically connected to the ground node.

8. The pre-regulator circuit according to claim 2, characterized in that, The first transistor and the second transistor are NPN transistors.

9. The pre-regulator circuit according to claim 6, characterized in that, The first transistor, the second transistor, the third transistor, and the eighth transistor are P-type transistors.

10. The pre-regulator circuit according to claim 6, characterized in that, The fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the ninth transistor are N-type transistors.

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