Method, device, computer equipment and storage medium for reading data in register

Abstract

The present application discloses a method, apparatus, computer equipment and storage medium for reading data in a register, belonging to the field of artificial intelligence technology. In the method, the traversal coordinates of a target TLR in a TLR array on an artificial intelligence chip are obtained, wherein the TLR array is used to store a data block, and the traversal coordinates are determined according to the data arrangement size of multiple unit data in a single TLR configured when storing the data block. According to the traversal coordinates, the data arrangement size corresponding to the single TLR, and the TLR arrangement description information of a single sub-block in the data block, the index of the target TLR is determined, and then the data in the target TLR is read from the TLR array according to the index, thereby providing a general technical solution for reading data in the TLR according to the arrangement information of the TLR array corresponding to the data block.

Description

Technical Field

[0001] The present application relates to the field of artificial intelligence technology, and in particular to a method, device, computer equipment and storage medium for reading data in a register. Background Art

[0002] In actual applications, when a data block such as a tensor is loaded into the thread local register (TLR) array of an artificial intelligence chip, the arrangement information of the TLR array can be set.

[0003] Since the arrangement information of the TLR array has been determined in the same scenario, the index of the TLR in the TLR array is also fixed, so the data in the TLR can be read directly through the index of the TLR. However, the arrangement information of the TLR array is different in different scenarios, which results in that the index of the TLR in the TLR array can no longer be fixed, but changes with the arrangement information. In this case, how to read the data in the TLR according to the arrangement information of the TLR array corresponding to the data block has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] Embodiments of the present application provide a method, apparatus, computer device, and storage medium for reading data in a register, so as to provide a solution for reading data in a TLR according to arrangement information of a TLR array corresponding to a data block.

[0005] In a first aspect, an embodiment of the present application provides a method for reading data in a register, comprising:

[0006] Obtaining a traversal coordinate of a target thread local register TLR in a TLR array on an artificial intelligence chip, wherein the TLR array is used to store a data block, and the traversal coordinate is determined according to a data arrangement size of a plurality of unit data in a single TLR configured when storing the data block;

[0007] Determine the index of the target TLR according to the traversal coordinates, the data arrangement size corresponding to a single TLR, and TLR arrangement description information of a single sub-block in the data block configured when storing the data block;

[0008] According to the index of the target TLR, data in the target TLR is read from the TLR array.

[0009] In some embodiments, the TLR arrangement description information includes a TLR arrangement size, and determining the index of the target TLR according to the traversal coordinates, the data arrangement size corresponding to a single TLR, and the TLR arrangement description information of a single sub-block in the data block configured when storing the data block includes:

[0010] Determine the register coordinates of the target TLR according to the traversal coordinates and the data arrangement size corresponding to the single TLR, the register coordinates including the height coordinate and the width coordinate of the target TLR in the TLR array;

[0011] Determine the sub-block coordinates of the target sub-block to which the target TLR belongs according to the traversal coordinates and the data arrangement size corresponding to the single sub-block, wherein the data arrangement size corresponding to the single sub-block is determined according to the TLR arrangement size and the data arrangement size corresponding to the single TLR, and the sub-block coordinates include the height coordinate and the width coordinate of the target sub-block in each sub-block;

[0012] The index of the target TLR is determined according to the register coordinates, the sub-block coordinates and the TLR arrangement description information.

[0013] In some embodiments, the TLR arrangement description information further includes a TLR index order, and determining the index of the target TLR according to the register coordinates, the sub-block coordinates and the TLR arrangement description information includes:

[0014] Determine an index offset of the target TLR within the target sub-block according to the register coordinates, the sub-block coordinates and the TLR arrangement description information;

[0015] Determine the total number of TLRs included in the first sub-block and the second sub-block in the data block according to the sub-block coordinates, the width of the data block and the TLR arrangement size, wherein the height coordinate of the first sub-block is smaller than the height coordinate of the target sub-block, and the height coordinate of the second sub-block is equal to the height coordinate of the target sub-block, but the width coordinate is smaller than the width coordinate of the target sub-block;

[0016] The sum of the index of the first TLR in the TLR array, the total number of TLRs, and the index offset is determined as the index of the target TLR.

[0017] In some embodiments, determining the index offset of the target TLR in the target sub-block according to the register coordinates, the sub-block coordinates and the TLR arrangement description information includes:

[0018] Determine a height offset of the target TLR within the target sub-block according to the height coordinate of the target TLR, the height coordinate of the target sub-block, and the TLR arrangement size;

[0019] Determine a width offset of the target TLR within the target sub-block according to the width coordinate of the target TLR, the width coordinate of the target sub-block, and the width size in the TLR arrangement size;

[0020] The index offset of the target TLR in the target sub-block is determined according to the TLR arrangement description information and the height offset and the width offset of the target TLR in the target sub-block.

[0021] In some embodiments, determining the index offset of the target TLR in the target sub-block according to the TLR arrangement description information and the height offset and width offset of the target TLR in the target sub-block includes:

[0022] Determining a relative position of the target TLR in the target sub-block according to a height offset and a width offset of the target TLR in the target sub-block;

[0023] The index offset corresponding to the relative position of the target TLR in the target sub-block is determined according to the correspondence between different relative positions and index offsets in a single sub-block of the data block, wherein the correspondence is pre-established according to the TLR arrangement description information.

[0024] In some embodiments, determining the total number of TLRs included in the first sub-block and the second sub-block in the data block according to the sub-block coordinates, the width of the data block, and the TLR arrangement size includes:

[0025] Determine the number of TLRs included in the first sub-block according to the height coordinate of the target sub-block, the number of sub-blocks in the width direction of the data block, and the number of TLRs included in a single sub-block in the data block, wherein the number of sub-blocks is determined according to the width of the data block and the width size in the TLR arrangement size, and the number of TLRs included in the single sub-block is determined according to the TLR arrangement size;

[0026] Determine the number of TLRs included in the second sub-block according to the width coordinate of the target sub-block and the number of TLRs included in the single sub-block;

[0027] The sum of the numbers of TLRs included in the first sub-block and the second sub-block is determined as the total number of TLRs.

[0028] In a second aspect, an embodiment of the present application provides a device for reading data in a register, including:

[0029] An acquisition module, used for acquiring the traversal coordinates of the target thread local register TLR in the TLR array on the artificial intelligence chip, wherein the TLR array is used for storing a data block, and the traversal coordinates are determined according to the data arrangement size of multiple unit data in a single TLR configured when storing the data block;

[0030] A determination module, configured to determine the index of the target TLR according to the traversal coordinates, the data arrangement size corresponding to a single TLR, and TLR arrangement description information of a single sub-block in the data block configured when storing the data block;

[0031] A reading module is used to read the data in the target TLR from the TLR array according to the index of the target TLR.

[0032] In a third aspect, an embodiment of the present application provides a computer device, including a memory, an artificial intelligence chip, and a computer program stored in the memory and executable on the artificial intelligence chip, wherein the artificial intelligence chip implements any of the above-mentioned methods for reading data in a register when executing the computer program.

[0033] In a fourth aspect, an embodiment of the present application provides a storage medium. When a computer program in the storage medium is executed by a processor of a computer device, the computer device can execute any of the above-mentioned methods for reading data in a register.

[0034] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, which implements any of the above-mentioned methods for reading data in a register when executed by a processor.

[0035] In an embodiment of the present application, the traversal coordinates of the target TLR in the TLR array on the artificial intelligence chip are obtained, wherein the TLR array is used to store a data block, and the traversal coordinates are determined according to the data arrangement size of multiple unit data in a single TLR configured when storing the data block. The index of the target TLR is determined according to the traversal coordinates, the data arrangement size corresponding to the single TLR, and the TLR arrangement description information of a single sub-block in the data block, and then the data in the target TLR is read from the TLR array according to the index, thereby providing a general technical solution for reading data in the TLR according to the arrangement information of the TLR array corresponding to the data block. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0037] Figure 1 A schematic diagram of the structure of an artificial intelligence chip provided in an embodiment of the present application;

[0038] Figure 2 A flowchart of a method for reading data in a register provided in an embodiment of the present application;

[0039] Figure 3A schematic diagram of a TLR array corresponding to a data block provided in an embodiment of the present application;

[0040] Figure 4 A schematic diagram of a TLR array corresponding to another data block provided in an embodiment of the present application;

[0041] Figure 5 A schematic diagram of a TLR array corresponding to another data block provided in an embodiment of the present application;

[0042] Figure 6 A flowchart of determining an index of a target TLR provided in an embodiment of the present application;

[0043] Figure 7 A schematic diagram of the structure of a device for reading data in a register provided in an embodiment of the present application;

[0044] Figure 8 A schematic diagram of the structure of a computer device for implementing a method for reading data in a register provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to provide a solution for reading data in a TLR according to arrangement information of a TLR array corresponding to a data block, embodiments of the present application provide a method, an apparatus, a computer device, and a storage medium for reading data in a register.

[0046] The preferred embodiments of the present application are described below in conjunction with the drawings in the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In addition, the embodiments and features in the embodiments of the present application may be combined with each other if there is no conflict.

[0047] See also Figure 1 , Figure 1 A structural diagram of an artificial intelligence chip 100 provided in an embodiment of the present application at least includes: a video memory 101, an on-chip cache 102 and multiple computing units 103.

[0048] The video memory 101 may be a high bandwidth memory (HBM) or other types of memory. The on-chip cache 102 is a temporary memory with a smaller capacity than the video memory 101 but a faster data read and write speed than the video memory 101 .

[0049] The calculation unit 103 may be used to execute various types of operators, including but not limited to: a matrix multiplication operator, a matrix addition operator, and a matrix inverse operator.

[0050] The computing unit 103 can read and write data to the video memory 101, and can also read and write data to the on-chip cache 102. For example, the computing unit 103 can read data from the video memory 101 for calculation, or read data from the video memory 101, then write the read data to the on-chip cache 102, and then read data from the on-chip cache 102 for calculation.

[0051] In addition to the above-mentioned structure, the artificial intelligence chip 100 in the embodiment of the present application may also include other structures, which are not specifically limited in the embodiment of the present application.

[0052] In addition, the artificial intelligence chip 100 can be: a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a domain-specific architecture (DSA), etc.

[0053] In actual applications, when a data block such as a tensor is loaded into the TLR array of an artificial intelligence chip, the arrangement information of the TLR array can be set.

[0054] The arrangement information of the TLR array includes the data arrangement size of multiple unit data in a single TLR and the TLR arrangement description information of a single sub-block in a data block. The unit data refers to the data size that can be stored by a thread. Generally, there can be 32 threads in each TLR. Taking 32 floating points (FP) as an example, each thread can store 4 bytes of data, that is, the unit data is 4 bytes. The data arrangement size of multiple unit data in a single TLR refers to how many rows and columns 32 4-byte data are arranged in. Generally, X*Y=32 is satisfied. 32 4-byte data can be arranged into X rows and Y columns or Y rows and X columns. The TLR arrangement description information (or TLR layout) of a single sub-block includes the TLR arrangement size and the TLR arrangement order. The TLR arrangement size is used to indicate how many TLRs a sub-block contains in the width direction and the height direction respectively. The TLR arrangement order is used to indicate what the index order of the TLR in a single sub-block is, such as walking first and then walking in columns in a single sub-block, walking in columns first and then walking in a single sub-block, etc.

[0055] Since the arrangement information of the TLR array has been determined in the same scenario, the index of the TLR in the TLR array is also fixed, so the data in the TLR can be read directly through the index of the TLR. However, the arrangement information of the TLR array is different in different scenarios, which results in that the index of the TLR in the TLR array can no longer be fixed, but changes with the arrangement information. In this case, how to read the data in the TLR according to the arrangement information of the TLR array corresponding to the data block has become a technical problem that needs to be solved urgently.

[0056] To this end, this application proposes a method for reading data in a register, see Figure 2 , Figure 2 A flowchart of a method for reading data in a register provided in an embodiment of the present application includes the following steps.

[0057] In step 201, the traversal coordinates of the target TLR in the TLR array on the artificial intelligence chip are obtained. The TLR array is used to store a data block. The traversal coordinates are determined according to the data arrangement size of multiple unit data in a single TLR configured when storing the data block.

[0058] Among them, each time a data block is stored on the artificial intelligence chip, the arrangement information of the TLR array corresponding to the data block can be reconfigured. The arrangement information includes the data arrangement size of multiple unit data in a single TLR and the TLR arrangement description information of a single sub-block in the data block.

[0059] See also Figure 3 , Figure 3 A schematic diagram of a TLR array corresponding to a data block provided in an embodiment of the present application, wherein the size of the TLR array is (H, W) = (16, 24), that is, the TLR array contains 16 unit data in the height direction and 24 unit data in the width direction. Assume that the index of the first TLR in the TRL array is 0, Ri represents the index of 12 TLRs (i.e., the amount to be calculated later), i = 0~11, and the data arrangement size of multiple unit data in a single TLR is 8 rows and 4 columns (i.e., 8 in height and 4 in width). The TLR arrangement description information of a single sub-block includes: the TLR arrangement size is that a single sub-block contains 2 TLRs in both the width and height directions, and the TLR index order is to walk 2 in a single sub-block first and then walk 2 in the columns. In the Figure 3 When traversing the TLR in , the step length in the width direction is 4 and the step length in the height direction is 8. Then, the traversal coordinates of R0~R11 are:

[0060] {(0, 0), (0, 4), (0, 8), (0, 12), (0, 16), (0, 20);

[0061] (8, 0), (8, 4), (8, 8), (8, 12), (8, 16), (8, 20)}.

[0062] See also Figure 4 , Figure 4 A schematic diagram of a TLR array corresponding to another data block provided in an embodiment of the present application, wherein the size of the data block is (H, W) = (32, 24), assuming that the index of the first TLR in the TRL array is 0, Ri represents the index of 24 TLRs (i.e., the amount to be calculated later), i = 0~23, and the data arrangement size of multiple unit data in a single TLR is 8 rows and 4 columns (i.e., 8 in height and 4 in width). The TLR arrangement description information of a single sub-block includes: TLR sorting information includes 2 TLRs in the height direction and 3 TLRs in the width direction, and the TLR index order is to walk 3 in a single sub-block first and then walk 3 in the column. Figure 4 When traversing the TLR in , the step length in the width direction is 4 and the step length in the height direction is 8. Then, the traversal coordinates of R0~R23 are:

[0063] {(0, 0), (0, 4), (0, 8), (0, 12), (0, 16), (0, 20);

[0064] (8,0), (8,4), (8,8), (8,12), (8,16), (8,20);

[0065] (16, 0), (16, 4), (16, 8), (16, 12), (16, 16), (16, 20);

[0066] (24, 0), (24, 4), (24, 8), (24, 12), (24, 16), (24, 20)}.

[0067] Will Figure 4 The first two rows of data are Figure 3 By comparing the data in Figure 4 When storing a data block, the data arrangement size of multiple unit data in a single TLR does not change, but the TLR arrangement size of a single sub-block changes, which also changes the index of the TLR at the same traversal coordinate in the TLR array.

[0068] See also Figure 5 , Figure 5A schematic diagram of a TLR array corresponding to another data block provided in an embodiment of the present application, wherein the size (H, W) of the data block is (32, 24), assuming that the index of the first TLR in the TRL array is 0, Ri represents the index of 24 TLRs (i.e., the amount to be calculated later), i=0~23, and the data arrangement size of multiple unit data in a single TLR is 8 rows and 4 columns (i.e., 8 in height and 4 in width). The TLR arrangement description information of a single sub-block includes: TLR sorting information includes 2 TLRs in the height direction and 3 TLRs in the width direction, and the TLR index order is to go by column in a single sub-block, i.e., go to the next column after finishing one column. Figure 5 When traversing the TLR in , the step length in the width direction is 4 and the step length in the height direction is 8. Then, the traversal coordinates of R0~R23 are:

[0069] {(0, 0), (0, 4), (0, 8), (0, 12), (0, 16), (0, 20);

[0070] (8,0), (8,4), (8,8), (8,12), (8,16), (8,20);

[0071] (16, 0), (16, 4), (16, 8), (16, 12), (16, 16), (16, 20);

[0072] (24, 0), (24, 4), (24, 8), (24, 12), (24, 16), (24, 20)}.

[0073] Compared to Figure 4 In terms of Figure 5 When storing data blocks, the data arrangement size of multiple unit data in a single TLR does not change, but the TLR index order in a single sub-block changes, which also changes the index of the TLR at some identical traversal coordinates in the TLR array.

[0074] In step 202, the index of the target TLR is determined according to the traversal coordinates, the data arrangement size corresponding to a single TLR, and the TLR arrangement description information of a single sub-block in the data block configured when the data block is stored.

[0075] In some implementations, the TLR arrangement description information includes the TLR arrangement size. In specific implementations, the index of the target TLR may be determined according to the following steps.

[0076] Step 1: Determine the register coordinates of the target TLR according to the traversal coordinates and the data arrangement size corresponding to a single TLR. The register coordinates include the height coordinates and the width coordinates of the target TLR in the TLR array.

[0077] For example, the register coordinates (h_idx, w_idx) of the target TLR can be determined according to the following formula:

[0078] h_idx = h / TLR_H;

[0079] w_idx = w / TLR_W;

[0080] Among them, (h, w) is the traversal coordinate of the target TLR, (TLR_H, TLR_W) is the data arrangement size of multiple unit data in a single TLR, TLR_H represents the height of multiple unit data in a single TLR (that is, the number of unit data contained in a single TLR in the height direction), and TLR_W represents the width of multiple unit data in a single TLR (that is, the number of unit data contained in a single TLR in the width direction).

[0081] The target TLR is Figure 3 Take the data of TLR at position (8, 16) as an example, then:

[0082] h_idx = h / TLR_H = 8 / 8 = 1;

[0083] w_idx = w / TLR_W = 16 / 4 = 4;

[0084] It can be seen that the register coordinates of the target TLR are (1, 4), and the coordinate numbers in the height and width directions both start from 0.

[0085] The target TLR is Figure 4 Take the data of TLR at position (16, 8) as an example, then:

[0086] h_idx = h / TLR_H = 16 / 8 = 2;

[0087] w_idx = w / TLR_W = 8 / 4 = 2;

[0088] It can be seen that the register coordinates of the target TLR are (2, 2), and the coordinate numbers in the height and width directions both start from 0.

[0089] The target TLR is Figure 5 Take the data of TLR at position (16, 8) as an example, then:

[0090] h_idx = h / TLR_H = 16 / 8 = 2;

[0091] w_idx = w / TLR_W = 8 / 4 = 2;

[0092] It can be seen that the register coordinates of the target TLR are (2, 2), and the coordinate numbers in the height and width directions both start from 0.

[0093] Step 2: Determine the sub-block coordinates of the target sub-block to which the target TLR belongs according to the traversal coordinates and the data arrangement size corresponding to a single sub-block. The sub-block coordinates include the height coordinates and the width coordinates of the target sub-block in each sub-block.

[0094] The arrangement size corresponding to a single sub-block is determined according to the TLR arrangement size and the data arrangement size corresponding to the single TLR.

[0095] Assume that the arrangement size corresponding to a single sub-block is (TLR_H_BLOCK, TLR_W_BLOCK), TLR_H_BLOCK indicates how many unit data a single sub-block contains in the height direction, and TLR_W_BLOCK indicates how many unit data a single sub-block contains in the width direction, then,

[0096] TLR_H_BLOCK=TLR_H_NUM *TLR_H, TLR_W_BLOCK=TLR_W_NUM*TLR_W,

[0097] Among them, (TLR_H_NUM, TLR_W_NUM) is the TLR arrangement size, TLR_H_NUM represents the number of TLRs contained in a single sub-block in the height direction, and TLR_W_NUM represents the number of TLRs contained in a single sub-block in the width direction; (TLR_H, TLR_W) is the data arrangement size of multiple unit data in a single TLR, TLR_H represents the number of unit data contained in a single sub-block in the height direction, and TLR_W represents the number of unit data contained in a single sub-block in the width direction.

[0098] Figure 3 In, (TLR_H_NUM, TLR_W_NUM) = (2, 2), (TLR_H, TLR_W) = (8, 4), therefore, the data arrangement size corresponding to a single sub-block is (TLR_H_BLOCK, TLR_W_BLOCK) = (16, 8); in Figure 4 and Figure 5 In the example, (TLR_H_NUM, TLR_W_NUM) = (2, 3), (TLR_H, TLR_W) = (8, 4), therefore, the data arrangement size corresponding to a single sub-block is (TLR_H_BLOCK, TLR_W_BLOCK) = (16, 12).

[0099] During specific implementation, the sub-block coordinates (block_h_idx, block_w_idx) of the target sub-block to which the target TLR belongs may be determined according to the following formula:

[0100] block_h_idx = floor(h / TLR_H_BLOCK);

[0101] block_w_idx = floor(w / TLR_W_BLOCK);

[0102] Among them, (h, w) is the traversal coordinate of the target TLR, and floor (*) means rounding down.

[0103] The target TLR is Figure 3 Take the data of TLR at position (8, 16) as an example, then:

[0104] block_h_idx = floor(h / TLR_H_BLOCK)=floor(8 / 16)=0;

[0105] block_w_idx = floor(w / TLR_W_BLOCK)= floor(16 / 8)=2;

[0106] It can be seen that the sub-block coordinates of the target TLR are (0, 2), and the coordinate numbers in the height and width directions both start from 0.

[0107] The target TLR is Figure 4 Take the data of TLR at position (16, 8) as an example, then:

[0108] block_h_idx = floor(h / TLR_H_BLOCK)=floor(16 / 16)=1;

[0109] block_w_idx = floor(w / TLR_W_BLOCK)= floor(8 / 12)=0;

[0110] It can be seen that the sub-block coordinates of the target TLR are (1, 0), and the coordinate numbers in the height and width directions both start from 0.

[0111] The target TLR is Figure 5 Take the data of TLR at position (16, 8) as an example, then:

[0112] block_h_idx = floor(h / TLR_H_BLOCK)=floor(16 / 16)=1;

[0113] block_w_idx = floor(w / TLR_W_BLOCK)= floor(8 / 12)=0;

[0114] It can be seen that the sub-block coordinates of the target TLR are (1, 0), and the coordinate numbers in the height and width directions both start from 0.

[0115] Step 3: Determine the index of the target TLR according to the register coordinates, the sub-block coordinates and the TLR arrangement description information.

[0116] In some embodiments, the arrangement description information also includes a TLR index order. Figure 6 , please refer to Figure 6 The process shown determines the index of the target TLR, and the process includes the following steps.

[0117] In step 2021, the index offset of the target TLR in the target sub-block is determined according to the register coordinates, the sub-block coordinates and the TLR arrangement description information.

[0118] In specific implementation, the offsets of the target TLR in the height direction and the width direction in the target sub-block can be calculated respectively, and then, according to the offsets of the target TLR in the height direction and the width direction in the target sub-block and the TLR arrangement description information, the index offset of the target TLR in the target sub-block is determined. The process is described in detail below.

[0119] Step a, calculating the offset of the target TLR in the height direction within the target sub-block.

[0120] Here, the height offset of the target TLR in the target sub-block may be determined according to the height coordinate of the target TLR, the height coordinate of the target sub-block, and the TLR arrangement size.

[0121] For example, the height offset offset_h of the target TLR in the target sub-block is determined according to the following formula:

[0122] offset_h=h_idx–block_h_idx*TLR_H_NUM;

[0123] Among them, h_idx is the height coordinate of the target TLR, block_h_idx is the height coordinate of the target sub-block,

[0124] TLR_H_NUM indicates the number of TLRs contained in a single sub-block in the height direction.

[0125] In the formula, block_h_idx * TLR_ H _NUM is the number of TLRs of all sub-blocks on the upper side of the target sub-block (i.e., in the h direction), so subtracting block_h_idx * TLR_ H _NUM from h_idx is the offset of the target TLR in the h direction within the target sub-block.

[0126] The target TLR is Figure 3Taking the data of TLR at position (8, 16) as an example, offset_h=h_idx–block_h_idx*TLR_H_NUM =1-0*2=1.

[0127] The target TLR is Figure 4 Taking the data of TLR at position (16, 8) as an example, offset_h=h_idx–block_h_idx*TLR_H_NUM =2-1*2=0.

[0128] The target TLR is Figure 5 Taking the data of TLR at position (16, 8) as an example, offset_h=h_idx–block_h_idx*TLR_H_NUM=2-1*2=0.

[0129] Step b: Calculate the offset of the target TLR in the width direction within the target sub-block.

[0130] Here, the width offset of the target TLR in the target sub-block may be determined according to the width coordinate of the target TLR, the width coordinate of the target sub-block, and the width size in the TLR arrangement size.

[0131] For example, the height offset offset_w of the target TLR in the target sub-block is determined according to the following formula:

[0132] offset_w=w_idx–block_w_idx * TLR_W_NUM;

[0133] Among them, w_idx is the width coordinate of the target TLR, block_w_idx is the width coordinate of the target sub-block, and TLR_W_NUM is the width size in the TLR arrangement size, indicating the number of TLRs contained in a single sub-block in the width direction.

[0134] In the formula, block_w_idx * TLR_W_NUM is calculated in the w direction, the number of TLRs in the w direction of all sub-blocks to the left of the target sub-block, so w_idx minus block_w_idx * TLR_W_NUM is the offset of the target TLR in the w direction within the target sub-block.

[0135] The target TLR is Figure 3 Taking the data of TLR at position (8, 16) as an example, offset_w=w_idx–block_w_idx * TLR_W_NUM=4-2*2=0.

[0136] The target TLR is Figure 4Taking the data of TLR at position (16, 8) as an example, offset_w=w_idx–block_w_idx * TLR_W_NUM=2-0*3=2.

[0137] The target TLR is Figure 5 Taking the data of TLR at position (16, 8) as an example, offset_w=w_idx–block_w_idx * TLR_W_NUM=2-0*3=2.

[0138] Step c: determining the index offset of the target TLR in the target sub-block according to the offset of the target TLR in the height direction and the width direction in the target sub-block and the TLR arrangement description information.

[0139] In a specific implementation, the relative position of the target TLR in the target sub-block can be determined based on the height offset and width offset of the target TLR in the target sub-block, and then the index offset corresponding to the relative position of the target TLR in the target sub-block can be determined based on the correspondence between different relative positions and index offsets in a single sub-block of the data block, wherein the correspondence between different relative positions and index offsets in a single sub-block is pre-established based on the TLR arrangement description information.

[0140] The target TLR is Figure 3 Take the data of TLR at position (8, 16) as an example, its (offset_h, offset_w) = (1, 0), and Figure 3 The 4 TLRs {(0, 0), (0, 1), (1, 0), (1, 1)} in a single sub-block are walked 2 at a time and then 2 in a row, so the offsets of these 4 TLRs are 0, 1, 2, and 3 respectively. Then the index offset corresponding to (offset_h, offset_w) = (1, 0) is 2.

[0141] The target TLR is Figure 4 Take the data of TLR at position (16, 8) as an example, its (offset_h, offset_w) = (0, 2), and Figure 4 The 6 TLRs {(0, 0), (0, 1), (0, 2), (1, 0), (1, 1), (1, 2)} in a single sub-block are walked 3 times first and then 3 times in a row, so the offsets of these 6 TLRs are 0, 1, 2, 3, 4, 5 respectively. Then the index offset corresponding to (offset_h, offset_w) = (0, 2) is 2.

[0142] The target TLR is Figure 5 Take the data of TLR at position (16, 8) as an example, its (offset_h, offset_w) = (0, 2), and Figure 5 The 6 TLRs {(0, 0), (0, 1), (0, 2), (1, 0), (1, 1), (1, 2)} in a single sub-block are arranged 2 by column, so the offsets of these 6 TLRs are 0, 2, 4, 1, 3, 5 respectively. Then the index offset corresponding to (offset_h, offset_w) = (0, 2) is 4.

[0143] In step 2022, the total number of TLRs contained in the first sub-block and the second sub-block in the data block is determined based on the sub-block coordinates, the width of the data block and the TLR arrangement size, the height coordinate of the first sub-block is smaller than the height coordinate of the target sub-block, the height coordinate of the second sub-block is equal to the height coordinate of the target sub-block, but the width coordinate is smaller than the width coordinate of the target sub-block.

[0144] In specific implementation, the number of TLRs included in the first sub-block above the target sub-block and the number of TLRs included in the second sub-block at the same height as the target sub-block but located on the left side of the target sub-block can be calculated, and the sum of the two numbers is the total number of TLRs. This process is described in detail below.

[0145] Step a: Calculate the number of TLRs contained in the first sub-block above the target sub-block.

[0146] Here, the number of TLRs contained in the first sub-block can be determined based on the height coordinate of the target sub-block, the number of sub-blocks in the data block in the width direction, and the number of TLRs contained in a single sub-block in the data block, wherein the number of sub-blocks is determined based on the width of the data block and the width dimension in the TLR arrangement dimension, and the number of TLRs contained in a single sub-block is determined based on the TLR arrangement dimension.

[0147] For example, the number N1 of TLRs included in the first sub-block is determined according to the following formula:

[0148] N1=block_h_idx*block_w* TLR_NUM,

[0149] Among them, block_h_idx is the height coordinate of the target sub-block, block_w is the number of sub-blocks in the data block in the width direction, block_w= floor(W / TLR_W_BLOCK), W is the number of unit data contained in the data block in the width direction (that is, how many unit data does the data block contain in the width direction), TLR_W_BLOCK represents the number of unit data contained in a single sub-block in the width direction, floor (*) means rounding down, TLR_NUM is the total number of TLRs contained in a single sub-block, TLR_NUM= TLR_H_NUM* TLR_W_NUM.

[0150] The target TLR is Figure 3Taking the data of TLR at position (8, 16) as an example, N1=block_h_idx*block_w*TLR_NUM=0*3*4=0.

[0151] The target TLR is Figure 4 Taking the data of TLR at position (16, 8) as an example, N1=block_h_idx*block_w*TLR_NUM=1*2*6=12.

[0152] The target TLR is Figure 5 Taking the data of TLR at position (16, 8) as an example, N1=block_h_idx*block_w*TLR_NUM=1*2*6=12.

[0153] Step b: Calculate the number of TLRs contained in a second sub-block that is at the same height as the target sub-block but located on the left side of the target sub-block.

[0154] Here, the number of TLRs included in the second sub-block may be determined according to the width coordinate of the target sub-block and the number of TLRs included in a single sub-block.

[0155] For example, the number N2 of TLRs included in the second sub-block is determined according to the following formula:

[0156] N2 = block_w_idx * TLR_NUM,

[0157] Wherein, block_w_idx is the width coordinate of the target sub-block, TLR_NUM is the total number of TLRs contained in a single sub-block, and TLR_NUM = TLR_H_NUM* TLR_W_NUM.

[0158] The target TLR is Figure 3 Taking the data of TLR at position (8, 16) as an example, N2 = block_w_idx* TLR_NUM = 2*4=8.

[0159] The target TLR is Figure 4 Taking the data of TLR at position (16, 8) as an example, N2 = block_w_idx* TLR_NUM = 0*6=0.

[0160] The target TLR is Figure 5 Taking the data of TLR at position (16, 8) as an example, N2 = block_w_idx* TLR_NUM = 0*6=0.

[0161] Step b: Calculate the sum of the numbers of TLRs included in the first sub-block and the second sub-block to determine the total number of TLRs.

[0162] The target TLR is Figure 3 Taking the data of TLR at position (8, 16) as an example, N = N1+N2=0+8=8.

[0163] The target TLR is Figure 4 Taking the data of TLR at position (16, 8) as an example, N = N1+N2=12+0=12.

[0164] The target TLR is Figure 5 Taking the data of TLR at position (16, 8) as an example, N = N1+N2=12+0=12.

[0165] In step 2023, the sum of the index of the first TLR in the TLR array, the total number of TLRs, and the index offset is determined as the index of the target TLR.

[0166] The target TLR is Figure 3 Taking the data of the TLR at position (8, 16) as an example, the index of the target TLR is index=0+8+2=10.

[0167] The target TLR is Figure 4 Taking the data of the TLR at position (16, 8) as an example, the index of the target TLR is index=0+12+2=14.

[0168] The target TLR is Figure 5 Taking the data of the TLR at position (16, 8) as an example, the index of the target TLR is index=0+12+4=16.

[0169] In step 203, data in the target TLR is read from the TLR array according to the index of the target TLR.

[0170] In this way, no matter what the arrangement information of the TLR array corresponding to a data block is, the index of the TLR can be determined by the traversal coordinates of a TLR in the TLR array combined with the specific arrangement information, thereby providing a general traversal solution for indefinite TLRlayout.

[0171] Subsequently, the read data may be calculated. For example, if the read data is an operand of an operator, the read data may be calculated and processed according to the calculation method corresponding to the operator.

[0172] See also Figure 3, assuming that a certain operator accumulates the first row of data in the TLR array, the first row of data can be traversed, and the traversal coordinates are (0, 0), (0, 4), (0, 8), (0, 12), (0, 16), (0, 20) in sequence. For each traversal coordinate, the index of the TLR can be calculated using the method provided in the embodiment of the present application, which is 0, 1, 4, 5, 8, 9 in sequence, and then the data in the corresponding TLR is read and accumulated according to the index calculated each time. The process of traversing a column of data in the TLR array is similar and will not be repeated here.

[0173] Based on the same technical concept, an embodiment of the present application also provides a device for reading data in a register. The principle of solving the problem by the device for reading data in a register is similar to that of the above-mentioned method for reading data in a register. Therefore, the implementation of the device for reading data in a register can refer to the implementation of the method for reading data in a register, and the repeated parts will not be repeated.

[0174] Figure 7 A schematic diagram of a structure of a device for reading data in a register provided in an embodiment of the present application includes:

[0175] An acquisition module 701 is used to acquire the traversal coordinates of the target thread local register TLR in the TLR array on the artificial intelligence chip, wherein the TLR array is used to store a data block, and the traversal coordinates are determined according to the data arrangement size of multiple unit data in a single TLR configured when storing the data block;

[0176] A determination module 702, configured to determine an index of the target TLR according to the traversal coordinates, a data arrangement size corresponding to a single TLR, and TLR arrangement description information of a single sub-block in the data block configured when storing the data block;

[0177] The reading module 703 is configured to read the data in the target TLR from the TLR array according to the index of the target TLR.

[0178] In some embodiments, the TLR arrangement description information includes a TLR arrangement size, and the determining module 702 is specifically configured to:

[0179] Determine the register coordinates of the target TLR according to the traversal coordinates and the data arrangement size corresponding to the single TLR, the register coordinates including the height coordinate and the width coordinate of the target TLR in the TLR array;

[0180] Determine the sub-block coordinates of the target sub-block to which the target TLR belongs according to the traversal coordinates and the data arrangement size corresponding to the single sub-block, wherein the data arrangement size corresponding to the single sub-block is determined according to the TLR arrangement size and the data arrangement size corresponding to the single TLR, and the sub-block coordinates include the height coordinate and the width coordinate of the target sub-block in each sub-block;

[0181] The index of the target TLR is determined according to the register coordinates, the sub-block coordinates and the TLR arrangement description information.

[0182] In some embodiments, the TLR arrangement description information further includes a TLR index sequence, and the determining module 702 is specifically configured to:

[0183] Determine an index offset of the target TLR within the target sub-block according to the register coordinates, the sub-block coordinates and the TLR arrangement description information;

[0184] Determine the total number of TLRs included in the first sub-block and the second sub-block in the data block according to the sub-block coordinates, the width of the data block and the TLR arrangement size, wherein the height coordinate of the first sub-block is smaller than the height coordinate of the target sub-block, and the height coordinate of the second sub-block is equal to the height coordinate of the target sub-block, but the width coordinate is smaller than the width coordinate of the target sub-block;

[0185] The sum of the index of the first TLR in the TLR array, the total number of TLRs, and the index offset is determined as the index of the target TLR.

[0186] In some embodiments, the determining module 702 is specifically configured to:

[0187] Determine a height offset of the target TLR within the target sub-block according to the height coordinate of the target TLR, the height coordinate of the target sub-block, and the TLR arrangement size;

[0188] Determine a width offset of the target TLR within the target sub-block according to the width coordinate of the target TLR, the width coordinate of the target sub-block, and the width size in the TLR arrangement size;

[0189] The index offset of the target TLR in the target sub-block is determined according to the TLR arrangement description information and the height offset and the width offset of the target TLR in the target sub-block.

[0190] In some embodiments, the determining module 702 is specifically configured to:

[0191] Determining a relative position of the target TLR in the target sub-block according to a height offset and a width offset of the target TLR in the target sub-block;

[0192] The index offset corresponding to the relative position of the target TLR in the target sub-block is determined according to the correspondence between different relative positions and index offsets in a single sub-block of the data block, wherein the correspondence is pre-established according to the TLR arrangement description information.

[0193] In some embodiments, the determining module 702 is specifically configured to:

[0194] Determine the number of TLRs included in the first sub-block according to the height coordinate of the target sub-block, the number of sub-blocks in the width direction of the data block, and the number of TLRs included in a single sub-block in the data block, wherein the number of sub-blocks is determined according to the width of the data block and the width size in the TLR arrangement size, and the number of TLRs included in the single sub-block is determined according to the TLR arrangement size;

[0195] Determine the number of TLRs included in the second sub-block according to the width coordinate of the target sub-block and the number of TLRs included in the single sub-block;

[0196] The sum of the numbers of TLRs included in the first sub-block and the second sub-block is determined as the total number of TLRs.

[0197] The division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, the functional modules in the embodiments of the present application may be integrated in a processor, or may exist physically separately, or two or more modules may be integrated in one module. The coupling between the modules may be achieved through some interfaces, which are usually electrical communication interfaces, but it is not excluded that they may be mechanical interfaces or other forms of interfaces. Therefore, the modules described as separate components may or may not be physically separated, and may be located in one place or distributed to different locations of the same or different devices. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0198] Based on the same technical concept, the embodiment of the present application provides a computer device, such as Figure 8 As shown, it includes at least one artificial intelligence chip 100 and a memory 801 connected to the at least one artificial intelligence chip 100. The specific connection medium between the artificial intelligence chip 100 and the memory 801 is not limited in the embodiment of the present application. Figure 8In the example, the artificial intelligence chip 100 and the memory 801 are connected via a bus. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0199] In an embodiment of the present application, the memory 801 stores instructions that can be executed by at least one artificial intelligence chip 100. At least one artificial intelligence chip 100 can perform the steps of the above-mentioned cache line scheduling method by executing the instructions stored in the memory 801.

[0200] Among them, the artificial intelligence chip 100 is the control center of the computer device, and various interfaces and lines can be used to connect various parts of the computer device, and the data in the register can be read by running or executing instructions stored in the memory 801 and calling the data stored in the memory 801. Optionally, the artificial intelligence chip 100 may include one or more processing units, and the artificial intelligence chip 100 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the artificial intelligence chip 100. In some embodiments, the artificial intelligence chip 100 and the memory 801 can be implemented on the same chip, and in some embodiments, they can also be implemented separately on independent chips.

[0201] The artificial intelligence chip 100 can be a general-purpose processor, such as a digital signal processor, an application-specific integrated circuit (ASIC), a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, which can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor.

[0202] The memory 801 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 801 may include at least one type of storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory, a random access memory (Random Access Memory, RAM), a static random access memory (Static Random Access Memory, SRAM), a programmable read-only memory (Programmable Read Only Memory, PROM), a read-only memory (Read Only Memory, ROM), an electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), a magnetic memory, a disk, an optical disk, and the like. The memory 801 is any other medium that can be used to carry or store the desired program code in the form of an instruction or data structure and can be accessed by a computer device, but is not limited thereto. The memory 801 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0203] In an exemplary embodiment, a storage medium is also provided. When a computer program in the storage medium is executed by a computer device

[0204] When the processor executes, the computer device can execute the above method of reading data in the register. Optionally, the storage medium can be a non-temporary computer-readable storage medium, for example, the non-temporary computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0205] In an exemplary embodiment, a computer program product is also provided. When the computer program product is executed by a computer device, the computer device can implement any exemplary method provided in the present application.

[0206] It should be noted that, although several units or subunits of the device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided into multiple units to be embodied.

[0207] In addition, although the operations of the method of the present application are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0208] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0209] The present application is described with reference to the flowcharts and / or block diagrams of the methods, apparatus (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0210] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0211] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0212] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0213] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application also includes these modifications and variations.

Claims

1. A method for reading data in a register, characterized in that: include: Obtaining a traversal coordinate of a target thread local register TLR in a TLR array on an artificial intelligence chip, wherein the TLR array is used to store a data block, and the traversal coordinate is determined according to a data arrangement size of a plurality of unit data in a single TLR configured when storing the data block; Determine the index of the target TLR according to the traversal coordinates, the data arrangement size corresponding to a single TLR, and TLR arrangement description information of a single sub-block in the data block configured when storing the data block; According to the index of the target TLR, data in the target TLR is read from the TLR array.

2. The method according to claim 1, characterized in that The TLR arrangement description information includes a TLR arrangement size, and determining an index of the target TLR according to the traversal coordinates, the data arrangement size corresponding to a single TLR, and the TLR arrangement description information of a single sub-block in the data block configured when storing the data block, including: Determine the register coordinates of the target TLR according to the traversal coordinates and the data arrangement size corresponding to the single TLR, the register coordinates including the height coordinate and the width coordinate of the target TLR in the TLR array; Determine the sub-block coordinates of the target sub-block to which the target TLR belongs according to the traversal coordinates and the data arrangement size corresponding to the single sub-block, wherein the data arrangement size corresponding to the single sub-block is determined according to the TLR arrangement size and the data arrangement size corresponding to the single TLR, and the sub-block coordinates include the height coordinate and the width coordinate of the target sub-block in each sub-block; The index of the target TLR is determined according to the register coordinates, the sub-block coordinates and the TLR arrangement description information.

3. The method according to claim 2, characterized in that The TLR arrangement description information further includes a TLR index order, and determining the index of the target TLR according to the register coordinates, the sub-block coordinates and the TLR arrangement description information includes: Determine an index offset of the target TLR within the target sub-block according to the register coordinates, the sub-block coordinates and the TLR arrangement description information; Determine the total number of TLRs included in the first sub-block and the second sub-block in the data block according to the sub-block coordinates, the width of the data block and the TLR arrangement size, wherein the height coordinate of the first sub-block is smaller than the height coordinate of the target sub-block, and the height coordinate of the second sub-block is equal to the height coordinate of the target sub-block, but the width coordinate is smaller than the width coordinate of the target sub-block; The sum of the index of the first TLR in the TLR array, the total number of TLRs, and the index offset is determined as the index of the target TLR.

4. The method according to claim 3, characterized in that Determining an index offset of the target TLR in the target sub-block according to the register coordinates, the sub-block coordinates and the TLR arrangement description information includes: Determine a height offset of the target TLR within the target sub-block according to the height coordinate of the target TLR, the height coordinate of the target sub-block, and the TLR arrangement size; Determine a width offset of the target TLR within the target sub-block according to the width coordinate of the target TLR, the width coordinate of the target sub-block, and the width size in the TLR arrangement size; The index offset of the target TLR in the target sub-block is determined according to the TLR arrangement description information and the height offset and the width offset of the target TLR in the target sub-block.

5. The method according to claim 4, characterized in that Determining an index offset of the target TLR in the target sub-block according to the TLR arrangement description information and a height offset and a width offset of the target TLR in the target sub-block includes: Determining a relative position of the target TLR in the target sub-block according to a height offset and a width offset of the target TLR in the target sub-block; The index offset corresponding to the relative position of the target TLR in the target sub-block is determined according to the correspondence between different relative positions and index offsets in a single sub-block of the data block, wherein the correspondence is pre-established according to the TLR arrangement description information.

6. The method according to claim 3, characterized in that Determining the total number of TLRs included in the first sub-block and the second sub-block in the data block according to the sub-block coordinates, the width of the data block, and the TLR arrangement size, including: Determine the number of TLRs included in the first sub-block according to the height coordinate of the target sub-block, the number of sub-blocks in the width direction of the data block, and the number of TLRs included in a single sub-block in the data block, wherein the number of sub-blocks is determined according to the width of the data block and the width size in the TLR arrangement size, and the number of TLRs included in the single sub-block is determined according to the TLR arrangement size; Determine the number of TLRs included in the second sub-block according to the width coordinate of the target sub-block and the number of TLRs included in the single sub-block; The sum of the numbers of TLRs included in the first sub-block and the second sub-block is determined as the total number of TLRs.

7. A device for reading data in a register, characterized in that: include: An acquisition module, used for acquiring the traversal coordinates of the target thread local register TLR in the TLR array on the artificial intelligence chip, wherein the TLR array is used for storing a data block, and the traversal coordinates are determined according to the data arrangement size of multiple unit data in a single TLR configured when storing the data block; A determination module, configured to determine the index of the target TLR according to the traversal coordinates, the data arrangement size corresponding to a single TLR, and TLR arrangement description information of a single sub-block in the data block configured when storing the data block; A reading module is used to read the data in the target TLR from the TLR array according to the index of the target TLR.

8. A computer device comprising a memory, an artificial intelligence chip, and a computer program stored in the memory and executable on the artificial intelligence chip, characterized in that: When the artificial intelligence chip executes the computer program, the steps of the method as described in any one of claims 1 to 6 are implemented.

9. A storage medium, characterized in that: When the computer program in the storage medium is executed by a processor of a computer device, the computer device can execute the method according to any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises a computer program, wherein when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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