Pixel driving circuit and driving method thereof, and display device

Abstract

The present disclosure provides a pixel driving circuit and a driving method thereof, and a display device, relating to the field of display technology. The pixel driving circuit includes a driving transistor, a data writing module, a third node reset module, and a first node reset module. The third node reset module is located between the first reset signal terminal and the third node, and the first node reset module is located between the first node and the third node. The signal of the third node is reset by the third node reset module, and the signal of the first node is reset by the third node reset module and the first node reset module. Such an arrangement is conducive to reducing leakage paths, thereby facilitating improvement of flickering of a display panel. At the same time, the first node reset module includes a first sub-transistor and a second sub-transistor. The threshold voltage of the first sub-transistor is positively biased, which is conducive to reducing leakage, thereby facilitating stabilization of the voltage of the first node, and further facilitating improvement of flickering of the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, and a display device. Background Art

[0002] With the development of display technology, active matrix organic light emitting diode (AMOLED) display panels have gradually entered the market. Compared with traditional thin film transistor liquid crystal display (TFT LCD) panels, AMOLED display panels have the advantages of low energy consumption, self-luminescence, wide viewing angle, fast response speed, and easy application of flexible display technology. AMOLED display panels can usually be driven by current, that is, the light emitting module is controlled by the driving current.

[0003] Variable frequency drive technology is increasingly being applied to display panels. For example, a higher refresh rate drive is used to display dynamic images (such as sports events or gaming scenes) to ensure smooth display, while a lower refresh rate drive is used to display slow-motion images or static images to reduce power consumption. In low-frequency mode, display panels are more prone to flickering. Summary of the Invention

[0004] In order to solve the above technical problems, the present disclosure provides a pixel driving circuit and a driving method thereof, and a display device, which are used to improve the low-frequency flicker problem of a display panel.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit, comprising:

[0006] a driving transistor, wherein a gate of the driving transistor is connected to the first node, a first electrode is connected to the second node, and a second electrode is connected to the third node;

[0007] a data writing module connected between the data signal terminal and the second node;

[0008] A third node reset module connected between the first reset signal terminal and the third node;

[0009] a first node reset module, connected between the third node and the first node, the first node reset module being reused as a threshold compensation module;

[0010] In the first node reset phase, the third node reset module and the first node reset module are both turned on; in the data writing phase, the data writing module and the first node reset module are turned on, and the third node reset module is turned off;

[0011] The first node reset module includes a first sub-transistor and a second sub-transistor connected in series between the first node and the third node, the first sub-transistor is connected between the second sub-transistor and the first node, and the ion doping concentration of the channel region of the first sub-transistor is greater than the ion doping concentration of the channel region of the second sub-transistor.

[0012] In a second aspect, based on the same inventive concept, the present disclosure provides a driving method for a pixel driving circuit, comprising a third node reset phase, a first node reset phase, and a data writing phase;

[0013] In the third node reset phase, the third node reset module is turned on, and the signal of the first reset signal terminal is transmitted to the third node;

[0014] During the first node reset phase, the third node reset module remains turned on, the first node reset module is turned on, and the signal at the first reset signal terminal is transmitted to the first node through the third node reset module and the first node reset module;

[0015] During the data writing phase, the first node reset module remains turned on, the data writing module is turned on, the signal at the data signal end is transmitted to the second node, and the signal at the first node is threshold compensated by the first node reset module.

[0016] In a third aspect, based on the same inventive concept, the present disclosure further provides a display device, comprising the pixel driving circuit provided in the first aspect.

[0017] The technical solution provided by the embodiments of the present disclosure has the following advantages over the prior art:

[0018] The present disclosure provides a pixel driving circuit and a driving method thereof, and a display device, wherein the pixel driving circuit includes a driving transistor, a data writing module, a third node reset module, and a first node reset module. The third node reset module is located between the first reset signal terminal and the third node, and the first node reset module is located between the first node and the third node. The signal of the third node is reset by the third node reset module, and the signal of the first node is reset by the third node reset module and the first node reset module. Such an arrangement is conducive to reducing leakage paths, thereby stabilizing the voltage of the first node, and further improving the flicker phenomenon of the display panel; at the same time, the first node reset module includes a first sub-transistor and a second sub-transistor, the ion doping concentration of the channel region of the first sub-transistor is greater than the ion doping concentration of the channel region of the second sub-transistor, the threshold voltage of the first sub-transistor is positively biased, and the voltage between the first electrode and the second electrode of the first sub-transistor is reduced, which is conducive to reducing leakage, thereby stabilizing the voltage of the first node, and further improving the flicker phenomenon of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0020] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 FIG2 is a schematic structural diagram of a pixel driving circuit in the prior art;

[0022] Figure 2 FIG2 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0023] Figure 3 FIG2 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present disclosure;

[0024] Figure 4 FIG2 is a structural schematic diagram of the ion doping process of the first sub-transistor provided by an embodiment of the present disclosure;

[0025] Figure 5 FIG2 is another structural schematic diagram of the ion doping process of the first sub-transistor provided by an embodiment of the present disclosure;

[0026] Figure 6 FIG2 is a flow chart of a driving method provided by an embodiment of the present disclosure;

[0027] Figure 7 Shown is the disclosure Figure 2 A driving timing diagram corresponding to the pixel driving circuit in FIG.

[0028] Figure 8 FIG2 is a flow chart of another driving method provided by an embodiment of the present disclosure;

[0029] Figure 9 Shown is the disclosure Figure 3 A driving timing diagram corresponding to the pixel driving circuit in FIG.

[0030] Figure 10 FIG2 is a flow chart of another driving method provided by an embodiment of the present disclosure;

[0031] Figure 11 Shown is a schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0033] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0034] The inventors discovered during research that some display panels are prone to flickering in low-frequency display mode. One of the main reasons for the flickering is that the gate potential of the driving transistor is unstable. Figure 1 The figure shows a schematic diagram of a pixel driving circuit in the prior art. Figure 1 , Figure 1A pixel driving circuit 000' is shown in FIG. , which includes a first transistor M1', a second transistor M2', a third transistor M3', a fourth transistor M4', a fifth transistor M5', a sixth transistor M6', a seventh transistor M7', and a capacitor C'. The third transistor M3' is a driving transistor for providing a driving current to the light-emitting unit D0'. The gate, the first electrode, and the second electrode of the driving transistor are respectively connected to the first node N1', the second node N2', and the third node N3'. The first electrode and the second electrode of the fourth transistor M4' are respectively connected to the first node N1' and the third node N3'. The first electrode and the second electrode of the fifth transistor M5' are respectively connected to the first reset signal terminal Vref1' and the first node N1'. Since the fourth transistor M4' and the fifth transistor M5' have a large leakage current when turned off, they will both leak to the first node N1'. The leakage path is as follows: Figure 1 As shown by the middle arrow, there are two leakage paths. When the frequency decreases, the frame time decreases. Therefore, the position of the first node will change, resulting in a phenomenon of continuous decrease in brightness within the frame, causing the display panel to flicker.

[0035] Therefore, how to solve the above problems has become one of the technical problems that need to be solved urgently at this stage.

[0036] In view of this, the present disclosure provides a pixel driving circuit and a driving method thereof, and a display device, for improving the low-frequency flicker problem of a display panel.

[0037] Figure 2 FIG2 is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure. Figure 2 The present disclosure provides a pixel driving circuit 100, comprising:

[0038] a driving transistor M1 , wherein a gate of the driving transistor M1 is connected to a first node N1 , a first electrode is connected to a second node N2 , and a second electrode is connected to a third node N3 ;

[0039] A data writing module 20 is connected between the data signal terminal Vdata and the second node N2;

[0040] A third node reset module 30 connected between the first reset signal terminal Vref1 and the third node N3;

[0041] A first node reset module 40 is connected between the third node N3 and the first node N1, and the first node reset module 40 is multiplexed as a threshold compensation module;

[0042] In the first node reset phase, the third node reset module 30 and the first node reset module 40 are both turned on; in the data write phase, the data write module 20 and the first node reset module 40 are turned on, and the third node reset module 30 is turned off;

[0043] The first node reset module 40 includes a first sub-transistor M4-1 and a second sub-transistor M4-2 connected in series between the first node N1 and the third node N3, the first sub-transistor M4-1 is connected between the second sub-transistor M4-2 and the first node N1, and the ion doping concentration of the channel region of the first sub-transistor M4-1 is greater than the ion doping concentration of the channel region of the second sub-transistor M4-2.

[0044] Specifically, the present disclosure provides a pixel driving circuit 100, which includes a driving transistor M1, a data writing module 20, a third node reset module 30, and a first node reset module 40. The driving transistor M1 is used to provide a corresponding driving current to the light-emitting module 50, driving the light-emitting module 50 to display different grayscales, thereby allowing the display panel to display the image to be displayed. The driving transistor M1 includes a gate, a first electrode, and a second electrode. The gate of the driving transistor M1 is connected to the first node N1, the first electrode is connected to the second node N2, and the second electrode is connected to the third node N3. The data writing module 20 is connected between the data signal terminal Vdata and the second node N2 and is used to transmit a data voltage to the second node N2, that is, to transmit the data voltage to the first electrode of the driving transistor M1. Optionally, the data writing module 20 includes a second transistor M2, the first electrode and the second electrode of the second transistor M2 being connected to the data signal terminal Vdata and the second node N2, respectively. The third node reset module 30 is connected between the first reset signal terminal Vref1 and the third node N3 and is used to reset the signal at the third node N3, that is, to reset the second electrode of the driving transistor M1. The first node reset module 40 is connected between the third node N3 and the first node N1. On the one hand, it is used to reset the signal of the first node N1, that is, to reset the gate of the driving transistor M1; on the other hand, it is reused as a threshold compensation module to compensate for the threshold voltage of the driving transistor M1.

[0045] The first node reset module 40 includes a first sub-transistor M4-1 and a second sub-transistor M4-2. The first sub-transistor M4-1 and the second sub-transistor M4-2 are connected in series between the first node N1 and the third node N3. The first sub-transistor M4-1 is connected between the first node N1 and the second sub-transistor M4-2. The ion doping concentration of the channel region of the first sub-transistor M4-1 is greater than the ion doping concentration of the channel region of the second sub-transistor M4-2, so that the threshold voltage of the first sub-transistor M4-1 is positively biased, the voltage of the node between the first sub-transistor M4-1 and the second sub-transistor M4-2 decreases, and the voltage between the first electrode and the second electrode of the first sub-transistor M4-1 decreases, which is beneficial to reducing leakage, thereby stabilizing the voltage of the first node N1, and further improving the flicker phenomenon of the display panel.

[0046] In the first node reset stage, the third node reset module 30 and the first node reset module 40 are both turned on, and the signal of the first reset signal terminal Vref1 is transmitted to the first node N1 through the third node reset module 30 and the first node reset module 40, and the gate of the driving transistor M1 connected to the first node N1 is reset, which is conducive to clearing the residual charge of the previous frame image, thereby facilitating the improvement of the display effect of the display panel; at the same time, the signal of the first node N1 is reset by the third node reset module 30 and the first node reset module 40, compared with Figure 1 In the pixel driving circuit 000 provided by the prior art shown, the first node reset module 40 in the present disclosure is reused as a threshold compensation module, and there is no need to separately introduce a first node reset module and a threshold compensation module connected to the first node N1 in the pixel driving circuit. The transistor directly connected to the first node N1 in the present disclosure only includes the first sub-transistor M4-1 in the first node reset module 40, which is equivalent to reducing the number of transistors directly connected to the first node N1, reducing the leakage path, and is beneficial to stabilizing the voltage of the first node N1, thereby helping to improve the flicker phenomenon of the display panel.

[0047] During the data writing phase, the data writing module 20 and the first node reset module 40 are turned on, the third node reset module 30 is turned off, and the signal of the data signal terminal Vdata is written into the driving transistor M1 through the data writing module 20. At the same time, the first node reset module 40 is connected between the first node N1 and the third node N3 (equivalent to the first node reset module 40 being connected between the gate and the second electrode of the driving transistor M1). The first node reset module 40 reuses the threshold compensation module and is turned on during the data writing phase to capture the threshold voltage of the driving transistor M1 to the gate of the driving transistor M1, thereby realizing compensation of the threshold voltage of the driving transistor M1.

[0048] It can be understood that the pixel driving circuit 100 provided by the present disclosure is provided with a third node reset module 30 and a first node reset module 40. The third node reset module 30 is located between the first reset signal terminal Vref1 and the third node N3, and the first node reset module 40 is located between the first node N1 and the third node N3. The signal of the third node N3 is reset by the third node reset module 30, and the signal of the first node N1 is reset by the third node reset module 30 and the first node reset module 40. Such a configuration is conducive to reducing the leakage path, thereby stabilizing the voltage of the first node N1, and thus having It is beneficial to improve the flicker phenomenon of the display panel; at the same time, the first node reset module 40 includes a first sub-transistor M4-1 and a second sub-transistor M4-2. By heavily doping the channel region of the first sub-transistor M4-1, the ion doping concentration of the channel region of the first sub-transistor M4-1 is made greater than the ion doping concentration of the channel region of the second sub-transistor M4-2, so that the threshold voltage of the first sub-transistor M4-1 is positively biased, and the voltage between the first electrode and the second electrode of the first sub-transistor M4-1 is reduced, which is beneficial to reducing leakage, thereby stabilizing the voltage of the first node N1, and is more beneficial to improving the flicker phenomenon of the display panel.

[0049] It should be noted that, in the drawings of this disclosure, Figure 2The illustrated pixel driving circuit 100 further includes a light-emitting control module 60, a second reset module 80, and a storage module 70. Optionally, the light-emitting control module 60 includes a fifth transistor M5 and a sixth transistor M6, the second reset module 80 includes a seventh transistor M7, and the storage module 70 includes a storage capacitor Cst. The first and second electrodes of the fifth transistor M5 in the light-emitting control module 60 are respectively connected to the first power supply signal terminal PVDD and the second node N2. The first and second electrodes of the sixth transistor M6 in the light-emitting control module 60 are respectively connected to the third node N3 and the fourth node N4. The fourth node N4 is connected to the anode of the light-emitting module 50. The gates of the fifth transistor M5 and the sixth transistor M6 are both connected to the light-emitting control signal terminal Emit. The light-emitting control module 60 is configured to control the light-emitting module 50 and is turned on during the light-emitting phase. The first and second electrodes of the seventh transistor M7 in the second reset module 80 are respectively connected to the second reset signal terminal Vref2 and the fourth node N4. The second reset module 80 is configured to reset the anode of the light-emitting module 50. The first plate of the storage capacitor Cst in the storage module 70 is connected to the first electrode of the fifth transistor M5, and the second plate is connected to the first node N1. The storage module 70 can maintain the gate potential of the driving transistor M1 to prevent the gate potential of the driving transistor M1 from being coupled and changing when the first node reset module 40 is turned off. The cathode of the light-emitting module 50 is connected to the second power signal terminal PVEE. It should be noted that in the pixel driving circuit 100 of this embodiment, only the transistors are P-type transistors as an example for description, but the type of transistor is not limited. This disclosure is only based on Figure 2 The pixel driving circuit 100 is shown as an example to illustrate other modules in the pixel driving circuit 100, but is not limited thereto. It should also be noted that the light emitting module 50 includes a light emitting element, which can be an organic light emitting diode or an inorganic light emitting diode, which is not specifically limited in this disclosure.

[0050] Please continue to refer to Figure 2To improve leakage in the first-node reset module 40, the present disclosure sets the threshold voltage of the first sub-transistor M4-1 to a positive bias. This is achieved by heavily doping the channel region of the first sub-transistor M4-1. It should be noted that a higher doping concentration results in more charge in the depletion layer of the channel region when no voltage is applied to the gate. To form a conductive channel, a higher voltage must be applied to the gate to overcome the effect of this charge, thereby increasing the threshold voltage. Optionally, the ion implantation energy of the channel region of the first sub-transistor M4-1 is 5keV to 8keV (inclusive). When the ion implantation energy of the channel region of the first sub-transistor M4-1 is less than 5keV, the ion implantation energy is too low, and the kinetic energy obtained by the ions is weak, causing the ions to be mainly concentrated near the surface of the channel region, with a shallow doping depth and a relatively narrow distribution range. When the ion implantation energy of the channel region of the first sub-transistor M4-1 is greater than 8keV, the ion implantation energy is too high, and the kinetic energy obtained by the ions is strong, causing the ions to penetrate deeper into the semiconductor material. As the implantation depth increases, the collision and scattering of the ions with the semiconductor lattice will increase, causing the distribution of the ions to gradually become dispersed, thereby reducing the doping concentration per unit volume. Therefore, the present disclosure sets the ion implantation energy of the channel region of the first sub-transistor M4-1 to 5keV to 8keV, which is conducive to forming a more suitable ion doping concentration.

[0051] The present disclosure provides an optional embodiment in which the ion implantation energy of the channel region of the first sub-transistor M4-1 is 6keV; the present disclosure provides another optional embodiment in which the ion implantation energy of the channel region of the first sub-transistor M4-1 is 7keV; the present disclosure provides another optional embodiment in which the ion implantation energy of the channel region of the first sub-transistor M4-1 is 5.5keV to 6.5keV (inclusive); the present disclosure provides another optional embodiment in which the ion implantation energy of the channel region of the first sub-transistor M4-1 is 6.2keV to 7.8keV (inclusive). Optionally, the ion doping concentration is 5×10 11 / cm 3 ~1×10 14 / cm 3 When the ion doping concentration of the channel region of the first sub-transistor M4-1 is less than 5×10 11 / cm 3 When the ion doping concentration is too low, the depletion layer is narrow, and it is relatively easy to form a conductive channel, so the threshold voltage is low. In order to avoid the threshold voltage of the first sub-transistor M4-1 being too high, the present disclosure sets the upper limit of the ion doping concentration in the channel region of the first sub-transistor M4-1 to 1×10 14 / cm 3 Therefore, the present disclosure sets the ion doping concentration of the channel region of the first sub-transistor M4-1 to 5×1011 / cm 3 ~1×10 14 / cm 3 Such a setting is beneficial to controlling the threshold voltage within a suitable range, thereby improving the leakage problem of the first node reset module 40, and thus improving the flicker phenomenon of the display panel.

[0052] The present disclosure provides an optional embodiment in which the ion doping concentration of the channel region of the first sub-transistor M4-1 is 6.3×10 12 / cm 3 Another optional embodiment provided by the present disclosure is that the ion doping concentration of the channel region of the first sub-transistor M4-1 is 2.7×10 13 / cm 3 Another optional embodiment provided by the present disclosure is that the ion doping concentration of the channel region of the first sub-transistor M4-1 is 6×10 11 / cm 3 ~8×10 12 / cm 3 Another optional embodiment provided by the present disclosure is that the ion doping concentration of the channel region of the first sub-transistor M4-1 is 5×10 12 / cm 3 ~9×10 13 / cm 3 .

[0053] Please continue to refer to Figure 2 The present disclosure provides an optional implementation in which the ion doping concentration of the channel region of the second sub-transistor M4-2 is the same as the ion doping concentration of the channel regions of other transistors in the pixel driving circuit 100.

[0054] Specifically, the pixel driving circuit 100 provided by the present disclosure includes a first node reset module 40, which is connected between the first node N1 and the third node N3. The first node reset module 40 includes a first sub-transistor M4-1 and a second sub-transistor M4-2. The first sub-transistor M4-1 is located between the first node N1 and the second sub-transistor M4-2. The ion doping concentration of the channel region of the first sub-transistor M4-1 is greater than the ion doping concentration of the channel region of the second sub-transistor M4-2, so that the threshold voltage of the first sub-transistor M4-1 is positively biased, the voltage of the intermediate node between the first sub-transistor M4-1 and the second sub-transistor M4-2 decreases, and the voltage between the first electrode and the second electrode of the first sub-transistor M4-1 is reduced, which is beneficial to reducing leakage, thereby stabilizing the voltage of the first node N1, and further improving the flicker phenomenon of the display panel. In this embodiment, the ion doping concentration of the channel region of the second sub-transistor M4-2 is the same as the ion doping concentration of the channel region of other transistors in the pixel driving circuit 100, that is, the ion doping concentration of the channel region of the first sub-transistor M4-1 is greater than the ion doping concentration of the channel region of other transistors in the pixel driving circuit 100. Such a setting not only improves the leakage problem of the first node reset module 40, but also helps to ensure the normal operation of other transistors and improve the stability of the display panel; and, the ion doping concentration of the channel region of the second sub-transistor M4-2 is the same as the ion doping concentration of the channel region of other transistors in the pixel driving circuit 100, which is conducive to the simultaneous manufacture of the second sub-transistor M4-2 and the other transistors in the pixel driving circuit 100, thereby helping to simplify the manufacturing process.

[0055] Figure 3 FIG2 is a schematic diagram of another pixel driving circuit provided by an embodiment of the present disclosure. Figure 3 The present disclosure provides an optional implementation scheme in which the gate of the first sub-transistor M4-1 is connected to the first control signal terminal SN2-1, and the gate of the second sub-transistor M4-2 is connected to the second control signal terminal SN2-2; the pixel driving circuit 100 includes a light-emitting stage, in which the first sub-transistor M4-1 is turned on and the second sub-transistor M4-2 is turned off.

[0056] Specifically, the first node reset module 40 of the pixel driving circuit 100 provided by the present disclosure includes a first sub-transistor M4-1 and a second sub-transistor M4-2. In this embodiment, the gate of the first sub-transistor M4-1 is connected to the first control signal terminal SN2-1, and the gate of the second sub-transistor M4-2 is connected to the second control signal terminal SN2-2, that is, the first sub-transistor M4-1 and the second sub-transistor M4-2 are independently controlled to be turned on and off. The pixel driving circuit 100 includes a data writing phase and a light emitting phase. The data writing phase precedes the light emitting phase. During the data writing phase, the data writing module 20 and the first node reset module 40 are turned on, that is, the first sub-transistor M4-1, the second sub-transistor M4-2, and the second transistor M2 are turned on simultaneously. The signal at the data signal terminal Vdata is written to the driving transistor M1 through the second transistor M2. At the same time, the first node reset module 40 reuses the threshold compensation module to capture the threshold voltage of the driving transistor M1 and transfer it to the gate of the driving transistor M1, thereby compensating the threshold voltage of the driving transistor M1. During the light-emitting stage, the first sub-transistor M4-1 remains turned on under the control of the first control signal terminal SN2-1, and the second sub-transistor M4-2 is turned off under the control of the second control signal terminal SN2-2. With this arrangement, during the light-emitting stage, the first sub-transistor M4-1 remains in the state of the data writing stage and no signal jump occurs. Therefore, it is beneficial to reduce the impact on the potential of the first node N1, thereby helping to reduce the impact on the driving transistor M1, and further helping to improve the display effect.

[0057] Please refer to Figure 2 The present disclosure provides an optional implementation in which the gates of the first sub-transistor M4-1 and the second sub-transistor M4-2 are connected to the first control signal terminal SN2-1.

[0058] Specifically, the pixel driving circuit 100 provided by the present disclosure includes a first node reset module 40, and the first node reset module 40 includes a first sub-transistor M4-1 and a second sub-transistor M4-2. The gates of the first sub-transistor M4-1 and the second sub-transistor M4-2 are both connected to the first control signal terminal SN2-1, that is, the first control signal terminal SN2-1 is used to simultaneously control the conduction and cutoff of the first sub-transistor M4-1 and the second sub-transistor M4-2. The first sub-transistor M4-1 and the second sub-transistor M4-2 are both turned on in the data writing stage, and the first sub-transistor M4-1 and the second sub-transistor M4-2 are both cut off in the light-emitting stage. Such a setting is conducive to reducing the number of signal terminals and signal lines, thereby simplifying the structure of the display panel, and further simplifying the manufacturing process of the display panel.

[0059] Please refer to Figure 2 and Figure 3In an optional embodiment, the present disclosure provides that the driving transistor M1, the first sub-transistor M4-1 and the second sub-transistor M4-2 are all PMOS transistors, and the ions doped in the channel region of the first sub-transistor M4-1 are phosphorus.

[0060] Specifically, in the pixel driving circuit 100 provided by the present disclosure, the driving transistor M1, the first sub-transistor M4-1 and the second sub-transistor M4-2 are all PMOS tubes. It can be understood that the threshold voltage of the PMOS tube is usually a negative value. Therefore, providing a lower voltage can turn on the PMOS tube, which is beneficial to reducing the power consumption of the pixel driving circuit 100; at the same time, the present disclosure sets the ion doping concentration of the channel region of the first sub-transistor M4-1 to be greater than the doping concentration of the channel region of the second sub-transistor M4-2, and sets the first sub-transistor M4-1 and the second sub-transistor M4-2 to be PMOS tubes. During doping, it is easier to make the threshold voltage of the first sub-transistor M4-1 positively biased, which is beneficial to reducing the production difficulty. In order to improve the leakage problem of the first node reset module 40, the present disclosure performs phosphorus doping on the channel region of the first sub-transistor M4-1, so that the ion doping concentration of the channel region of the first sub-transistor M4-1 is greater than the ion doping concentration of the channel region of the second sub-transistor M4-2, thereby making the threshold voltage of the first sub-transistor M4-1 positively biased. In this embodiment, phosphorus doping is performed on the channel region of the first sub-transistor M4-1, which is conducive to the positive bias of the threshold voltage of the first sub-transistor M4-1, thereby helping to improve the leakage problem of the first node reset module 40.

[0061] It should be noted that, for the manufacturing method in which the ion doping concentration of the channel region of the first sub-transistor M4-1 is greater than the doping concentration of the channel region of the second sub-transistor M4-2, the present disclosure provides an optional implementation method. Figure 4 FIG. 1 is a structural diagram of the ion doping process of the first sub-transistor provided by an embodiment of the present disclosure. Figure 5 FIG. 1 is another structural diagram of the ion doping process of the first sub-transistor provided by the embodiment of the present disclosure, please refer to FIG. Figure 2 、 Figure 4 and Figure 5 First, the polysilicon layer 01 is ion doped as a whole ( Figure 4 The middle arrow indicates ion doping), and the photoresist layer 02 is used to cover the area that does not need to be doped twice, and the channel region of the first sub-transistor M4-1 is doped twice ( Figure 5 The arrow in the middle indicates ion doping), and finally the photoresist layer 02 is removed and the subsequent process is performed. It should be noted that the present disclosure is only described by this example and is not limited thereto.

[0062] Please refer to Figure 2 and Figure 3The present disclosure provides an optional embodiment in which the third node reset module 30 includes a third sub-transistor M3-3 and a fourth sub-transistor M3-4 connected in series between the first reset signal terminal Vref1 and the third node N3, and the gates of the third sub-transistor M3-3 and the fourth sub-transistor M3-4 are connected to the third control signal terminal SN1.

[0063] Specifically, the pixel driving circuit 100 includes a third node reset module 30 connected between the first reset signal terminal Vref1 and the third node N3 for resetting the signal at the third node N3, that is, resetting the second electrode of the driving transistor M1. In this embodiment, the third node reset module 30 includes a third sub-transistor M3-3 and a fourth sub-transistor M3-4. The third sub-transistor M3-3 and the fourth sub-transistor M3-4 are connected in series between the first reset signal terminal Vref1 and the third node N3. That is, the third node reset module 30 uses a dual-gate transistor. The gates of the third sub-transistor M3-3 and the fourth sub-transistor M3-4 are both connected to the third control signal terminal SN1. That is, the third control signal terminal SN1 is used to simultaneously control the conduction and cutoff of the third sub-transistor M3-3 and the fourth sub-transistor M3-4. This configuration helps reduce the number of signal terminals and signal lines, thereby simplifying the structure of the display panel and reducing the difficulty of manufacturing the display panel. At the same time, the use of dual-gate transistors helps increase the ability to control carriers in the channel region, so that when the transistor is in the off state, it can more effectively suppress the flow of carriers, thereby improving leakage problems.

[0064] Based on the same inventive concept, the present disclosure provides a driving method of any pixel driving circuit 100 provided in the embodiments of the present disclosure, Figure 6 FIG. 1 is a flow chart of a driving method provided by an embodiment of the present disclosure. Figure 7 Shown is the disclosure Figure 2 For a driving timing diagram corresponding to the pixel driving circuit in Figure 2 、 Figure 6 and Figure 7 , the driving method includes but is not limited to steps S110 to S130, and the driving method includes a third node reset phase T1, a first node reset phase T2 and a data writing phase T3;

[0065] Step S110: In the third node reset phase T1, the third node reset module 30 is turned on, and the signal of the first reset signal terminal Vref1 is transmitted to the third node N3;

[0066] Step S120: In the first node reset phase T2, the third node reset module 30 remains turned on, the first node reset module 40 is turned on, and the signal of the first reset signal terminal Vref1 is transmitted to the first node N1 through the third node reset module 30 and the first node reset module 40;

[0067] Step S130, in the data writing phase T3, the first node reset module 40 remains turned on, the data writing module 20 is turned on, the signal of the data signal terminal Vdata is transmitted to the second node N2, and the first node reset module 40 performs threshold compensation on the signal of the first node N1.

[0068] Specifically, the present disclosure further provides a driving method for a pixel driving circuit 100, which is used to drive any of the pixel driving circuits 100 provided in the embodiments of the present disclosure. The driving method includes a third node reset module T1, a first node reset phase T2, and a data writing phase T3. During the third node reset phase T1, the signal at the third node N3 is reset, that is, the second electrode of the driving transistor M1 is reset. The third control signal terminal SN1 provides a low-level signal to the third node reset module 30, which turns on and transmits the signal at the first reset signal terminal Vref1 to the third node N3. In the first node reset stage T2, the third control signal terminal SN1 continues to provide a low-level signal to the third node reset module 30, the third node reset module 30 remains turned on, the first control signal terminal SN2-1 provides a low-level signal to the first node reset module 40, the first node reset module 40 is also turned on, and the signal of the first reset signal terminal Vref1 is transmitted to the first node N1 through the third node reset module 30 and the first node reset module 40, resetting the gate of the driving transistor M1 connected to the first node N1, thereby facilitating the clearing of residual charge of the previous frame, and further facilitating the improvement of the display effect of the display panel. In the data writing stage T3, the first control signal terminal SN2-1 continues to provide a low-level signal to the first node reset module 40, the first node reset module 40 remains turned on, the first scan line Scan provides a low-level signal to the data writing module 20, the data writing module 20 is also turned on, the signal of the third control signal terminal SN1 jumps to a high-level signal, the third node reset module 30 is disconnected, and the signal of the data signal terminal Vdata is written into the driving transistor M1 through the data writing module 20. At the same time, the first node reset module 40 reuses the threshold compensation module to capture the threshold voltage of the driving transistor M1 to the gate of the driving transistor M1, thereby realizing compensation of the threshold voltage of the driving transistor M1.

[0069] It can be understood that the driving method of the pixel circuit provided by the present disclosure resets the signal of the third node N3 through the third node reset module 30 in the third node reset stage T1; in the first node reset stage T2, on the basis of the third node reset stage T1, the third node reset module 30 is kept turned on, and then the first node reset module 40 is turned on, thereby resetting the signal of the first node N1; in the data writing stage T3, the first node reset module 40 is kept turned on, the third node reset module 30 is turned off, and the data writing module 20 is turned on, and the signal of the data signal end Vdata is transmitted to the second node N2, and the signal of the first node N1 is threshold compensated through the first node reset module 40 (reused as a threshold compensation module at this time). With this arrangement, the signals of the first node N1, the second node N2 and the third node N3 are all reset, and at the same time, the signal of the first node N1 is threshold compensated, which is beneficial to improving the display effect of the display panel.

[0070] Figure 8 FIG. 1 is a flow chart of another driving method provided by an embodiment of the present disclosure. Figure 9 Shown is the disclosure Figure 3 For a driving timing diagram corresponding to the pixel driving circuit in Figure 3 、 Figure 8 and Figure 9 The present disclosure provides an optional implementation scheme, in which, in the pixel driving circuit 100, the first node reset module 40 includes a first sub-transistor M4-1 and a second sub-transistor M4-2 connected in series between the first node N1 and the third node N3; the gate of the first sub-transistor M4-1 is connected to the first control signal terminal SN2-1, and the gate of the second sub-transistor M4-2 is connected to the second control signal terminal SN2-2.

[0071] The driving method further includes step S140 , a light emitting stage T4 performed after the data writing stage T3 . In the light emitting stage T4 , the first sub-transistor M4 - 1 remains turned on, and the second sub-transistor M4 - 2 is turned off.

[0072] Specifically, in the pixel driving circuit 100, the first node reset module 40 includes a first sub-transistor M4-1 and a second sub-transistor M4-2, which are connected in series between the first node N1 and the third node N3. The first sub-transistor M4-1 is connected between the first node N1 and the second sub-transistor M4-2. The gate of the first sub-transistor M4-1 is connected to the first control signal terminal SN2-1, which controls the conduction and cutoff of the first sub-transistor M4-1. The gate of the second sub-transistor M4-2 is connected to the second control signal terminal SN2-2, which controls the conduction and cutoff of the second sub-transistor M4-2. Optionally, the third node reset module 30 includes a third sub-transistor M3-3 and a fourth sub-transistor M3-4, the data writing module 20 includes a second transistor M2, and the light-emitting module 50 includes a light-emitting diode D0. Optionally, the pixel driving circuit 100 also includes a light-emitting control module 60, a second reset module 80, and a storage module 70. The light emitting control module 60 includes a fifth transistor M5 and a sixth transistor M6, the second reset module 80 includes a seventh transistor M7, and the storage module 70 includes a storage capacitor Cst. It should be noted that in the pixel driving circuit 100 of this embodiment, only each transistor is a P-type transistor as an example for description, but the type of transistor is not limited. Figure 3 The pixel driving circuit 100 shown is used as an example to illustrate other modules in the pixel driving circuit 100 , but the present invention is not limited thereto.

[0073] against Figure 3 The pixel driving circuit 100 shown in the present disclosure provides an optional driving method, which includes a third node reset phase T1, a first node reset phase T2, a data writing phase T3 and a light emitting phase T4. Figure 8 and Figure 9In the third node reset phase T1, the third control signal terminal SN1 provides a low-level signal to the third sub-transistor M3-3 and the fourth sub-transistor M3-4, and the third sub-transistor M3-3 and the fourth sub-transistor M3-4 are turned on. The signal of the first reset signal terminal Vref1 is transmitted to the third node N3 to reset the signal of the third node N3. In the first node reset phase T2, the third control signal terminal SN1 continues to provide a low-level signal to the third sub-transistor M3-3 and the fourth sub-transistor M3-4, and the third sub-transistor M3-3 and the fourth sub-transistor M3-4 are turned on. -4 remains turned on, the first control signal terminal SN2-1 provides a low-level signal to the first sub-transistor M4-1 to control the first sub-transistor M4-1 to be turned on, the second control signal terminal SN2-2 provides a low-level signal to the second sub-transistor M4-2 to control the second sub-transistor M4-2 to be turned on, and the signal of the first reset signal terminal Vref1 is transmitted to the first node N1 to reset the signal of the first node N1; in the data writing phase T3, the third control signal terminal SN1 jumps to a high-level signal, and the third sub-transistor M3-3 and the fourth sub-transistor M3-4 are turned off. , the first control signal terminal SN2-1 provides a low-level signal to the first sub-transistor M4-1, and the first sub-transistor M4-1 remains turned on. The second control signal terminal SN2-2 provides a low-level signal to the second sub-transistor M4-2, and the second sub-transistor M4-2 remains turned on. The first scan line Scan provides a high-level signal to the second transistor M2, and the second transistor M2 is turned on. The signal of the data signal terminal Vdata is transmitted to the second node N2, and the signal of the first node N1 is threshold-compensated through the first sub-transistor M4-1 and the second sub-transistor M4-2. compensation; in the light-emitting stage T4, the first control signal terminal SN2-1 maintains a low-level signal, the first sub-transistor M4-1 remains turned on, the second control signal terminal SN2-2 jumps to a high-level signal, and the second sub-transistor M4-2 is turned off, which is conducive to stabilizing the potential of the first node N1, and the driving transistor M1 is turned on. At the same time, the light-emitting control signal terminal Emit provides a low-level signal to the fifth transistor M5 and the sixth transistor M6, and the fifth transistor M5 and the sixth transistor M6 are both turned on, providing a driving current for the light-emitting module 50, and the light-emitting diode D0 emits light in response to the driving current.

[0074] Figure 10 The figure shows a flow chart of another driving method provided by the embodiment of the present disclosure. Figure 2 、 Figure 7 and Figure 10 The present disclosure provides an optional embodiment in which the first node reset module 40 includes a first sub-transistor M4-1 and a second sub-transistor M4-2 connected in series between the first node N1 and the third node N3; the gate of the first sub-transistor M4-1 and the gate of the second sub-transistor M4-2 are both connected to the first control signal terminal SN2-1;

[0075] The driving method further includes step S150 , a light emitting stage T4 performed after the data writing stage T3 , in which the first sub-transistor M4 - 1 and the second sub-transistor M4 - 2 are both turned off.

[0076] For details, please refer to Figure 2 In the pixel driving circuit 100, the first node reset module 40 includes a first sub-transistor M4-1 and a second sub-transistor M4-2, which are connected in series between the first node N1 and the third node N3. The first sub-transistor M4-1 is connected between the first node N1 and the second sub-transistor M4-2. The gates of the first sub-transistor M4-1 and the second sub-transistor M4-2 are both connected to the first control signal terminal SN2-1, and the conduction and cutoff of the first sub-transistor M4-1 and the second sub-transistor M4-2 are controlled by the first control signal terminal SN2-1. Optionally, the third node reset module 30 includes a third sub-transistor M3-3 and a fourth sub-transistor M3-4, the data writing module 20 includes a second transistor M2, and the light-emitting module 50 includes a light-emitting diode D0. Optionally, the pixel driving circuit 100 also includes a light-emitting control module 60, a second reset module 80, and a storage module 70. The light emitting control module 60 includes a fifth transistor M5 and a sixth transistor M6, the second reset module 80 includes a seventh transistor M7, and the storage module 70 includes a storage capacitor Cst. It should be noted that in the pixel driving circuit 100 of this embodiment, only each transistor is a P-type transistor as an example for description, but the type of transistor is not limited. Figure 2 The pixel driving circuit 100 shown is used as an example to illustrate other modules in the pixel driving circuit 100 , but the present invention is not limited thereto.

[0077] against Figure 2 The pixel driving circuit 100 shown in the present disclosure provides an optional driving method including a third node reset phase T1, a first node reset phase T2, a data writing phase T3 and a light emitting phase T4. Figure 7 and Figure 10In the third node reset phase T1, the third control signal terminal SN1 provides a low-level signal to the third sub-transistor M3-3 and the fourth sub-transistor M3-4, and the third sub-transistor M3-3 and the fourth sub-transistor M3-4 are turned on. The signal of the first reset signal terminal Vref1 is transmitted to the third node N3 to reset the signal of the third node N3. In the first node reset phase T2, the third control signal terminal SN1 continues to provide a low-level signal to the third sub-transistor M3-3 and the fourth sub-transistor M3-4, and the third sub-transistor M3-3 and the fourth sub-transistor M3-4 remain turned on. The first control signal terminal SN2-1 provides a low-level signal to the first sub-transistor M4-1 and the second sub-transistor M4-2, and the first sub-transistor M4-1 and the second sub-transistor M4-2 are turned on. The signal of the first reset signal terminal Vref1 is transmitted to the first node N1 to reset the signal of the first node N1. In the data writing phase T3, the third control signal terminal SN1 jumps to a high-level signal, and the third sub-transistor M3-3 and the fourth sub-transistor M3-4 are turned on. The transistor M3-3 and the fourth sub-transistor M3-4 are turned off, the first control signal terminal SN2-1 continues to provide a low-level signal to the first sub-transistor M4-1 and the second sub-transistor M4-2, the first sub-transistor M4-1 and the second sub-transistor M4-2 remain turned on, the first scan line Scan provides a high-level signal to the second transistor M2, the second transistor M2 is turned on, the signal of the data signal terminal Vdata is transmitted to the second node N2, and the threshold compensation of the signal of the first node N1 is performed through the first sub-transistor M4-1 and the second sub-transistor M4-2; in the light-emitting stage T4, the first control signal terminal SN2-1 jumps to a high-level signal, the first sub-transistor M4-1 and the second sub-transistor M4-2 are turned off, the driving transistor M1 is turned on, and at the same time, the light-emitting control signal terminal Emit provides a low-level signal to the fifth transistor M5 and the sixth transistor M6, the fifth transistor M5 and the sixth transistor M6 are both turned on, providing a driving current to the light-emitting module 50, and the light-emitting diode D0 emits light in response to the driving current.

[0078] Based on the same inventive concept, the present disclosure also provides a display device, Figure 11 FIG2 is a schematic diagram of a display device provided by an embodiment of the present disclosure, please refer to FIG2 Figure 2 、 Figure 3 and Figure 11 , the display device 200 includes any one of the pixel driving circuits 100 provided in the embodiments of the present disclosure.

[0079] It should be noted that the embodiment of the display device 200 provided in the present disclosure can be referred to in the embodiment of the pixel driving circuit 100 described above, and will not be repeated here. The display device 200 provided in the present disclosure can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a touch controller, a laptop computer, a navigation system, or the like.

[0080] It can be seen from the above embodiments that the pixel driving circuit and driving method thereof, and the display device provided by the present disclosure achieve at least the following beneficial effects:

[0081] The present disclosure provides a pixel driving circuit and a driving method thereof, and a display device, wherein the pixel driving circuit includes a driving transistor, a data writing module, a third node reset module, and a first node reset module. The third node reset module is located between the first reset signal terminal and the third node, and the first node reset module is located between the first node and the third node. The signal of the third node is reset by the third node reset module, and the signal of the first node is reset by the third node reset module and the first node reset module. Such an arrangement is conducive to reducing leakage paths, thereby stabilizing the voltage of the first node, and further improving the flicker phenomenon of the display panel; at the same time, the first node reset module includes a first sub-transistor and a second sub-transistor, the ion doping concentration of the channel region of the first sub-transistor is greater than the ion doping concentration of the channel region of the second sub-transistor, the threshold voltage of the first sub-transistor is positively biased, and the voltage between the first electrode and the second electrode of the first sub-transistor is reduced, which is conducive to reducing leakage, thereby stabilizing the voltage of the first node, and further improving the flicker phenomenon of the display panel.

[0082] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0083] The foregoing description is intended only to provide specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but rather to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. A pixel driving circuit, characterized in that: include: a driving transistor, wherein a gate of the driving transistor is connected to the first node, a first electrode is connected to the second node, and a second electrode is connected to the third node; a data writing module connected between the data signal terminal and the second node; A third node reset module connected between the first reset signal terminal and the third node; a first node reset module, connected between the third node and the first node, the first node reset module being reused as a threshold compensation module; In the first node reset phase, the third node reset module and the first node reset module are both turned on; in the data writing phase, the data writing module and the first node reset module are turned on, and the third node reset module is turned off; The first node reset module includes a first sub-transistor and a second sub-transistor connected in series between the first node and the third node, the first sub-transistor is connected between the second sub-transistor and the first node, and the ion doping concentration of the channel region of the first sub-transistor is greater than the ion doping concentration of the channel region of the second sub-transistor.

2. The pixel driving circuit according to claim 1, wherein: The ion implantation energy of the channel region of the first sub-transistor is 5keV to 8keV, and the ion doping concentration is 5×10 11 / cm 3 ~1×10 14 / cm 3 .

3. The pixel driving circuit according to claim 1, wherein: The ion doping concentration of the channel region of the second sub-transistor is the same as the ion doping concentration of the channel regions of other transistors in the pixel driving circuit.

4. The pixel driving circuit according to claim 1, wherein: The gate of the first sub-transistor is connected to the first control signal terminal, and the gate of the second sub-transistor is connected to the second control signal terminal; the pixel driving circuit includes a light-emitting stage, in which the first sub-transistor is turned on and the second sub-transistor is turned off.

5. The pixel driving circuit according to claim 1, wherein: The gates of the first sub-transistor and the second sub-transistor are connected to a first control signal terminal.

6. The pixel driving circuit according to claim 1, wherein: The driving transistor, the first sub-transistor and the second sub-transistor are all PMOS transistors, and the ions doped in the channel region of the first sub-transistor are phosphorus.

7. The pixel driving circuit according to claim 1, wherein: The third node reset module includes a third sub-transistor and a fourth sub-transistor connected in series between the first reset signal terminal and the third node, and gates of the third sub-transistor and the fourth sub-transistor are connected to a third control signal terminal.

8. A driving method for a pixel driving circuit according to any one of claims 1 to 7, characterized in that: It includes a third node reset phase, a first node reset phase and a data writing phase; During the third node reset phase, the third node reset module is turned on, and the signal of the first reset signal terminal is transmitted to the third node; During the first node reset phase, the third node reset module remains turned on, the first node reset module is turned on, and the signal at the first reset signal terminal is transmitted to the first node through the third node reset module and the first node reset module; During the data writing phase, the first node reset module remains turned on, the data writing module is turned on, the signal at the data signal end is transmitted to the second node, and the signal at the first node is threshold compensated by the first node reset module.

9. The driving method according to claim 8, wherein: The first node reset module includes a first sub-transistor and a second sub-transistor connected in series between the first node and the third node; the gate of the first sub-transistor is connected to the first control signal terminal, and the gate of the second sub-transistor is connected to the second control signal terminal; The driving method further includes a light emitting phase performed after the data writing phase, in which the first sub-transistor remains turned on and the second sub-transistor is turned off.

10. The driving method according to claim 8, wherein: The first node reset module includes a first sub-transistor and a second sub-transistor connected in series between the first node and the third node; the gate of the first sub-transistor and the gate of the second sub-transistor are both connected to the first control signal terminal; The driving method further includes a light emitting stage performed after the data writing stage, in which the first sub-transistor and the second sub-transistor are both turned off.

11. A display device, characterized in that: The pixel driving circuit comprises the pixel driving circuit according to any one of claims 1 to 7.

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