Metal-insulator-metal capacitors and their formation methods

Abstract

The present invention provides a metal-insulator-metal capacitor and a method for forming the same, and belongs to the technical field of semiconductor device manufacturing. The formation method comprises: providing a substrate; forming a first conductive material layer on the substrate; forming an insulating material layer on the first conductive material layer; wet etching a portion of the insulating material layer and the first conductive material layer to form a bottom electrode layer and an insulating layer on the substrate; forming a second conductive material layer on the substrate and the insulating layer; wet etching a portion of the second conductive material layer so that the remaining second conductive material layer forms a top electrode layer on the insulating layer. The present invention avoids introducing redeposition defects on the sidewalls of the MIM capacitor, and introduces a pattern load effect on the surface of the MIM capacitor, thereby effectively ensuring the capacitance density and structural reliability of the MIM capacitor.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a metal-insulator-metal capacitor and a forming method thereof. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, integrated circuits have increased the density of semiconductor components in a given area by reducing the size of semiconductor components. Although this has effectively improved the operating speed of the entire integrated circuit, it has also made the noise interference between components in the integrated circuit increasingly serious.

[0003] Therefore, metal-insulator-metal capacitor (MIM) is introduced into the integrated circuit as a filter to filter and shield external noise interference to meet the design requirements of the integrated circuit. At present, in the existing process of forming MIM capacitors, a conductive material layer on the insulating layer is usually etched to form a top electrode layer that clamps the insulating layer relative to the bottom electrode layer. However, due to the defect that the existing etching process is difficult to control the etching speed, the MIM capacitor formed by etching is prone to introduce capacitor structure defects due to insufficient or excessive etching, and when the existing process forms multiple MIM capacitors of different area sizes on the substrate at one time, it is easy to introduce a pattern load effect on the formation of the MIM capacitor, thereby affecting the capacitance density and reliability of the formed capacitor device.

[0004] Therefore, it is necessary to design a metal-insulator-metal capacitor and a method for forming the same to solve the above problems. Summary of the invention

[0005] In view of the above shortcomings of the prior art, the present invention provides a metal-insulator-metal capacitor and a method for forming the same, so as to improve the technical problem that structural defects are easily introduced when forming a MIM capacitor structure in the existing process, thereby causing a loss of capacitance density and reliability.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for forming a metal-insulator-metal capacitor, the method comprising:

[0007] providing a substrate;

[0008] forming a first conductive material layer on the substrate;

[0009] forming an insulating material layer on the first conductive material layer;

[0010] Wet etching a portion of the insulating material layer and the first conductive material layer to form a bottom electrode layer and an insulating layer on the substrate;

[0011] forming a second conductive material layer on the substrate and the insulating layer;

[0012] A portion of the second conductive material layer is wet-etched so that the remaining second conductive material layer forms a top electrode layer on the insulating layer.

[0013] The present invention also provides a conductive connection structure, which includes a substrate, a bottom electrode layer, an insulating layer and a top electrode layer. The bottom electrode layer is arranged on the substrate; the insulating layer is arranged on the bottom electrode layer; the top electrode layer is arranged on the insulating layer; along the direction perpendicular to the surface of the substrate, the projection of the top electrode layer on the substrate is located within the projection of the insulating layer on the substrate, and the projection of the insulating layer on the substrate is covered by the projection of the bottom electrode layer on the substrate; in each direction parallel to the surface of the substrate, the height of the outer edge of the bottom electrode layer is less than or equal to the height of the outer edge of the insulating layer.

[0014] In summary, the above-mentioned metal-insulator-metal capacitor and its formation method, through a wet etching process, etches a bottom electrode layer and an insulating layer on a substrate, and etches a top electrode layer on the insulating layer. During the etching process, the mask is matched and the etching time is controlled to maintain the consistency of etching in the height direction and the horizontal direction, so as to avoid the introduction of redeposition defects on the sidewalls of the MIM capacitor and the introduction of pattern loading effects on the surface of the MIM capacitor, thereby effectively ensuring the capacitance density and structural reliability of the MIM capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A schematic diagram of a structure of a MIM capacitor formed by an existing process;

[0017] Figure 2 Another schematic diagram of the structure of a MIM capacitor formed by an existing process;

[0018] Figure 3 Schematic diagram of a process for forming a MIM capacitor according to an embodiment of the present invention;

[0019] Figures 4 to 6 It is a schematic diagram of sequentially forming a first conductive material layer and an insulating material layer on a substrate in one embodiment of the present invention;

[0020] Figure 7This is a flow chart of step S4 in one embodiment of the present invention;

[0021] Figure 8 is a schematic diagram of forming a first mask layer on an insulating material layer in one embodiment of the present invention;

[0022] Fig. 9 It is a schematic diagram of wet etching a portion of the insulating material layer and the first conductive material layer to form a bottom electrode layer and an insulating layer in one embodiment of the present invention;

[0023] Fig.10 It is a schematic diagram of forming a second conductive material layer on a substrate and an insulating layer in one embodiment of the present invention;

[0024] Fig.11 It is a schematic diagram of forming a silicon oxide material layer on the second conductive material layer in one embodiment of the present invention;

[0025] Fig.12 This is a flow chart of step S6 in one embodiment of the present invention;

[0026] Fig.13 It is a schematic diagram of forming a second mask layer on the second conductive material layer in one embodiment of the present invention;

[0027] Fig.14 It is a schematic diagram of removing a portion of the second conductive material layer by wet etching to form a top electrode layer in one embodiment of the present invention;

[0028] Figure 15 to Figure 16 It is a schematic diagram of forming a covering layer on the surfaces of a substrate, a bottom electrode layer, an insulating layer and a top electrode layer in one embodiment of the present invention;

[0029] Figure 17 to Figure 18 It is a schematic diagram of forming a first conductive structure and a second conductive structure above a MIM capacitor according to an embodiment of the present invention;

[0030] Fig.19 FIG. 4 is a schematic diagram of a MIM capacitor cascaded between a first conductive layer and a second conductive layer in one embodiment of the present invention.

[0031] Component number description

[0032] 100, substrate; 110, first conductive layer; 200, first conductive material layer; 210, bottom electrode layer; 300, insulating material layer; 310, insulating layer; 400, first mask layer; 500, second conductive material layer; 510, top electrode layer; 600, silicon oxide material layer; 610, silicon oxide layer; 700, second mask layer; 800, covering layer; 810, silicon material layer; 820, silicon nitride material layer; 900, interlayer dielectric layer; 910, first through hole; 911, first conductive structure; 920, second through hole; 921, second conductive structure; 930, third through hole; 931, third conductive structure; 940, second conductive layer. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0035] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0036] See also Figure 1 and Figure 2 At present, in the existing process of preparing MIM capacitor structure, a dry etching process is usually used to sequentially etch the bottom electrode layer 210, the insulating layer 310 and the top electrode layer 510 on the substrate 100. However, the inventors have found that the etching rate of the dry etching process is difficult to accurately control when etching small-sized structures, and it is easy to introduce structural defects when preparing MIM capacitors, resulting in the loss of capacitance density and reliability performance of MIM capacitors. For example, Figure 1As shown, when dry etching etches the conductive material film layer covering the substrate 100, the bottom electrode layer 210 and the insulating layer 310 to form the top electrode layer 510, redeposition may occur on the sidewall of the MIM capacitor due to insufficient etching. The above defects may change the thickness of the insulating layer 310 relatively covered between the bottom electrode layer 210 and the top electrode layer 510 in the capacitor, causing the capacitance density of the capacitor to decrease or introducing additional parasitic capacitance, thereby affecting the capacitance density and reliability performance of the formed MIM capacitor. Figure 2 As shown, when MIM capacitor structures of different area sizes are formed on the substrate 100 by dry etching, the pattern load effect is introduced on the formed MIM capacitor due to the non-uniformity of the dry etching rate when etching different areas or different pattern densities (for example, the etching rate is low when etching a large area film layer, and the etching rate is high when etching a small area film layer), thereby affecting the capacitance density and reliability performance of the formed MIM capacitor.

[0037] To improve the above problems, the present invention provides a metal-insulator-metal capacitor and a method for forming the same, wherein a first conductive material layer 200 and an insulating material layer 300 are etched by a wet etching process to form a bottom electrode layer 210 and an insulating layer 310 on a substrate 100, and the second conductive material on the substrate 100 and the insulating layer 310 is further etched by a wet etching process to form a top electrode layer 510 on the insulating layer 310. The above method utilizes the consistency of the wet etching rate in the height direction, and through mask matching and etching time control, can effectively avoid introducing structural defects on the outer edges of each film layer forming the MIM capacitor during the etching process, thereby ensuring the consistency of the outer diameter dimensions of the bottom electrode layer 210 and the insulating layer 310 (that is, in all directions parallel to the surface of the substrate 100, the maximum edge outer diameter of the insulating layer 310 is less than or equal to the minimum edge outer diameter of the bottom electrode layer 210), and ensuring that insufficient or excessive etching defects are not introduced on the outer edge of the junction between the top electrode layer 510 and the insulating layer 310; and, when multiple MIM capacitor structures are formed at the same time, no pattern load effect will be introduced on the formed MIM capacitor due to the different etching areas in different regions, thereby effectively ensuring the capacitance density and structural reliability of the formed MIM capacitor.

[0038] See also Figures 3 to 13 , Figures 3 to 13 Schematic diagram of the process and structure corresponding to each step of the method for forming a MIM capacitor in some embodiments.

[0039] See also Figure 3 In one aspect, the present invention provides a method for forming a MIM capacitor. In some embodiments, the method for forming a MIM capacitor comprises the following steps:

[0040] S1, providing a substrate 100; (see Figure 4 )

[0041] S2, forming a first conductive material layer 200 on the substrate 100; (see Figure 5 )

[0042] S3, forming an insulating material layer 300 on the first conductive material layer 200; (see Figure 6 )

[0043] S4, wet-etching a portion of the insulating material layer 300 and the first conductive material layer 200 to form a bottom electrode layer 210 and an insulating layer 310 on the substrate 100; (see Fig. 9 )

[0044] S5, forming a second conductive material layer 500 on the substrate 100 and the insulating layer 310; (see Fig.10 )

[0045] S6, wet-etching a portion of the second conductive material layer 500, so that the remaining second conductive material layer 500 forms a top electrode layer 510 on the insulating layer 310. (See Fig.14 )

[0046] Combine the following Figures 3 to 14 The steps of the method for preparing the conductive connection structure in the embodiment of the present invention are described in detail.

[0047] like Figure 4 As shown, in some embodiments, in step S1, the provided substrate 100 can be any material that meets the requirements of the integrated circuit substrate. As an example, the substrate 100 can include any one or more combinations of semiconductor materials and insulating materials. When the substrate 100 is made of semiconductor materials, for example, single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or other III / V compound semiconductors can be selected. In addition to the semiconductor materials listed above, the substrate 100 can also be Si / SiGe, Si / SiC, silicon on insulator (SOI), germanium on insulator (GOI) or silicon germanium on insulator (SGOI), etc. When the substrate 100 is made of insulating material, the insulating material can be an organic insulator, an inorganic insulator or a combination thereof. This application is described in detail by taking the substrate 100 as an insulating substrate as an example.

[0048] like Figure 5As shown, in some embodiments, in step S2, a first conductive material layer 200 is formed on the surface of the substrate 100, and the first conductive material covers the surface of the substrate 100. Specifically, the first conductive material layer 200 can be formed on the substrate 100 by conventional deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or conventional sputtering processes.

[0049] Among them, the material of the first conductive material layer 200 can be selected from metal, alloy, metal silicide, metal nitride or a combination thereof, the metal can be selected from one of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru), tantalum (Ta), and titanium (Ti), the alloy can be selected from any two or more combinations of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru), tantalum (Ta), and titanium (Ti), the metal silicide can be selected from one or more of titanium silicide (TiSi2), cobalt silicide (CoSi2), and nickel silicide (NiSi), and the metal nitride can be selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (TiN), and zirconium nitride (ZrN). Optionally, in some embodiments, the material of the first conductive material layer 200 is selected from metal nitride, for example, in one example, the material of the first conductive material layer 200 is selected from TiN.

[0050] like Figure 6 As shown, in some embodiments, in step S3, an insulating material layer 300 is formed on the first conductive material layer 200, and the insulating material layer 300 covers the surface of the first conductive material layer 200. Specifically, the insulating material layer 300 can be formed on the first conductive material layer 200 by CVD, PVD, PECVD, ALD or thermal oxidation process. Among them, the material of the insulating material layer 300 is an insulating material with a high dielectric constant. In one example, the insulating material layer 300 is an insulating material with a relative dielectric constant of any value in the range of 4 to 400. For example, the insulating material can be silicon nitride (SiN), silicon oxynitride (SiO x N y ), zirconium oxide (ZrO2), hafnium zirconium oxide (ZrSiO2), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxide (HfSiNO), titanium oxide (Ti x O y), Tantalum Oxide (Ta x O y ), titanium oxynitride (Ti x O y N z ) or titanium oxynitride (Ti x O y N z ), where x, y, and z are all real numbers.

[0051] like Figures 7 to 9 As shown, in step S4, a portion of the insulating material layer 300 and the first conductive material layer 200 on the substrate 100 are removed by a wet etching process to form a bottom electrode layer 210 and an insulating layer 310 on the substrate 100. The bottom electrode layer 210 is formed on the surface of the substrate 100, and the insulating layer 310 is formed on the surface of the bottom electrode layer 210. Since the wet etching rate is consistent in the height direction, the wet etching rate of removing the insulating material layer 300 and the first conductive material layer 200 in different regions along the height direction can be kept consistent, so that the outer edges of the bottom electrode layer 210 and the insulating layer 310 formed by etching have continuity. In the direction perpendicular to the surface of the substrate 100, the projection of the insulating layer 310 formed in step S4 on the surface of the substrate 100 is covered by the projection of the bottom electrode layer 210 on the surface of the substrate 100, which is manifested as the projection of the insulating layer 310 on the surface of the substrate 100 completely overlaps with the projection of the bottom electrode layer 210 on the surface of the substrate 100, or is located within the projection of the bottom electrode layer 210 on the surface of the substrate 100, that is, in each direction parallel to the surface of the substrate 100, the outer diameter of the edge of the insulating layer 310 is less than or equal to the outer diameter of the edge of the bottom electrode layer 210. Among them, the outer diameters of the insulating layer 310 and the bottom electrode layer 210 at the junction are equal; while at other height positions, the outer diameters of the edges of the insulating layer 310 in the directions parallel to the surface of the substrate 100 are less than the smallest outer diameter of the edge of the bottom electrode layer 210. The wet etching in step S4 can effectively avoid the introduction of structural defects on the outer edges of the formed bottom electrode layer 210 and the insulating layer 310.

[0052] Specifically, Figure 7 As shown, in some embodiments, step S4 includes the following steps:

[0053] S41, forming a first mask layer 400 on the insulating material layer 300;

[0054] like Figure 8 As shown, in step S41, a photoresist is coated on the surface of the insulating material layer 300 to form a photoresist layer, and the photoresist layer covers the surface of the insulating material layer 300; the photoresist layer is exposed and developed to pattern the photoresist layer according to design requirements, a portion of the photoresist layer is removed, and the remaining photoresist layer forms a first mask layer 400 on the insulating layer 310.

[0055] S42 , wet-etching the insulating material layer 300 and the first conductive material layer 200 along the first mask layer 400 to form a bottom electrode layer 210 and an insulating layer 310 on the substrate 100 .

[0056] like Figures 8 to 9 As shown, in step S42, the insulating material layer 300 and the first conductive material layer 200 are removed from the periphery of the first mask layer 400 by a wet etching process using the first mask layer 400 as a mask, for example, the insulating material layer 300 and the first conductive material layer 200 are removed from the periphery of the first mask layer 400 by selective wet etching without etching and damaging the substrate 100; after etching, the first mask layer 400 made of photoresist is removed by a conventional ashing or stripping process to retain the bottom electrode layer 210 and the insulating layer 310 formed by etching on the substrate 100. Due to the non-directionality of wet etching, the outer edges of the bottom electrode layer 210 and the insulating layer 310 formed by wet etching have continuity, and structural defects will not be introduced on the outer edges of the bottom electrode layer 210 and the insulating layer 310 due to insufficient or excessive etching.

[0057] like Fig.10 As shown, in some embodiments, in step S5, a second conductive material layer 500 is formed on the insulating layer 310 and the substrate 100 not covered by the bottom electrode layer 210 and the insulating layer 310, and the second conductive material layer 500 covers the exposed surface of the substrate 100, the sidewall surface of the bottom electrode layer 210, and the sidewall and top surface of the insulating layer 310. In step S5, the second conductive material layer 500 can be formed on the substrate 100 by conventional deposition processes such as CVD, PVD, PECVD, ALD, or conventional sputtering processes.

[0058] Among them, the material of the second conductive material layer 500 can be selected from metal, alloy, metal silicide, metal nitride or a combination thereof, the metal can be selected from one of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru), tantalum (Ta), and titanium (Ti), the alloy can be selected from any two or more combinations of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru), tantalum (Ta), and titanium (Ti), the metal silicide can be selected from one or more of titanium silicide (TiSi2), cobalt silicide (CoSi2), and nickel silicide (NiSi), and the metal nitride can be selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (TiN), and zirconium nitride (ZrN). Optionally, in some embodiments, the material of the second conductive material layer 500 is selected from metal nitride, for example, in one example, the material of the second conductive material layer 500 is selected from TiN.

[0059] like Figure 12 to Figure 14As shown, in step S6, the second conductive material layer 500 on the substrate 100 and a portion of the second conductive material layer 500 on the insulating layer 310 are removed by a wet etching process, thereby forming a top electrode layer 510 on the insulating layer 310, and the top electrode layer 510 and the bottom electrode layer 210 clamp the insulating layer 310 relative to each other to form a MIM capacitor. Among them, since wet etching has no directionality, wet etching can selectively remove the second conductive material layer 500 on the surface of the substrate 100, the bottom electrode layer 210 and the insulating layer 310. The wet etching process can completely remove the second conductive material layer 500 on the outer edge surface of the insulating layer 310 while removing the second conductive material layer 500 in the preset area on the surface of the substrate 100 and the insulating layer 310 in the height direction, so as to avoid the second conductive material layer 500 deposited on the outer edge of the bottom electrode layer 210 from spreading to the outer edge surface of the insulating layer 310 due to insufficient etching, and effectively prevent the redeposition defect at the side wall of the MIM capacitor.

[0060] Specifically, after wet etching, along the direction perpendicular to the substrate 100, the projection of the top electrode layer 510 formed by etching on the substrate 100 is located within the projection of the insulating layer 310 on the substrate 100, that is, in all directions parallel to the surface of the substrate 100, the outer diameter of the edge of the top electrode layer 510 is smaller than the outer diameter of the edge of the insulating layer 310. In addition, for the etching of the second conductive material layer 500 on the substrate 100, it can be ensured that the projection of the insulating layer 310 formed by etching on the substrate 100 is covered by the projection of the bottom electrode layer 210 on the substrate 100, that is, the side walls of the insulating layer 310 and the bottom electrode layer 210 are in a smooth and continuous slope shape. Among them, in all directions parallel to the surface of the substrate 100, the outer diameter size of the junction of the insulating layer 310 and the bottom electrode layer 210 is equal, the outer diameter of the edge of the insulating layer 310 at other height positions is smaller than the minimum outer diameter of the bottom electrode layer 210, and the outer edge height of the bottom electrode layer 210 is less than or equal to the outer edge height of the insulating layer 310. It can be seen that the wet etching process in step S6 can avoid introducing over-etching recesses or redeposition defects at the outer edge of the bottom electrode layer 210 .

[0061] At the same time, since the wet etching rate is consistent in the height direction, when multiple MIM capacitor structures are formed at the same time, no pattern load effect will be introduced on the formed MIM capacitor due to different etching areas, thereby effectively ensuring the capacitance density and structural reliability of the formed MIM capacitor.

[0062] Specifically, Fig.12 As shown, in some embodiments, step S6 includes the following steps:

[0063] S61, forming a second mask layer 700 on the second conductive material layer 500, wherein the second mask layer 700 is located above the insulating layer 310;

[0064] like Fig.13 As shown, specifically, a photoresist is coated on the surface of the second conductive material layer 500 to form a photoresist layer, and the photoresist layer covers the surface of the second conductive material layer 500; the photoresist layer is exposed and developed to pattern the photoresist layer according to design requirements, and the photoresist layer located above the substrate 100 and partially located above the insulating layer 310 is removed, and the remaining photoresist layer forms a second mask layer 700 above the insulating layer 310. In the direction perpendicular to the substrate 100, the projection of the second mask layer 700 on the substrate 100 is located within the projection of the insulating layer 310 on the substrate 100.

[0065] S62 , wet-etching the second conductive material layer 500 along the second mask layer 700 , so that the remaining second conductive material layer 500 forms a top electrode layer 510 on the insulating layer 310 .

[0066] like Fig.13 and Fig.14 As shown, in step S62, the second mask layer 700 is used as a mask, and a wet etching process is adopted to remove the second conductive material layer 500 outside the second mask layer 700. For example, selective wet etching is adopted to remove the second conductive material layer 500 located outside the second mask layer 700 without etching and damaging the insulating layer 310. After etching, a conventional ashing or stripping process is adopted to remove the second mask layer 700 made of photoresist material to retain the top electrode layer 510 formed by etching on the insulating layer 310.

[0067] like Figure 15 to Figure 16 As shown, in some embodiments, the method for forming the MIM capacitor further includes forming a covering layer 800 on the surfaces of the substrate 100, the bottom electrode layer 210, the insulating layer 310 and the top electrode layer 510. Specifically, as Fig.15 As shown, a silicon material layer 810 is first formed on the surfaces of the substrate 100, the bottom electrode layer 210, the insulating layer 310 and the top electrode layer 510. For example, any suitable deposition process such as CVD, PVD, PECVD, ALD, etc. can be used to form the silicon material layer 810 on the exposed surfaces of the substrate 100, the bottom electrode layer 210, the insulating layer 310 and the top electrode layer 510. Then, as shown in FIG. Fig.16 As shown, chemical vapor deposition or nitrogen ion implantation is performed on the silicon material layer 810 to form a silicon nitride material layer 820 on the surface of the silicon material layer 810, so that the silicon material layer 810 is transformed into a silicon nitride material, thereby completing the formation of the covering layer 800. In addition to covering the MIM capacitor body, the covering layer 800 located on the substrate 100 can achieve better electrical isolation and thermal stability between different MIM capacitors, thereby further improving the reliability of the MIM capacitor.

[0068] Furthermore, in some embodiments, Fig.12 As shown, after step S5, a silicon oxide material layer 600 is formed on the second conductive material layer 500, wherein the silicon oxide material layer 600 can be formed by any suitable deposition process such as CVD, PVD, PECVD, ALD, etc. For example, the silicon oxide material layer 600 is deposited on the second conductive material layer 500 by CVD, specifically, tetraethoxysilane (TEOS) and ozone (O3) are filled, and tetraethoxysilane (TEOS) and ozone (O3) are used as precursor materials to form the silicon oxide material layer 600 by thermal reaction on the second conductive material layer 500. Figure 13 to Figure 14 As shown, in step S6, in the process of wet etching the second conductive material layer 500 to form the top electrode layer 510, the silicon oxide material layer 600 located at the periphery of the second mask layer 700 is etched away together with the second conductive material layer 500, while the silicon oxide material layer 600 located under the second mask layer 700 is retained, thereby forming a silicon oxide layer 610 on the top electrode layer 510. Fig.15 and Fig.16 As shown, the silicon oxide layer 610 remaining on the top electrode layer 510 can serve as a protective layer for the top electrode layer 510 to prevent the precursor material of the subsequent deposition process of the cover layer 800 from reacting with the top electrode layer 510. It can be understood by those skilled in the art that the silicon oxide material layer 600 may not be provided if the above-mentioned beneficial effects of the silicon oxide material layer 600 are not considered.

[0069] like Figure 17 to Figure 18 As shown, in some embodiments, the method for forming the MIM capacitor further includes forming a first conductive structure 911 on the bottom electrode layer 210 and forming a second conductive structure 921 on the top electrode layer 510; wherein the first conductive structure 911 is located above the bottom electrode layer 210, the second conductive structure 921 is located above the top electrode layer 510, and the first conductive structure 911 and the second conductive structure 921 are insulated and isolated from each other. Specifically, as Fig.17As shown, an interlayer dielectric layer 900 is formed on the substrate 100, the insulating layer 310 and the top electrode layer 510 by conventional deposition or sputtering processes. For example, in one example, the interlayer dielectric layer 900 is formed on the cover layer 800, wherein the interlayer dielectric layer 900 can be made of insulating materials such as silicon oxide (SiO2), silicon nitride (SiN), hydrogen silsesquioxane polymer (HSQ), methane silsesquioxane polymer (MSQ), methyl silicate compounds, carbon-doped oxides, etc.; A first through hole 910 and a second through hole 920 are formed on the interlayer dielectric layer 900 by conventional photolithography. The first through hole 910 is located above the bottom electrode layer 210 and penetrates the interlayer dielectric layer 900, the cover layer 800 and the insulating layer 310 to expose a portion of the surface of the bottom electrode layer 210. The second through hole 920 is located above the top electrode layer 510 and penetrates the interlayer dielectric layer 900 and the cover layer 800 to expose a portion of the surface of the top electrode layer 510. Then, as shown in FIG. Fig.18 As shown, a diffusion barrier layer, a seed layer and a metal layer are sequentially formed in the first through hole 910 and the second through hole 920 by a conventional deposition process, so that a first conductive structure 911 is filled in the first through hole 910 and a second conductive structure 921 is filled in the second through hole 920.

[0070] See also Fig.14 In another aspect, the present invention provides a metal-insulator-metal capacitor, which is prepared by the formation method described above. The MIM capacitor includes a substrate 100, a bottom electrode layer 210, an insulating layer 310 and a top electrode layer 510.

[0071] The substrate 100 can be any material that meets the requirements of the integrated circuit substrate. As an example, the substrate 100 can include any one or more combinations of semiconductor materials and insulating materials. When the substrate 100 is made of semiconductor materials, for example, single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or other III / V compound semiconductors can be selected. In addition to the semiconductor materials listed above, the substrate 100 can also be Si / SiGe, Si / SiC, silicon on insulator (SOI), germanium on insulator (GOI) or silicon germanium on insulator (SGOI), etc. When the substrate 100 is made of insulating material, the insulating material can be an organic insulator, an inorganic insulator or a combination thereof. This application is described in detail by taking the substrate 100 as an insulating substrate as an example, for example, the material of the substrate 100 is SiO2.

[0072] The bottom electrode layer 210 is disposed on the substrate 100, the insulating layer 310 is disposed on the bottom electrode layer 210, and the top electrode layer 510 is disposed on the insulating layer 310. Along the direction perpendicular to the substrate 100, the projection of the top electrode layer 510 on the substrate 100 is located within the projection of the insulating layer 310 on the substrate 100, and the projection of the insulating layer 310 on the substrate 100 is covered by the projection of the bottom electrode layer 210 on the substrate 100, that is, the projection of the insulating layer 310 on the substrate 100 overlaps with the projection of the bottom electrode layer 210 on the substrate 100, or is located within the projection of the bottom electrode layer 210 on the substrate 100. The above is specifically manifested as follows: in each direction parallel to the surface of the substrate 100, the edge outer diameter of the top electrode layer 510 is smaller than the edge outer diameter of the insulating layer 310, so that there is enough area on the insulating layer 310 that is not covered by the top electrode layer 510, so as to set the conductive structure of the bottom electrode layer 210 connecting the upper layer; and in each direction parallel to the surface of the substrate 100, the edge outer diameter of the insulating layer 310 is less than or equal to the edge outer diameter of the bottom electrode layer 210, the outer edge height of the bottom electrode layer 210 is less than or equal to the outer edge height of the insulating layer 310, and the outer edges of the insulating layer 310 and the bottom electrode layer 210 are smooth and continuous at the junction and present a slope shape. On the substrate 100, the top electrode layer 510 and the bottom electrode layer 210 relatively clamp the insulating layer 310 to form a MIM capacitor. Since the outer edge of the bottom electrode layer 210 will not spread to the outside of the outer edge of the insulating layer 310, it is avoided to introduce redeposition defects on the side wall of the MIM capacitor.

[0073] Among them, the top electrode layer 510 and the bottom electrode layer 210 are made of conductive materials, for example, metals, alloys, metal silicides, metal nitrides or combinations thereof. The metal can be selected from one of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru), tantalum (Ta), and titanium (Ti). The alloy can be selected from any two or more of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru), tantalum (Ta), and titanium (Ti). The metal silicide can be selected from one or more of titanium silicide (TiSi2), cobalt silicide (CoSi2), and nickel silicide (NiSi). The metal nitride can be selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (TiN), and zirconium nitride (ZrN). Optionally, in some embodiments, the material of the top electrode layer 510 and the bottom electrode layer 210 is metal nitride. For example, in one example, the material of the top electrode layer 510 and the bottom electrode layer 210 is TiN.

[0074] The insulating layer 310 may be made of silicon nitride (SiN), silicon oxynitride (SiO x N y), zirconium oxide (ZrO2), hafnium zirconium oxide (ZrSiO2), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxide (HfSiNO), titanium oxide (Ti x O y ), Tantalum Oxide (Ta x O y ), titanium oxynitride (Ti x O y N z ) or titanium oxynitride (Ti x O y N z ), where x, y, and z are all real numbers.

[0075] like Fig.15 and Fig.16 As shown, in some embodiments, the MIM capacitor also includes a covering layer 800, which covers the exposed surfaces of the substrate 100, the bottom electrode layer 210, the insulating layer 310 and the top electrode layer 510. The covering layer 800 can achieve better electrical isolation and thermal stability between different MIM capacitors, thereby further improving the reliability of the MIM capacitor. The covering layer 800 is made of an insulating material or a combination of a semiconductor material and an insulating material. The insulating material can be silicon oxide (SiO2), silicon nitride (SiN), hydrogen silsesquioxane polymer (HSQ), methane silsesquioxane polymer (MSQ), methyl silicate compound or carbon-doped oxide. Optionally, in an example, the covering layer 800 includes a silicon material layer 810 and a silicon nitride material layer 820, the silicon material layer 810 covers the exposed surfaces of the substrate 100, the bottom electrode layer 210, the insulating layer 310 and the top electrode layer 510, and the silicon nitride material layer 820 is located on the silicon material layer 810.

[0076] like Fig.16 As shown, in some embodiments, a silicon oxide layer 610 is disposed on the top electrode layer 510, and the silicon oxide layer 610 is located between the top electrode layer 510 and the covering layer 800. The silicon oxide layer 610 located on the top electrode layer 510 can serve as a protective layer for the top electrode layer 510 to prevent the precursor material of the deposition process of the covering layer 800 from reacting with the top electrode layer 510.

[0077] like Fig.18As shown, in some embodiments, a first conductive structure 911 is provided on the bottom electrode layer 210, and a second conductive structure 921 is provided on the top electrode layer 510, and the first conductive structure 911 and the second conductive structure 921 are insulated and isolated from each other. Specifically, an interlayer dielectric layer 900 is provided above the MIM capacitor, and the interlayer dielectric layer 900 is located above the substrate 100, the insulating layer 310 and the top electrode layer 510, and a first through hole 910 and a second through hole 920 are provided on the interlayer dielectric layer 900. The first through hole 910 is located above the bottom electrode layer 210, and the first through hole 910 penetrates the interlayer dielectric layer 900, the cover layer 800 and the insulating layer 310 to expose a portion of the surface of the bottom electrode layer 210, and the first through hole 910 is filled with the first conductive structure 911, and the bottom of the first conductive structure 911 is conductively connected to the bottom electrode layer 210. The second through hole 920 is located above the top electrode layer 510. The second through hole 920 penetrates the interlayer dielectric layer 900 and the cover layer 800 to expose a portion of the surface of the top electrode layer 510. The second through hole 920 is filled with a second conductive structure 921. The bottom of the second conductive structure 921 is conductively connected to the top electrode layer 510. The first conductive structure 911 and the second conductive structure 921 are insulated and isolated by the interlayer dielectric layer 900.

[0078] The interlayer dielectric layer 900 may be made of insulating materials such as silicon oxide (SiO2), silicon nitride (SiN), hydrogen silsesquioxane polymer (HSQ), methane silsesquioxane polymer (MSQ), methyl silicate compounds, and carbon-doped oxides.

[0079] like Fig.19As shown, the MIM capacitor is cascaded between the conductive interconnect structures of different film layers to shield the interference of electrical noise signals, thereby playing the role of a filter. In some embodiments, a first conductive layer 110 is provided in the substrate 100, an interlayer dielectric layer 900 is provided above the MIM capacitor, and a second conductive layer 940 is provided on the interlayer dielectric layer 900. A first through hole 910, a second through hole 920 and a third through hole 930 are provided in the interlayer dielectric layer 900. The first through hole 910 penetrates the interlayer dielectric layer 900 and exposes a portion of the surface of the bottom electrode layer 210. The first through hole 910 is filled with a first conductive structure 911. The bottom of the first conductive structure 911 is in conductive contact with the bottom electrode layer 210, and the top of the first conductive structure 911 is in conductive contact with the second conductive layer 940. The first conductive structure 911 makes the bottom electrode layer 210 and the second conductive layer 940 conductively connected. The second through hole 920 penetrates the interlayer dielectric layer 900 and exposes a portion of the surface of the top electrode layer 510. The bottom of the second conductive structure 921 is in conductive contact with the top electrode layer 510, and the top of the second conductive structure 921 is in conductive contact with the second conductive layer 940. The second conductive structure 921 enables conductive communication between the top and bottom electrode layers 210 and the second conductive layer 940. In addition, a third through hole 930 is provided on the interlayer dielectric layer 900. The third through hole 930 penetrates the interlayer dielectric layer 900 and the substrate 100 to expose a portion of the surface of the first conductive layer 110. The third through hole 930 is filled with a third conductive structure 931. The bottom of the third conductive structure 931 is conductively connected to the first conductive layer 110, and the top of the third conductive structure 931 is conductively connected to the second conductive layer 940. The third conductive structure 931 enables conductive communication between the first conductive layer 110 and the second conductive layer 940.

[0080] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for forming a metal-insulator-metal capacitor, characterized in that: include: providing a substrate; forming a first conductive material layer on the substrate; forming an insulating material layer on the first conductive material layer; forming a first mask layer on the insulating material layer, and wet-etching a portion of the insulating material layer and the first conductive material layer along the first mask layer to form a bottom electrode layer and an insulating layer on the substrate; forming a second conductive material layer on the substrate and the insulating layer; A second mask layer is formed on the second conductive material layer, and a portion of the second conductive material layer is wet-etched along the second mask layer so that the remaining second conductive material layer forms a top electrode layer on the insulating layer; wherein, along a direction perpendicular to the surface of the substrate, a projection of the second mask layer on the substrate is within a projection of the insulating layer on the substrate.

2. The forming method according to claim 1, characterized in that: Also includes: A covering layer is formed on surfaces of the substrate, the bottom electrode layer, the insulating layer and the top electrode layer.

3. The forming method according to claim 1 or 2, characterized in that: Also includes: forming a first conductive structure on the bottom electrode layer and forming a second conductive structure on the top electrode layer; The first conductive structure and the second conductive structure are insulated and isolated from each other.

4. The forming method according to claim 1, characterized in that: The materials of the first conductive material layer and the second conductive material layer are metal nitride.

5. A metal-insulator-metal capacitor prepared by the formation method according to any one of claims 1 to 4, characterized in that: include: substrate; A bottom electrode layer, which is disposed on the substrate; an insulating layer, disposed on the bottom electrode layer; a top electrode layer, disposed on the insulating layer; a covering layer, the covering layer covering surfaces of the substrate, the bottom electrode layer, the insulating layer and the top electrode layer; a silicon oxide layer disposed between the top electrode layer and the cover layer; Among them, along the direction perpendicular to the surface of the substrate, the projection of the top electrode layer on the substrate is located within the projection of the insulating layer on the substrate, and the projection of the insulating layer on the substrate is covered by the projection of the bottom electrode layer on the substrate; the height of the outer edge of the bottom electrode layer is less than or equal to the height of the outer edge of the insulating layer; the outer edges of the insulating layer and the bottom electrode layer are continuous at the junction and are in the shape of a slope increasing from the outer diameter to the bottom.

6. The metal-insulator-metal capacitor according to claim 5, characterized in that: A first conductive structure is disposed on the bottom electrode layer, and a second conductive structure is disposed on the top electrode layer. The first conductive structure and the second conductive structure are insulated and isolated from each other.

7. The metal-insulator-metal capacitor according to claim 6, characterized in that: A first conductive layer is provided in the substrate, an interlayer dielectric layer is provided on the metal-insulator-metal capacitor, a second conductive layer is provided on the interlayer dielectric layer, the second conductive layer is conductively connected to the bottom electrode layer via the first conductive structure, the second conductive layer is conductively connected to the top electrode layer via the second conductive structure, the second conductive layer is conductively connected to the first conductive layer via a third conductive structure, and the first conductive structure, the second conductive structure and the third conductive structure are insulated and isolated from each other.

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