Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a drift layer, a P-type modulation layer, a current blocking layer, a channel layer, a barrier layer, a first trench, a PGaN active layer, a gate, a source and a drain. The P-type modulation layer is arranged on a middle region of one side surface of the drift layer; the current blocking layer is located at the periphery of the P-type modulation layer; the channel layer is located at the side, away from the drift layer, of the P-type modulation layer and the current blocking layer, and the channel layer covers the P-type modulation layer and part of the current blocking layer; the first trench penetrates the channel layer and the P-type modulation layer; the barrier layer is located at the side, away from the drift layer, of the channel layer and in the first trench, and the barrier layer at the side, away from the drift layer, of the channel layer forms a heterojunction structure with the channel layer; the PGaN active layer is located in the first trench; the gate is located at the side, away from the drift layer, of the PGaN active layer; and the source is located at least at the side, away from the drift layer, of the current blocking layer and is in contact with the heterojunction structure.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a semiconductor device and its fabrication method. Background Technology

[0002] GaN materials have a wider bandgap, allowing for smaller device sizes while maintaining the same breakdown voltage requirements, leading to their increasing application in semiconductor devices. Currently, mainstream gallium nitride (GaN) device manufacturing still uses planar structures, where the gate and drain are roughly at the same height along the thickness of the semiconductor device, resulting in significant waste of device area. Summary of the Invention

[0003] According to a first aspect of the present invention, a semiconductor device is provided, comprising:

[0004] Drift layer;

[0005] A P-type modulation layer is disposed on the middle region of one side surface of the drift layer in the thickness direction of the semiconductor device;

[0006] A current blocking layer is disposed on the same side surface of the drift layer as the P-type modulation layer, and is located on the periphery of the P-type modulation layer;

[0007] The channel layer is located on the side of the P-type modulation layer and the current blocking layer away from the drift layer, and the channel layer covers the P-type modulation layer and a portion of the width of the current blocking layer near the P-type modulation layer; the current blocking layer includes a first blocking portion that overlaps with the channel layer, and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer.

[0008] The first trench penetrates the channel layer and the P-type modulation layer in the thickness direction of the semiconductor device;

[0009] The barrier layer, located on the side of the channel layer away from the drift layer and in the first trench, includes a first barrier portion located on the side of the channel layer away from the drift layer and a second barrier portion located in the first trench. The first barrier portion and the second barrier portion are formed in different processes, and the first barrier portion forms a heterojunction structure with the channel layer.

[0010] The PGaN active layer is located in the first trench;

[0011] The gate is located on the side of the PGaN active layer away from the drift layer;

[0012] The source electrode is located at least on the side of the second blocking portion of the current blocking layer away from the drift layer and is in contact with the heterojunction structure.

[0013] The drain is located on the side of the drift layer away from the heterojunction structure.

[0014] In some embodiments, in the thickness direction of the semiconductor device, the bottom wall of the first trench is higher than the bottom surface of the current blocking layer on the side facing the drift layer.

[0015] In some embodiments, the top surface of the current blocking layer on the side opposite to the drift layer is at the same height as the top surface of the P-type modulation layer on the side opposite to the drift layer, or the top surface of the current blocking layer on the side opposite to the drift layer is higher than the top surface of the P-type modulation layer on the side opposite to the drift layer.

[0016] In some embodiments, the semiconductor device is a GaN power device with a PGaN structure, and the gate is a Schottky metal; and / or,

[0017] The current blocking layer is made of P-type gallium nitride.

[0018] In some embodiments, the semiconductor device further includes:

[0019] A passivation layer is located on the side of the gate and the first barrier portion away from the drift layer;

[0020] The source electrode is located on the side of the second blocking portion of the current blocking layer away from the drift layer and on the side of the passivation layer away from the drift layer.

[0021] According to a second aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising:

[0022] Drift layer;

[0023] A current blocking layer is disposed on the peripheral region of the surface of the drift layer on one side of the semiconductor device in the thickness direction, and the central region of the surface of the drift layer in which the current blocking layer is disposed is exposed from the center of the current blocking layer.

[0024] The channel layer is located on the same side as the drift layer and the current blocking layer, and the channel layer covers the drift layer exposed from the middle of the current blocking layer and a portion of the width of the current blocking layer; the current blocking layer includes a first blocking portion that overlaps with the channel layer, and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer;

[0025] The second trench penetrates the channel layer in the thickness direction of the semiconductor device;

[0026] A barrier layer is located on the side of the channel layer away from the drift layer and in the second trench. The barrier layer includes a first barrier portion located on the side of the channel layer away from the drift layer and a second barrier portion located in the second trench. The first barrier portion and the second barrier portion are formed in different processes, and the first barrier portion forms a heterojunction structure with the channel layer.

[0027] The PGaN active layer is located in the second trench and is in contact with the barrier layer;

[0028] The gate is located on the side of the PGaN active layer away from the drift layer.

[0029] The gate is located on the side of the PGaN active layer away from the drift layer;

[0030] The source electrode is located at least on the side of the second blocking portion of the current blocking layer away from the drift layer and is in contact with the heterojunction structure.

[0031] The drain is located on the side of the drift layer away from the heterojunction structure.

[0032] In some embodiments, in the thickness direction of the semiconductor device, the bottom wall of the second trench is higher than the bottom surface of the current blocking layer on the side facing the drift layer; and / or,

[0033] The semiconductor device is a GaN power device with a PGaN structure, and the gate is a Schottky metal; and / or,

[0034] The current blocking layer is made of P-type gallium nitride; and / or,

[0035] The semiconductor device further includes a passivation layer located on the side of the gate and the first barrier portion away from the drift layer;

[0036] The source electrode is located on the side of the second blocking portion of the current blocking layer away from the drift layer and on the side of the passivation layer away from the drift layer.

[0037] According to a third aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising:

[0038] A substrate is provided, and a drift layer is formed on one side of the substrate;

[0039] A P-type modulation layer is formed in the central region of the surface of the drift layer on the side opposite to the substrate;

[0040] A current blocking layer is formed on the surface of the drift layer opposite to the substrate, located around the P-type modulation layer;

[0041] A channel layer, a first trench, a barrier layer, a PGaN active layer, and a gate are formed on the side of the P-type modulation layer and the current blocking layer away from the drift layer. The channel layer covers the P-type modulation layer and a portion of the width of the current blocking layer near the P-type modulation layer. The current blocking layer includes a first blocking portion overlapping the channel layer and a second blocking portion located outside the first blocking portion and not overlapping the channel layer. The first trench penetrates the channel layer and the P-type modulation layer in the thickness direction of the semiconductor device. The barrier layer is located on the side of the channel layer away from the drift layer and in the first trench. The barrier layer includes a first barrier portion located on the side of the channel layer away from the drift layer and a second barrier portion located in the first trench. The first barrier portion and the second barrier portion are formed in different processes. The first barrier portion forms a heterojunction structure with the channel layer. The PGaN active layer is located in the first trench and is in contact with the barrier layer. The gate is located on the side of the PGaN active layer away from the drift layer.

[0042] A source electrode is formed, wherein the source electrode is at least located on the side of the second blocking portion of the current blocking layer away from the drift layer and is in contact with the heterojunction structure;

[0043] The substrate is removed and a drain is formed, the drain being located on the side of the drift layer opposite to the heterojunction structure.

[0044] In some embodiments, after providing a substrate and before forming a drift layer on one side of the substrate, the method includes:

[0045] A nucleation layer and a buffer layer are formed on one side of the substrate. The nucleation layer is an AlN layer, and the buffer layer includes an AlGaN layer, an interleaved stacked multilayer AlN / GaN layer, a low-temperature GaN layer, and a high-temperature GaN layer sequentially stacked on the nucleation layer.

[0046] The formation of a drift layer on one side of the substrate includes:

[0047] A drift layer is formed on the side of the buffer layer opposite to the substrate.

[0048] In some embodiments, during or after substrate removal but before drain formation, the method further includes:

[0049] Remove the nucleation layer; or,

[0050] Remove the nucleation layer and at least a portion of the buffer layer.

[0051] In some embodiments, the method further includes, prior to forming the source, the following:

[0052] A passivation layer is formed, the passivation layer being located on the side of the gate and the first barrier portion away from the drift layer;

[0053] After the source is formed, the source is located on the side of the second blocking portion of the current blocking layer away from the drift layer and on the side of the passivation layer away from the drift layer.

[0054] According to a fourth aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising:

[0055] A substrate is provided, and a drift layer is formed on one side of the substrate;

[0056] A current blocking layer is formed in the peripheral region of the surface of the drift layer on one side of the semiconductor device in the thickness direction; the central region of the surface of the drift layer in which the current blocking layer is provided is exposed from the center of the current blocking layer;

[0057] A channel layer, a second trench, a barrier layer, a PGaN active layer, and a gate are formed on the same side of the drift layer and the current blocking layer. The channel layer covers the drift layer exposed from the middle of the current blocking layer and a portion of the width of the current blocking layer. The current blocking layer includes a first blocking portion overlapping the channel layer and a second blocking portion located outside the first blocking portion and not overlapping the channel layer. The second trench penetrates the channel layer in the thickness direction of the semiconductor device. The barrier layer is located on the side of the channel layer away from the drift layer and in the second trench. The barrier layer includes a first barrier portion on the side of the channel layer away from the drift layer and a second barrier portion in the second trench. The first barrier portion and the second barrier portion are formed in different processes, and the first barrier portion forms a heterojunction structure with the channel layer. The PGaN active layer is located in the second trench. The gate is located on the side of the PGaN active layer away from the drift layer.

[0058] A source electrode is formed, wherein the source electrode is at least located on the side of the second blocking portion of the current blocking layer away from the drift layer and is in contact with the heterojunction structure;

[0059] The substrate is removed and a drain is formed, the drain being located on the side of the drift layer opposite to the heterojunction structure.

[0060] In some embodiments, after providing a substrate and before forming a drift layer on one side of the substrate, the method includes:

[0061] A nucleation layer and a buffer layer are formed on one side of the substrate. The nucleation layer is an AlN layer, and the buffer layer includes an AlGaN layer, an interleaved stacked multilayer AlN / GaN layer, a low-temperature GaN layer, and a high-temperature GaN layer sequentially stacked on the nucleation layer.

[0062] The formation of a drift layer on one side of the substrate includes:

[0063] A drift layer is formed on the side of the buffer layer opposite to the substrate;

[0064] The method further includes, during or after substrate removal but before drain formation:

[0065] Remove the nucleation layer; or,

[0066] Remove the nucleation layer and at least a portion of the buffer layer.

[0067] In some embodiments, the method further includes, prior to forming the source, the following:

[0068] A passivation layer is formed, the passivation layer being located on the side of the gate and the first barrier portion away from the drift layer;

[0069] After the source is formed, the source is located on the side of the second blocking portion of the current blocking layer away from the drift layer and on the side of the passivation layer away from the drift layer.

[0070] The main technical effects achieved by the embodiments of this application are:

[0071] The semiconductor device and its fabrication method provided in this application embodiment configure the semiconductor device as a vertical structure, which is beneficial for controlling the size of the device. Furthermore, the blocking effect of the current blocking layer below the source can reduce turn-off leakage current, thereby achieving better reliability and lower power consumption. The presence of a PGaN active layer below the gate can increase the barrier layer height, raising the potential energy at the trench below the gate above the Fermi level. A high electron barrier is formed at the interface between the drift layer and the barrier layer, better confining electrons within the 2DEG channel and improving electron mobility. Attached Figure Description

[0072] Figure 1 A top view of a semiconductor device provided according to an embodiment of the present invention;

[0073] Figure 2 For along Figure 1 The sectional view obtained by section line A-A' shown;

[0074] Figure 3 A cross-sectional view of another semiconductor device provided in an embodiment of the present invention;

[0075] Figure 4 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0076] Figures 5 to 27This is a structural diagram corresponding to some process steps in the fabrication of a semiconductor device according to an embodiment of the present invention.

[0077] Figure 28 A flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention;

[0078] Figure 29 and Figure 30 This is a structural diagram corresponding to some process steps in the fabrication of a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0079] This application provides a semiconductor device and a method for fabricating the same. The semiconductor device and its fabrication method according to the embodiments of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features in the following embodiments can complement or combine with each other.

[0080] Please refer to Figure 1 and Figure 2 And, when necessary, in conjunction with other accompanying drawings, embodiments of this application provide a semiconductor device, the semiconductor device 100 including a drift layer 10, a current blocking layer 20, a P-type modulation layer 30, a channel layer 41, a barrier layer 42, a first trench 101, a PGaN active layer 50, a gate 60, a source 80, and a drain 90.

[0081] The P-type modulation layer 30 is disposed on the middle region of one side surface of the drift layer 10 in the thickness direction T of the semiconductor device.

[0082] The current blocking layer 20 and the P-type modulation layer 30 are disposed on the same side surface of the drift layer 10 and are located on the periphery of the P-type modulation layer 30.

[0083] The channel layer 41 is located on the side of the P-type modulation layer 30 and the current blocking layer 20 opposite to the drift layer 10, and the channel layer 41 covers the P-type modulation layer 30 and a portion of the width of the current blocking layer 20 near the P-type modulation layer 30; the current blocking layer 20 includes a first blocking portion 21 overlapping the channel layer 41, and a second blocking portion 22 located around the first blocking portion 21 and not overlapping the channel layer 41. Here, "overlap" refers to projective overlap along the thickness direction. For example, as... Figure 2 As shown, the projection of the first blocking part 21 along the thickness direction falls within the projection of the channel layer 41 along the thickness direction, while the projection of the second blocking part 22 along the thickness direction falls outside the projection of the channel layer 41 along the thickness direction.

[0084] The first trench 101 penetrates the channel layer 41 and the P-type modulation layer 30 in the thickness direction T of the semiconductor device.

[0085] The barrier layer 42 is located on the side of the channel layer 41 away from the drift layer 10 and in the first trench 101. The barrier layer 42 includes a first barrier portion 421 located on the side of the channel layer 41 away from the drift layer 10 and a second barrier portion 422 located in the first trench 101. The first barrier portion 421 and the second barrier portion 422 are formed in different processes. The first barrier portion 421 and the channel layer 41 form a heterojunction structure 40.

[0086] The PGaN active layer 50 is located in the first trench 101 and is in contact with the barrier layer 42.

[0087] The gate 60 is located on the side of the PGaN active layer away from the drift layer.

[0088] The source electrode 80 is located at least on the side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and is in contact with the heterojunction structure 40.

[0089] The drain 90 is located on the side of the drift layer 10 away from the heterojunction structure 40.

[0090] The semiconductor device 100 is configured with a vertical structure, which is beneficial for controlling the size of the device. Furthermore, the combined effect of the current blocking layer 20 below the source 80 and the P-type modulation layer below the channel layer 41 increases the device's saturation output current and reduces turn-off leakage current, thereby achieving better reliability and lower power consumption. The presence of the PGaN active layer 50 below the gate 60 increases the height of the barrier layer 42, raising the potential energy at the trench below the gate 60 above the Fermi level. A high electron barrier is formed at the interface between the drift layer 10 and the barrier layer 42, better confining electrons within the 2DEG channel and improving electron mobility.

[0091] The drift layer 10 provides the path for most of the current in the semiconductor device and mainly withstands the voltage during device operation.

[0092] Since doping concentration directly affects the breakdown voltage and on-resistance of semiconductor devices, the inventors have discovered that, in some embodiments, the drift layer 10 can be a structural layer formed using undoped or lightly doped (1e15-1e16 / cm-3) gallium nitride. When the drift layer 10 is lightly doped gallium nitride, N-type silicon can be doped into the gallium nitride.

[0093] Generally, increasing the thickness of the drift layer 10 increases the breakdown voltage of the semiconductor device, but also increases the on-resistance. The inventors discovered that the thickness of the drift layer 10 can be set within the range of 1μm-20μm. This ensures that the drift layer 10 is not too thin, making it prone to breakdown, nor too thick, resulting in excessive on-resistance. For example, the thickness of the drift layer 10 can be set to a size within the range of 1μm-20μm, such as 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm…19μm, 20μm. The specific thickness of the drift layer 10 can be determined based on the structure of the semiconductor device, the target breakdown voltage, and other factors.

[0094] The current blocking layer 20 can block charge transmission between the source 80 and the drain 90, so that when the device containing the semiconductor device 100 is working, under the control of the gate 60, the current can flow from the drain 90, the drift layer 10, and the heterojunction structure 40 to the source 80 in a better sequence.

[0095] In some embodiments, the current blocking layer 20 is made of p-type gallium nitride. The thickness of the current blocking layer 20 can be 200nm-600nm. This ensures that charge transmission between the source 80 and the drain 90 is blocked, but the layer is not too thick, which would affect the device size and waste material. For example, the thickness of the current blocking layer 20 can be within the range of 200nm-600nm, such as 200nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, or 600nm.

[0096] It should be noted that in some other embodiments, the current blocking layer 20 may also be made of N-type gallium nitride.

[0097] The P-type modulation layer 30 can be used to adjust the electric field distribution in the drift layer 10 to optimize the device's breakdown voltage and current handling capability. The P-type modulation layer 30 can create a space charge region in the drift layer 10, helping to smooth the electric field distribution, reduce the local electric field strength, and thus improve the device's breakdown voltage.

[0098] In some embodiments, the material of the P-type modulation layer 30 may be P-type gallium nitride. The P-type modulation layer 30 may be a doped modulation layer formed by doping with one or two elements selected from dopable trivalent elements, such as aluminum (Al) or boron (B), and its doping concentration may be 1e16 / cm-3 to 1e17 / cm-3.

[0099] In some embodiments, the thickness of the P-type modulation layer 30 ranges from 50nm to 500nm. For example, the thickness of the P-type modulation layer 30 can be within the range of 50nm-500nm, such as 50nm, 100nm, 110nm, 150nm, 200nm, 300nm...500nm.

[0100] The channel layer 41 can perform drain-to-source current transfer.

[0101] In some embodiments, the material of the channel layer 41 may be GaN without intentional doping.

[0102] In some embodiments, the thickness of the channel layer 41 can be 0.3μm-1μm. For example, the thickness of the channel layer 41 can be within the range of 0.3μm-1μm, such as 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1μm, etc.

[0103] In some embodiments, to facilitate the fabrication of the first trench 101, the first trench 101 may penetrate a portion of the drift layer 10. Of course, in other embodiments, the first trench may penetrate exactly to the top surface of the drift layer facing the channel layer.

[0104] The first barrier portion 421 in the barrier layer 42 forms a heterojunction structure with the channel layer 41. The spontaneous polarization effect and piezoelectric polarization effect of this heterojunction structure induce a built-in polarization electric field, thereby generating a high-density, high-mobility 2DEG. The second barrier portion 422 located in the first trench 101 in the barrier layer 42 can cover the sidewalls and bottom wall of the first trench 101.

[0105] In some embodiments, the barrier layer 42 is made of AlGaN.

[0106] In some embodiments, the thickness of the barrier layer 42 can be in the range of 20nm-30nm. For example, the thickness of the barrier layer 42 can be 20nm, 21nm, 22nm, 23nm, 24nm, 25nm, 26nm, 27nm, 28nm, 29nm, 30nm, etc., which are sizes of 20nm-30nm.

[0107] In some embodiments, the PGaN active layer 50 is made of p-type gallium nitride. The thickness of the PGaN active layer 50 can be 200nm-600nm. For example, the thickness of the current blocking layer 20 can be in the range of 200nm-600nm, such as 200nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, or 600nm.

[0108] In some embodiments, the gate 60 is a Schottky metal, such as platinum or nickel. The semiconductor device is a GaN power device with a PGaN structure. The PGaN active layer below the gate 60 can increase the barrier layer height, raising the potential energy at the trench below the gate above the Fermi level. A high electron barrier is formed at the interface between the drift layer and the barrier layer, better confining electrons within the 2DEG channel and improving electron mobility.

[0109] The source electrode 80 is an ohmic metal and can be a stacked structure composed of Ti, Al, Ni and Ag layers stacked in sequence.

[0110] The drain electrode 90 is made of a metallic material, such as one or more of Ti, Ni, and Ag. If the drain electrode 90 is made of multiple metallic materials, it can be a multilayer structure composed of multiple layers of different metallic materials.

[0111] In some embodiments, in the thickness direction T of the semiconductor device, the bottom wall 1011 of the first trench 101 is higher than the bottom surface 2001 of the current blocking layer 20 on the side facing the drift layer 10, so that the current blocking layer 20 can balance the charge at the lower corner of the gate 60, so that the electric field distribution at the lower corner of the gate 60 is more uniform and the device performance is improved.

[0112] In some embodiments, the top surface 2002 of the current blocking layer 20 on the side opposite to the drift layer 10 is flush with the top surface 3001 of the P-type modulation layer 30 on the side opposite to the drift layer 10.

[0113] In other embodiments, the top surface 2002 of the current blocking layer 20 on the side opposite to the drift layer 10 is higher than the top surface 3001 of the P-type modulation layer 30 on the side opposite to the drift layer 10.

[0114] In some embodiments, the semiconductor device 100 further includes a passivation layer 70. The passivation layer 70 is located on the side of the gate 60 and the first barrier portion 421 opposite to the drift layer 10. Specifically, the passivation layer 70 is located on the side of the gate 60 and the first barrier portion 421 opposite to the drift layer 10.

[0115] The passivation layer 70 can be made of silicon nitride. The thickness of the passivation layer 70 can be 0.1 μm to 1.5 μm. For example, the thickness of the passivation layer 70 can be 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, etc.

[0116] Accordingly, such as Figure 2 As shown, the source electrode 80 can be located on the side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and on the side of the passivation layer 70 away from the drift layer 10.

[0117] In some other embodiments, the source 80 may also be located only on the side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10.

[0118] In some embodiments, a buffer layer may be included between the drift layer 10 and the drain 90. For example, the buffer layer may include a low-temperature GaN layer 110 and a high-temperature GaN layer 120. Of course, in other embodiments, the buffer layer may consist of only one gallium nitride layer, such as only the high-temperature GaN layer 120. Alternatively, in other embodiments, the drift layer 10 is in direct contact with the drain 90, without a buffer layer in between.

[0119] like Figure 3 As shown, this application also provides a semiconductor device 100'. The semiconductor device 100' includes a drift layer 10, a current blocking layer 20, a channel layer 41, a barrier layer 42, a first trench 101, a PGaN active layer 50, a gate 60, a source 80, and a drain 90.

[0120] A current blocking layer 20 is disposed in the peripheral region of the surface of the drift layer 10 on one side of the semiconductor device in the thickness direction T, and the central region of the surface of the drift layer 10 in which the current blocking layer 20 is disposed is exposed from the center of the current blocking layer 20.

[0121] The channel layer 41 is located on the same side of the drift layer 10 and the current blocking layer 20, and the channel layer 41 covers the drift layer 10 exposed from the middle of the current blocking layer 20 and a portion of the width of the current blocking layer 20; the current blocking layer 20 includes a first blocking portion 21 that overlaps with the channel layer 41, and a second blocking portion 22 located around the first blocking portion 21 and not overlapping with the channel layer 41.

[0122] The second trench 201 penetrates the channel layer 41 in the thickness direction T of the semiconductor device.

[0123] The barrier layer 42 is located on the side of the channel layer 41 away from the drift layer 10 and in the second trench 201. The barrier layer 42 includes a first barrier portion 421 located on the side of the channel layer 41 away from the drift layer 10 and a second barrier portion 422 located in the second trench 201. The first barrier portion 421 and the second barrier portion 422 are formed in different processes, and the first barrier portion 421 forms a heterojunction structure 40 with the channel layer 41.

[0124] The PGaN active layer 50 is located in the second trench 201 and is in contact with the second barrier portion 422 of the barrier layer 42.

[0125] The gate 60 is located on the side of the PGaN active layer away from the drift layer.

[0126] The source electrode 80 is located at least on the side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and is in contact with the heterojunction structure 40.

[0127] The drain 90 is located on the side of the drift layer 10 away from the heterojunction structure 40.

[0128] The semiconductor device 100' features a vertical structure, which facilitates control over the device's size. Furthermore, the current-blocking layer beneath the source reduces turn-off leakage, resulting in better reliability and lower power consumption. The presence of a PGaN active layer below the gate increases the barrier layer height, raising the potential energy at the trench below the gate above the Fermi level. This creates a high electron barrier at the interface between the drift layer and the barrier layer, better confining electrons within the 2DEG channel and improving electron mobility.

[0129] In some embodiments, in the thickness direction T of the semiconductor device, the bottom surface of the gate 60 facing the drift layer 10 is higher than the bottom surface of the current blocking layer 20 facing the drift layer 10.

[0130] In some embodiments, the gate 60 is a Schottky metal. The semiconductor device is a GaN power device with a PGaN structure.

[0131] The PGaN active layer below the gate 60 can increase the height of the barrier layer and raise the potential energy in the trench below the gate to above the Fermi level. A high electronic barrier will be formed at the interface between the drift layer and the barrier layer, which will better confine electrons in the 2DEG channel and improve electron mobility.

[0132] The source electrode 80 is an ohmic metal and can be a stacked structure composed of Ti, Al, Ni and Ag layers stacked in sequence.

[0133] The drain electrode 90 is made of a metallic material, such as one or more of Ti, Ni, and Ag. If the drain electrode 90 is made of multiple metallic materials, it can be a multilayer structure composed of multiple layers of different metallic materials.

[0134] In some embodiments, the current blocking layer 20 is made of P-type gallium nitride.

[0135] In some embodiments, the semiconductor device further includes a passivation layer 70 located on the side of the gate 60 and the first barrier portion 421 away from the drift layer 10.

[0136] Accordingly, such as Figure 3 As shown, the source electrode 80 is located on the side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and on the side of the passivation layer 70 away from the drift layer 10.

[0137] In some other embodiments, the source 80 may also be located only on the side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10.

[0138] In some embodiments, a buffer layer may be included between the drift layer 10 and the drain 90. For example, the buffer layer may include a low-temperature GaN layer 110 and a high-temperature GaN layer 120. Of course, in other embodiments, the buffer layer may consist of only one gallium nitride layer, such as only the high-temperature GaN layer 120. Alternatively, in other embodiments, the drift layer 10 is in direct contact with the drain 90, without a buffer layer in between.

[0139] It should be noted that, in some embodiments, to facilitate the fabrication of the second trench 201, the second trench 201 may penetrate a portion of the drift layer 10. Of course, in other embodiments, the second trench may penetrate precisely to the top surface of the drift layer facing the channel layer.

[0140] The semiconductor device 100' differs from the semiconductor device 100 described above in that it does not include the P-type modulation layer 30. Other similar or identical structures are described in the relevant descriptions above and will not be repeated here.

[0141] It should be noted that neither the semiconductor device 100 nor the semiconductor device 100' described in this application has a separate substrate layer. The drift layer 10, in addition to serving as a drift layer for the device, also provides some support for the semiconductor device 100 and the semiconductor device 100'. Compared to semiconductor devices using a separate substrate, this is beneficial for controlling the thickness of the semiconductor device 100 and the semiconductor device 100', reducing device resistance, and facilitating heat dissipation.

[0142] It should also be noted that in the aforementioned semiconductor device 100 and semiconductor device 100', the source electrode 80 can be in direct contact with the current blocking layer 20, or it can be separated by a channel layer of a certain thickness. Among them, the method of direct contact between the source electrode 80 and the current blocking layer 20 is more conducive to improving the current blocking effect of the current blocking layer 20.

[0143] like Figure 4As shown, this application also provides a method for fabricating a semiconductor device, which includes the following steps S110 to S160:

[0144] In step S110, a substrate is provided, and a drift layer is formed on one side of the substrate;

[0145] In step S120, a P-type modulation layer is formed in the central region of the surface of the drift layer on the side opposite to the substrate;

[0146] In step S130, a current blocking layer is formed on the surface of the drift layer facing away from the substrate, located around the P-type modulation layer;

[0147] In step S140, a channel layer, a second trench, a barrier layer, a PGaN active layer, and a gate are formed on the side of the P-type modulation layer and the current blocking layer away from the drift layer. The channel layer covers the P-type modulation layer and a portion of the width of the current blocking layer near the P-type modulation layer. The current blocking layer includes a first blocking portion overlapping the channel layer and a second blocking portion located outside the first blocking portion and not overlapping the channel layer. The first trench penetrates the channel layer and the P-type modulation layer in the semiconductor thickness direction. The barrier layer is located on the side of the channel layer away from the drift layer and in the first trench. The barrier layer includes a first barrier portion located on the side of the channel layer away from the drift layer and a second barrier portion located in the first trench. The first barrier portion and the second barrier portion are formed in different processes. The first barrier portion forms a heterojunction structure with the channel layer. The PGaN active layer is located in the first trench and is in contact with the barrier layer. The gate is located on the side of the PGaN active layer away from the drift layer.

[0148] In step S150, a source electrode is formed, which is located at least on the side of the second blocking portion of the current blocking layer away from the drift layer and is in contact with the heterojunction structure.

[0149] In step S160, the substrate is removed and a drain is formed, the drain being located on the side of the drift layer away from the heterojunction structure.

[0150] The method for fabricating this semiconductor device can be used to fabricate semiconductor device 100 or similar semiconductor devices as described above. The following is in conjunction with... Figures 5 to 27 The method for fabricating the semiconductor device is described in detail.

[0151] like Figures 5 to 12 In step S110, a substrate 200 is provided, and a drift layer 10 is formed on one side of the substrate 200.

[0152] like Figure 5 and Figure 6As shown, a substrate 200 is provided. The substrate 200 may be diamond.

[0153] Of course, in some other embodiments, the substrate may also be a silicon substrate, a sapphire substrate, etc.

[0154] For a diamond substrate 200, before forming the drift layer 10 on one side of the substrate 200, the method may further include forming a nucleation layer 210 and a buffer layer on one side of the substrate 200. The nucleation layer 210 is an AlN layer. The buffer layer includes a first buffer layer 220, a second buffer layer 230, a third buffer layer 110, and a fourth buffer layer 120 sequentially stacked on the nucleation layer 210. The first buffer layer 220 may be an AlGaN layer. The second buffer layer 230 is an interleaved stacked multilayer AlN / GaN layer. The third buffer layer 110 may be a low-temperature GaN layer. The fourth buffer layer 120 may be a high-temperature GaN layer.

[0155] like Figure 7 As shown, a nucleation layer 210 is formed on one side surface of the substrate 200 to reduce the lattice mismatch between the substrate and the subsequent GaN layer. This nucleation layer 210 can be formed using an epitaxial growth process. The thickness of the nucleation layer 210 can be 10nm-30nm, such as 10nm, 13nm, 15nm, 18nm, or 20nm.

[0156] like Figure 8 As shown, a first buffer layer 220 is formed on the side of the nucleation layer 210 facing away from the substrate 200 to further reduce the lattice mismatch between the substrate and the subsequent GaN layer. The thickness of the first buffer layer 220 is 0.1 μm-0.2 μm, such as 0.1 μm, 0.12 μm, 0.15 μm, 0.16 μm, 0.18 μm, 0.2 μm, etc.

[0157] like Figure 9 As shown, a second buffer layer 230 is formed on the side of the first buffer layer 220 facing away from the substrate 200. This second buffer layer 230 is a multilayer AlN / GaN layer with staggered stacking. The dislocation density is reduced through a multi-layered alternating stress field, making the semiconductor layer structure, such as the subsequently added drift layer 10, more flat and uniform. The specific number of layers that can be stacked in the second buffer layer 230 can be determined according to specific circumstances, such as 10 pairs of AlN / GaN layers, 20 pairs of AlN / GaN layers, or other multilayer AlN / GaN layers. The thickness of each AlN or GaN layer can be several nanometers, such as 2 nm.

[0158] like Figure 10As shown, a third buffer layer 110 is formed on the side of the second buffer layer 230 facing away from the substrate 200 to improve the adhesion quality and growth rate of subsequent layer structures. This third buffer layer 110 can be formed using an epitaxial growth process. Its thickness can be 100nm-300nm, such as 100nm, 150nm, 180nm, 200nm, 250nm, or 300nm.

[0159] like Figure 11 As shown, a fourth buffer layer 120 is formed on the side of the third buffer layer 110 facing away from the substrate 200, serving as the basis for the drift layer in subsequent device fabrication. The fourth buffer layer 120 can be formed using an epitaxial growth process. The thickness of the fourth buffer layer 120 can be 1μm-2μm, such as 1μm, 1.2μm, 1.5μm, 1.8μm, 2μm, etc.

[0160] like Figure 12 As shown, forming the drift layer 10 on one side of the substrate 200 includes forming the drift layer 10 on the side of the buffer layer opposite to the substrate 200. The drift layer 10 can be formed using an epitaxial growth process.

[0161] The thickness of the drift layer 10 can be set in the range of 1μm-20μm. This ensures that the drift layer 10 is not easily broken down due to being too thin, nor does it have excessively high on-resistance due to being too thick. For example, the thickness of the drift layer 10 can be set to a size within the range of 1μm-20μm, such as 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm...19μm, 20μm. The specific thickness of the drift layer 10 can be determined based on the structure of the semiconductor device, the target breakdown voltage, and other factors.

[0162] like Figures 13 to 15 In step S120, a P-type modulation layer 30 is formed in the central region of the surface of the drift layer 10 on the side opposite to the substrate 200.

[0163] like Figure 13 As shown, when forming the P-type modulation layer 30, a P-type modulation material layer 301 can be first placed on the surface of the drift layer 10 away from the substrate 200.

[0164] like Figure 14 and Figure 15 Subsequently, using the patterned photoresist 240 as a mask layer, a plasma etching process is employed to etch away the P-type modulation material layer 301 located at the edge, forming the P-type modulation layer 30 located in the center. After etching away the P-type modulation material layer 301 located at the edge, a trench 102 can be formed at the edge. The depth of this trench 102 can be 200nm-600nm, for example, 500nm.

[0165] like Figure 16 In step S130, a current blocking layer 20 is formed on the surface of the drift layer 10 facing away from the substrate 200, located around the P-type modulation layer 30.

[0166] The current blocking layer 20 can be formed in the trench 102 using metal-organic chemical vapor deposition (MOCVD).

[0167] like Figures 17 to 25 In step S140, a channel layer 41, a first trench 101, a barrier layer 42, a PGaN active layer 50, and a gate 60 are formed on the side of the P-type modulation layer 30 and the current blocking layer 20 away from the drift layer. The channel layer 41 covers the P-type modulation layer and a portion of the width of the current blocking layer near the P-type modulation layer. The current blocking layer includes a first blocking portion overlapping the channel layer and a second blocking portion located outside the first blocking portion and not overlapping the channel layer. The first trench penetrates the channel layer and the P-type modulation layer in the thickness direction of the semiconductor device. A barrier layer 42 is located on the side of the channel layer 41 away from the drift layer 10 and in the first trench 101. The barrier layer 42 includes a first barrier portion 421 located on the side of the channel layer 41 away from the drift layer 10 and a second barrier portion 422 located in the first trench 101. The first barrier portion 421 and the second barrier portion 422 are formed in different processes. The first barrier portion 421 forms a heterojunction structure 40 with the channel layer 41. A PGaN active layer 50 is located in the first trench 101 and is in contact with the barrier layer 42. A gate 60 is located on the side of the PGaN active layer 50 away from the drift layer 10.

[0168] like Figure 17 As shown, a channel material layer 410 is formed on the side of the P-type modulation layer 30 and the current blocking layer 20 away from the drift layer.

[0169] like Figure 18 Subsequently, a first barrier material layer 4210 is formed on the side of the channel material layer 410 away from the drift layer 10.

[0170] like Figure 19 As shown, a first trench 101 is subsequently formed, which penetrates the first barrier material layer 4210, the channel material layer 410 and the P-type modulation layer 30 in the thickness direction of the semiconductor device.

[0171] The patterned photoresist 250 can be used as a mask layer, and the middle part of the P-type modulation layer 30, the channel material layer 410 and the first barrier material layer 4210 can be etched away using a plasma etching process to form the first trench 101.

[0172] In some embodiments, to facilitate the fabrication of the first trench 101, a portion of the drift layer 10 can be etched away during the formation of the first trench 101, and correspondingly, the first trench 101 penetrates a portion of the drift layer 10. Of course, in other embodiments, during the formation of the first trench, the top surface of the drift layer facing the channel layer can be etched precisely, and correspondingly, the first trench can penetrate precisely to the top surface of the drift layer facing the channel layer.

[0173] like Figure 20 As shown, a second barrier portion 422 is subsequently formed in the first trench 101, covering the sidewalls and bottom wall of the first trench 101.

[0174] like Figure 21 As shown, subsequently, a PGaN active layer 50 is formed by filling the first trench 101 with PGaN active layer material, and the PGaN active layer 50 is in contact with the second barrier portion 422 of the barrier layer 42.

[0175] like Figure 22 As shown, a gate 60 is subsequently formed on the side of the PGaN active layer 50 opposite to the drift layer 10.

[0176] like Figure 23 As shown, a passivation material layer 701 is then formed on the side of the gate 60 and the barrier layer 42 (specifically the first barrier portion 421) away from the drift layer 10.

[0177] The passivation material layer 701 can be made of silicon nitride. Its thickness can be 0.5 μm to 1.5 μm.

[0178] like Figure 24 and Figure 25 As shown, subsequently, using the patterned photoresist 260 as a mask layer, a plasma etching process is employed to etch away the edge regions of the channel material layer 410, the first barrier material layer 4210, and the passivation material layer 701, forming the channel layer 41, the first barrier portion 421, and the passivation layer 70, as well as the trench 103 located around the channel layer 41, the barrier layer 42, and the passivation layer 70. The first barrier portion 421 and the second barrier portion 422 form the barrier layer 42.

[0179] like Figure 26 As shown, in step S150, a source electrode 80 is formed. The source electrode 80 is located at least on the side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and is in contact with the heterojunction structure 40.

[0180] The source electrode 80 is an ohmic metal. The source electrode 80 may be a stacked structure formed by sequentially depositing Ti, Al, Ni, and Ag layers using a deposition process.

[0181] like Figure 26 As shown, after the source 80 is formed, the source 80 is located on the side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and on the side of the first barrier portion 421 away from the drift layer 10.

[0182] In some other embodiments, the source may also be located only on the side of the second barrier away from the drift layer.

[0183] like Figure 27 As shown, in step S160, the substrate 200 is removed and a drain 90 is formed, the drain 90 being located on the side of the drift layer 10 away from the heterojunction structure 40.

[0184] In some embodiments, during or after removing the substrate 200, but before forming the drain 90, the nucleation layer 210 and a portion of the buffer layer may be removed, such as removing the first buffer layer 220 and the second buffer layer 230, to form a nucleation layer 210 and a portion of the buffer layer 220. Figure 27 The semiconductor device 100 includes a third buffer layer 110 and a fourth buffer layer 120.

[0185] In other embodiments, when or after removing the substrate 200 and before forming the drain 90, all buffer layers and nucleation layer 210 may be removed, or only nucleation layer 210 may be removed while all buffer layers are retained. Alternatively, nucleation layer and other parts of the buffer layer may be removed, such as nucleation layer 210 and first buffer layer 220.

[0186] like Figure 28 As shown, this application also provides a method for fabricating a semiconductor device, which includes the following steps S210 to S250:

[0187] In step S210, a substrate is provided, and a drift layer is formed on one side of the substrate;

[0188] In step S220, a current blocking layer is formed in the peripheral region of the surface of the drift layer on one side of the semiconductor device in the thickness direction; the central region of the surface of the drift layer where the current blocking layer is provided is exposed from the center of the current blocking layer;

[0189] In step S230, on the same side of the drift layer and the current blocking layer, there is a channel layer, a second trench, a barrier layer, a PGaN active layer, and a gate. The channel layer covers the drift layer exposed from the middle of the current blocking layer and a portion of the width of the current blocking layer. The current blocking layer includes a first blocking portion overlapping the channel layer and a second blocking portion located outside the first blocking portion and not overlapping the channel layer. The second trench penetrates the channel layer in the thickness direction of the semiconductor device in the semiconductor thickness direction. The gate is located in the second trench. The barrier layer is located on the side of the channel layer away from the drift layer and in the second trench. The barrier layer includes a first barrier portion located on the side of the channel layer away from the drift layer and a second barrier portion located in the second trench. The first barrier portion and the second barrier portion are formed in different processes, and the first barrier portion forms a heterojunction structure with the channel layer. The PGaN active layer is located in the second trench and is in contact with the barrier layer. The gate is located on the side of the PGaN active layer away from the drift layer.

[0190] In step S240, a source electrode is formed, which is located at least on the side of the second blocking portion of the current blocking layer away from the drift layer and is in contact with the heterojunction structure;

[0191] In step S250, the substrate is removed and a drain is formed, the drain being located on the side of the drift layer away from the heterojunction structure.

[0192] This semiconductor fabrication method can be used to prepare semiconductors such as... Figure 3 The semiconductor device 100' shown is a similar semiconductor device. The following is in conjunction with... Figure 29 and Figure 30 The semiconductor fabrication method is illustrated in the accompanying drawings and other figures.

[0193] In step S210, it can be combined with Figures 5 to 11 as well as Figure 29 As shown, a substrate 200 is provided, and a drift layer 10 is formed on one side of the substrate 200.

[0194] In some embodiments, after providing the substrate 200 and before forming the drift layer 10 on one side of the substrate 200, the method includes:

[0195] A nucleation layer 210 and a buffer layer are formed on one side of the substrate 200. The nucleation layer is an AlN layer, and the buffer layer includes an AlGaN layer, an interleaved stacked multilayer AlN / GaN layer, a low-temperature GaN layer, and a high-temperature GaN layer sequentially stacked on the nucleation layer.

[0196] Combination Figure 29 As shown, forming the drift layer 10 on one side of the substrate 200 includes:

[0197] A drift layer 10 is formed on the side of the buffer layer opposite to the substrate 200, forming a drift layer 10 as shown in the figure. Figure 29 The intermediate structure shown.

[0198] like Figure 30 As shown, in step S220, a current blocking layer 20 is formed in the peripheral region of the surface of the drift layer 10 on one side of the semiconductor device in the thickness direction T; the central region of the surface of the drift layer 10 where the current blocking layer 20 is provided is exposed from the center of the current blocking layer 20.

[0199] In step S230, a channel layer 41, a second trench 201, a barrier layer 42, a PGaN active layer 50, and a gate 60 are formed on the same side of the drift layer 10 and the current blocking layer 20. The channel layer 41 covers the drift layer 10 exposed from the middle of the current blocking layer 20 and a portion of the width of the current blocking layer 20. The current blocking layer 20 includes a first blocking portion 21 overlapping the channel layer 41 and a second blocking portion 22 located outside the first blocking portion 21 and not overlapping the channel layer 41. The second trench 201 penetrates the channel layer 41 in the thickness direction T of the semiconductor device; the gate 60 is located in the second trench 201. The barrier layer is located on the side of the channel layer away from the drift layer and in the second trench, and the barrier layer on the side of the channel layer away from the drift layer forms a heterojunction structure with the channel layer; the PGaN active layer is located in the second trench and is in contact with the barrier layer; the gate is located on the side of the PGaN active layer away from the drift layer.

[0200] It should be noted that, in some embodiments, to facilitate the fabrication of the second trench 201, a portion of the drift layer 10 can be etched away during the formation of the second trench 201, and correspondingly, the second trench 201 penetrates a portion of the drift layer 10. Of course, in other embodiments, during the formation of the second trench, the top surface of the drift layer facing the channel layer can be etched precisely, and correspondingly, the second trench can precisely penetrate the top surface of the drift layer facing the channel layer.

[0201] In step S240, a source electrode 80 is formed, which is located at least on the side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and is in contact with the heterojunction structure 40.

[0202] In some embodiments, prior to forming the source 80, the method further includes:

[0203] A passivation layer 70 is formed, which is located on the side of the gate 60 and the first barrier portion 421 away from the drift layer 10.

[0204] After the source electrode 80 is formed, the source electrode 80 is located on the side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and on the side of the passivation layer 70 away from the drift layer 10.

[0205] In some other embodiments, the source may also be located only on the side of the second barrier away from the drift layer.

[0206] In step S250, the substrate 200 is removed and a drain 90 is formed, the drain 90 being located on the side of the drift layer 10 away from the heterojunction structure 40.

[0207] In some embodiments, during or after removing the substrate 200, but before forming the drain 90, the nucleation layer 210 and a portion of the buffer layer may be removed, such as removing the first buffer layer 220 and the second buffer layer 230, to form a nucleation layer 210 and a portion of the buffer layer 220. Figure 30 The semiconductor device 100' includes a third buffer layer 110 and a fourth buffer layer 120.

[0208] In other embodiments, when or after removing the substrate 200 and before forming the drain 90, all buffer layers and nucleation layer 210 may be removed, or only nucleation layer 210 may be removed while all buffer layers are retained. Alternatively, nucleation layer and other parts of the buffer layer may be removed, such as nucleation layer 210 and first buffer layer 220.

[0209] It should be noted that, compared with the above regarding Figure 4 The semiconductor devices shown are fabricated differently, Figure 28 The method for fabricating the semiconductor device shown does not include the steps related to the fabrication of the P-type modulation layer 30. Other film layers and fabrication steps can be referred to the above-described method. Figure 4 The details of the fabrication method for the semiconductor device shown are not elaborated here.

[0210] The embodiments of the semiconductor device fabrication method provided in this application and the embodiments of the semiconductor device belong to the same inventive concept. The descriptions of relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0211] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Drift layer; A P-type modulation layer is disposed on the middle region of one side surface of the drift layer in the thickness direction of the semiconductor device; A current blocking layer is disposed on the same side surface of the drift layer as the P-type modulation layer, and is located on the periphery of the P-type modulation layer; The channel layer is located on the side of the P-type modulation layer and the current blocking layer away from the drift layer, and the channel layer covers the P-type modulation layer and a portion of the width of the current blocking layer near the P-type modulation layer; the current blocking layer includes a first blocking portion that overlaps with the channel layer, and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer. The first trench penetrates the channel layer and the P-type modulation layer in the thickness direction of the semiconductor device; A barrier layer is located on the side of the channel layer away from the drift layer and in the first trench. The barrier layer includes a first barrier portion located on the side of the channel layer away from the drift layer and a second barrier portion located in the first trench. The first barrier portion and the second barrier portion are formed in different processes. The first barrier portion forms a heterojunction structure with the channel layer. The material of the barrier layer is AlGaN. The PGaN active layer is located in the first trench and is in contact with the barrier layer; The gate is located on the side of the PGaN active layer away from the drift layer; The source electrode is located at least on the side of the second blocking portion of the current blocking layer away from the drift layer and is in contact with the heterojunction structure. The drain is located on the side of the drift layer away from the heterojunction structure.

2. The semiconductor device as claimed in claim 1, characterized in that, In the thickness direction of the semiconductor device, the bottom wall of the first trench is higher than the bottom surface of the current blocking layer on the side facing the drift layer.

3. The semiconductor device as described in claim 2, characterized in that, The top surface of the current blocking layer on the side away from the drift layer is at the same height as the top surface of the P-type modulation layer on the side away from the drift layer, or the top surface of the current blocking layer on the side away from the drift layer is higher than the top surface of the P-type modulation layer on the side away from the drift layer.

4. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device is a GaN power device with a PGaN structure, and the gate is a Schottky metal; and / or, The current blocking layer is made of P-type gallium nitride.

5. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes: A passivation layer is located on the side of the gate and the first barrier portion away from the drift layer; The source electrode is located on the side of the second blocking portion of the current blocking layer away from the drift layer and on the side of the passivation layer away from the drift layer.

6. A semiconductor device, characterized in that, The semiconductor device includes: Drift layer; A current blocking layer is disposed on the peripheral region of the surface of the drift layer on one side of the semiconductor device in the thickness direction, and the central region of the surface of the drift layer in which the current blocking layer is disposed is exposed from the center of the current blocking layer. The channel layer is located on the same side as the drift layer and the current blocking layer, and the channel layer covers the drift layer exposed from the middle of the current blocking layer and a portion of the width of the current blocking layer; the current blocking layer includes a first blocking portion that overlaps with the channel layer, and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer; The second trench penetrates the channel layer in the thickness direction of the semiconductor device; A barrier layer is located on the side of the channel layer away from the drift layer and in the second trench. The barrier layer includes a first barrier portion located on the side of the channel layer away from the drift layer and a second barrier portion located in the second trench. The first barrier portion and the second barrier portion are formed in different processes, and the first barrier portion forms a heterojunction structure with the channel layer. The material of the barrier layer is AlGaN. The PGaN active layer is located in the second trench and is in contact with the barrier layer; The gate is located on the side of the PGaN active layer away from the drift layer; The source electrode is located at least on the side of the second blocking portion of the current blocking layer away from the drift layer and is in contact with the heterojunction structure. The drain is located on the side of the drift layer away from the heterojunction structure.

7. The semiconductor device as claimed in claim 6, characterized in that, In the thickness direction of the semiconductor device, the bottom wall of the second trench is higher than the bottom surface of the current blocking layer on the side facing the drift layer; And / or, The semiconductor device is a GaN power device with a PGaN structure, and the gate is a Schottky metal; and / or, The current blocking layer is made of P-type gallium nitride; and / or, The semiconductor device further includes a passivation layer located on the side of the gate and the first barrier portion away from the drift layer; The source electrode is located on the side of the second blocking portion of the current blocking layer away from the drift layer and on the side of the passivation layer away from the drift layer.

8. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, and a drift layer is formed on one side of the substrate; A P-type modulation layer is formed in the central region of the surface of the drift layer on the side opposite to the substrate; A current blocking layer is formed on the surface of the drift layer opposite to the substrate, located around the P-type modulation layer; A channel layer, a first trench, a barrier layer, a PGaN active layer, and a gate are formed on the side of the P-type modulation layer and the current blocking layer away from the drift layer; the channel layer covers the P-type modulation layer and a portion of the width of the current blocking layer near the P-type modulation layer; the current blocking layer includes a first blocking portion that overlaps with the channel layer and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer; The first trench penetrates the channel layer and the P-type modulation layer in the thickness direction of the semiconductor device; The barrier layer is located on the side of the channel layer away from the drift layer and in the first trench. The barrier layer includes a first barrier portion located on the side of the channel layer away from the drift layer and a second barrier portion located in the first trench. The first barrier portion and the second barrier portion are formed in different processes. The first barrier portion and the channel layer form a heterojunction structure. The PGaN active layer is located in the first trench and is in contact with the barrier layer; The gate is located on the side of the PGaN active layer away from the drift layer; The material of the barrier layer is AlGaN; A source electrode is formed, wherein the source electrode is at least located on the side of the second blocking portion of the current blocking layer away from the drift layer and is in contact with the heterojunction structure; The substrate is removed and a drain is formed, the drain being located on the side of the drift layer opposite to the heterojunction structure.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, After providing the substrate and before forming a drift layer on one side of the substrate, the method includes: A nucleation layer and a buffer layer are formed on one side of the substrate. The nucleation layer is an AlN layer, and the buffer layer includes an AlGaN layer, an interleaved stacked multilayer AlN / GaN layer, a low-temperature GaN layer, and a high-temperature GaN layer sequentially stacked on the nucleation layer. The formation of a drift layer on one side of the substrate includes: A drift layer is formed on the side of the buffer layer opposite to the substrate.

10. The method for fabricating a semiconductor device as described in claim 9, characterized in that, The method further includes, during or after substrate removal but before drain formation: Remove the nucleation layer; or, Remove the nucleation layer and at least a portion of the buffer layer.

11. The method for fabricating a semiconductor device as described in claim 8, characterized in that, Before forming the source, the method further includes: A passivation layer is formed, the passivation layer being located on the side of the gate and the first barrier portion away from the drift layer; After the source is formed, the source is located on the side of the second blocking portion of the current blocking layer away from the drift layer and on the side of the passivation layer away from the drift layer.

12. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, and a drift layer is formed on one side of the substrate; A current blocking layer is formed in the peripheral region of the surface of the drift layer on one side of the semiconductor device in the thickness direction; the central region of the surface of the drift layer in which the current blocking layer is provided is exposed from the center of the current blocking layer; A channel layer, a second trench, a barrier layer, a PGaN active layer, and a gate are formed on the same side of the drift layer and the current blocking layer. The channel layer covers the drift layer exposed from the middle of the current blocking layer and a portion of the width of the current blocking layer. The current blocking layer includes a first blocking portion that overlaps with the channel layer and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer. The second trench penetrates the channel layer in the thickness direction of the semiconductor device. The barrier layer is located on the side of the channel layer away from the drift layer and in the second trench. The barrier layer includes a first barrier portion located on the side of the channel layer away from the drift layer and a second barrier portion located in the second trench. The first barrier portion and the second barrier portion are formed in different processes, and the first barrier portion forms a heterojunction structure with the channel layer. The PGaN active layer is located in the second trench; The gate is located on the side of the PGaN active layer away from the drift layer; The material of the barrier layer is AlGaN; A source electrode is formed, wherein the source electrode is at least located on the side of the second blocking portion of the current blocking layer away from the drift layer and is in contact with the heterojunction structure; The substrate is removed and a drain is formed, the drain being located on the side of the drift layer opposite to the heterojunction structure.

13. The method for fabricating a semiconductor device as described in claim 12, characterized in that, After providing the substrate and before forming a drift layer on one side of the substrate, the method includes: A nucleation layer and a buffer layer are formed on one side of the substrate. The nucleation layer is an AlN layer, and the buffer layer includes an AlGaN layer, an interleaved stacked multilayer AlN / GaN layer, a low-temperature GaN layer, and a high-temperature GaN layer sequentially stacked on the nucleation layer. The formation of a drift layer on one side of the substrate includes: A drift layer is formed on the side of the buffer layer opposite to the substrate; The method further includes, during or after substrate removal but before drain formation: Remove the nucleation layer; or, Remove the nucleation layer and at least a portion of the buffer layer.

14. The method for fabricating a semiconductor device as described in claim 12, characterized in that, Before forming the source, the method further includes: A passivation layer is formed, the passivation layer being located on the side of the gate and the first barrier portion away from the drift layer; After the source is formed, the source is located on the side of the second blocking portion of the current blocking layer away from the drift layer and on the side of the passivation layer away from the drift layer.

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