Solar cell and method of manufacture

Abstract

The present application relates to solar cells, and specifically provides a solar cell and a preparation method to improve the ohmic contact effect of the back electrode and the polysilicon layer. The preparation method of the solar cell provided by the present application comprises the following steps: providing a cell substrate, the cell substrate comprising a substrate and a first passivation layer and a polysilicon layer formed on the first surface of the substrate in sequence; forming an electron transport layer on the side of the polysilicon layer away from the substrate; annealing the electron transport layer to make the electron transport layer react with the polysilicon layer to form a metal silicide alloy layer; forming a second passivation layer on the side of the electron transport layer away from the substrate; forming an electrode, the electrode extending from the surface of the second passivation layer to the space between the electron transport layer and the first passivation layer, so that the electrode forms ohmic contact with the metal silicide alloy layer. The use of the metal silicide alloy layer can reduce the contact resistance between the polysilicon layer and the electrode, thereby improving the fill factor of the cell and ultimately improving the efficiency of the cell.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, and particularly provides a solar cell and a preparation method. BACKGROUND

[0002] At present, with the continuous consumption of traditional energy, energy problems have become an important issue of global concern, and the development of renewable energy has become the focus, among which solar energy has the advantages of being clean, safe, and resourceful, and gradually emerges as the main research and development focus. After decades of development, photovoltaic power generation technology has also made outstanding progress.

[0003] Among them, the TOPcon battery is a kind of solar cell, and the efficiency of the battery has broken through 26% or more, and has not yet reached the limit. The efficiency of the TOPcon battery (for example, in terms of improving the open circuit voltage and fill factor of the battery) still has a lot of room for improvement. The fill factor is the ratio of the product of the current and voltage when the battery has the maximum output power to the product of the short-circuit current and open-circuit voltage. The physical meaning of the fill factor is the uniformity of the electric field strength in the solar cell, and it can also be understood as the degree of resistance to the movement of electrons in the solar cell. The higher the fill factor, the smoother the flow of electrons in the battery, which can fully utilize solar energy to convert into electrical energy; on the contrary, the lower the fill factor, the more resistance to the flow of electrons in the solar cell, and the solar energy cannot be fully converted into electrical energy. Therefore, the fill factor can provide the actual performance of the output current and voltage of the solar cell, as well as the conversion efficiency of the solar cell.

[0004] In the structure of the TOPcon battery, the ohmic contact effect of the back electrode and the polysilicon layer is an important factor affecting the fill factor. The better the ohmic contact effect of the back electrode and the polysilicon layer, the higher the fill factor, and the higher the battery efficiency.

[0005] At present, the polysilicon layer is often heavily doped to improve the ohmic contact effect of the back electrode and the polysilicon layer, but the polysilicon layer with heavy doping absorbs more sunlight and has obvious parasitic absorption, which is not conducive to improving the battery efficiency.

[0006] Therefore, there is an urgent need for a solar cell and a preparation method to improve the ohmic contact effect of the back electrode and the polysilicon layer. SUMMARY

[0007] To solve the problems existing in the prior art, a solar cell and a preparation method are provided.

[0008] In a first aspect, the present application provides a method for manufacturing a solar cell, comprising: providing a cell substrate, the cell substrate comprising a substrate and a first passivation layer and a polysilicon layer formed on a first surface of the substrate in sequence; forming an electron transport layer on a side of the polysilicon layer away from the substrate; annealing the electron transport layer to make the electron transport layer react with the polysilicon layer to form a metal silicon compound alloy layer; forming a second passivation layer on a side of the electron transport layer away from the substrate; forming an electrode, the electrode extending from a surface of the second passivation layer to between the electron transport layer and the first passivation layer, so that the electrode forms an ohmic contact with the metal silicon compound alloy layer.

[0009] In the embodiment of the method for manufacturing a solar cell, the material of the electron transport layer is a metal compound, and the metal is at least one of molybdenum, nickel and titanium.

[0010] In the embodiment of the method for manufacturing a solar cell, the material of the electron transport layer is a metal nitride.

[0011] In the embodiment of the method for manufacturing a solar cell, the material of the electron transport layer is titanium nitride, the metal silicon compound alloy layer is a titanium silicon alloy layer, and the annealing temperature is 350-950°C.

[0012] In the embodiment of the method for manufacturing a solar cell, the thickness of the electron transport layer is 1 nm or more.

[0013] In the embodiment of the method for manufacturing a solar cell, the orthographic projection of the electrode on the substrate is within the orthographic projection of the electron transport layer on the substrate.

[0014] In the embodiment of the method for manufacturing a solar cell, the method further comprises: doping a second surface of the substrate to form a doped layer, and forming a third passivation layer and a fourth passivation layer on the doped layer in sequence.

[0015] In the embodiment of the method for manufacturing a solar cell, the polysilicon layer comprises a first polysilicon layer of a first doping type and a second polysilicon layer of a second doping type, the first polysilicon layer and the second polysilicon layer are insulated from each other, and the electron transport layer is formed on the first polysilicon layer and the second polysilicon layer.

[0016] In a second aspect, the present disclosure provides a solar cell, comprising: a substrate; a first passivation layer, a polysilicon layer, a metal silicide alloy layer, an electron transport layer and a second passivation layer sequentially arranged on a first surface of the substrate, the metal silicide alloy layer being arranged in the polysilicon layer; and an electrode extending from a surface of the second passivation layer to between the electron transport layer and the first passivation layer, and forming an ohmic contact with the metal silicide alloy layer.

[0017] In the above embodiment of the solar cell, the polysilicon layer and the substrate are of a first doping type, a second surface of the substrate has a doping layer of a second doping type, and a side of the doping layer away from the substrate sequentially has a third passivation layer and a fourth passivation layer; or the polysilicon layer comprises a first polysilicon layer and a second polysilicon layer insulated from each other, the first polysilicon layer and the second polysilicon layer are of opposite doping types, and the metal silicide alloy layer is arranged in the first polysilicon layer and the second polysilicon layer.

[0018] In the above embodiment of the solar cell, a projection of the electrode on the substrate is located within a projection of the electron transport layer on the substrate; or the electron transport layer has a thickness of 1 nm or more.

[0019] Compared with the prior art, the present application has the following beneficial effects:

[0020] The method for preparing the solar cell provided by the present disclosure comprises the following steps: providing a cell substrate, the cell substrate comprising a substrate and a first passivation layer and a polysilicon layer sequentially arranged on a first surface of the substrate; forming an electron transport layer on a side of the polysilicon layer away from the substrate; annealing the electron transport layer to make the electron transport layer react with the polysilicon layer to form a metal silicide alloy layer; forming a second passivation layer on a side of the electron transport layer away from the substrate; and forming an electrode extending from a surface of the second passivation layer to between the electron transport layer and the first passivation layer to make the electrode form an ohmic contact with the metal silicide alloy layer. The metal silicide alloy layer can reduce the contact resistance between the polysilicon layer and the electrode, thereby improving the fill factor of the cell and ultimately improving the efficiency of the cell.

[0021] Furthermore, the material of the electron transport layer is a metal nitride, and during the process of forming the metal silicide alloy layer by annealing, nitrogen atoms in the metal nitride can form nitrogen impurities, and the nitrogen atoms in the nitrogen impurities combine with hydrogen atoms to form nitrogen-hydrogen bonds, thereby capturing more hydrogen elements, improving the passivation performance of the cell, further improving the open-circuit voltage of the cell, and ultimately improving the efficiency of the cell. In addition, the nitrogen impurities can also inhibit the diffusion of phosphorus elements in the polysilicon layer, thereby improving the passivation effect of the polysilicon layer and ultimately improving the efficiency of the cell. BRIEF DESCRIPTION OF DRAWINGS

[0022] The preferred embodiments of the present application will be described below in conjunction with the accompanying drawings, in which:

[0023] Figure 1 is a flow chart of the solar cell preparation method provided by the present disclosure;

[0024] Figures 2A to 2E is a sectional view of a first solar cell in a preparation process of the present disclosure;

[0025] Figure 2F is a sectional view of the first solar cell provided by the present disclosure;

[0026] Figures 3A to 3E is a sectional view of a second solar cell in a preparation process of the present disclosure;

[0027] Figure 3F is a sectional view of the second solar cell provided by the present disclosure;

[0028] Figure 3G is a sectional view of a third solar cell provided by the present disclosure.

[0029] Explanation of reference signs:

[0030] 1, substrate; 11, doped layer; 2, first passivation layer; 3, polysilicon layer; 31, first polysilicon layer; 32, second polysilicon layer; 33, isolation region; 34, isolation groove; 4, third passivation layer; 5, fourth passivation layer; 6, second passivation layer; 7, electron transport layer; 8, metal silicon compound alloy layer; 91, first electrode; 92, second electrode. DETAILED DESCRIPTION

[0031] The preferred embodiments of the present application will be described below in conjunction with the accompanying drawings, in which:

[0032] It should be noted that, in the description of the present application, the terms "upper", "lower", "left", "right", "inner", "outer" and the like indicate the direction or positional relationship terms based on the direction or positional relationship shown in the drawings, which are merely for the convenience of description, and do not indicate or imply that the device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0033] Figure 1 is a flow chart of the solar cell preparation method provided by the present disclosure.

[0034] As Figure 1As shown, the present disclosure provides a preparation method of a solar cell, comprising: providing a cell substrate, the cell substrate comprising a substrate and a first passivation layer and a polysilicon layer formed on a first surface of the substrate in sequence; forming an electron transport layer on a side of the polysilicon layer away from the substrate; annealing the electron transport layer to make the electron transport layer react with the polysilicon layer to form a metal silicon compound alloy layer; forming a second passivation layer on a side of the electron transport layer away from the substrate; forming an electrode, the electrode extending from a surface of the second passivation layer to between the electron transport layer and the first passivation layer, so that the electrode forms an ohmic contact with the metal silicon compound alloy layer.

[0035] Next, the preparation method of the solar cell provided by the embodiment of the present disclosure is introduced.

[0036] Embodiment one

[0037] Figures 2A to 2E is a cross-sectional view of the first solar cell in the preparation process of the present disclosure; Figure 2F is a cross-sectional view of the first solar cell provided by the present disclosure. In this embodiment, the solar cell is specifically a TOPcon cell.

[0038] S1、as Figure 2A shown, a substrate 1 is provided, the substrate 1 has a first surface and a second surface opposite to the first surface, wherein the first surface is a back light surface and the second surface is a light receiving surface.

[0039] The substrate 1 is a semiconductor substrate 1 such as doped silicon or germanium. For example, the substrate 1 is an N-type doped silicon substrate, and the corresponding dopant can include any one or more of phosphorus (P), arsenic (As), bismuth (Bi) and antimony (Sb) in group V elements. For another example, the substrate 1 is a P-type doped silicon substrate, and the corresponding dopant can include any one or more of boron (B), aluminum (Al), gallium (Ga) and indium (In) in group III elements.

[0040] For example, the first surface and the second surface of the substrate 1 are textured; or the first surface and the second surface of the substrate 1 are textured, and then at least part of the first surface is polished to make the first surface have a planar structure or part of the first surface has a planar structure and part of the first surface has a textured structure. After the second surface is textured, the surface area and the surface complexity of the second surface can be increased, so as to reduce the reflection of incident light, thereby improving the short-circuit and current interruption of the cell, and further improving the photoelectric conversion efficiency of the cell. After the second surface of the substrate 1 is textured, the film layers formed on the second surface all have the same textured structure as the second surface.

[0041] For example, the substrate 1 is an N-type substrate 1, and the substrate 1 is immersed in a KOH or NaOH solution with a mass fraction of 1% to 3% and a temperature of 60°C to 80°C for texturing, and the control time for texturing is 15 min to 25 min.

[0042] S2, doping is performed on the second surface of the substrate 1 to form a doped layer 11 of a second doping type on the second surface.

[0043] For example, when the substrate 1 is N-type doped, the doping type of the doped layer 11 is P-type doping to form a PN junction. As a specific example, the N-type single crystal silicon substrate 1 is placed in a boron diffusion furnace tube for a boron diffusion process, and the process temperature for boron diffusion is 900°C to 1100°C. The boron diffusion can use trimethyl borate, boron tribromide, boron trichloride, or other boron sources. In the process of forming the boron doped layer 11 (i.e., the doped layer 11) on the second surface, a BSG (borosilicate glass) layer is naturally formed under the action of oxygen.

[0044] For example, the thickness of the doped layer 11 is 0.01 μm to 0.02 μm, and the sheet resistance is 100 ohm / sq to 180 ohm / sq.

[0045] It should be particularly noted that the present disclosure does not specifically limit the boron source, process temperature, and diffusion depth of the boron diffusion or phosphorus diffusion process, and those skilled in the art can design according to actual needs. The above limitations are only some specific examples.

[0046] S3, removing the boron diffusion layer diffused around the first surface while retaining the BSG layer on the second surface.

[0047] S4, sequentially forming a first passivation layer 2 and a doped polysilicon layer 3 on the first surface of the substrate 1 to form a structure as shown in Figure 2A The first passivation layer 2 can saturate the dangling bonds on the surface of the substrate 1, reduce the interface defect state density of the first surface of the substrate 1, thereby reducing the recombination centers on the first surface of the substrate 1, reducing the recombination rate of carriers, and ultimately increasing the open circuit voltage of the solar cell and improving the photoelectric conversion efficiency of the solar cell. The material of the first passivation layer 2 is a dielectric material, which can be at least one of silicon oxide, amorphous silicon, polysilicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. The first passivation layer 2 can contain a doping element of the same type as the doping element of the substrate 1.

[0048] The doping type of the polysilicon layer 3 is the same as that of the substrate 1. For example, when the substrate 1 is N-type doped, the doping type of the polysilicon layer 3 is also N-type, and the doping element is phosphorus. In addition, the polysilicon layer 3 can also be doped with one or more of oxygen, carbon, and nitrogen. For example, the thickness of the polysilicon layer 3 is 3-150 nm.

[0049] In some examples, the semiconductor structure prepared by steps S1-S4 can be used as a battery substrate to perform step S5 and subsequent steps.

[0050] S5. Forming an electron transport layer 7 on the side of the polysilicon layer 3 away from the substrate 1. The material of the electron transport layer 7 is a metal compound (such as a metal oxide or a metal nitride), wherein the metal is at least one of molybdenum, nickel, and titanium. For example, the material of the electron transport layer 7 is any one or more of titanium nitride, titanium oxide, molybdenum nitride, molybdenum oxide, nickel nitride, and nickel oxide.

[0051] In some examples, the electron transport layer 7 is formed on the entire polysilicon layer 3. In other examples, the electron transport layer 7 is formed only in a partial region on the polysilicon layer 3 by shielding with a mask plate, and the region where the electron transport layer 7 is formed corresponds to the back electrode of the battery, as shown in Figure 2B For example, the electron transport layer 7 is formed by magnetron sputtering.

[0052] S6. Annealing the electron transport layer 7 to make the electron transport layer 7 react with the polysilicon layer 3 to form a metal silicon compound alloy layer 8, as shown in Figure 2C The thickness of the electron transport layer 7 is greater than or equal to 1 nm to ensure that the electron transport layer 7 can react with the polysilicon layer 3 to form a metal silicon compound alloy layer 8 with sufficient thickness.

[0053] For example, when the material of the electron transport layer 7 is a metal compound of molybdenum, nickel, and titanium, the metal silicon compound alloy layer 8 is a molybdenum silicon alloy layer, a nickel silicon alloy layer, and a titanium silicon alloy layer, respectively.

[0054] In addition, when the electron transport layer 7 is a metal nitride, nitrogen atoms in the metal nitride can form nitrogen impurities during the annealing process to form a metal silicon compound. The nitrogen atoms in the nitrogen impurities combine with hydrogen atoms to form nitrogen-hydrogen bonds, thereby trapping more hydrogen elements, improving the passivation performance of the battery, and thus improving the open-circuit voltage of the battery, ultimately improving the efficiency of the battery. In addition, the nitrogen impurities can also inhibit the diffusion of phosphorus elements in the polysilicon layer 3, thereby improving the passivation effect of the polysilicon layer 3 and thus improving the efficiency of the battery.

[0055] As a specific example, the electron transport layer 7 is made of titanium nitride, and the annealing temperature is 350°C to 950°C, preferably 400°C to 900°C, to ensure that the electron transport layer 7 and the polycrystalline silicon layer 3 can fully react to form a titanium-silicon alloy layer.

[0056] S7, such as Figure 2D As shown, a third passivation layer 4 is formed on the side of the doped layer 11 away from the substrate 1.

[0057] As a specific example, the third passivation layer 4 is made of aluminum oxide and is formed by plasma-enhanced chemical vapor deposition. For example, a mixture of trimethylaluminum and oxygen or nitrogen oxide (i.e., a mixture of trimethylaluminum and oxygen, or a mixture of trimethylaluminum and nitrogen oxide) is introduced, and the reaction temperature is between 200°C and 350°C, thereby forming the third passivation layer 4 of aluminum oxide.

[0058] S8. A second passivation layer 6 is formed on the side of the electron transport layer 7 away from the substrate 1, and a fourth passivation layer 5 is formed on the side of the third passivation layer 4 away from the substrate 1. Wherein, when the electron transport layer 7 is only formed in a portion of the polysilicon layer 3 after being masked by a photomask, and the area where the electron transport layer 7 is formed corresponds to the back electrode of the battery, the second passivation layer 6 is specifically located on both the electron transport layer 7 and the exposed polysilicon layer 3, such as... Figure 2D As shown. The second passivation layer 6 and the fourth passivation layer 5 are also called anti-reflection layers, which mainly reduce the reflection of incident light to improve performance. They also have a certain passivation effect to improve the open-circuit voltage of the battery.

[0059] As a specific example, the second passivation layer 6 and the fourth passivation layer 5 are made of silicon nitride and are formed by plasma-enhanced chemical vapor deposition. For example, a mixed gas of SiH4 and NH3 is introduced, and the reaction temperature is between 300°C and 550°C, thereby forming the second passivation layer 6 and the fourth passivation layer 5 of silicon nitride.

[0060] S9. Form a first electrode 91 and a second electrode 92. The first electrode 91 extends from the surface of the fourth passivation layer 5 to the doped layer 11, and the second electrode 92 extends from the surface of the second passivation layer 6 to the space between the electron transport layer 7 and the first passivation layer 2 (i.e., extending into the metal-silicon compound alloy layer 8 or the polycrystalline silicon layer 3), forming an ohmic contact between the second electrode 92 and the metal-silicon compound alloy layer 8. The metal-silicon compound alloy layer reduces the contact resistance between the polycrystalline silicon layer 3 and the second electrode 92, thereby increasing the fill factor of the battery and ultimately improving the battery efficiency.

[0061] The specific process of forming the first electrode 91 and the second electrode 92 includes:

[0062] like Figure 2EAs shown, the metal paste on the second passivation layer 6 and the fourth passivation layer 5 is printed; the metal paste on the second passivation layer 6 is sintered to form ohmic contact with the doped layer 11 after etching the second passivation layer 6 and the first passivation layer 2, and the metal paste on the fourth passivation layer 5 is sintered to form ohmic contact with the metal silicide alloy layer 8 after etching the fourth passivation layer 5 and the electron transport layer 7. As shown in FIG. 9, the metal paste on the second passivation layer 6 forms the first electrode 91 after cooling, and the metal paste on the fourth passivation layer 5 forms the second electrode 92 after cooling. Figure 2F As shown, the metal paste on the second passivation layer 6 and the fourth passivation layer 5 is printed; the metal paste on the second passivation layer 6 is sintered to form ohmic contact with the doped layer 11 after etching the second passivation layer 6 and the first passivation layer 2, and the metal paste on the fourth passivation layer 5 is sintered to form ohmic contact with the metal silicide alloy layer 8 after etching the fourth passivation layer 5 and the electron transport layer 7. As shown in FIG. 9, the metal paste on the second passivation layer 6 forms the first electrode 91 after cooling, and the metal paste on the fourth passivation layer 5 forms the second electrode 92 after cooling.

[0063] In some possible examples, during the sintering process, the metal paste on the fourth passivation layer 5 can also etch part of the metal silicide alloy layer 8 and the polysilicon layer 3, so that the metal paste extends into the polysilicon layer 3. In this way, the second electrode 92 formed by the metal paste after cooling can form ohmic contact with the metal silicide alloy layer 8 and the polysilicon layer 3 at the same time.

[0064] For example, the orthogonal projection of the second electrode 92 on the substrate 1 is located in the orthogonal projection of the electron transport layer 7 on the substrate 1. When the metal paste for forming the second electrode 92 is printed, the metal paste is more likely to be aligned with the electron transport layer 7. In a specific embodiment, the grid line width of the mask plate used when forming the electron transport layer 7 is greater than the grid line width of the mask plate used when printing the metal paste for forming the second electrode 92.

[0065] In summary, the solar cell provided by the present disclosure has at least the following advantages:

[0066] (1) The electron transport layer 7 is formed on the polysilicon layer 3, and then the electron transport layer 7 is annealed to react with the polysilicon layer 3 to form the metal silicide alloy layer 8, and then the electrode is formed to form ohmic contact with the metal silicide alloy layer 8. The use of the metal silicide alloy layer can reduce the contact resistance between the polysilicon layer 3 and the second electrode 92, thereby improving the fill factor of the cell and ultimately improving the efficiency of the cell.

[0067] (2) The material of the electron transport layer 7 is metal nitride, and during the process of forming the metal silicide alloy by annealing, the nitrogen atoms in the metal nitride can form nitrogen impurities, and the nitrogen atoms in the nitrogen impurities combine with hydrogen atoms to form nitrogen-hydrogen bonds, thereby capturing more hydrogen elements, thereby improving the passivation performance of the cell, and further improving the open-circuit voltage of the cell, and ultimately improving the efficiency of the cell. In addition, the nitrogen impurities can also inhibit the diffusion of phosphorus elements in the polysilicon layer 3, thereby improving the passivation effect of the polysilicon layer 3 and improving the efficiency of the cell.

[0068] As shown in FIG. 9, the metal paste on the second passivation layer 6 and the fourth passivation layer 5 is printed; the metal paste on the second passivation layer 6 is sintered to form ohmic contact with the doped layer 11 after etching the second passivation layer 6 and the first passivation layer 2, and the metal paste on the fourth passivation layer 5 is sintered to form ohmic contact with the metal silicide alloy layer 8 after etching the fourth passivation layer 5 and the electron transport layer 7. As shown in FIG. 9, the metal paste on the second passivation layer 6 forms the first electrode 91 after cooling, and the metal paste on the fourth passivation layer 5 forms the second electrode 92 after cooling. Figure 2FAs shown, the embodiment of the present disclosure further provides a solar cell, which comprises a substrate 1. The substrate 1 has a first surface and a second surface, wherein the first surface is a back light surface and the second surface is a light receiving surface.

[0069] The second surface of the substrate 1 has a doped layer 11, and the doping type of the doped layer 11 is opposite to that of the substrate 1. For example, the doping type of the substrate 1 is N-type doping, and the doping type of the doped layer 11 is P-type doping, so as to form a PN junction.

[0070] The doped layer 11 is sequentially provided with a third passivation layer 4 and a fourth passivation layer 5 away from the substrate 1. The third passivation layer 4 is mainly used for passivating the doped layer 11. The fourth passivation layer 5 can not only strengthen the passivation effect of the light receiving surface of the cell, but also reduce the reflection of incident light, so that more sunlight can be absorbed by the solar cell, thereby increasing the short-circuit current of the cell, and also playing a certain passivation effect to improve the open-circuit voltage of the cell.

[0071] The first surface of the substrate 1 is sequentially provided with a first passivation layer 2 and a polysilicon layer 3 away from the substrate 1. The first passivation layer 2 can reduce the recombination rate of carriers, thereby increasing the open-circuit voltage of the solar cell, and ultimately improving the photoelectric conversion efficiency of the solar cell.

[0072] The polysilicon layer 3 is provided with a metal silicon compound alloy layer 8 and an electron transport layer 7. The material of the electron transport layer 7 is a metal compound (such as a metal oxide or a metal nitride), wherein the metal is at least one of molybdenum, nickel and titanium. The metal silicon compound alloy layer 8 is generated by the reaction of the metal atoms in the electron transport layer 7 with the polysilicon after annealing.

[0073] The exposed polysilicon layer 3 and the electron transport layer 7 are provided with a second passivation layer 6, which is used for passivating the back light surface of the cell.

[0074] The solar cell further comprises a first electrode 91 and a second electrode 92 which are insulated from each other. The first electrode 91 extends from the surface of the fourth passivation layer 5 to the doped layer 11, so that an ohmic contact is formed between the first electrode 91 and the doped layer 11. The second electrode 92 extends from the surface of the second passivation layer 6 to between the electron transport layer 7 and the first passivation layer 2 (i.e. into the metal silicon compound alloy layer 8 or the polysilicon layer 3), so that the second electrode 92 forms an ohmic contact with the metal silicon compound alloy layer 8. The use of the metal silicon compound alloy layer can reduce the contact resistance between the polysilicon layer 3 and the second electrode 92, thereby improving the fill factor of the cell and ultimately improving the efficiency of the cell.

[0075] Embodiment two

[0076] Figures 3A to 3E is a sectional view of a second solar cell of the present disclosure during preparation. Figure 3Fis a sectional view of a second solar cell provided by the present disclosure. Figure 3G is a sectional view of a third solar cell provided by the present disclosure. The solar cell in this embodiment is specifically a TBC (TOPCon back contact) cell.

[0077] The preparation method of the solar cell provided by the embodiments of the present disclosure is specifically as follows:

[0078] S1, as shown in Figure 3A , a substrate 1 is provided. The substrate 1 has a first surface and a second surface opposite to the first surface. Among them, the first surface of the substrate 1 is a back light surface, and the second surface of the substrate 1 is a light surface. The doping type of the substrate 1 can be P-type doping or N-type doping.

[0079] S2, the second surface of the substrate 1 is textured to reduce the reflection of incident light, thereby improving the short-circuit breaking of the cell and further improving the photoelectric conversion efficiency of the cell. After the second surface of the substrate 1 is textured, the film layers formed on the second surface all have the same textured structure as the second surface.

[0080] The first surface of the substrate 1 is also textured or polished.

[0081] S3, the third passivation layer 4 and the fourth passivation layer 5 are sequentially formed on the second surface of the substrate 1. For example, the method of forming the third passivation layer 4 and the fourth passivation layer 5 is the same as that of the first embodiment.

[0082] S4, the first passivation layer 2 and the intrinsic polysilicon layer 3 are sequentially formed on the first surface of the substrate 1, forming a structure as shown in Figure 3A . The material of the first passivation layer 2 is a dielectric material, which can be at least one of silicon oxide, amorphous silicon, polysilicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide or titanium oxide.

[0083] For example, the first passivation layer 2 and the intrinsic polysilicon layer 3 are formed by using LPCVD (Low Pressure Chemical Vapor Deposition).

[0084] S5, as shown in Figure 3B , the intrinsic polysilicon layer 3 is doped to form a first polysilicon layer 31 of a first doping type and a second polysilicon layer 32 of a second doping type, respectively. Among them, the first polysilicon layer 31 and the second polysilicon layer 32 have an isolation region 33 therebetween to ensure electrical insulation between the first polysilicon layer 31 and the second polysilicon layer 32.

[0085] S6, as shown in Figure 3CAs shown, an electron transport layer 7 is formed on the side of the polysilicon layer 3 away from the substrate 1, wherein the first polysilicon layer 31 and the second polysilicon layer 32 both have electron transport layers 7. As an example, the electron transport layer 7 is formed only in a portion of the first polysilicon layer 31 and the second polysilicon layer 32 after being shielded by a photomask, and the region where the electron transport layer 7 is formed corresponds to the back electrode of the battery.

[0086] The electron transport layer 7 is made of a metal compound (such as a metal oxide or a metal nitride), wherein the metal is at least one of molybdenum, nickel, and titanium. For example, the electron transport layer 7 is made of any one or more of titanium nitride, titanium oxide, molybdenum nitride, molybdenum oxide, nickel nitride, and nickel oxide.

[0087] S7, such as Figure 3D As shown, the electron transport layer 7 is annealed to react with the polysilicon layer 3 to form a metal-silicon compound alloy layer 8. The thickness of the electron transport layer 7 is greater than 1 nm to ensure that it can react with the polysilicon layer 3 to form a sufficiently thick metal-silicon compound alloy layer 8.

[0088] For example, when the electron transport layer 7 is made of metal compounds of molybdenum, nickel, and titanium, the metal silicon compound alloy layer 8 is a molybdenum silicon alloy layer, a nickel silicon alloy layer, and a titanium silicon alloy layer.

[0089] Furthermore, when the electron transport layer 7 is a metal nitride, nitrogen atoms in the metal nitride can form nitrogen impurities during the annealing process to form a metal silicon compound. Nitrogen atoms in these impurities combine with hydrogen atoms to form nitrogen-hydrogen bonds, thereby capturing more hydrogen elements, improving the passivation performance of the battery, increasing the open-circuit voltage, and ultimately improving the battery efficiency. Additionally, nitrogen impurities can suppress the diffusion of phosphorus elements in the polycrystalline silicon layer 3, thereby improving the passivation effect of the polycrystalline silicon layer 3 and further enhancing the battery efficiency.

[0090] As a specific example, the electron transport layer 7 is made of titanium nitride, and the annealing temperature is 350°C to 950°C, preferably 400°C to 900°C, to ensure that the electron transport layer 7 and the polycrystalline silicon layer 3 can fully react to form a titanium-silicon alloy layer.

[0091] S8, such as Figure 3E As shown, a second passivation layer 6 is formed on the side of the electron transport layer 7 away from the substrate 1. The second passivation layer 6 is specifically located on the electron transport layer 7 and the exposed polysilicon layer 3.

[0092] S9, forming the first electrode 91 and the second electrode 92.

[0093] Among them, such as Figure 3FAs shown, the first electrode 91 extends from the surface of the second passivation layer 6 to the space between the electron transport layer 7 and the first passivation layer 2, and forms an ohmic contact with the metal-silicon compound alloy layer 8 located within the first polysilicon layer 31; the second electrode 92 extends from the surface of the second passivation layer 6 to the space between the electron transport layer 7 and the first passivation layer 2, and forms an ohmic contact with the metal-silicon compound alloy layer 8 located within the second polysilicon layer 32. The use of the metal-silicon compound alloy layer can reduce the contact resistance between the first polysilicon layer 31 and the first electrode 91, as well as the contact resistance between the second polysilicon layer 32 and the second electrode 92, thereby improving the fill factor of the battery and ultimately increasing the battery efficiency.

[0094] The materials of the first electrode 91 and the second electrode 92 include, but are not limited to, one or more of aluminum, titanium, nickel, cobalt, silver, copper, and tin. The first electrode 91 and the second electrode 92 may be formed by screen printing, laser transfer, or electroplating. In the embodiments of this application, the first electrode 91 and the second electrode 92 can be understood as metal grid lines, and the width and thickness of the metal grid lines are not limited.

[0095] like Figure 3F As shown, some embodiments of this disclosure also provide a solar cell, including a substrate 1. The substrate 1 has a first surface and a second surface, the first surface being a backlight surface and the second surface being a light-facing surface.

[0096] A third passivation layer 4 and a fourth passivation layer 5 are sequentially disposed on the second surface of the substrate 1. Sunlight enters the substrate 1 through the fourth passivation layer 5 and the third passivation layer 4. The sunlight reflected by the substrate 1 is reflected again by the fourth passivation layer 5 and the third passivation layer 4 and then returns to the substrate 1, thereby improving the light absorption efficiency of the solar cell.

[0097] A first passivation layer 2 and a polysilicon layer 3 are sequentially disposed on the first surface of the substrate 1.

[0098] The first passivation layer 2 can reduce the recombination rate of charge carriers, thereby increasing the open-circuit voltage of the solar cell and ultimately improving the photoelectric conversion efficiency of the solar cell.

[0099] The polysilicon layer 3 includes a first polysilicon layer 31 and a second polysilicon layer 32 that are insulated from each other. The first polysilicon layer 31 and the second polysilicon layer 32 have opposite doping types; for example, the first polysilicon layer 31 is P-type doped and the second polysilicon layer 32 is N-type doped.

[0100] In some examples, such as Figure 3F As shown, there is an isolation region 33 between the first polysilicon layer 31 and the second polysilicon layer 32. The isolation region 33 contains undoped intrinsic polysilicon, and the intrinsic polysilicon layer 3 in the isolation region 33 isolates the first polysilicon layer 31 and the second polysilicon layer 32.

[0101] In some examples, as shown in FIG. 1, the first polysilicon layer 31 and the second polysilicon layer 32 are separated by an isolation groove 34. Figure 3G

[0102] The first polysilicon layer 31 and the second polysilicon layer 32 are both provided with a metal silicide alloy layer 8 and an electron transport layer 7. The material of the electron transport layer 7 is a metal compound (such as a metal oxide or a metal nitride), wherein the metal is at least one of molybdenum, nickel, and titanium. The metal silicide alloy layer 8 is generated by the reaction of the metal atoms in the electron transport layer 7 with the polysilicon after annealing.

[0103] The exposed first polysilicon layer 31, the exposed second polysilicon layer 32, and the electron transport layer 7 are provided with a second passivation layer 6, which is used to passivate the back surface of the cell.

[0104] The solar cell further includes a first electrode 91 and a second electrode 92 which are insulated from each other. The first electrode 91 extends from the surface of the second passivation layer 6 to between the electron transport layer 7 and the first passivation layer 2, and forms an ohmic contact with the metal silicide alloy layer 8 located in the first polysilicon layer 31. The second electrode 92 extends from the surface of the second passivation layer 6 to between the electron transport layer 7 and the first passivation layer 2, and forms an ohmic contact with the metal silicide alloy layer 8 located in the second polysilicon layer 32. The use of the metal silicide alloy layer can reduce the contact resistance between the first polysilicon layer 31 and the first electrode 91 and the contact resistance between the second polysilicon layer 32 and the second electrode 92, thereby improving the fill factor of the cell and ultimately improving the efficiency of the cell.

[0105] The following points need to be explained:

[0106] (1) The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0107] (2) For the sake of clarity, the thickness of the layers or regions is exaggerated or reduced in the drawings used to describe the embodiments of the present disclosure, i.e., these drawings are not drawn according to the actual proportions.

[0108] (3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0109] ​The technical scheme of the present application has been described in combination with the preferred embodiments shown in the drawings, but it is easy for those skilled in the art to understand that the protection scope of the present application is obviously not limited to these specific embodiments. Those skilled in the art can make equivalent changes or replacements to the related technical features without departing from the principles of the present application, and the technical schemes after the changes or replacements will all fall within the protection scope of the present application.

Claims

1. A method for producing a solar cell, characterized by, include: A battery substrate is provided, the battery substrate comprising a substrate and a first passivation layer and a polycrystalline silicon layer sequentially formed on a first surface of the substrate; An electron transport layer is formed on the side of the polysilicon layer away from the substrate; The electron transport layer is annealed to react with the polycrystalline silicon layer to form a metal-silicon compound alloy layer. A second passivation layer is formed on the side of the electron transport layer away from the substrate; An electrode is formed, which extends from the surface of the second passivation layer to the space between the electron transport layer and the first passivation layer, so that the electrode forms an ohmic contact with the metal silicon compound alloy layer; The electron transport layer is made of a metal nitride, and the metal is at least one of molybdenum, nickel, and titanium.

2. The method of producing a solar cell according to claim 1, wherein The electron transport layer is made of titanium nitride, the metal silicon compound alloy layer is a titanium silicon alloy layer, and the annealing temperature is 350°C to 950°C.

3. The method of claim 1, wherein the method further comprises: The thickness of the electron transport layer is greater than 1 nm.

4. The method of producing a solar cell according to claim 1, wherein The orthogonal projection of the electrode on the substrate lies within the orthogonal projection of the electron transport layer on the substrate.

5. The method of producing a solar cell according to claim 1, wherein The preparation method further includes: The second surface of the substrate is doped to form a doped layer, and a third passivation layer and a fourth passivation layer are sequentially formed on the doped layer.

6. The method of producing a solar cell according to claim 1, wherein The polysilicon layer includes a first polysilicon layer of a first doping type and a second polysilicon layer of a second doping type, wherein the first polysilicon layer and the second polysilicon layer are insulated from each other; The electron transport layer is formed on the first polysilicon layer and the second polysilicon layer.

7. A solar cell, characterized by include: Substrate; A first passivation layer, a polycrystalline silicon layer, a metal-silicon compound alloy layer, an electron transport layer, and a second passivation layer are sequentially disposed on the first surface of a substrate, wherein the metal-silicon compound alloy layer is located within the polycrystalline silicon layer; An electrode extends from the surface of the second passivation layer to the space between the electron transport layer and the first passivation layer, and an ohmic contact is formed between the electrode and the metal silicide. The electron transport layer is made of a metal nitride, and the metal is at least one of molybdenum, nickel, and titanium.

8. The solar cell according to claim 7, characterized in that, The polycrystalline silicon layer and the substrate are of a first doping type, the second surface of the substrate has a doped layer of a second doping type, and a third passivation layer and a fourth passivation layer are sequentially disposed on the side of the doped layer away from the substrate; or, The polycrystalline silicon layer includes a first polycrystalline silicon layer and a second polycrystalline silicon layer that are insulated from each other. The first polycrystalline silicon layer and the second polycrystalline silicon layer have opposite doping types. The metal silicon compound alloy layer is disposed in both the first polycrystalline silicon layer and the second polycrystalline silicon layer.

9. The solar cell according to claim 7 or 8, characterized in that, The orthographic projection of the electrode on the substrate lies within the orthographic projection of the electron transport layer on the substrate; or... The thickness of the electron transport layer is greater than 1 nm.

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