Method for preparing high-voltage light-emitting diode with reduced leakage risk

Abstract

The present invention relates to the technical field of light-emitting diode chip preparation, specifically to high-voltage light-emitting diodes with reduced leakage risk and their preparation methods. The method includes sequentially growing an N-type GaN layer, a light-emitting quantum well, and a P-type GaN layer on a substrate; fabricating N-region steps, insulating etched tracks, and insulating protection holes; and etching to form current blocking layers and current spreading layers. This improves reliability, reduces gold wire bonding, reduces the need for safety diodes, and achieves efficient current distribution.

Description

Technical Field

[0001] The present invention relates to the technical field of light-emitting diode chip preparation, and in particular to a high-voltage light-emitting diode with reduced leakage risk and a preparation method thereof. Background Art

[0002] Currently, in the design of high-voltage LED chips, multiple normal-voltage chips are usually connected in series to meet high-voltage working requirements. However, this design has the following problems:

[0003] Complex gold wire bonding: The series connection of multiple normal voltage chips requires a large amount of gold wire bonding, which increases the complexity and cost of the production process;

[0004] Safety protection diodes are required: To ensure chip safety in the event of unit failure, additional safety protection diodes are often required. This not only increases costs but can also affect the overall performance and efficiency of the chip.

[0005] Reliability issues: In existing high-voltage LED chip designs, each chip typically contains multiple cell groups connected in series. If one cell group short-circuits or burns out, the entire high-voltage LED chip will fail.

[0006] For example, a multi-crystal string high-voltage LED chip disclosed in publication number CN109461724A has a low reliability due to the series structure design, because the failure of any unit group will affect the normal operation of the entire chip, seriously affecting the stability and reliability of the LED lamp. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a high-voltage light-emitting diode and a preparation method thereof that reduces the risk of leakage.

[0008] The technical solution adopted by the present invention to solve the technical problem is: a method for preparing a high-voltage light-emitting diode with reduced leakage risk includes:

[0009] An N-type GaN layer, a light-emitting quantum well, and a P-type GaN layer are sequentially grown on the substrate;

[0010] Make N-region steps, insulation etching paths and insulation protection holes;

[0011] The current blocking layer and the current spreading layer are formed by etching.

[0012] The N-region steps, insulating etching paths and insulating protection holes are manufactured using plasma etching technology.

[0013] The current blocking layer and the current spreading layer are formed by wet etching.

[0014] The current blocking layer and the insulating protection hole are deposited with SiO2 by PECVD technology, and the ITO layer is prepared by sputtering method.

[0015] The electrodes of the light-emitting diode are formed by electron beam evaporation and adopt a multilayer structure of chromium-aluminum-chromium-platinum-gold.

[0016] The insulating etching track has an etching depth reaching the substrate;

[0017] The insulating etching path is bevel-type, with an inclination angle ranging from 30° to 50°.

[0018] After the insulating etching path is completed, the side is first insulated, and then the subsequent electrode bridging is carried out.

[0019] During the insulation treatment, SiO2 or Si3N4 is used for passivation insulation. SiO2 is deposited by PECVD at the same time as the current blocking layer, with a deposition thickness of 3000 Å ~4500 Å, and then photolithography and BOE wet etching are performed.

[0020] It also includes the simultaneous production of electrode bridge layers and metal electrode layers:

[0021] First use negative resist for photolithography,

[0022] Then evaporate chromium, aluminum, chromium, platinum, gold,

[0023] Finally, the stripping process is performed.

[0024] A high-voltage light-emitting diode with reduced leakage risk is prepared using the above-mentioned method for preparing a high-voltage light-emitting diode with reduced leakage risk. The prepared light-emitting diode chip includes at least two chip units, and the chip units are connected in parallel through two parallel units.

[0025] N-region steps are etched on both the chip unit and the parallel unit. The chip unit and the parallel unit are connected based on metal electrode plating. The side walls and dividing parts of the chip unit and the parallel unit are plated with an insulating layer.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] Improve reliability: By connecting some unit group chips in parallel, even if one unit group fails, the other unit groups can still work normally, ensuring the stability and reliability of the high-voltage LED chip;

[0028] Reduced gold wire bonding: The optimized chip structure reduces the gold wire bonding required for connecting multiple normal-voltage chips in series, simplifies the production process, and reduces production costs;

[0029] Reduce the need for additional safety protection diodes: The optimized high-voltage chip structure eliminates the need for additional safety protection diodes, reducing overall costs and improving system efficiency.

[0030] Efficient current distribution: Through the rational design of the insulating etching path, N-region steps, current blocking layer and current expansion layer, the current distribution is made more uniform, thereby improving the chip's luminous efficiency and working stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a structural schematic diagram of the present invention.

[0032] In the figure: 1. Insulation etching track; 2. N-region step; 3. Current blocking layer; 4. Current spreading layer; 5. Metal electrode layer; 6. Insulation protection hole; 7. Chip unit; 8. Parallel unit. DETAILED DESCRIPTION

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0034] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0035] In the present invention, unless otherwise specified or limited, the terms "connection" and "fixation" should be understood in a broad sense. For example, "fixation" can mean fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will be able to understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0036] The usual high-voltage chip design is a series structure, which has a simple structure and uniform current distribution. However, if one of the unit groups burns out and breaks the circuit, the entire chip will fail. Usually, the design of high-voltage chips is to optimize the design of multiple normal-voltage chips in series in general lighting products, which increases the cost of gold wire bonding. Therefore, the usage scenario usually requires low lighting brightness. This optimization design optimizes the high-voltage layout design and designs several unit groups in parallel. Multiple electrodes are connected from one unit group to several parallel unit groups. Under this design, the current in the parallel area is reduced during normal use, and the possibility of burning is reduced; therefore, the width of the metal electrode can be reduced to increase the light-emitting area and reduce the cost of precious metals. If one of the parallel unit groups fails, the chip lamp can still be lit and used normally. Specifically,

[0037] Reference Figure 1 The method for preparing a high-voltage light-emitting diode with reduced leakage risk includes:

[0038] An N-type GaN layer, a light-emitting quantum well, and a P-type GaN layer are sequentially grown on a substrate. This application employs organic chemical vapor deposition (MOCVD) technology to sequentially grow the N-type GaN layer (NG) to reduce the risk of leakage in a high-voltage light-emitting diode (N) (N-type GaN layer), the light-emitting quantum well, and the P-type GaN layer (PG) to reduce the risk of leakage in a high-voltage light-emitting diode (N) (P-type GaN layer). The substrate may be a sapphire substrate.

[0039] The N-region step 2, the insulating etched track 1 and the insulating protection hole 6 are manufactured; the N-region step 2, the insulating etched track 1 and the insulating protection hole 6 are manufactured by adopting the plasma etching ICP technology.

[0040] The current blocking layer 3 and the current spreading layer 4 are formed by wet etching. The current blocking layer 3 and the insulating protection hole 6 are deposited with SiO2 using PECVD technology, and the current spreading layer 4 is prepared by sputtering.

[0041] The electrodes of the light-emitting diode are formed by electron beam evaporation, using a multilayer structure of chromium-aluminum-chromium-platinum-gold. This application simplifies the manufacturing process and reduces costs by combining the sidewall insulation function and the bridge electrode layer with the current blocking layer and electrode production process.

[0042] The etching depth of the insulating etching track 1 reaches the substrate;

[0043] The insulating etching track 1 is of a bevel type, with an inclination angle ranging from 30° to 50°.

[0044] The unit position and area size are determined by the etching path. This application uses dry etching, and the depth needs to reach the sapphire substrate. The epitaxial wafer structure is usually about 7μm. The morphology of the insulating etching path is crucial to the subsequent process and the optoelectronic properties of the device. It can be designed as a bevel type with an inclination angle controlled between 30° and 50°. The designed insulating etching path has a depth of 7μm. After etching, the bottom width of the groove is about 9μm, the upper width is about 30μm, and the inclination angle is about 35°. And it is connected in parallel structure.

[0045] The following further describes the process of manufacturing the current blocking layer 3 as a sidewall protection and current blocking layer and the electrode. After the insulating etching path 1 is completed, the side edges are firstly insulated, and then the subsequent electrode bridging is performed.

[0046] Furthermore, in the insulation treatment of the present application, SiO2 or Si3N4 is used for passivation insulation, and SiO2 is deposited by PECVD at the same time as the current blocking layer 3, with a deposition thickness of 3000 Å ~ 4500 Å, and then photolithography and BOE wet etching are performed.

[0047] In addition, the present invention simultaneously manufactures the electrode bridge layer and the metal electrode layer 5; specifically, firstly, a negative photoresist is used for photolithography.

[0048] Then evaporate chromium, aluminum, chromium, platinum, gold,

[0049] Finally, the peeling process is carried out. The final electrode bridging effect is as follows Figure 1 Compared to separately fabricating sidewall insulation layers and bridging electrode layers, combining them with the CBL and P to reduce leakage risk in the high-voltage LED (D) manufacturing process can effectively reduce process steps and save costs. The high-strength bridging electrode layer ensures stable and reliable electrical interconnection between light-emitting units, thereby improving the reliability and lifespan of high-voltage LED devices. The parallel design helps optimize current distribution.

[0050] The present application realizes the differentiated connection of chip unit groups through the above design. Specifically, the insulating etching path is etched cleanly by ion etching to clean all GaN on the sapphire substrate, so that a chip is Figure 1 The CMOS is divided into independent small units, and then the small units are connected through the metal electrode layer 5. The design of the metal electrode layer 5 can be compared with the equivalent circuit to achieve the purpose of unit parallel connection.

[0051] A high-voltage light-emitting diode with reduced leakage risk is prepared using the above-mentioned method for preparing a high-voltage light-emitting diode with reduced leakage risk. The prepared light-emitting diode chip includes at least two chip units 7, and the chip units 7 are connected in parallel through two parallel units 8.

[0052] N-region steps are etched on both the chip unit 7 and the parallel unit 8. The chip unit 7 and the parallel unit 8 are connected based on metal electrode plating. The side walls and dividing parts of the chip unit 7 and the parallel unit 8 are plated with an insulating layer.

[0053] In this application, ICP etching is used to remove the N epitaxial layer of the high-voltage light-emitting diode G to reduce the risk of leakage. After a chip structure is divided into multiple unit groups, an N-region step is etched in each unit group so that each unit group can be powered on and emit light after the P and N electrodes are connected. The method of connecting the various unit groups is to connect the N electrode of one unit to the P electrode of the second unit through metal electrode plating, for example, and then connect multiple chip unit groups in sequence. In order to prevent the metal electrode from contacting the side walls of each unit group during plating and causing leakage, an insulating layer (SiO2 or Si3N4) is plated on the side walls and dividing points to prevent leakage.

[0054] The above descriptions are merely optional embodiments of the present invention and do not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present description and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A method for preparing a high-voltage light-emitting diode with reduced leakage risk, characterized in that: include An N-type GaN layer, a light-emitting quantum well, and a P-type GaN layer are sequentially grown on the substrate; Producing N-region steps (2), insulating etching paths (1) and insulating protection holes (6); Etching to form a current blocking layer (3) and a current spreading layer (4); After the insulating etching path (1) is completed, the side is first insulated, and then the subsequent electrode bridging is carried out; It also includes the simultaneous production of an electrode bridge layer and a metal electrode layer (5): firstly performing photolithography with a negative photoresist, then evaporating chromium, aluminum, chromium, platinum, and gold, and finally performing a lift-off process; The prepared light-emitting diode chip comprises at least two chip units (7), the chip units (7) are connected in parallel via two parallel units (8), N-region steps are etched on both the chip unit (7) and the parallel unit (8), the chip unit (7) and the parallel unit (8) are connected based on metal electrode plating, and the side walls and dividing portions of the chip unit (7) and the parallel unit (8) are plated with an insulating layer.

2. The method for preparing a high-voltage light-emitting diode with reduced leakage risk according to claim 1, characterized in that: The N-region step (2), the insulating etching path (1) and the insulating protection hole (6) are manufactured using plasma etching technology.

3. The method for preparing a high-voltage light-emitting diode with reduced leakage risk according to claim 1, characterized in that: The current blocking layer (3) and the current spreading layer (4) are formed by wet etching.

4. The method for preparing a high-voltage light-emitting diode with reduced leakage risk according to claim 1, characterized in that: The current blocking layer (3) and the insulating protection hole (6) are prepared by depositing SiO2 using PECVD technology, and the ITO layer is prepared by a sputtering method.

5. The method for preparing a high-voltage light-emitting diode with reduced leakage risk according to claim 1, characterized in that: The electrodes of the light-emitting diode are formed by electron beam evaporation and adopt a multilayer structure of chromium-aluminum-chromium-platinum-gold.

6. The method for preparing a high-voltage light-emitting diode with reduced leakage risk according to claim 1, characterized in that: The insulating etching path (1) has an etching depth reaching the substrate; The insulating etching path (1) is of an inclined surface type, and the inclination angle ranges from 30° to 50°.

7. The method for preparing a high-voltage light-emitting diode with reduced leakage risk according to claim 1, characterized in that: During the insulation treatment, SiO2 or Si3N4 is used for passivation insulation. SiO2 is deposited by PECVD at the same time as the current blocking layer (3). The deposition thickness is And perform photolithography and BOE wet etching.

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