A method for preparing a TCC-VCSEL containing a transversely coupled cavity

Abstract

This application discloses a method for preparing a high-speed, directly modulated, transversely coupled cavity (TCC-VCSEL) laser. The epitaxial structure of the VCSEL chip comprises, from top to bottom, an n-type GaAs substrate, an n-type buffer layer, an n-DBR layer, an active layer including quantum wells and barrier layers, a first p-DBR layer with arsenic ions implanted in a selective region defined by an oxide confinement layer window, an oxide confinement layer, a second p-DBR layer, and a highly doped p-contact layer. Two interconnected square oxide confinement windows form a normal VCSEL light-emitting window and a feedback cavity for the transversely coupled cavity that provides optical feedback. This application can effectively control the size of the VCSEL oxide confinement window, and in particular, can precisely control the size of the transversely coupled cavity and improve its uniformity, thereby increasing the VCSEL bandwidth and improving the yield. This allows low-cost VCSEL lasers to meet the needs of high-speed communications and reduce the cost of communication systems.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor laser technology, and in particular relates to a method for preparing a TCC-VCSEL containing a transversely coupled cavity. Background Art

[0002] Vertical-cavity surface-emitting lasers (VCSELs) are widely used in laser printing, optical storage, high-density optical storage and readout, free-space optical interconnection, and high-speed data transmission in single-mode optical fibers due to their advantages such as good monochromaticity, small divergence angle, single-longitudinal-mode lasing, low threshold current, high modulation bandwidth, easy coupling with optical fibers, ease of high-density integration, wafer-level detection, and low cost.

[0003] However, the maximum speed of directly modulated VCSELs is limited by the inherent limits of the relaxation oscillation frequency and its parasitic capacitance. Because the drive current increases with the square root of the resonant frequency, high current density is required to increase the modulation bandwidth, which leads to long-term reliability issues. Consequently, conventional VCSELs struggle to exceed 10 Gbps.

[0004] The photon-photon resonance (PPR) effect in the small-signal modulation response of single-mode edge-emitting semiconductor lasers, such as DBR edge-emitting semiconductor lasers, has been exploited to significantly increase the modulation bandwidth by 3 dB, exceeding the relaxation oscillation frequency. VCSELs using a transversely coupled cavity (TCC) can similarly increase bandwidth by a factor of three compared to conventional VCSELs by leveraging PPR feedback. For example, a bowtie TCC-VCSEL consists of two square oxide windows joined at one corner, forming a "bowtie" shape. One square is the normal VCSEL emission window, while the other is a transversely coupled cavity, connected by a narrow channel and insulated from each other by ion implantation. The oxide interface of the feedback cavity acts as a perfect lateral mirror, coupling lateral light back into the VCSEL emission window. To form the transversely coupled cavity structure, a bowtie-shaped mesa is formed by dry etching, followed by a wet oxidation process. The basic principle of bandwidth enhancement is the same as that of DBR lasers with extended cavities: providing photon-photon resonance in the small-signal modulation response. Due to slow light propagation, feedback cavities several micrometers long are sufficient to accommodate photon-photon resonances with spacings of tens of GHz (see APPLIED PHYSICS LETTERS 103, 091109, 2013). Because modulation bandwidth is achieved through the PPR effect, bandwidth enhancement is extremely sensitive to the lateral feedback cavity size. Modeling suggests that increasing the bowtie width from 0.5μm to 2μm reduces the lateral coupling strength from 98% to 50% (see SPIE Photonics West 2013, 2013, 8639-31). Therefore, in practical applications, the control of the oxide confinement window size and uniformity in TCC-VCSELs is extremely stringent.

[0005] Controlling the oxide confinement window of VCSELs is extremely complex. Strict control of the AlAs mole fraction, water (bath) temperature, sample temperature, and gas flow rate is crucial for repeatable and uniform oxide-confined VCSEL fabrication (see J. Phys. D: Appl. Phys. 56 (2023), 154002). Due to the nonuniformity of the epitaxial material composition during growth, this can lead to nonuniform wet thermal oxidation rates. Furthermore, dry etching can also cause nonuniformity in the shape of the etched mesas. To date, using the most advanced selective wet oxidation equipment and processes, the oxide window uniformity for 4-inch wafers is + / - 0.6 μm, and for 6-inch wafers is + / - 0.8 μm. However, the narrowest point of a bowtie-type laterally coupled cavity is only 0.5-3 μm. Therefore, current oxidation processes cannot meet the performance and yield requirements of TCC-VCSELs containing laterally coupled cavities.

[0006] Alternatively, proton implantation can be used to form a conductive confinement window in a VCSEL. Proton damage to the semiconductor material creates an insulating layer around the window, thus limiting the current injection region of the VCSEL device (see ELECTRONICSLETTERS, May 13, 1993, Vol. 29, No. 10, pp. 918-919). Because the proton implantation region is determined by the photolithography process, the proton implantation mask can be easily controlled to an accuracy and uniformity of ±0.1 μm. However, this method only provides conductive confinement. Laterally coupled cavities also require a difference in the refractive index of the materials. Typically, the oxide interface of the feedback cavity acts as a perfect lateral mirror to couple lateral light into the VCSEL, providing photon-photon resonance in the small-signal modulation reaction, thereby enhancing bandwidth. However, since proton implantation only provides current confinement and not optical emission, this method cannot be applied to the fabrication of VCSELs containing laterally coupled cavities. Summary of the Invention

[0007] The purpose of this application is to propose a method for fabricating a high-speed, directly modulated, transversely coupled cavity TCC-VCSEL. This method can significantly increase the oxidation rate of the oxide confinement layer grown on the first p-DBR by injecting arsenic ions into it. This difference in oxidation rate can make the oxidation process of the VCSEL confinement window a nearly self-terminating process. + Ion implantation area control is primarily determined by precise photolithography. This fabrication method not only improves precise control of oxide window dimensions but also reduces the uniformity of the oxide confinement window from + / - 0.6 μm to + / - 0.15 μm, thereby improving device optoelectronic performance, such as enhancing the high-frequency performance and controllability of VCSELs. It also significantly increases product yield. Because the critical dimension of the laterally integrated feedback cavity in TCC-VCSELs is only 0.5-3 μm, and its bandwidth enhancement performance is determined by the optical coupling strength within the lateral cavity, this method is particularly suitable for the fabrication of TCC-VCSELs for high-speed communications.

[0008] To this end, the present invention provides a method for preparing a TCC-VCSEL containing a laterally coupled cavity, comprising the following steps:

[0009] growing an n-buffer layer and an n-DBR layer on an n-substrate;

[0010] Growing an active layer including a light-emitting quantum well and a barrier layer embedded in an AlGaAs separated heterostructure layer with a thickness of 1-λ on the n-DBR layer;

[0011] growing a first p-DBR layer on the active layer;

[0012] The first p-DBR layer is oxidized to limit the As outside the window area. + ion implantation;

[0013] In being As + Continuing to grow an oxidized confinement layer on the ion-implanted first p-DBR layer;

[0014] Continuing to grow a second p-DBR layer on the oxidation restriction layer;

[0015] Continue to grow a highly doped p-type contact layer on the second p-DBR layer;

[0016] Performing mesa etching on the p-type contact layer, the second p-DBR layer, the oxidation restriction layer, the first p-DBR layer, the active layer, the n-DBR layer, and the buffer layer;

[0017] performing a high temperature wet oxidation operation on the oxidation restriction layer,

[0018] Here, λ thickness refers to the thickness of the VCSEL emission wavelength.

[0019] Optionally, the n-substrate is an n-type GaAs substrate.

[0020] Optionally, the quantum well and barrier layer of the active layer are made of InGaAs, AlGaAs, GaAs or InGaAsN quantum well materials and corresponding barrier layer materials that are lattice-matched to the GaAs substrate.

[0021] Optionally, the n-DBR, the first p-DBR, and the second p-DBR are made of a high-contrast AlGaAs / GaAs DBR pair lattice-matched to a GaAs substrate, such as Al0.92GaAs / Al0.16GaAs DBR material.

[0022] Optionally, the surface layer of the first p-DBR layer is a GaAs layer or an AlGaAs layer with a high Ga content, and the thickness thereof is N pairs, 1<N<4.

[0023] Optionally, the first p-DBR layer is oxidized to limit the As outside the window area. + Ion implantation specifically includes:

[0024] First, a photolithographic mask is formed on the first p-DBR layer according to an oxidation restriction window pattern;

[0025] Then proceed with As + Ion implantation, As + The ion implantation energy is 100KeV and the dose is 1x10 15 -2x10 16cm -3 ;

[0026] After completing As + After ion implantation, the mask material is removed and high temperature annealing is performed.

[0027] The annealing temperature and time are 700° C. and 2 hours respectively, and the mask material can be photoresist or other mask materials.

[0028] Optionally, performing mesa etching on the p-contact layer, the second p-DBR layer, the oxidation restriction layer, the first p-DBR layer and the active layer, the n-DBR layer and the n-buffer layer specifically includes:

[0029] First, a partial photolithography mask is formed on the p-contact layer, and then the p-contact layer, the second p-DBR layer, the oxidation restriction layer, the first p-DBR layer and the active layer, the n-DBR layer and the n-buffer layer are etched;

[0030] After etching is completed, the mask material is removed. The mask material may be photoresist or other mask materials.

[0031] Optionally, performing a high temperature wet oxidation operation on the oxidation restriction layer specifically includes:

[0032] Introduce N2 / H2O mixed gas or other oxidizing mixed gas to carry out controlled oxidation of the oxide layer.

[0033] Among them, the temperature is controlled at 400-425℃.

[0034] Optionally, after the step of performing high temperature wet oxidation on the oxidation restriction layer, the method further comprises:

[0035] A p-type metal contact electrode for RF signals is provided on the p-type contact layer corresponding to the VCSEL light-emitting window, and a p-type metal contact electrode for DC signals is provided on the p-type contact layer corresponding to the lateral coupling cavity.

[0036] Optionally, after a p-type metal contact electrode for RF signal is provided on the p-type contact layer corresponding to the VCSEL light emitting window, and a p-type metal contact electrode for DC signal is provided corresponding to the transverse coupling cavity, the method further includes:

[0037] After thinning the n-type substrate, n multi-layer metal layers are deposited and subjected to high-temperature alloying.

[0038] Optionally, after thinning the n-type substrate and depositing n multi-layer metal layers and performing high-temperature alloying, the method further includes:

[0039] In the p-DBR, multi-level energy proton injection is used to electrically isolate the light-emitting window and the lateral feedback cavity of the TCC-VCSEL to ensure that the p-type DBRs on the top of the VCSEL are insulated from each other.

[0040] The proton injection voltage ranges from 60 kV to 350 kV, and the fixed injection dose is 1×10 15 cm 2 .

[0041] The preparation method of the TCC-VCSEL containing a lateral coupling cavity of the present invention, wherein when the top-emitting TCC-VCSEL optoelectronic device is manufactured by the method, the first p-DBR layer is first oxidized outside the restriction window area by As + Ion implantation and high temperature annealing are performed, and then the oxide confinement layer and the second p-DBR layer are grown. More generally, this oxide confinement layer must be grown on As + This fabrication method can be applied to the manufacture of any oxide-confined window-type VCSEL chip grown on a GaAs substrate, and is particularly suitable for the production of high-bandwidth TCC-VCSELs with very strict requirements on the size and uniformity of the lateral coupling cavity.

[0042] The present invention also provides another method for preparing a TCC-VCSEL containing a transversely coupled cavity, comprising the following steps:

[0043] (1) Grow a 500nm silicon-doped GaAs buffer layer on an n-type GaAs substrate and grow 40 pairs of silicon-doped n-type Al 0.92 GaAs / Al 0.16 GaAs DBR;

[0044] (2) Continue to grow Al embedded in 1-λ thickness 0.3 Ga 0.7 As separates the three pairs of In heterostructure layers 0.2 GaAs / GaAs quantum well active layer;

[0045] (3) Continue to grow the first carbon-doped p-type Al 0.92 GaAs / Al 0.16 GaAs DBR pair;

[0046] (4) A bowtie-shaped oxidation restriction window is defined by a photolithography process, and the window area is covered with photoresist and As + Perform ion implantation, remove the photoresist after the ion implantation is completed, and perform high-temperature annealing;

[0047] (5) Then grow 300A Al 0,92 GaAs and complete the growth of the second carbon-doped p-type Al0.92 GaAs / Al 0.16 GaAsDBR pair, and highly doped p-contact layer.

[0048] (6) After forming the bow-tie VCSEL mesa using photolithography and dry etching processes, the photoresist or other mask materials are removed, and then the oxide layer is selectively oxidized under wet heat conditions to form a normal square VCSEL light-emitting window and a laterally coupled feedback cavity. The two squares are connected at right angles to form a "bow tie" shape;

[0049] (7) Use BCB or polyimide to protect the sidewalls of the mesa and achieve surface flatness, and then deposit two separate p-metal contact areas, RF and DC, on the p-contact layer;

[0050] (8) After thinning the n-type substrate, depositing n multi-layer metal layers and performing high-temperature alloying.

[0051] (9) Finally, multi-level energy ion implantation is used to electrically isolate the light-emitting cavity and the lateral coupling cavity of the oxide confinement layer, and ensure that the p-type DBRs on the top of the VCSEL are insulated from each other.

[0052] When the TCC-VCSEL chip is manufactured using the present application, an active layer of lattice-matched AlGaAs / GaAs DBR and InGaAs, AlGaAs, GaAs or InGaAsN quantum well materials and corresponding barrier layer materials are grown on an n-type GaAs substrate.

[0053] When the TCC-VCSEL chip is manufactured by the present invention, 2-3 pairs of Al2O3 are first grown on the active layer. 0.92 GaAs / Al 0.16 GaAs first DBR, the surface layer is a DBR layer with high Ga content, and then photoresist is used to protect the oxidation limit window area from arsenic ion implantation. + The ion implantation energy is 100 KeV and the dose is 1x10 15 -2x10 16 cm -3 ,After removing the photoresist, the wafer was annealed at 700 ℃ for 2 hours.

[0054] When the present application is used to manufacture a TCC-VCSEL chip, the As + 300A of AlAs or AlGaAs oxide confinement layer material and the remaining second p-DBR are grown on the surface of the ion-implanted p-DBR. The total p-type Al 0.92 GaAs / Al 0.16 There are 26 GaAsDBR pairs.

[0055] When using this application to make TCC-VCSEL chips, the wafer after epitaxial growth is subjected to photolithography and dry etching to form a bow tie-shaped mesa. Then, under wet and hot conditions, N2 / H2O mixed gas is introduced to control oxidation of the oxide layer. The temperature is controlled at 400-425°C. + The oxidation rate of the oxide confinement layer grown on the ion implantation area is about 0.5 μm / min, while in the absence of As + The oxidation rate of the oxide confinement layer grown above the ion implanted area is approximately 0.12µm / min. After oxidation, the TCC-VCSEL's light emission window and lateral coupling cavity are between 3 and 6µm in width. They connect at right angles, forming a bowtie shape. The narrowest point where the two blocks meet is only 0.5 to 3µm.

[0056] When using this application to manufacture a TCC-VCSEL chip, it is necessary to electrically isolate the light emission window of the oxide confinement layer and the lateral coupling cavity. The isolation depth must penetrate the p-DBR. Proton implantation with a graded 60-350 KeV and a dose of 10 15 cm -3 The isolation depth is approximately 4 μm, the isolation resistance reaches 10 MΩ, and the leakage current is less than 10 μA.

[0057] The characteristic of this application is that after growing 1-3 pairs of first p-DBR layers, regional As + Ion implantation, the shape of the oxidation window area can be precisely controlled by the photolithography process according to the design requirements. Then continue to complete the conventional oxidation confinement layer, the second p-DBR layer and the p contact layer epitaxial growth. + The oxidation rate of the oxide restriction layer in the ion implantation area under the wet heat condition of 400-425℃ is not As + The oxidation rate is 2-4 times that of the ion implanted area. By exploiting this difference in oxidation rates, the oxidation interface is relatively stationary after reaching the oxidation window, thereby achieving precise control of the size and uniformity of the oxidation window. Because this oxidation restriction window is defined by photolithography and ion implantation, its accuracy can be significantly improved. This method avoids the uncontrollable oxidation process caused by non-uniformities in the oxide layer epitaxial material and mesa etching. Especially for complex cavity structures like TCC-VCSELs, these uncontrollable factors can severely impact the high-frequency performance of the laser chip, failing to meet design requirements. The method of this application can significantly reduce the difficulty of TCC-VCSEL fabrication, facilitate increasing the mass production capability of this product, improve yield, and expand the application of VCSEL laser chips in high-speed communication scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] To further illustrate the content of this application, the following further describes this application in conjunction with the accompanying drawings and specific examples, which will make the technical solutions and other beneficial effects of this application more apparent.

[0059] Figure 1A Schematic diagram of a bowtie TCC-VCSEL structure with a transversely coupled cavity in one embodiment of the present application;

[0060] Figure 1B A partial cross-sectional view of a bowtie TCC-VCSEL with a transversely coupled cavity according to an embodiment of the present application;

[0061] Figure 2 For an embodiment of this application, the As + Flowchart of the TCC-VCSEL process with ion implantation of the first p-DBR to control the growth of the oxide confinement layer window;

[0062] Figure 3A As in the epitaxial process of TCC-VCSEL material in one embodiment of the present application + Schematic diagram of the structure before ion implantation into the first p-DBR layer;

[0063] Figure 3B As in the epitaxial process of TCC-VCSEL material in one embodiment of the present application + Schematic diagram of the structure after ion implantation into the first p-DBR layer; Figure 4 In one embodiment of the present application, there is As + and no As + Al oxide confinement layer grown on ion implanted DBR 0.95 Ga 0.05 Comparison of As oxidation rates under wet heat conditions;

[0064] Figure 4 In one embodiment of the present application, there is As + and no As + Ion implantation of Al oxide layer grown on the first p-DBR 0.95 Ga 0.05 Comparison of As oxidation rates under wet heat conditions;

[0065] Figure 5 In one embodiment of this application, As + Al grown on the first p-DBR by ion implantation 0.95 Ga 0.05 Cross-sectional view of a VCSEL with an As oxide confinement layer window;

[0066] Figure 6 In one embodiment of the present application, As +Schematic diagram of the TCC-VCSEL chip structure with a laterally coupled cavity and ion implantation to control the oxidation confinement layer window. DETAILED DESCRIPTION

[0067] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0068] like Figure 1A and Figure 1B The figures show a schematic diagram of the bowtie TCC-VCSEL structure with a laterally coupled cavity and a partial cross-sectional view thereof, respectively, wherein the epitaxial layer structure thereof is composed of an n-type GaAs substrate 100, an n-buffer layer 110, an n-DBR layer 120, an active layer 130 including a semiconductor quantum well and a barrier layer, an oxidation confinement layer 140, a p-DBR layer 150 and a p-contact layer 160.

[0069] Reference Figure 1B On the oxide confinement layer 140, the unoxidized left block 141 represents the normal VCSEL emission window. The unoxidized right block and the connection region 142 form the lateral feedback cavity, connected by a narrow channel several microns wide to allow transverse traveling waves to pass. The oxide interface of the feedback cavity acts as a lateral mirror, coupling the lateral light back into the VCSEL emission window. Ion implantation is used to form an insulating band 500 to electrically isolate the emission window from the lateral coupling cavity. An n-metal layer 400 is deposited on the substrate bottom, while the p-metal contact layers are the RF metal contact 320 on the emission cavity and the DC metal contact 310 on the coupling cavity. The fundamental principle of bandwidth enhancement is that the feedback cavity can provide photon-photon resonance in the small-signal modulation response. Due to slow light feedback, the feedback cavity of several microns can accommodate photon-photon spacings of tens of GHz. Therefore, the bandwidth enhancement is achieved through the PPR effect.

[0070] See also Figure 2 、 Figure 3A 、 Figure 3B , Figure 2 To adopt As + TCC-VCSEL process flow chart of the oxide confinement layer window with ion implantation to control the growth of the first p-DBR. Figure 3A and Figure 3B The regions As used in the TCC-VCSEL epitaxy process are + Schematic diagram of the structure before and after ion implantation into the first p-DBR layer. This application proposes a method for preparing a TCC-VCSEL with a transversely coupled cavity, which includes the following steps:

[0071] (1) In a specific embodiment, Figure 2 (S1) and Figure 3A 、 Figure 3B As shown, first, a silicon-doped GaAs buffer layer 110 is grown on an n-type GaAs substrate 100 and a silicon-doped n-type Al 0.92 GaAs / Al 0.16 GaAs DBR layer 120 .

[0072] In a specific implementation, the thickness of the silicon-doped GaAs buffer layer 110 is 400-800 nm. 0.92 GaAs / Al 0.16 The number of pairs of the GaAs DBR layer 120 is 38-41 pairs.

[0073] (2) In specific implementation, refer to Figure 2 (S2) and Figure 3, this application chooses Al embedded in 1-λ thickness 0.3 Ga 0.7 As separates the three pairs of In heterostructure layers 0.2 Active layer 130 of GaAs / GaAs quantum well and barrier layers,

[0074] Here, λ thickness refers to the thickness of the VCSEL emission wavelength.

[0075] In a specific implementation, the quantum well material of the VCSEL may also be InGaAs, AlGaAs, GaAs, or InGaAsN that is lattice-matched to GaAs and a corresponding barrier layer.

[0076] (3) Continue to refer to Figure 2 (S3) and Figure 3A 、 Figure 3B In the embodiment of the present application, a carbon-doped first p-DBR layer 151 is first grown on the VCSEL active layer 130 ;

[0077] In a specific implementation, the first p-DBR layer 151 is made of P-doped Al 0.92 GaAs / Al 0.16 The first p-DBR layer 151 is composed of GaAs or similar high-contrast materials. The number of DBR pairs in the first p-DBR layer 151 needs to be greater than 1 pair and less than 4 pairs. Furthermore, the surface layer of the first p-DBR layer 151 is a high-Ga and low-Al material layer.

[0078] (4) In the embodiments of this application, refer to Figure 2 (S4-S5) and Figure 3A 、 Figure 3BA bowtie-shaped oxidation restriction window photoresist mask 200 is defined on the first p-DBR layer 151 according to the design using a photolithography process. The design of this window pattern needs to comprehensively consider the VCSEL emission window, the lateral feedback cavity length, and the width of the narrowest part in the middle of the connecting square bowtie.

[0079] In the specific implementation, refer to Figure 3A , the window is covered by photoresist 200, and the area outside the window is coated with As + The first p-DBR layer 151 is subjected to As + Ion implantation. + The ion implantation energy is 100 KeV and the dose is 1x10 15 -2x10 16 cm -3 . Reference Figure 3B , in As + After the ion implantation process, an arsenic-rich first p-DBR layer 155 and a bowtie-shaped first p-DBR layer 151 in the non-implanted region are formed. The advantage of using ion implantation to form an arsenic-rich GaAs layer is that the excess arsenic concentration and the associated gallium vacancy density can be flexibly controlled by adjusting the implantation dose. This gallium vacancy density determines the increased oxidation rate of the oxide confinement layer.

[0080] In the case of As + and no As + Ion implantation of Al oxide layer grown on the first p-DBR 0.95 Ga 0.05 Comparison of As oxidation rates under wet heat conditions (see Figure 4 ) is displayed in the + The oxidation rate of the oxide confinement layer grown in the ion implanted area is four times that of the non-implanted area. This increase in the oxidation rate of the AlGaAs layer with a high aluminum content is mainly attributed to the As + The gallium vacancies caused by ion implantation can enhance the ability to remove arsenic-containing byproducts of the oxidation reaction process. This leads to accelerated oxidation of the AlGaAs layer and improved oxide-GaAs interface quality. Since the oxidation rate of the AlGaAs layer is related to the As + The increase in oxidation rate is determined by the defect density under the injection dose. The saturation dose is set at 10x16cm -2 the following.

[0081] It should be noted that after completing As + After ion implantation, the photoresist is removed with a solvent, and the epitaxial wafer is then annealed at 700°C for 2 hours to form a good surface for further epitaxy.

[0082] (5) In the embodiments of this application, refer to Figure 2(S6-S7) and Figure 5 As + Al grown on the first p-DBR by ion implantation 0.95 Ga 0.05 As a VCSEL cross-sectional view of the oxidation confinement layer window, the oxidation confinement layer 140 and the remaining carbon-doped second p-DBR layer 152 and the highly doped p-contact layer 160 are then grown for 300A.

[0083] In a specific implementation, the oxidation restriction layer 140 may be made of Al 0.95 Ga 0.05 As, AlAs or similar materials with high aluminum content. The composition material of the second p-DBR layer 152 is generally the same as the composition material of the first p-DBR layer 151.

[0084] Furthermore, a highly doped p-contact layer 160 is finally grown epitaxially to reduce the contact resistance between the semiconductor and the metal after the p-metal layer is deposited on this surface;

[0085] (6) Reference Figure 2 (S8-S9), Figure 3A 、 Figure 3B and Figure 5 , using photolithography and dry etching process to form bow tie VCSEL mesa, the bow tie shape is non-As + A magnification of the ion implantation area 151, from the sidewall of the mesa to the As + The edge distances of the ion implanted bow tie shape should be as consistent as possible.

[0086] In a specific implementation, a fluorine-containing corrosive gas is used to inductively couple plasma etching to transfer the bowtie-shaped photolithography pattern to a SiO2 or SiNx passivation film, and finally, the bowtie-shaped mesa structure of the TCC-VCSEL is formed by inductively coupling plasma etching under the passivation mask. The chemical reaction gas can be chlorine-containing gas, nitrogen, argon and helium, as well as a combination of these gases. The etching depth must at least exceed the active layer. Furthermore, the etching depth of the mesa can reach the GaAs substrate to reduce the parasitic effect of the device at high frequencies. The mesa structure formed after etching is as follows: Figure 6 As + The schematic diagram of the TCC-VCSEL chip structure with a transversely coupled cavity and ion implantation to control the oxidation confinement layer window is shown.

[0087] In a specific implementation, after removing the photoresist and passivation mask, the wafer is heated at 400-425°C and a N2 / H2O mixed gas is introduced to the oxidation restriction layer (Al 0.95 Ga 0.05 As)155 is selectively oxidized.

[0088] It should be further pointed out that + The difference in oxidation rate between the confinement layer grown on the implanted area and the non-implanted area is such that when the oxidation process enters the designed window 151 (non-implanted area), the oxidation rate will be significantly reduced, thus suppressing the oxidation process. This substantially reduces the problems that may occur during the oxidation process and improves the uniformity of the VCSEL oxidation confinement window. Therefore, by adding a bottom AlGaAs:As + The first p-DBR layer can increase the yield of VCSEL and reduce manufacturing costs.

[0089] Equally important, another advantage of the present application is that the implantation region is defined by a photolithography process, and the photolithography accuracy can easily reach + / - 0.05 μm. In contrast, in conventional oxidation processes, the initial oxidation point is located on the sidewalls of the mesa etching. Since the oxidation restriction layer is located at the bottom of the p-DBR layer, an etching depth exceeding 3 μm is generally required to expose the sidewalls of the oxidation restriction layer. Therefore, in conventional processes, the initial oxidation point accuracy is difficult to control to less than + / - 0.25 μm.

[0090] Reference Figure 1A 、 Figure 1B and Figure 6 , the final oxidation window consists of a normal square VCSEL light-emitting window 141 and a laterally coupled feedback cavity 142, with two blocks connected at right angles to form a "bow tie" shape;

[0091] (7) Reference Figure 2 (S10-S11) and Figure 6 The sidewalls of the mesa are protected and the surface is flattened 600 using BCB or polyimide. The BCB or polyimide on the mesa surface is removed by photolithography and reactive ion etching to expose the highly doped p-contact layer 160 on the surface. The etching gas can be a fluorine-containing corrosive gas, oxygen and argon, or a combination of these gases, which is not limited here.

[0092] Furthermore, the wafer surface is patterned again and a p-type metal layer is deposited. The wafer after deposition is subjected to metal stripping in a heated solvent to form a p-metal layer separated from the top of the table and RF (320) and DC (310) pads. The p-metal layer is generally composed of Ti / Pt / Au multilayer metal, which is not limited here.

[0093] (8) Reference Figure 2 Process flow chart (S12-S14) and Figure 6 In a possible implementation, after thinning the n-type GaAs substrate, a multi-layer n-metal layer 400 is deposited. The n-metal layer is generally composed of Au / Ge / Ni / Au multi-layer metal, which is not limited here.

[0094] Furthermore, the wafer after n-type metal deposition is alloyed at a high temperature of 400-450°C to form an ohmic contact between the substrate and the metal.

[0095] (9) Reference Figure 2 (S15) and Figure 6 , multi-level energy proton implantation is used to electrically isolate the light-emitting cavity and the lateral feedback cavity of the VCSEL 500, and ensure that the p-DBR layer 152 on the top of the VCSEL is insulated from left to right.

[0096] In the specific implementation, the following six different proton injection voltages were used: 60 kV, 120 kV, 180 kV, 240 kV, 300 kV and 350 kV, and a fixed injection dose of 1×10 15 cm 2 The light-emitting cavity and the lateral feedback cavity are electrically isolated. This isolation depth must penetrate the 4µm thick p-DBR. The isolation resistance reaches 10MΩ, and the leakage current is less than 10µA. This ensures that DC current is injected into the feedback cavity, thereby controlling the phase and amplitude of the optical coupling fed back to the VCSEL (see Figures 1A and 1B). Figure 1B Schematic diagram).

[0097] In the specific implementation, the entire TCC-VCSEL chip is finally produced through grinding wheel cutting or laser cutting cleavage.

[0098] Figure 6 Is to use As + Schematic diagram of the structure of a TCC-VCSEL chip with a transversely coupled cavity and controlled oxidation confinement layer window by ion implantation. Referring to the above specific fabrication steps (1)-(9), a complete optoelectronic chip with a transversely coupled cavity TCC-VCSEL as described in this application is realized.

[0099] Transversely coupled cavity (TCC-VCSEL) lasers (TCC-VCSELs) are an important technological approach for improving the high-frequency performance of VCSELs. Precise control of the device's emission window, lateral feedback cavity, and the connecting region between them is essential for ensuring chip performance. These critical dimensions are only 0.5-2 μm. Because the lateral coupling strength is highly sensitive to critical dimension control, the method proposed in this application significantly reduces the difficulty of controlling the oxidation process of the oxidation restriction window in transversely coupled cavity TCC-VCSELs, thereby improving the VCSEL's high-frequency performance and significantly reducing the cost of the TCC-VCSEL chip by improving yield.

[0100] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0101] The above is a detailed introduction to a method for preparing a VCSEL containing a laterally coupled cavity provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the technical solutions and core ideas of the present application. Those skilled in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features therein can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a TCC-VCSEL containing a transversely coupled cavity, characterized in that: The steps include: growing an n-buffer layer and an n-DBR layer on an n-type substrate; An active layer including a light-emitting quantum well and a barrier layer is grown on the n-DBR layer, wherein the active layer is embedded with an AlGaAs separated heterostructure layer with a thickness of λ, where λ is the VCSEL light emission wavelength; growing a first p-DBR layer on the active layer; The first p-DBR layer is oxidized to limit the As outside the window area. + ion implantation; The oxidation restriction window region is designed to be in a bow tie shape, including a VCSEL light emitting region and a lateral coupling feedback cavity region; In being As + Continuing to grow an oxidized restriction layer on the ion-implanted first p-DBR layer; and continuing to grow a second p-DBR layer on the oxidized restriction layer; Continue to grow a highly doped p-type contact layer on the second p-DBR layer; The p-type contact layer, the second p-DBR layer, the oxidized confinement layer, the first p-DBR layer, the active layer, the n-DBR layer, and the n-buffer layer are subjected to mesa etching to form a bowtie mesa structure, wherein the bowtie mesa structure includes the mutually connected VCSEL light-emitting region and the laterally coupled feedback cavity region; the oxidized confinement layer is subjected to a high-temperature wet oxidation operation to form a VCSEL light-emitting window and a laterally coupled feedback cavity after oxidation, wherein the VCSEL light-emitting window and the laterally coupled feedback cavity are connected to form a laterally coupled cavity.

2. The method for preparing a TCC-VCSEL containing a transversely coupled cavity according to claim 1, wherein: The n-type substrate is an n-type GaAs substrate.

3. The method for preparing a TCC-VCSEL containing a transversely coupled cavity according to claim 1, wherein: The quantum well and barrier layer of the active layer adopt InGaAs, AIGaAs, GaAs or InGaAsN quantum well materials and corresponding barrier layer materials that are lattice-matched with the GaAs substrate.

4. The method for preparing a TCC-VCSEL containing a transversely coupled cavity according to claim 1, wherein: The n-DBR, the first p-DBR and the second p-DBR are made of a high-contrast AlGaAs / GaAs DBR pair that is lattice-matched with the GaAs substrate.

5. The method for preparing a TCC-VCSEL containing a transversely coupled cavity according to claim 1, wherein: The surface layer of the first p-DBR layer is GaAs or AlGaAs with high Ga content, and its thickness is N pairs, 1 <N<4。 6. The method for preparing a TCC-VCSEL containing a transversely coupled cavity according to claim 1, wherein: The first p-DBR layer is oxidized to limit the As outside the window area. + Ion implantation specifically includes: First, a photolithographic mask is formed on the first p-DBR layer according to an oxidation restriction window pattern; Then proceed with As + Ion implantation, As + The ion implantation energy is 100 KeV and the dose is 1x10 15 -2x10 16 cm -3 ; After completing As + After ion implantation, the mask material is removed and high temperature annealing is performed. The annealing temperature and time are 700°C and 2 hours respectively.

7. The method for preparing a TCC-VCSEL containing a transversely coupled cavity according to claim 1, wherein: Performing mesa etching on the p-type contact layer, the second p-DBR layer, the oxidation restriction layer, the first p-DBR layer, the active layer, the n-DBR layer, and the n-buffer layer specifically includes: First, a partial photolithography mask is performed on the p-type contact layer, and then the p-type contact layer, the second p-DBR layer, the oxidation restriction layer, the first p-DBR layer, the active layer, the n-DBR layer and the n-buffer layer are etched; After etching is complete, the mask material is removed.

8. The method for preparing a TCC-VCSEL containing a transversely coupled cavity according to claim 1, wherein: The high temperature wet oxidation operation of the oxidation restriction layer specifically includes: Introduce N2 / H2O mixed gas or other oxidizing mixed gas to carry out controlled oxidation of the oxide layer. Among them, the temperature is controlled at 400-425C°.

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