A solenoid valve output timing processing method to improve satellite jet control stability

Abstract

The present invention belongs to the technical field of spacecraft attitude orbit jet control, and specifically relates to a solenoid valve output timing processing method for improving the stability of satellite jet control. When the FPGA receives two adjacent digital instructions from the CPU to control the solenoid valve to open at the connection moment, the FPGA does not control the solenoid valve to close at the connection moment, and always keeps the output control solenoid valve open. The present invention reduces the number of frequent switching times of the thruster during continuous control of each cycle, reduces control jitter, and thus improves the stability of thruster control.

Description

Technical Field

[0001] The present invention belongs to the technical field of spacecraft attitude orbit jet control, and specifically relates to a solenoid valve output timing processing method for improving satellite jet control stability, which is used for the control timing coordination of a host computer CPU and an interface control logic chip FPGA for jet control pulse width modulation output. Background Art

[0002] The satellite propulsion system is used for orbital maneuvers, attitude maneuvers, attitude maintenance, and even momentum wheel unloading. In order to achieve both orbital maneuvers and attitude adjustments, a satellite is generally equipped with multiple propulsion systems, which are installed in different positions and directions of the satellite, and pulse width modulation methods are used for attitude orbit coupling control, or time-sharing multiplexing control.

[0003] The patent "A method for satellite attitude and orbit control using oblique thrusters" provides a four-oblique thruster arrangement, adopts pulse width modulation working mode, and based on the phase plane control method, calculates the jet switch pulse width of the thruster for simultaneous attitude adjustment and orbit control in each control cycle (the cycle is generally set to 1s or 2s), thereby achieving the purpose of maintaining attitude pointing while improving orbit control efficiency.

[0004] The patent "A small satellite orbit control method based on time division multiplexing" provides a method of using four oblique thrusters to open the solenoid valves in sequence according to the control cycle. Each pulse width modulation output of the thrust contains the orbit control reference pulse To and the attitude control pulse Ta. The pulse width output is updated in each control cycle. The attitude control pulse is to achieve momentum wheel unloading, thereby achieving the purpose of attitude orbit time division multiplexing.

[0005] The patented "New Low-Cost Satellite Three-Axis Attitude Time-Sharing Decoupling High-Reuse Jet Control Method" provides a three-axis time-sharing decoupling jet control algorithm with four thruster outputs. The three-axis command control torque is time-sharingly processed to the torque distribution pulse width modulation algorithm of the four thruster pulse widths, which converts the command torque into specific jet pulses to achieve three-axis attitude decoupling control.

[0006] All of the above methods involve pulse width modulation output of thruster solenoid valves, and each control cycle requires updating the pulse width duration of the solenoid valve switch. However, none of the existing technologies involve the problem of how to accurately transition the pulse width modulation output timing in each control cycle. Summary of the invention

[0007] In order to solve the above problems, the present invention provides a solenoid valve output timing processing method for improving the stability of satellite jet control, so that the number of frequent switching of the thruster is reduced during continuous control of each cycle, the control jitter is reduced, and the stability of thruster control is improved.

[0008] The present invention is implemented by providing a solenoid valve output timing processing method for improving satellite jet control stability, comprising the following steps:

[0009] Step 1: Define the satellite jet control period in the CPU as T milliseconds, and define the digital signal periodically output by the CPU to the FPGA as two parameters [a, b], where a represents the solenoid valve opening time and b represents the solenoid valve opening time, a+b≤T;

[0010] Step 2: In the FPGA, set the following four types of pulse width modulation digital signal control to be processed as follows:

[0011] Control type V1: When a and b are both 0, the FPGA will output the control solenoid valve to close from the moment it receives the CPU digital signal until T milliseconds;

[0012] Control type V2: When a is 0 and b is t1, 0<t1<T, FPGA outputs the control solenoid valve to open from the moment it receives the CPU digital signal to t1 milliseconds, and outputs the control solenoid valve to close from t1 milliseconds to T milliseconds;

[0013] Control type V3: When a is t2 and b is t3, t2+t3=T. From the moment FPGA receives the digital signal from the CPU, it outputs the control solenoid valve to close within t2 milliseconds, and from t2 to T, it outputs the control solenoid valve to open within t3 milliseconds.

[0014] Control type V4: When a is 0 and b is T, the FPGA will output the control solenoid valve to open within 0~T milliseconds from the moment it receives the CPU digital instruction;

[0015] Step 3: Set the FPGA to output and control the solenoid valve action according to the new digital instruction from the moment it receives a new digital instruction from the CPU, and store the digital instruction of the previous beat;

[0016] Step 4: When the FPGA receives two adjacent digital instructions from the CPU to control the solenoid valve to open at the connection time, the FPGA does not close the solenoid valve at the connection time and always keeps the output control solenoid valve open.

[0017] Preferably, step 4 is specifically as follows: when the digital instruction sent by the CPU in the previous shot is control type V3 or control type V4, and the digital instruction in the current shot is control type V2 or control type V4, the FPGA always keeps the output control solenoid valve open at the connection moment between the digital instruction in the previous shot and the digital instruction in the current shot.

[0018] Further preferably, when there is a clock error of Tq milliseconds between the CPU's jet control cycle T and the FPGA timer, step 4 is specifically as follows:

[0019] When the digital instruction sent by the CPU in the previous cycle is control type V3 or control type V4, and the digital instruction in the current cycle is control type V2 or control type V4, the FPGA output control solenoid valve will continue to control the solenoid valve to open for Tq milliseconds after the digital instruction in the previous cycle is completed. At the connection moment between the digital instruction in the previous cycle and the clock error, and at the connection moment between the clock error and the digital instruction in the current cycle, the FPGA will not control the solenoid valve to close, and will always keep the output control solenoid valve open.

[0020] Compared with the prior art, the advantages of the present invention are:

[0021] 1. When the control type V3 / V4 transitions to the control type V2 / V4, the FPGA considers that if the previous beat is on at the trigger time and the current beat is also on at the beginning, then at the cycle connection, the FPGA's pull-up level clock register continues to accumulate, and the pull-up level is maintained until the current beat is on for the duration before being pulled down, so as to achieve infrequent switching at the cycle connection, thus ensuring that there is no jitter in the attitude and orbit control, and improving the control pointing accuracy;

[0022] 2. The problem of clock error Tq between the CPU control trigger period T and the FPGA timer is solved. The solenoid valve is always kept open during the Tq period, thus covering the time error gap between the two processors and greatly reducing the control jitter. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is the schematic diagram of the satellite thruster pulse width output control;

[0024] Figure 2 This is a schematic diagram of connecting two adjacent digital instructions in Example 1;

[0025] Figure 3 This is a schematic diagram of the connection of three adjacent digital instructions in Example 2;

[0026] Figure 4 This is a schematic diagram of the connection between two adjacent digital instructions in Example 3. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0028] The working principle of spacecraft thruster pulse width output control is as follows Figure 1As shown in the figure, the satellite attitude and orbit control algorithm belongs to the application layer code, which is generally run in a processor CPU with strong computing power, and runs according to the timing division of the operating system. The control cycle is generally implemented by timed trigger interrupts. The satellite needs to manage many unit interfaces. Generally, a logic chip FPGA with parallel processing capability is selected to manage the input / output of each interface, so that timely processing can be carried out to improve the real-time response of the system. The thruster pulse width control duration digital signal calculated by the attitude and orbit control code cycle running in the CPU is given to the FPGA. After timing processing, the FPGA can generate a gated OC level with high time precision to control the pulse width and give it to the solenoid valve drive circuit. The drive circuit generates a pull-up / pull-down level with a time length to switch the solenoid valve, thereby realizing the thruster pulse width modulation control. However, due to the clock division accuracy, the large number of CPU processing tasks, the large number of interrupts and the priority of interrupt response, the time length of each cycle of the original fixed trigger is not completely consistent, and there is usually a time fluctuation error of Tq=±100ns~1ms (the actual situation is related to the CPU model and code volume used). In order to solve the problem of frequent switching of the solenoid valve and resulting in jitter, the present invention provides a solenoid valve output timing processing method for improving the stability of satellite jet control, comprising the following steps:

[0029] Step 1: Define the satellite jet control period in the CPU as T milliseconds, and define the digital signal periodically output by the CPU to the FPGA as two parameters [a, b], where a represents the solenoid valve opening time and b represents the solenoid valve opening time, a+b≤T;

[0030] Step 2: In the FPGA, set the following four types of pulse width modulation digital signal control to be processed as follows:

[0031] Control type V1: When a and b are both 0, the FPGA will output the control solenoid valve to close from the moment it receives the CPU digital signal until T milliseconds;

[0032] Control type V2: When a is 0 and b is t1, 0<t1<T (short-time pulse operation), the FPGA outputs the control solenoid valve to open from the moment it receives the CPU digital signal to t1 milliseconds, and outputs the control solenoid valve to close from t1 milliseconds to T milliseconds;

[0033] Control type V3: When a is t2 and b is t3, t2+t3=T. From the moment FPGA receives the digital signal from the CPU, it outputs the control solenoid valve to close within t2 milliseconds, and from t2 to T, it outputs the control solenoid valve to open within t3 milliseconds.

[0034] Control type V4: When a is 0 and b is T (near steady-state operation), the FPGA will output the control solenoid valve to open within 0~T milliseconds from the moment it receives the CPU digital instruction;

[0035] Step 3: Set the FPGA to output and control the solenoid valve action according to the new digital instruction from the moment it receives a new digital instruction from the CPU, and store the digital instruction of the previous beat;

[0036] Step 4: When the FPGA receives two adjacent digital instructions from the CPU to control the solenoid valve to open at the connection moment, the FPGA does not close the control solenoid valve at the connection moment, and always keeps the output control solenoid valve open, thereby ensuring the stability of control and reducing jitter.

[0037] Example 1

[0038] refer to Figure 2 In this embodiment, T is 1000 ms. The digital instruction sent by the CPU in the previous shot is control type V3=[300, 700], and the digital instruction in the current shot is control type V2=[0, 30]. At the connection moment between the digital instruction in the previous shot and the digital instruction in the current shot, the FPGA always keeps the output control solenoid valve open, that is, the control solenoid valve is kept open for 700ms in control type V3, and then the control solenoid valve is kept open for 30ms in control type V2. The total opening time of the control solenoid valve under the two digital instruction control cycles is 730ms. A smooth transition between the two digital instructions is achieved. Instead of closing and then opening at the time of connection, the thruster switch is prevented from causing response jitter, and the response time is saved at the same time, because each thrust pulse width response cycle is more than 5ms, and some thrusters are even longer up to 100ms.

[0039] Example 2

[0040] refer to Figure 3 In this embodiment, T is 1000 ms. This embodiment exemplifies three adjacent numerical instruction control cycles. The first beat of the digital instruction sent by the CPU is control type V3, the second beat is control type V4, and the third beat is control type V2. At the connection moment of two adjacent beats of digital instructions, the FPGA is open at the end of the previous beat and at the beginning of the next beat, because both are open at the end of the previous beat and at the beginning of the next beat, and in this embodiment, V4 is open throughout the entire cycle T, so the FPGA always keeps the output control solenoid valve open at the connection moment, which lasts for 1730ms in total in this embodiment.

[0041] Example 3

[0042] refer to Figure 4In this embodiment, T is 1000 ms, there is a clock error of 5 milliseconds between the CPU's jet control cycle T and the FPGA timer, the digital instruction sent by the CPU in the previous beat is the control type V3, and the digital instruction in the current beat is the control type V2, then the FPGA output control solenoid valve continues to control the solenoid valve to open for 5 milliseconds after the digital instruction in the previous beat is completed, and at the connection moment of the digital instruction in the previous beat and the clock error, and the connection moment of the clock error and the digital instruction in the current beat, the FPGA does not control the solenoid valve to close, and always keeps the output control solenoid valve open. In this embodiment, it is continuously opened for a total of 735ms.

Claims

1. A solenoid valve output timing processing method for improving satellite jet control stability, characterized in that: The steps include: Step 1: Define the satellite jet control period in the CPU as T milliseconds, and define the digital signal periodically output by the CPU to the FPGA as two parameters [a, b], where a represents the solenoid valve opening time and b represents the solenoid valve opening time, a+b≤T; Step 2: In the FPGA, set the following four types of pulse width modulation digital signal control to be processed as follows: Control type V1: When a and b are both 0, the FPGA will output the control solenoid valve to close from the moment it receives the CPU digital signal until T milliseconds; Control type V2: When a is 0 and b is t1, 0<t1<T, FPGA outputs the control solenoid valve to open from the moment it receives the CPU digital signal to t1 milliseconds, and outputs the control solenoid valve to close from t1 milliseconds to T milliseconds; Control type V3: When a is t2 and b is t3, t2+t3=T. From the moment FPGA receives the digital signal from the CPU, it outputs the control solenoid valve to close within t2 milliseconds, and from t2 to T, it outputs the control solenoid valve to open within t3 milliseconds. Control type V4: When a is 0 and b is T, the FPGA will output the control solenoid valve to open within 0~T milliseconds from the moment it receives the CPU digital instruction; Step 3: Set the FPGA to output and control the solenoid valve action according to the new digital instruction from the moment it receives a new digital instruction from the CPU, and store the digital instruction of the previous beat; Step 4: When the FPGA receives two adjacent digital instructions from the CPU to control the solenoid valve to open at the connection time, the FPGA does not close the solenoid valve at the connection time and always keeps the output control solenoid valve open.

2. The solenoid valve output timing processing method for improving satellite jet control stability according to claim 1 is characterized in that: Step 4 is specifically as follows: when the digital instruction sent by the CPU in the previous shot is control type V3 or control type V4, and the digital instruction in the current shot is control type V2 or control type V4, the FPGA always keeps the output control solenoid valve open at the connection moment between the digital instruction in the previous shot and the digital instruction in the current shot.

3. The solenoid valve output timing processing method for improving satellite jet control stability according to claim 2 is characterized in that: When there is a clock error of Tq milliseconds between the CPU's jet control cycle T and the FPGA timer, step 4 is specifically as follows: When the digital instruction sent by the CPU in the previous cycle is control type V3 or control type V4, and the digital instruction in the current cycle is control type V2 or control type V4, the FPGA output control solenoid valve will continue to control the solenoid valve to open for Tq milliseconds after the digital instruction in the previous cycle is completed. At the connection moment between the digital instruction in the previous cycle and the clock error, and at the connection moment between the clock error and the digital instruction in the current cycle, the FPGA will not control the solenoid valve to close, and will always keep the output control solenoid valve open.

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