Display panel and display device

Abstract

The present disclosure relates to the technical field of display, and provides a display panel and a display device. The display panel comprises a display area, the display area comprises a plurality of columns of sub-pixels which are sequentially and spacedly distributed in a row direction, and a first column of sub-pixels and a last column of sub-pixels are both provided with a data signal line away from one side of the first column of sub-pixels and one side of the last column of sub-pixels. The display panel of the present disclosure can provide data signals for part of the sub-pixels of the second column which are blocked by the outer frame through the first data signal line, and provide data signals for another part of the sub-pixels of the second column through the second data signal line which is behind the first data signal line, so that each sub-pixel of the second column can be pre-charged. Similarly, each sub-pixel of the penultimate column which is blocked by the outer frame can also be pre-charged. Therefore, the display panel of the present disclosure can solve the problem of uneven display of the edge.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular, to a display panel and a display device. BACKGROUND

[0002] In order to improve product profits, existing display products reduce the number of COF (Chip on film) of the panel to reduce costs.

[0003] In the related art, in order to match the low-cost product architecture, the display product has the problem of uneven brightness at the edge, which is manifested as sawtooth-shaped edge defects.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a display panel and a display device.

[0006] According to one aspect of the present disclosure, a display panel is provided, comprising a display area, the display area comprising a plurality of columns of sub-pixels arranged in a row direction, a first column of sub-pixels being away from one side of a last column of sub-pixels and the last column of sub-pixels being away from one side of the first column of sub-pixels, and a data signal line being arranged on each side.

[0007] In an exemplary embodiment of the present disclosure, the display panel comprises a color film substrate, the color film substrate comprising: a first substrate; a color resistance layer located on one side of the first substrate and in a display area, the color resistance layer comprising a plurality of sub-pixels arranged in an array; a frame area arranged circumferentially around the display area, the frame area comprising a first frame and a second frame arranged opposite in the row direction; wherein the first frame covers the first column of sub-pixels in the first substrate and partially overlaps with the second column of sub-pixels in the first substrate in the first substrate projection; and the second frame covers the last column of sub-pixels in the first substrate and partially overlaps with the second last column of sub-pixels in the first substrate in the first substrate projection.

[0008] In an exemplary embodiment of the present disclosure, the data signal line on the side of the first column of sub-pixels away from the last column of sub-pixels is a first data signal line, the data signal line on the side of the last column of sub-pixels away from the first column of sub-pixels is a first data signal line, the first data signal line is electrically connected to part of the sub-pixels of the second column, and the first data signal line is electrically connected to part of the sub-pixels of the second last column.

[0009] In the example embodiment of the present disclosure, the first data signal line is also electrically connected to part of the sub-pixels of the first pixel column, and the sub-pixels of the first pixel column connected to the first data signal line are located in the same row as the sub-pixels of the second pixel column connected to the first data signal line; the first inverse data signal line is also electrically connected to part of the sub-pixels of the Nth pixel column, and the sub-pixels of the Nth pixel column connected to the first inverse data signal line are located in the same row as the sub-pixels of the (N-1)th pixel column connected to the first inverse data signal line.

[0010] In the example embodiment of the present disclosure, in each sub-pixel of the same pixel column, the sub-pixel located in the odd row is connected to the same data signal line, and the sub-pixel located in the even row is connected to another data signal line; in two adjacent pixel columns distributed on both sides of the same data signal line, the even row sub-pixels of the former pixel column are connected to the same data signal line as the odd row sub-pixels of the latter pixel column; in two pixel columns distributed between adjacent two data signal lines, the sub-pixels located in the odd row are connected to the former data signal line, and the sub-pixels located in the even row are connected to the latter data signal line.

[0011] In the example embodiment of the present disclosure, the display panel includes a driving substrate and a color film substrate arranged in a cell, the sub-pixels are located on the color film substrate, and the color resistance layer includes a plurality of sub-pixels arrayed in a row and column direction; the driving substrate includes a second substrate, a common electrode layer located on one side of the second substrate, the common electrode layer includes a plurality of common electrode lines located in a display area, the plurality of common electrode lines extend in the column direction and are sequentially and spacedly distributed in the row direction in the orthographic projection of the second substrate, and a source-drain metal layer located on the side of the common electrode layer away from the second substrate, the source-drain metal layer includes a plurality of data signal lines; wherein the display panel includes a plurality of data signal lines, the orthographic projection of the data signal lines and the common electrode lines on the second substrate are located between the orthographic projections of adjacent two pixel columns on the second substrate, and the orthographic projections of the plurality of data signal lines and the plurality of common electrode lines on the second substrate are sequentially and alternately distributed in the row direction.

[0012] In the example embodiment of the present disclosure, the display area includes n pixel columns, m data signal lines and k common electrode lines, wherein m = n / 2 + 1, k = n / 2, n is a natural number greater than or equal to 2, and m and k are natural numbers.

[0013] In the example embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits, and each pixel driving circuit includes a transistor, and a gate of the transistor is connected to a gate signal terminal; the display panel includes a driving substrate and a color film substrate arranged in a cell, and the driving substrate includes: a second substrate; a gate metal layer located on one side of the second substrate, and the gate metal layer includes: a plurality of conductive blocks located in a non-display area of the display panel, and the conductive blocks are connected to output signal lines of a shift register unit through a via; and a plurality of gate signal lines located in a display area, and the gate signal lines are connected to the conductive blocks, and part of the structure of the gate signal lines is used to form the gate of the transistor; wherein a part of the conductive blocks are located in a projection of the first frame on the second substrate, and a part of the conductive blocks are located in a projection of the second frame on the second substrate; any two adjacent sub-pixels in a row direction have a first interval in the row direction, and a shortest distance between the conductive block and the sub-pixel adjacent to the conductive block in the projection of the second substrate on the row direction matches the first interval.

[0014] In the example embodiment of the present disclosure, a ratio of the shortest distance between the conductive block and the sub-pixel adjacent to the conductive block in the projection of the second substrate on the row direction to the first interval is greater than or equal to 0.8 and less than or equal to 1.2.

[0015] In the example embodiment of the present disclosure, the shortest distance is greater than or equal to 18 μm and less than or equal to 26 μm.

[0016] In the example embodiment of the present disclosure, the frame area further includes a third frame and a fourth frame arranged opposite in a column direction; and the display panel further includes: a fan-out area located on a side of the third frame away from the display area, and the fan-out area includes: a plurality of data fan-out lines, and one data signal line is connected to one data fan-out line, and an electrostatic discharge unit is connected between the first data signal line and the corresponding data fan-out line and between the last data signal line and the corresponding data fan-out line, and the electrostatic discharge unit is further connected to a common electrode line.

[0017] In the example embodiment of the present disclosure, the display panel further includes a plurality of chips, and the fan-out area further includes a plurality of virtual data fan-out lines; wherein a number of data channels of the chip is equal to a sum of a number of data fan-out lines corresponding to the chip and a number of virtual data fan-out lines corresponding to the chip.

[0018] In the example embodiment of the present disclosure, the number of virtual data fan-out lines corresponding to at least part of the chips is different from the number of virtual data fan-out lines corresponding to other chips.

[0019] In the example embodiment of the present disclosure, the plurality of chips include a first chip connected to the first data signal line and a second chip connected to the first inverse data signal line; the number of virtual data fan-out lines corresponding to the first chip and the number of virtual data fan-out lines corresponding to the second chip are both less than the number of virtual data fan-out lines corresponding to other chips.

[0020] In the example embodiment of the present disclosure, the first chip and the second chip both correspond to one of the virtual data fan-out lines.

[0021] In the example embodiment of the present disclosure, the frame area further includes a third frame and a fourth frame oppositely arranged in the column direction; the first data signal line and the first inverse data signal line are both connected to an electrostatic discharge unit in the non-display area on the side of the fourth frame, and the electrostatic discharge unit is further connected to a common electrode line.

[0022] According to the second aspect of the present disclosure, a display device is further provided, which includes the display panel of any of the embodiments of the present disclosure.

[0023] In the display panel provided by the present disclosure, the data signal lines are arranged on the side of the first column of sub-pixels away from the last column of sub-pixels and on the side of the last column of sub-pixels away from the first column of sub-pixels. Taking the data signal line on the side of the first column of sub-pixels away from the last column of sub-pixels as the first data signal line and the data signal line on the side of the last column of sub-pixels away from the first column of sub-pixels as the first inverse data signal line as an example, the first data signal line can provide data signals for the part of the second column of sub-pixels that is blocked by the outer frame, and the second data signal line can provide data signals for the other part of the second column of sub-pixels, so that each sub-pixel of the second column can be pre-charged. Similarly, the last data signal line can provide data signals for the part of the second-to-last column of sub-pixels that is blocked by the outer frame, and the second-to-last data signal line can provide data signals for the other sub-pixels of the second-to-last column, so that each sub-pixel of the second-to-last column that is blocked by the outer frame can be pre-charged. Therefore, the display panel of the present disclosure can solve the problem of uneven display of the edge.

[0024] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0025] The drawings herein are incorporated into the specification and form part of the specification, show embodiments consistent with the present disclosure, and together with the specification serve to explain the principles of the present disclosure. It is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0026] Figure 1 A structural schematic diagram of a display panel according to an embodiment of the present disclosure;

[0027] Figure 2 A partial enlarged view of the left and right side frames in FIG. 1; Figure 1

[0028] Figure 3 A cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure;

[0029] Figure 4 A distribution schematic diagram of a data signal line in the related art;

[0030] Figure 5 A connection schematic diagram of a sub-pixel and a data signal line according to an embodiment of the present disclosure;

[0031] Figure 6 A wiring schematic diagram of a display panel according to an embodiment of the present disclosure;

[0032] Figure 7 A partial enlarged view of M in FIG. 2; Figure 6 DETAILED DESCRIPTION

[0033] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided as non-limiting examples so that this disclosure will fully convey the scope of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and thus description of the same will be omitted. In addition, the drawings are only schematic and the dimensions are not necessarily to scale.

[0034] Although relative terms such as "upper", "lower", etc. are used herein to describe one component's relationship to another component as the figure is oriented, such terms are used only for convenience in describing the example embodiments shown in the figures and are not otherwise intended to limit the scope of the example embodiments. It is to be understood that other examples can be utilized and structural or logical modifications can be made without departing from the scope of the example embodiments. The described implementation includes other implementations, such as structure receiving, to, and or holding other structures, unless with specific structures expressly so limited. It is to be understood that the use of "or" in the examples is used only to convey a non-exclusive "or" relationship between a first member and a second member, unless otherwise indicated.

[0035] ​​The terms "one", "a", "an", "said", and "the" are used to indicate the presence of one or more elements / supplements / etc.; the terms "include" and "have" are used to indicate an open-ended inclusion and refer to additional elements / supplements / etc. in addition to the listed elements / supplements / etc.; the terms "first", "second", and "third" are used only as markers and are not a limitation on the number of their objects.

[0036] Figure 1 A schematic view of the structure of a display panel according to an embodiment of the present disclosure, Figure 2 A schematic view of the structure of a display panel according to an embodiment of the present disclosure, Figure 1 A partial enlarged view of the left and right side frames, as shown in Figure 1 A partial enlarged view of the left and right side frames, as shown in Figure 2 The display panel can include a display area including a plurality of columns of sub-pixels spaced apart in sequence in a row direction X, and a data signal line Data is arranged on a side of a first column of sub-pixels Pixel-F away from a last column of sub-pixels Pixel-L and on a side of the last column of sub-pixels Pixel-L away from the first column of sub-pixels Pixel-F.

[0037] In the display panel provided by the present disclosure, a data signal line Data is arranged on a side of a first column of sub-pixels Pixel-F away from a last column of sub-pixels Pixel-L and on a side of the last column of sub-pixels Pixel-L away from the first column of sub-pixels Pixel-F. Taking the data signal line Data on the side of the first column of sub-pixels Pixel-F away from the last column of sub-pixels Pixel-L as a first data signal line DT1 and the data signal line Data on the side of the last column of sub-pixels Pixel-L away from the first column of sub-pixels Pixel-F as a last data signal line DTN, for example, a second column of sub-pixels partially blocked by the outer frame BMO can be provided with data signals by the first data signal line DT1, and another second column of sub-pixels can be provided with data signals by a second data signal line Data behind the first data signal line DT1, so that each sub-pixel of the second column can be pre-charged. Similarly, a second-to-last column of sub-pixels partially blocked by the outer frame BMO can be provided with data signals by the last data signal line Data, and other sub-pixels of the second-to-last column can be provided with data signals by a second-to-last data signal line Data, so that each sub-pixel of the second-to-last column partially blocked by the outer frame BMO can be pre-charged. Thus, the display panel of the present disclosure can solve the problem of uneven display of brightness and darkness at the edge.

[0038] The display panel of the present disclosure can be a liquid crystal display panel, Figure 3 A schematic view of the structure of a display panel according to an embodiment of the present disclosure, Figure 3As shown, the liquid crystal display panel may include a color filter substrate and a driving substrate disposed opposite each other, with a bezel and a color resist layer CL disposed on the color filter substrate. Data signal lines Data, pixel electrodes Vpixel, and a common electrode Vcon are disposed on the driving substrate.

[0039] like Figure 1 As shown, the display panel disclosed herein may include an outer bezel (BMO) and an inner bezel (BMI). The outer bezel (BMO) may include a first bezel (GPL) and a second bezel (GPR) disposed opposite each other in the row direction (X), and a third bezel (DP) and a fourth bezel (DPO) disposed opposite each other in the column direction (Y). Both the outer bezel (BMO) and the inner bezel (BMI) can be black matrices. The outer bezel (BMO) is mainly used to prevent light leakage from subpixels at the edge of the display area. The inner bezel (BMI) can be grid-like, which can isolate adjacent light-emitting areas to prevent light leakage and color mixing; further details are omitted here.

[0040] For ease of description, this disclosure refers only to the first column of sub-pixels, Pixel-F. Figure 2 The leftmost column of sub-pixels and the last column of sub-pixels, Pixel-L, are Figure 2 Let's take the rightmost column of sub-pixels as an example. It's understandable that... Figure 2 From left to right, the sub-pixels are arranged as follows: first column Pixel-F, second column Pixel, ..., second to last column Pixel, and last column Pixel-L.

[0041] Data signal lines are provided on both the side of the first column sub-pixel Pixel-F furthest from the last column sub-pixel Pixel-L and the side of the last column sub-pixel Pixel-L furthest from the first column sub-pixel Pixel-F. Figure 1 and Figure 2 Data signal lines Data are provided on the left side of the first column of sub-pixels Pixel-F and the right side of the last column of sub-pixels Pixel-L, meaning that data signal lines Data are provided on both the left and right sides of the display area. The purpose of this arrangement of data signal lines Data is that, with data signal lines Data on both sides of the display area, when the outer bezel BMO of the display panel obscures the first and last columns of sub-pixels Pixel-L, the luminous area of ​​the display panel is effectively the second to penultimate columns of sub-pixels. Thus, the two data signal lines Data on both sides of the display area can provide data signals to a portion of the sub-pixels in the second and penultimate columns, allowing these sub-pixels to be pre-charged. Furthermore, other portions of the sub-pixels in the second and penultimate columns can be pre-charged through other connected data signal lines Data, thereby enabling the first and last columns of sub-pixels in the effective display area of ​​the display panel of this disclosure to be pre-charged.

[0042] It should be understood that the pre-charging of the sub-pixel by the data signal line Data in the present disclosure refers to that the data signal line Data connected to the sub-pixel can write data signals to the sub-pixel in advance by controlling the gate signal line Gate connected to the sub-pixel to be turned on in advance.

[0043] The present disclosure will be further described below with reference to the accompanying drawings.

[0044] In combination with Figure 2 And Figure 3 The color film substrate can include a first substrate BP1, a color resistance layer CL located on one side of the first substrate BP1 and in a display area, and the color resistance layer CL includes a plurality of sub-pixels arranged in an array; a frame area BMA is arranged circumferentially around the display area, and the frame area BMA can include the first frame GPL and the second frame GPR arranged opposite to each other in the row direction X and the third frame DP and the fourth frame DPO arranged opposite to each other in the column direction Y. Wherein, the first frame GPL covers the first column of sub-pixels Pixel-F in the first substrate BP1 in the orthographic projection and partially overlaps the second column of sub-pixels in the first substrate BP1 in the orthographic projection, that is, after the color film substrate and the driving substrate are set in a box, the first frame GPL completely blocks the first column of sub-pixels Pixel-F, so that the first column of sub-pixels Pixel-F does not emit light, and at the same time, the first frame GPL also partially blocks the second column of sub-pixels, so that the second column of sub-pixels is the left edge of the actual light-emitting area of the display panel. Similarly, the second frame GPR covers the last column of sub-pixels Pixel-L in the first substrate BP1 in the orthographic projection and partially overlaps the second-to-last column of sub-pixels in the first substrate BP1 in the orthographic projection, that is, after the color film substrate and the driving substrate are set in a box, the second frame GPR completely blocks the last column of sub-pixels Pixel-L, so that the last column of sub-pixels Pixel-L also does not emit light. At the same time, the second frame GPR also partially blocks the second-to-last column of sub-pixels, so that the second-to-last column of sub-pixels is the right edge of the actual light-emitting area of the display panel. In this way, the first column of sub-pixels Pixel-F and the last column of sub-pixels Pixel-L are blocked by the outer frame BMO and cannot emit light, so that the actual display area of the display panel is the second column of sub-pixels to the second-to-last column of sub-pixels. The present disclosure is to solve the problem of uneven brightness of the second column of sub-pixels and the second-to-last column of sub-pixels.

[0045] Figure 4 For the distribution diagram of the data signal line in the related art, as Figure 4As shown, in the related art, the first data signal line Data is located between the first column of sub-pixels Pixel-F and the second column of sub-pixels, the last data signal line is located between the last column of sub-pixels Pixel-L and the second last column of sub-pixels, the first data signal line Data connects part of the sub-pixels in the second column, and the remaining sub-pixels in the second column are connected to the second data signal line Data behind, which causes the part of the sub-pixels in the second column connected to the first data signal line Data to be unable to be pre-charged, i.e., the part of the sub-pixels in the second column is unable to be pre-charged. In the process of charging the part of the sub-pixels in the second column connected to the first data signal line Data, the second data signal line Data behind can be used to pre-charge the remaining sub-pixels in the second column connected to the second data signal line Data, i.e., the sub-pixels in the second column connected to the second data signal line Data can be pre-charged, which causes the part of the sub-pixels in the second column to be able to be pre-charged and the part of the sub-pixels in the second column to be unable to be pre-charged, thereby causing the second column of sub-pixels to have uneven brightness when displaying, i.e., to have a jagged edge display defect. Similarly, the second last column of sub-pixels also has uneven brightness when displaying, i.e., to have a jagged edge display defect.

[0046] Figure 5 A connection diagram of a sub-pixel and a data signal line according to an embodiment of the present disclosure is shown in FIG. 1. As shown, the first data signal line Data is connected to the first column of sub-pixels Pixel-F, the second data signal line Data is connected to the second column of sub-pixels, the third data signal line Data is connected to the third column of sub-pixels, and the last data signal line Data is connected to the last column of sub-pixels Pixel-L. Figure 5As shown, the display panel of the present disclosure shows that the data signal line Data away from the side of the last column of sub-pixels Pixel-L of the first column of sub-pixels Pixel-F is the first data signal line DT1, and the data signal line Data away from the side of the first column of sub-pixels Pixel-F of the last column of sub-pixels Pixel-L is the first data signal line DTN, and the first data signal line DT1 can be electrically connected with part of the sub-pixels of the second pixel column, and the first data signal line DTN can be electrically connected with part of the sub-pixels of the second pixel column. In this way, the first data signal line DT1 can be used to provide data signals for part of the sub-pixels of the second column, and through timing design, the first data signal line DT1 can be used to pre-charge part of the sub-pixels of the second column connected therewith, for example, the first data signal line DT1 provides data signals for the first column of sub-pixels Pixel-F synchronously, that is, the charging time of the second column of sub-pixels partially overlaps with the charging time of the first column of sub-pixels Pixel-F, for example, the on level of the gate signal line Gate connected with the first column of sub-pixels Pixel-F and the on level of the gate signal line Gate connected with the second column of sub-pixels are set to partially overlap, so that the data writing time of the sub-pixels of the second column connected with the first data signal line DT1 can partially overlap with the data writing time of the first column of sub-pixels Pixel-F, thereby pre-charging the sub-pixels of the second column connected with the first data signal line DT1. The other part of the sub-pixels of the second column can use the second data signal line Data to write data signals for the remaining sub-pixels of the second column during the process of writing data signals by the first data signal line DT1, so that the remaining sub-pixels of the second column can also be pre-charged. In this way, by arranging the first data signal line DT1 away from the side of the last column of sub-pixels Pixel-L of the first column of sub-pixels Pixel-F, the sub-pixels of the second column can all be pre-charged, that is, the first column of sub-pixels Pixel-F actually displayed can be pre-charged. Similarly, by arranging the first data signal line DTN away from the side of the first column of sub-pixels Pixel-F of the last column of sub-pixels Pixel-L, and connecting part of the sub-pixels of the second column with the first data signal line DTN, the first data signal line DTN can be used to provide data signals for part of the sub-pixels of the second column. At the same time, the remaining sub-pixels of the second column are connected with the second data signal line Data, that is, the second data signal line Data can be used to provide data signals for the remaining sub-pixels of the second column, so that the sub-pixels of the second column can all be pre-charged, that is, the last column of sub-pixels Pixel-L actually displayed can be pre-charged. Therefore, the display panel of the present disclosure can solve the problem of jagged display caused by uneven brightness at the edge.

[0047] As shown in Figure 5 the actual product, the first data signal line DT1 can also be connected to part of the sub-pixels in the first column, and the remaining sub-pixels in the first column can be connected to the second data signal line Data behind, so that the connection mode of the first column of sub-pixels Pixel-F and the data signal line Data is the same as that of the sub-pixels in the pixel column behind and the data signal line Data. Similarly, the last data signal line DTN can also be connected to part of the sub-pixels in the last column, and the remaining sub-pixels in the last column can be connected to the second data signal line Data. Of course, in other embodiments, the first column of sub-pixels Pixel-F and the last column of sub-pixels Pixel-L can also not be connected to the data signal line Data, as long as the data signal line Data has the above arrangement.

[0048] Continuing to refer to Figure 5 , the present disclosure shows that in the same pixel column, the sub-pixels in the odd rows are connected to the same data signal line Data, and the sub-pixels in the even rows are connected to another data signal line Data; among the two columns of sub-pixels distributed on both sides of the same data signal line Data and adjacent to each other, the even row sub-pixels of the former column of sub-pixels are connected to the same data signal line Data as the odd row sub-pixels of the latter pixel column. Among the two columns of sub-pixels between the two adjacent data signal lines Data, the sub-pixels in the odd rows are connected to the former data signal line Data, and the sub-pixels in the even rows are connected to the latter data signal line Data.

[0049] For example, taking the second pixel column as an example, the first row of sub-pixels, the third row of sub-pixels, the fifth row of sub-pixels, etc. of the second pixel column are all connected to the first data signal line DT1, and the second row of sub-pixels, the fourth row of sub-pixels, the sixth row of sub-pixels, etc. of the second pixel column are all connected to the second data signal line Data. In this way, part of the sub-pixels of the second pixel column can be pre-charged using the first data signal line DT1, and the remaining sub-pixels can be pre-charged using the second data signal line Data.

[0050] The fourth column of sub-pixels and the fifth column of sub-pixels are distributed on both sides of the third data signal line Data, so the second row of sub-pixels, the fourth row of sub-pixels, the sixth row of sub-pixels, etc. of the fourth pixel column and the first row of sub-pixels, the third row of sub-pixels, the fifth row of sub-pixels, etc. of the fifth pixel column are all connected to the third data signal line Data.

[0051] If the first pixel column and the second pixel column are located between the first data signal line and the second data signal line, then the odd-numbered rows of sub-pixels in the first pixel column and the second pixel column, such as the first row of sub-pixels, the third row of sub-pixels, the fifth row of sub-pixels, etc., are all connected to the first data signal line, and the even-numbered rows of sub-pixels in the first pixel column and the second pixel column, such as the second row of sub-pixels, the fourth row of sub-pixels, the sixth row of sub-pixels, etc., are all connected to the second data signal line.

[0052] In addition, such as Figure 3 As shown, the driving substrate may include a second substrate BP2 and a common electrode layer located on one side of the second substrate BP2. The common electrode layer may include multiple common electrode lines COM and a common electrode Vcom. Figure 2 As shown, the data signal lines Data and common electrode lines COM distributed in the display area are all located between the orthographic projections of two adjacent columns of sub-pixels on the second substrate BP2, and the orthographic projections of multiple data signal lines Data and multiple common electrode lines COM on the second substrate BP2 are alternately distributed in the row direction X.

[0053] Combination Figure 2 and Figure 4 This publicly disclosed display panel can be used Figure 1 Based on the display panel, the data signal line Data and the common electrode line COM are shifted to the left. Then, a new data signal line Data is added to the right of the last column of sub-pixels Pixel-L, and a new common electrode line COM is added between the last column of sub-pixels Pixel-L and the second-to-last column of sub-pixels. This gives the data signal line Data the arrangement structure shown in this disclosure. Then, according to... Figure 5 The connection method shown connects the data signal line to the corresponding sub-pixel.

[0054] Continue to refer to Figure 2 In this disclosed display panel, the display area may include n columns of sub-pixels, m data signal lines (Data), and k common electrode lines (COM), where m = n / 2 + 1, k = n / 2, n is a natural number greater than or equal to 2, and m and k are both natural numbers. For example, if the display area may include 4000 columns of sub-pixels, then the number of data signal lines (Data) in this disclosure is 2001, and the number of common electrode lines (COM) is 2000. (Comparison) Figure 4 It can be seen that in the related technologies, the number of data signal lines (Data) is 2000, and the number of common electrode lines (COM) is 1999. Clearly, the number of data signal lines (Data) and common electrode lines (COM) in the display panel of this disclosure differs from the number of data signal lines (Data) and common electrode lines (COM) in the related technologies.

[0055] Furthermore, the structure of the surrounding area of ​​the display panel disclosed herein may differ somewhat from that in related technologies. This will be further explained below with reference to the accompanying drawings.

[0056] Figure 6 This is a schematic diagram of the wiring of a display panel according to one embodiment of the present disclosure. The diagram only exemplarily shows the structure of some sub-pixels and some data signal lines Data on the second bezel GPR side, the third bezel DP side, and the fourth bezel DPO side. It should be understood that in actual products, there are a large number of pixel rows between the third bezel DP and the fourth bezel DPO. Here, only a three-row, five-column sub-pixel layout is used as an example to illustrate the wiring of the data signal lines Data. In an exemplary embodiment, the display panel also includes a fan-out area located on the side of the third bezel DP away from the display area, such as... Figure 6 As shown, the fan-out area may include multiple data fan-out lines (FIPs). Each data signal line (Data) is connected to one data fan-out line (FIP). Electrostatic discharge (ESD) units are connected between the first data signal line (DT1) and its corresponding data fan-out line (FIP), and between the last data signal line (DTN) and its corresponding data fan-out line (FIP). The ESD units are also connected to the common electrode line (COM). One end of each data fan-out line (FIP) is bonded to a chip, and the other end is connected to the data signal line (Data) via the ESD unit. In other words, the chip's data signal is transmitted to the corresponding data signal line (Data) through the data fan-out line (FIP). It should be understood that in this exemplary embodiment, both the first data signal line (DT1) and the last data signal line (DTN) are connected to their corresponding data fan-out line (FIP) via the ESD unit. That is, the first data signal line (DT1) and the last data signal line (DTN) have the same structure as the other data signal lines (Data) connected to the data fan-out line (FIP). The electrostatic discharge unit (ESD) is also connected to the common electrode line (COM). The ESD unit can release large currents through the common electrode line (COM), thereby preventing large currents from damaging the data signal line (Data).

[0057] As we know, a chip can have multiple data channels, and each data channel corresponds to a data fan-out line (FIP). In actual products, the number of channels on a chip can be greater than the number of data fan-out lines (FIPs). Therefore, the fan-out area can also include multiple dummy data fan-out lines (Dummy lines), so the sum of the number of dummy data fan-out lines and the number of data fan-out line FIPs equals the number of channels on the chip. The dummy data fan-out lines can improve the uniformity of the panel.

[0058] It is worth noting that the data fan-out line FIP corresponding to a certain chip in the display panel refers to the data fan-out line FIP connected to the chip. The dummy data fan-out line Dummy corresponding to a certain chip refers to the dummy data fan-out line Dummy located between the data fan-out line FIP connected to the chip and the data fan-out line FIP connected to an adjacent chip.

[0059] Further, the display panel in the present disclosure shows that the number of dummy data fan-out lines Dummy corresponding to at least some chips is different from the number of dummy data fan-out lines Dummy corresponding to other chips. For example, the plurality of chips can include a first chip connected to a first data signal line DT1, a second chip connected to a last data signal line DTN, and other chips, and the number of dummy data fan-out lines Dummy corresponding to the first chip and the number of dummy data fan-out lines Dummy corresponding to the second chip are both less than the number of dummy data fan-out lines Dummy corresponding to the other chips. For example, the display panel can be bound to have six chips connected, the first chip needs to be connected to the first data signal line DT1 through the data fan-out line FIP connected thereto, and the second chip needs to be connected to the last data signal line DTN through the data fan-out line FIP connected thereto. Therefore, the number of dummy data fan-out lines Dummy corresponding to the first chip and the second chip is reduced compared to the number of dummy data fan-out lines Dummy corresponding to the other chips. For example, the number of dummy data fan-out lines Dummy corresponding to the other chips can be two, and the first chip and the second chip each correspond to one dummy data fan-out line Dummy. Of course, the number of dummy data fan-out lines Dummy can be different in different products, and can be determined according to the number of channels of the chip.

[0060] Continuing to refer to Figure 6 In the present exemplary embodiment, the connection structure of the first data signal line DT1 and the last data signal line DTN at the fourth side frame DPO is the same as the connection structure of the other data signal lines Data at the fourth side frame DPO. For example, the first data signal line DT1 and the last data signal line DTN are each connected to an electrostatic discharge unit ESD at the fourth side frame DPO, and the electrostatic discharge unit ESD is also connected to the common electrode line COM to protect the data signal line Data through the electrostatic discharge unit ESD.

[0061] As shown in Figure 6 The last data signal line DTN is located between the last column of sub-pixels Pixel-L and the non-display area, and therefore, in the present exemplary embodiment, the spacing distance between the last column of sub-pixels Pixel-F and the non-display area boundary needs to be increased to ensure the routing space of the last data signal line DTN.

[0062] As described above, the display panel of the present disclosure can include a driving substrate and a color film substrate arranged in a cell, in an exemplary embodiment, the driving substrate can include a second substrate BP2 and a gate metal layer located on one side of the second substrate BP2, the gate metal layer can include a plurality of conductive blocks 100 located in the non-display area and a plurality of gate signal lines Gate located in the display area, part of the structure of the gate signal lines Gate is used to form the gate of the transistor T, the conductive blocks 100 are located in the non-display area close to the edge of the display area, the conductive blocks 100 are connected to the output signal lines of the shift register unit on one side through the via, and are connected to the gate signal lines Gate on the other side, that is, the output signal lines of the shift register unit in the non-display area are connected to the gate signal lines Gate in the display area through the conductive blocks 100, so as to provide the gate control signal to the transistor T through the gate signal lines Gate.

[0063] The orthographic projection of part of the conductive blocks 100 on the second substrate BP2 is located in the orthographic projection of the first frame GPL on the second substrate BP2, and the orthographic projection of part of the conductive blocks 100 on the second substrate BP2 is located in the orthographic projection of the second frame GPR on the second substrate BP2, that is, a plurality of conductive blocks 100 are distributed at the first frame GPL and the second frame GPR, wherein any two adjacent sub-pixels in the row direction X have a first interval d1 in the row direction X, and the shortest distance d0 between the orthographic projection of the conductive block 100 and the adjacent sub-pixel on the second substrate BP2 in the row direction X matches the first interval d1.

[0064] Specifically, Figure 7 For Figure 6 The local enlarged view at M in the middle, combined with Figure 6 And Figure 7The first interval d1 represents the pixel size of two sub-pixels in the row direction X. The conductive block 100 is located at the edge of the non-display area, so that the shortest distance d0 of the conductive block 100 and the sub-pixel adjacent to it in the orthographic projection of the second substrate BP2 in the row direction X is the shortest distance d0 between the first column of sub-pixels Pixel-F or the last column of sub-pixels Pixel-L and the non-display area boundary. Obviously, the shortest distance d0 represents the distance between the left sub-pixel and the left non-display area boundary and the distance between the right sub-pixel and the right non-display area boundary. The shortest distance d0 matches the first interval d1, which can be understood as the shortest distance d0 being the same as the first interval d1 or the shortest distance d0 being close to the first interval d1. For example, in actual products, when the ratio of the shortest distance d0 of the conductive block 100 and the sub-pixel adjacent to it in the orthographic projection of the second substrate BP2 in the row direction X to the first interval d1 is greater than or equal to 0.8 and less than or equal to 1.2, it can be considered that the shortest distance d0 matches the first interval d1. In this way, on the one hand, the gap between the first column of sub-pixels Pixel-F or the last column of sub-pixels Pixel-L and the non-display area boundary can be used to arrange the first data signal line DT1 and the last data signal line DTN, and on the other hand, the shortest distance d0 matches the row direction X distance between the sub-pixels in the display area, which can make the parasitic effect of the first data signal line DT1 and the last data signal line DTN with the corresponding column of sub-pixels and the parasitic effect of other positions in the display area the same, thereby ensuring the uniformity of display. Of course, in actual products, because the first column of sub-pixels Pixel-F and the last column of sub-pixels Pixel-L are both blocked by the outer frame BMO and do not display, the shortest distance d0 can also differ from the first interval d1, which all belong to the protection scope of the present disclosure.

[0065] It is worth noting that the shortest distance d0 of the conductive block 100 and the sub-pixel adjacent to it in the orthographic projection of the second substrate BP2 in the row direction X can be understood as the orthographic projection of the conductive block 100 on the second substrate BP2 having a first side edge close to the display area, and the orthographic projection of the first column of sub-pixels Pixel-F or the last column of sub-pixels Pixel-L on the second substrate BP2 having a second side edge close to the non-display area. The distance from any node on the first side edge to the second side edge in the row direction X is the shortest distance d0.

[0066] In the example embodiment, the shortest distance d0 of the conductive block 100 and the sub-pixel adjacent thereto in the orthographic projection on the row direction X of the second substrate BP2 can be greater than or equal to 18 μm and less than or equal to 26 μm, for example, can be 18 μm, 19 μm, 20 μm, 21 μm, 22 μm, 23 μm, 24 μm, 24.2 μm, 25 μm, 26 μm, etc. In this way, the shortest distance d0 can be matched to the first interval d1 between the adjacent sub-pixels in the display area, and the first data signal line DT1 can be arranged outside the first column of sub-pixels Pixel-F and the first data signal line DTN can be arranged outside the last column of sub-pixels Pixel-F.

[0067] It should be understood that the wiring structure of the first data signal line DT1 at the first frame GPL is similar to the wiring structure of the first data signal line DT1 at the second frame GPR, which will not be described here. Figure 6 The wiring structure of the first data signal line DTN at the second frame GPR is similar to that shown in the figure, which will not be described here.

[0068] The present disclosure also provides a display device, which can include a television, a tablet, etc., and the display device can include the display panel according to any of the embodiments of the present disclosure.

[0069] Other embodiments of the present disclosure will be apparent to those skilled in the art after consideration of the specification and practice of the application disclosed herein. The application is intended to cover any variations, uses or adaptations of the present disclosure following, in general, the principles of the present disclosure and including such departures from the present disclosure that come within known or customary practice within the art to which the present disclosure pertains. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the present disclosure are indicated by the claims.

Claims

1. A display panel, characterized by, The display area includes a plurality of columns of sub-pixels arranged in sequence and at intervals in a row direction, and a data signal line is arranged on one side of the first column of sub-pixels away from the last column of sub-pixels and on one side of the last column of sub-pixels away from the first column of sub-pixels. The display panel includes a color filter substrate, and the color filter substrate includes: a first substrate substrate; a color resistance layer located on one side of the first substrate substrate and in a display area, the color resistance layer including a plurality of sub-pixels arranged in an array; a frame area arranged circumferentially around the display area, the frame area including a first frame and a second frame arranged opposite each other in a row direction; wherein the first frame covers the first column of sub-pixels in the first substrate substrate in orthographic projection and partially overlaps the second column of sub-pixels in the first substrate substrate in orthographic projection; the second frame covers the last column of sub-pixels in the first substrate substrate in orthographic projection and partially overlaps the penultimate column of sub-pixels in the first substrate substrate in orthographic projection; the first frame and the second frame are both black matrices.

2. The display panel of claim 1, wherein, The data signal line on one side of the first column of sub-pixels away from the last column of sub-pixels is a first data signal line, and the data signal line on one side of the last column of sub-pixels away from the first column of sub-pixels is a penultimate data signal line, the first data signal line is electrically connected to part of the sub-pixels of the second pixel column, and the penultimate data signal line is electrically connected to part of the sub-pixels of the penultimate column.

3. The display panel of claim 2, wherein, The first data signal line is also electrically connected to part of the sub-pixels of the first pixel column, and the sub-pixels of the first pixel column connected to the first data signal line and the sub-pixels of the second pixel column connected to the first data signal line are located in the same row. The penultimate data signal line is also electrically connected to part of the sub-pixels of the Nth pixel column, and the sub-pixels of the Nth pixel column connected to the penultimate data signal line and the sub-pixels of the (N-1)th pixel column connected to the penultimate data signal line are located in the same row.

4. The display panel of claim 1, wherein, Among the sub-pixels of the same pixel column, the sub-pixels in the odd-numbered rows are connected to the same data signal line, and the sub-pixels in the even-numbered rows are connected to another data signal line. Among the two columns of sub-pixels distributed on both sides of the same data signal line and adjacent to each other, the even-numbered row sub-pixels of the previous column of sub-pixels are connected to the same data signal line as the odd-numbered row sub-pixels of the next pixel column. Among the two columns of sub-pixels distributed between the adjacent two data signal lines, the sub-pixels in the odd-numbered rows are connected to the previous data signal line, and the sub-pixels in the even-numbered rows are connected to the next data signal line.

5. The display panel of claim 1, wherein, The display panel includes a driving substrate and a color filter substrate arranged in a cell, the sub-pixels are located on the color filter substrate, and the color resistance layer includes a plurality of sub-pixels arranged in an array along the row and column directions. The driving substrate includes: a second substrate substrate; a common electrode layer located on one side of the second substrate substrate, the common electrode layer including: a plurality of common electrode lines located in a display area, the plurality of common electrode lines extending in a column direction in orthographic projection on the second substrate substrate and arranged in sequence and at intervals in a row direction. A source-drain metal layer is located on a side of the common electrode layer away from the second substrate, and the source-drain metal layer includes a plurality of data signal lines; The display panel includes a plurality of data signal lines, and the data signal lines and the common electrode lines are located between adjacent two columns of sub-pixels in the orthogonal projection of the second substrate, and the orthogonal projections of the plurality of data signal lines and the plurality of common electrode lines are alternately arranged in the row direction.

6. The display panel of claim 5, wherein, The display area includes n columns of sub-pixels, m data signal lines, and k common electrode lines, where m = n / 2 + 1, k = n / 2, n is a natural number greater than or equal to 2, and m and k are natural numbers.

7. The display panel of claim 1, wherein, The display panel includes a plurality of pixel driving circuits, and each pixel driving circuit includes a transistor, and a gate of the transistor is connected to a gate signal terminal; the display panel includes a driving substrate and a color film substrate arranged in a cell-by-cell manner, and the driving substrate includes: A second substrate; A gate metal layer is located on a side of the second substrate, and the gate metal layer includes: A plurality of conductive blocks are located in the non-display area of the display panel, and the conductive blocks are connected to the output signal lines of the shift register unit through vias; A plurality of gate signal lines are located in the display area, the gate signal lines are connected to the conductive blocks, and part of the structure of the gate signal lines is used to form the gate of the transistor; Part of the orthogonal projection of the conductive blocks on the second substrate is located in the orthogonal projection of the first frame on the second substrate, and part of the orthogonal projection of the conductive blocks on the second substrate is located in the orthogonal projection of the second frame on the second substrate; Any two adjacent sub-pixels in the row direction have a first interval in the row direction, and the shortest distance between the orthogonal projection of the conductive block and the adjacent sub-pixel on the second substrate in the row direction matches the first interval.

8. The display panel of claim 7, wherein, The ratio of the shortest distance between the orthogonal projection of the conductive block and the adjacent sub-pixel on the second substrate in the row direction to the first interval is greater than or equal to 0.8 and less than or equal to 1.

2.

9. The display panel of claim 7, wherein, The shortest distance is greater than or equal to 18 μm and less than or equal to 26 μm.

10. The display panel of claim 1, wherein, The frame area further includes a third frame and a fourth frame arranged opposite in the column direction; the display panel further includes: A fan-out area is located on a side of the third frame away from the display area, and the fan-out area includes: A plurality of data fan-out lines, one data signal line is connected to one data fan-out line, and an electrostatic discharge unit is connected between the first data signal line and the corresponding data fan-out line and between the last data signal line and the corresponding data fan-out line, and the electrostatic discharge unit is also connected to the common electrode line.

11. The display panel of claim 10, wherein, The display panel further includes a plurality of chips, and the fan-out area further includes a plurality of virtual data fan-out lines; The number of data channels of the chip is equal to the sum of the number of data fan-out lines and virtual data fan-out lines corresponding to the chip.

12. The display panel of claim 11, wherein, The number of virtual data fan-out lines corresponding to at least part of the chips is different from the number of virtual data fan-out lines corresponding to other chips.

13. The display panel of claim 12, wherein, The plurality of chips include a first chip connected to the first data signal line and a second chip connected to the last first data signal line. The number of virtual data fan-out lines corresponding to the first chip and the number of virtual data fan-out lines corresponding to the second chip are both less than the number of virtual data fan-out lines corresponding to other chips.

14. The display panel of claim 13, wherein, The first chip and the second chip both correspond to one virtual data fan-out line.

15. The display panel of claim 1, wherein, The frame region further includes a third frame and a fourth frame oppositely arranged in the column direction. The first data signal line and the last first data signal line are both connected to an electrostatic discharge unit in a non-display area on one side of the fourth frame, and the electrostatic discharge unit is further connected to a common electrode line.

16. A display device comprising: The display panel includes any one of claims 1-15.

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