A method, device, equipment and storage medium for pre-order storage

Abstract

The present application discloses a method, device, equipment and storage medium for storing pending orders, which relates to the technical field of data storage, and includes: when receiving a pending order, querying whether there is an address of the first-level address management area of the order placement channel number in the preset FPGA internal address management according to the order placement channel number corresponding to the pending order; if it exists, reading the first-level address management area according to the address to obtain the maximum order number of each second-level data storage area, and determining the insertion position of the pending order based on the size relationship between the maximum order number and the order number of the pending order; querying the address of the second-level data storage area in the first-level address management area by using the insertion position, and reading the second-level data storage area based on the address of the second-level data storage area to obtain each target order number; determining the to-be-inserted address of the pending order based on the size order of each target order number, and storing the pending order into the second-level data storage area according to the to-be-inserted address. The present application realizes the optimized storage of pending orders.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and particularly relates to a method, device, equipment and storage medium for storing pending orders. Background Art

[0002] In the process of securities and futures trading, for professional investors in high-frequency trading, achieving '0 latency' in processing orders is one of the technical goals pursued. Therefore, the function of pending orders has emerged. Orders are placed in advance before the market opens, and after the market opens, the orders are directly reported to the exchange. So the number of orders is large and the corresponding storage will also be relatively large. Since the orders stored on different platforms are different, in order to ensure the maximum utilization rate of the storage space, a storage management algorithm for pending orders is generated. Thus, within an FPGA (Field Programmable Gate Array), under the same resource storage format, it is one of the research topics of high-frequency trading counters to be able to reuse these storage spaces as much as possible and use the storage space flexibly. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a method, device, equipment and storage medium for storing pending orders, which can optimize the scheme of the pending order storage method, greatly reduce the storage space, and improve the utilization rate of the space. The specific scheme is as follows:

[0004] In a first aspect, the present application discloses a method for storing pending orders, including:

[0005] When receiving a pending order, query whether there is an address of a preset first-level address management area corresponding to the order placement channel number in the preset internal address management of the FPGA according to the order placement channel number corresponding to the pending order;

[0006] If it exists, read the preset first-level address management area according to the address of the preset first-level address management area, obtain the maximum order number of each preset second-level data storage area, and determine the insertion position of the pending order based on the size relationship between the maximum order number and the order number of the pending order;

[0007] Query the address of the preset second-level data storage area in the preset first-level address management area by using the insertion position, and read the preset second-level data storage area based on the address of the preset second-level data storage area to obtain the target order numbers of the stored pending orders;

[0008] Determine the to-be-inserted address of the pending order based on the size order of each of the target order numbers, and store the pending order in the preset second-level data storage area according to the to-be-inserted address.

[0009] Optionally, after querying whether there is a preset first-level address management area address corresponding to the order placement channel number in the preset FPGA internal address management according to the order placement channel number corresponding to the limit order, the method further includes:

[0010] If there is no preset first-level address management area address corresponding to the order placement channel number in the preset FPGA internal address management, a first-level address management area and a second-level address management area are newly created to store the information of the limit order.

[0011] Optionally, determining the insertion position of the limit order based on the size relationship between the maximum order number and the order number of the limit order includes:

[0012] If the order number of the limit order is less than the maximum order number, the preset second-level data storage area corresponding to the maximum order number is determined as the insertion position of the limit order.

[0013] Optionally, the method further includes:

[0014] If the number of preset second-level address management area addresses stored in the preset first-level address management area reaches a first quantity threshold, a new first-level address management area is applied for, and the new first-level address management area address corresponding to the new first-level address management area is stored in the preset first-level address management area;

[0015] If the number of limit orders stored in the preset second-level address management area reaches a second quantity threshold, a new second-level address management area is applied for, and the new second-level address management area address corresponding to the new second-level address management area is stored in the current first-level address management area.

[0016] Optionally, the method further includes:

[0017] If there is no first-level address management area of the next link in the preset first-level address management area, when the limit order is deleted at the front end, the preset first-level address management area address is recycled to the preset address cache pool, so that the preset first-level address management area address can be reused when the front end applies for a first-level address management area address;

[0018] If there is a first-level address management area of the next link in the preset first-level address management area and there is no first-level address management area of the previous link, when the limit order is deleted at the front end, the preset first-level address management area address is recycled to the preset address cache pool, so that the preset first-level address management area address can be reused when the front end applies for a first-level address management area address, and the first-level address management area address of the next link is written into the preset FPGA internal address management;

[0019] If there are the first-level address management areas of the next link and the previous link in the preset first-level address management area, and the first-level address management area of the previous link is an address read from non-preset FPGA internal address management, when deleting the pending order at the front end, recycle the preset first-level address management area address to the preset address cache pool, so that the preset first-level address management area address can be reused when the front end applies for a first-level address management area address, and write the first-level address management area address of the next link to the first address bit corresponding to the first-level address management area of the previous link to eliminate the invalid link.

[0020] Optionally, after storing the pending order to the preset second-level data storage area according to the to-be-inserted address, it further includes:

[0021] If the number of pending orders in the preset second-level data storage area reaches the third quantity threshold, apply for a new second-level data storage area, and store the order numbers of the pending orders in the preset second-level data storage area that meet the preset conditions to the new second-level data storage area.

[0022] Optionally, the method further includes:

[0023] When deleting the pending order at the front end, if there is one pending order in the preset second-level data storage area, recycle the preset second-level data storage area address to the preset address cache pool, so that the preset second-level data storage area address can be reused when the front end applies for a second-level address management area address;

[0024] When deleting the pending order at the front end, if there are several pending orders in the preset second-level data storage area, delete the pending orders in the preset second-level data storage area according to the to-be-inserted address, rearrange the remaining pending orders in the preset second-level data storage area, and then write the rearranged pending orders to the preset second-level data storage area.

[0025] In a second aspect, the present application discloses a pending order storage device, including:

[0026] An address query module, configured to query whether there is a preset first-level address management area address corresponding to the order placement channel number in the preset FPGA internal address management when receiving a pending order according to the order placement channel number corresponding to the pending order;

[0027] An insertion position determination module, configured to, if it exists, read a preset primary address management area according to the preset primary address management area address, obtain the maximum order number of each preset secondary data storage area, and determine the insertion position of the pending order based on the size relationship between the maximum order number and the order number of the pending order;

[0028] An order number acquisition module, configured to query the preset secondary data storage area address in the preset primary address management area by using the insertion position, and read the preset secondary data storage area based on the preset secondary data storage area address to obtain the target order numbers of the stored pending orders;

[0029] A pending order storage module, configured to determine the pending insertion address of the pending order based on the size order of each of the target order numbers, and store the pending order in the preset secondary data storage area according to the pending insertion address.

[0030] In a third aspect, the present application discloses an electronic device, including:

[0031] A memory, configured to store a computer program;

[0032] A processor, configured to execute the computer program to implement the pending order storage method as described above.

[0033] In a fourth aspect, the present application discloses a computer-readable storage medium, configured to store a computer program, wherein the computer program, when executed by a processor, implements the pending order storage method as described above.

[0034] When this application stores the pre-arranged order, first, when receiving the pre-arranged order, it queries whether there is an address of the preset first-level address management area corresponding to the order placement channel number in the preset FPGA internal address management according to the order placement channel number corresponding to the pre-arranged order; if it exists, it reads the preset first-level address management area according to the address of the preset first-level address management area, obtains the maximum order number of each preset second-level data storage area, and determines the insertion position of the pre-arranged order based on the size relationship between the maximum order number and the order number of the pre-arranged order; then it queries the address of the preset second-level data storage area in the preset first-level address management area using the insertion position, and reads the preset second-level data storage area based on the address of the preset second-level data storage area to obtain the target order numbers of the stored pre-arranged orders; finally, it determines the address to be inserted for the pre-arranged order based on the size order of each target order number, and stores the pre-arranged order in the preset second-level data storage area according to the address to be inserted. It can be seen that this application dynamically allocates the address of the order placement channel number of the pre-arranged order through the FPGA internal address management, the first-level address management area, and the second-level data storage area, greatly increasing the storage space utilization rate. Each index is dynamically allocated, greatly saving the consumption of FPGA internal resources, greatly reducing the storage space, further improving the processing speed of order information, and sorting the orders in ascending order of the order number, which is convenient for the FPGA to process the pre-arranged orders in sequence. Brief Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0036] Figure 1 It is a flowchart of a method for storing pre-arranged orders disclosed in this application;

[0037] Figure 2 It is a schematic diagram of the data format of the first-level address management area disclosed in this application;

[0038] Figure 3 It is a schematic diagram of the process after the second-level data storage area is full of 16 disclosed in this application;

[0039] Figure 4 It is a schematic diagram of the structure of a device for storing pre-arranged orders disclosed in this application;

[0040] Figure 5 It is a structural diagram of an electronic device disclosed in this application. Detailed Embodiments

[0041] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0042] Currently, the storage method builds a dynamic storage space according to the internal storage resources and external storage resources of the FPGA. Each index can apply for a piece of space to store the current order number. After the current index is full, another piece of storage space is applied for. And the pending orders under the current index are stored in ascending order of the order number. After the pending order is sent out, the pending order with the current order number is deleted to ensure that the read pending orders are all valid. However, when the current pending order cannot be reported to the exchange for 1v2 search, querying all the pending orders under the current index will result in a very slow query time response because all the order numbers need to be read from the external storage resources of the FPGA, so it takes a relatively long time, but the resource reuse rate is relatively high. To solve the above technical problems, this application discloses a method for storing pending orders, which can optimize the storage method of pending orders on the basis of the existing high-frequency trading system, greatly reducing the storage space and improving the utilization rate of the space.

[0043] See Figure 1 As shown, the embodiments of the present invention disclose a method for storing pending orders, including:

[0044] Step S11: When receiving a pending order, query whether there is an address of a preset first-level address management area corresponding to the order placement channel number in the preset FPGA internal address management according to the order placement channel number corresponding to the pending order.

[0045] In this embodiment, the storage of pending orders in this application is divided into three parts in total: FPGA internal address management, first-level address management area, and second-level data storage area. Each index in the FPGA internal address management is unique and stores the address of the first-level address management area. A total of 16 data can be stored in one piece in the first-level address management area, including 15 addresses of the second-level data storage area and the largest order number of the current second-level data storage area. There is also one data storing the address of the next first-level address management area. Second-level data storage area: A total of 16 data can be stored in this piece, all of which are order numbers of pending orders, and the order numbers are arranged in ascending order. And each order number carries other relevant field information that needs to be stored.

[0046] When receiving a pre-order, query whether there is a preset first-level address management area address corresponding to the order placement channel number in the preset FPGA internal address management according to the order placement channel number corresponding to the pre-order. Here, the order placement channel number corresponding to the pre-order also refers to the current index. According to the index of the order, all order numbers below the current index can be queried, and it is also supported to query all order numbers smaller than a certain order number. According to the index of the order, all order numbers below the current index can also be deleted. When querying whether the order of this index exists next time, directly query and return that there is none. In this way, the corresponding first-level address management area address can be queried more simply and efficiently. If there is no preset first-level address management area address corresponding to the order placement channel number in the preset FPGA internal address management, a first-level address management area and a second-level address management area are newly created to store the information of the pre-order. That is, there is no pre-order hanging, indicating that this pre-order is the first order in this channel and three storage areas need to be applied for by itself. In addition, it should be noted that when the front end deletes one of the pre-orders, and this pre-order is the last pre-order under this index, the data in the corresponding index in the FPGA internal address management needs to be cleared at this time. This data refers to the stored data corresponding to this pre-order. After all are cleared, this pre-order cannot be found when querying again.

[0047] Step S12: If it exists, read the preset first-level address management area according to the preset first-level address management area address, obtain the maximum order number of each preset second-level data storage area, and determine the insertion position of the pre-order based on the size relationship between the maximum order number and the order number of the pre-order.

[0048] In this embodiment, if there is a preset first-level address management area address corresponding to the order placement channel number in the preset FPGA internal address management, it indicates that there is a corresponding pre-order for the current order placement channel number. At this time, the newly placed pre-order needs to be mounted under this channel to form a tree structure with the previous orders. If there is no hanging pre-order, then a new address needs to be applied for as the start of the tree. Then, the preset first-level address management area is read according to the preset first-level address management area address, and the maximum order number of each preset second-level data storage area is obtained. Then, judge the order number of the pre-order of the current index in which second-level data storage area (the data format stored in the first-level storage area, the corresponding second-level data storage area address, and the maximum order number of the corresponding second-level data storage area). By comparing the order number of the pre-order with the maximum order number of each piece in the first-level storage area, the insertion position of the current pre-order can be quickly found. That is, if the order number of the pre-order is less than the maximum order number, the preset second-level data storage area corresponding to the maximum order number is determined as the insertion position of the pre-order.

[0049] Step S13: Query the preset secondary data storage area address in the preset primary address management area using the insertion position, and read the preset secondary data storage area based on the preset secondary data storage area address to obtain each target order number of the stored pending orders.

[0050] In this embodiment, the secondary data storage area address can be queried using the insertion position (if it is the first pending order in this channel, then the maximum order number of the corresponding secondary data storage is infinite), and the data storage format is as Figure 2 shown.

[0051] However, as Figure 3 shown, after 16 pending orders are stored in the secondary data storage area, a new secondary address management area needs to be applied for, and then the address of the corresponding secondary address management area is stored in the current primary address management area. In addition, when 15 secondary address management areas are stored in the primary address management area, a primary address management area needs to be applied for, and then the address of the newly applied primary address management area is stored in the first address of the previous primary address management area to form an address link for easy jump to the next primary address management area.

[0052] Finally, read the preset secondary data storage area based on the preset secondary data storage area address queried from the primary address management area to obtain each target order number of the stored pending orders.

[0053] Step S14: Determine the insertion address of the pending order based on the size order of each target order number, and store the pending order in the preset secondary data storage area according to the insertion address.

[0054] In this embodiment, after obtaining the order numbers of each target pre-arranged order that has been stored, it is determined which address in the current secondary data storage area the order number of the currently indexed pre-arranged order should be inserted into, and the corresponding order numbers are stored in the secondary data storage area in sequence (arranged from small to large). That is, the address where the pre-arranged order is to be inserted is determined based on the size order of each target order number, and the pre-arranged order is stored in the preset secondary data storage area according to the address to be inserted. However, if the current order becomes 16 addresses after insertion, another secondary data storage area needs to be applied for, and then the first 8 order numbers are stored in the previous secondary data storage area, and the last 8 order numbers are stored in the subsequent secondary data storage area. Since the order numbers corresponding to the pre-arranged orders are irregular, space needs to be reserved so that when subsequent orders come, there is a position to write, avoiding frequent applications. For example, the order numbers 1, 2, 3, 4, 5, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18 corresponding to the pre-arranged orders in channel 0 are received. The first 8 order numbers from 1 to 10 are stored in the previous secondary data storage area, and the last 8 order numbers from 11 to 18 are stored in the subsequent secondary data storage area. At this time, if a 9 comes, it can be directly written into the first area without introducing a large number of logical operations due to inability to insert, wasting resources.

[0055] In addition, when there is only one pre-arranged order in the current secondary data storage area and the front end wants to delete this pre-arranged order, then directly recycle the current secondary address management area to the preset address cache pool and enter the queuing sequence for use when applying next time. If the front end comes to delete and there are multiple pre-arranged orders in the current secondary data storage area, then find the position where the current pre-arranged order is located, and after removing it, rearrange and write it into the secondary data storage area. In this way, in addition to making full use of the parallel processing characteristics of the FPGA, based on the characteristics of the algorithm itself, the processing speed of order information in the high-frequency trading system is further improved, and the space of the address cache pool is more flexible, with dynamic address allocation, supporting applying for as much as needed and releasing the space after use. And this application is also applicable to storage processing situations related to other fields.

[0056] When this application stores the pre-arranged order, first, when receiving the pre-arranged order, it queries whether there is an address of the preset first-level address management area corresponding to the order placement channel number in the preset FPGA internal address management according to the order placement channel number corresponding to the pre-arranged order; if it exists, it reads the preset first-level address management area according to the address of the preset first-level address management area, obtains the maximum order number of each preset second-level data storage area, and determines the insertion position of the pre-arranged order based on the size relationship between the maximum order number and the order number of the pre-arranged order; then it queries the address of the preset second-level data storage area in the preset first-level address management area using the insertion position, and reads the preset second-level data storage area based on the address of the preset second-level data storage area to obtain the target order numbers of the stored pre-arranged orders; finally, it determines the address to be inserted for the pre-arranged order based on the size order of each target order number, and stores the pre-arranged order in the preset second-level data storage area according to the address to be inserted. It can be seen that this application dynamically allocates the address of the order placement channel number of the pre-arranged order through the FPGA internal address management, the first-level address management area, and the second-level data storage area, greatly increasing the storage space utilization rate. Each index is dynamically allocated, greatly saving the consumption of FPGA internal resources, greatly reducing the storage space, further improving the processing speed of order information, and sorting the orders in ascending order of the order number, which is convenient for the FPGA to process the pre-arranged orders in sequence.

[0057] Based on the previous embodiment, when 15 second-level address management areas are stored in the first-level address management area, a first-level address management area needs to be applied for, and then the address of the newly applied first-level address management area is stored in the first address of the previous first-level address management area to form an address link for easy jump to the next first-level address management area. Next, when there is only one second-level address management area left in the first-level address management area and there is only one pre-arranged order left in this second-level address management area, the front end wants to delete this pre-arranged order, and the possible scenarios will be described.

[0058] First, there is no first-level address management area for the next link in the current first-level address management area:

[0059] That is to say, if there is no first-level address management area for the next link in the preset first-level address management area, when the front end deletes the pre-embedded order, the address of the preset first-level address management area is recycled to the preset address cache pool, so that the preset first-level address management area address can be reused when the front end applies for the first-level address management area address. The address cache pool in this application supports the functions of applying for addresses and returning addresses. Currently, the address cache pool built by using the internal storage resources and external storage resources of the FPGA will first apply for 8 addresses and place them in the address cache pool during initialization. When there is no data in the address cache pool, 8 more addresses will be applied and stored in the address cache pool. Each application is for 8 addresses. If there is no data in the internal storage resources of the FPGA, but there is data in the external storage resources of the FPGA, the addresses in the external storage resources of the FPGA need to be moved to the internal storage resources of the FPGA, and each move is for 8 addresses. When the front end applies for an address, it will directly read it from the address cache pool and send it out. When the front end returns an address, the address will be placed in the address cache pool for queuing. The queuing method is as follows: First: When there is no data in the external storage resources of the FPGA and the internal storage resources of the FPGA are not full of data, it is directly stored in the internal storage resources of the FPGA. Second: After the internal storage resources of the FPGA are full of data, it starts to be stored in the external storage resources of the FPGA. Third: When there is data in the external storage resources of the FPGA, even if the internal storage resources of the FPGA are not full, it needs to be stored in the external storage resources of the FPGA. In this way, the recycled addresses need to enter the address cache pool, which can achieve absolute utilization of space and will not waste space.

[0060] Second, the current first-level address management area has a next link, but no previous link, and the first-level address management area is the address read out by the FPGA internal address management:

[0061] That is to say, if there is a first-level address management area for the next link in the preset first-level address management area and there is no first-level address management area for the previous link, when the front end deletes the pre-embedded order, the address of the preset first-level address management area is recycled to the preset address cache pool, so that the preset first-level address management area address can be reused when the front end applies for the first-level address management area address, and the address of the first-level address management area of the next link is written into the preset FPGA internal address management. At this time, the current first-level address management area is recycled, and the address of the first-level address management area of the next link is written into the FPGA internal address management.

[0062] Third, the current first-level address management area has a next link and a previous link, and the first-level address management area is not the address read out by the FPGA internal address management:

[0063] That is to say, if there are the first-level address management areas of the next link and the previous link in the preset first-level address management area, and the first-level address management area of the previous link is an address read from non-preset FPGA internal address management, then when deleting the limit order in the front end, the address of the preset first-level address management area is recycled to the preset address cache pool, so that when the front end applies for the address of the first-level address management area, the address of the preset first-level address management area can be reused, and the address of the first-level address management area of the next link is written to the first address bit corresponding to the first-level address management area of the previous link to eliminate the invalid link. At this time, the current first-level address management area is recycled, and the address of the first-level address management area of the next link is written to the first address bit of the first-level address management area of the previous link, forming the function of eliminating the invalid link of the link.

[0064] In this way, the space of the address cache pool is more flexible, the address is dynamically allocated, supporting applying for as much as needed and quickly releasing the space after use, greatly increasing the storage space utilization rate and greatly saving the consumption of FPGA internal resources.

[0065] See Figure 4 As shown, an embodiment of the present invention discloses a limit order storage device, including:

[0066] An address query module 11, configured to, when receiving a limit order, query whether there is an address of a preset first-level address management area corresponding to the order placement channel number in the preset FPGA internal address management according to the order placement channel number corresponding to the limit order;

[0067] An insertion position determination module 12, configured to, if it exists, read the preset first-level address management area according to the address of the preset first-level address management area, obtain the maximum order number of each preset second-level data storage area, and determine the insertion position of the limit order based on the size relationship between the maximum order number and the order number of the limit order;

[0068] An order number acquisition module 13, configured to query the address of the preset second-level data storage area in the preset first-level address management area by using the insertion position, and read the preset second-level data storage area based on the address of the preset second-level data storage area to obtain the target order numbers of the stored limit orders;

[0069] A limit order storage module 14, configured to determine the to-be-inserted address of the limit order based on the size order of each target order number, and store the limit order in the preset second-level data storage area according to the to-be-inserted address.

[0070] When this application stores the pre-arranged order, first, when receiving the pre-arranged order, it queries whether there is a corresponding preset first-level address management area address in the preset FPGA internal address management according to the order placement channel number corresponding to the pre-arranged order; if it exists, it reads the preset first-level address management area according to the preset first-level address management area address, obtains the maximum order number of each corresponding preset second-level data storage area, and determines the insertion position of the pre-arranged order based on the size relationship between the maximum order number and the order number of the pre-arranged order; then it uses the insertion position to query the preset second-level data storage area address in the preset first-level address management area, and reads the preset second-level data storage area based on the preset second-level data storage area address to obtain the target order numbers of the stored pre-arranged orders; finally, it determines the to-be-inserted address of the pre-arranged order based on the size order of each target order number, and stores the pre-arranged order in the preset second-level data storage area according to the to-be-inserted address. It can be seen that this application dynamically allocates the address of the order placement channel number of the pre-arranged order through the FPGA internal address management, the first-level address management area, and the second-level data storage area, greatly increasing the storage space utilization rate. Each index is dynamically allocated, greatly saving the consumption of FPGA internal resources, greatly reducing the storage space, further improving the processing speed of order information, and sorting the orders in ascending order of the order number, which is convenient for the FPGA to process the pre-arranged orders in sequence.

[0071] In some specific embodiments, the device is further configured to, if there is no corresponding preset first-level address management area address in the preset FPGA internal address management, create a first-level address management area and a second-level address management area to store the information of the pre-arranged order.

[0072] In some specific embodiments, the insertion position determination module 12 may specifically be configured to, if the order number of the pre-arranged order is less than the maximum order number, determine the preset second-level data storage area corresponding to the maximum order number as the insertion position of the pre-arranged order.

[0073] In some specific embodiments, the device is further configured to, if the number of preset second-level address management area addresses stored in the preset first-level address management area reaches the first quantity threshold, apply for a new first-level address management area, and store the new first-level address management area address corresponding to the new first-level address management area in the preset first-level address management area; if the number of pre-arranged orders stored in the preset second-level address management area reaches the second quantity threshold, apply for a new second-level address management area, and store the new second-level address management area address corresponding to the new second-level address management area in the current first-level address management area.

[0074] In some specific embodiments, the device is further configured to, if there is no first-level address management area of the next link in the preset first-level address management area, when deleting the pre-arranged order at the front end, recycle the address of the preset first-level address management area to a preset address cache pool, so that when the front end applies for an address of the first-level address management area, the address of the preset first-level address management area can be reused; if there is a first-level address management area of the next link in the preset first-level address management area and there is no first-level address management area of the previous link, when deleting the pre-arranged order at the front end, recycle the address of the preset first-level address management area to the preset address cache pool, so that when the front end applies for an address of the first-level address management area, the address of the preset first-level address management area can be reused, and write the address of the first-level address management area of the next link into the preset internal address management of the FPGA; if there are a first-level address management area of the next link and a first-level address management area of the previous link in the preset first-level address management area, and the first-level address management area of the previous link is an address read from a non-preset internal address management of the FPGA, when deleting the pre-arranged order at the front end, recycle the address of the preset first-level address management area to the preset address cache pool, so that when the front end applies for an address of the first-level address management area, the address of the preset first-level address management area can be reused, and write the address of the first-level address management area of the next link into the first address bit corresponding to the first-level address management area of the previous link to eliminate invalid links.

[0075] In some specific embodiments, the device is further configured to, if the number of pre-arranged orders in the preset second-level data storage area reaches a third quantity threshold, reapply for a new second-level data storage area, and store the order numbers that meet the preset conditions in the preset second-level data storage area into the new second-level data storage area.

[0076] In some specific embodiments, the device is further configured to, when deleting the pre-arranged order at the front end, if there is one pre-arranged order in the preset second-level data storage area, recycle the address of the preset second-level data storage area to a preset address cache pool, so that when the front end applies for an address of the second-level address management area, the address of the preset second-level address management area can be reused; when deleting the pre-arranged order at the front end, if there are several pre-arranged orders in the preset second-level data storage area, delete the pre-arranged orders in the preset second-level data storage area according to the address to be inserted, rearrange the remaining pre-arranged orders in the preset second-level data storage area, and then write the corresponding rearranged pre-arranged orders into the preset second-level data storage area.

[0077] Furthermore, an embodiment of the present application also discloses an electronic device. Figure 5It is a structural diagram of an electronic device 20 shown according to an exemplary embodiment, and the content in the figure should not be regarded as any limitation on the scope of use of this application.

[0078] Figure 5 This is a schematic structural diagram of an electronic device 20 provided by an embodiment of this application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the pre-order storage method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0079] In this embodiment, the power supply 23 is used to provide operating voltages for the various hardware devices on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of this application, and specific limitations are not imposed on it here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitations are imposed here.

[0080] In addition, as a carrier for resource storage, the memory 22 may be a read-only memory, a random access memory, a magnetic disk, or an optical disc, etc., and the resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage method may be temporary storage or permanent storage.

[0081] Among them, the operating system 221 is used to manage and control the various hardware devices and the computer program 222 on the electronic device 20, and it may be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the pre-order storage method executed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 222 may further include computer programs that can be used to complete other specific tasks.

[0082] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the pre-order storage method disclosed above. For the specific steps of this method, reference may be made to the corresponding content disclosed in the foregoing embodiments, and details are not repeated here.

[0083] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section.

[0084] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0085] The steps of the methods or algorithms described in combination with the embodiments disclosed in this article can be directly implemented by hardware, software modules executed by a processor, or a combination of both. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0086] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, the element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0087] The above has introduced the technical solutions provided by this application in detail. Specific examples are used in this article to elaborate on the principles and implementation manners of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A method for storing a pre-buried order, characterized in that: include: When receiving a pre-buried order, query whether there is a preset first-level address management area address corresponding to the order channel number in the preset FPGA internal address management according to the order channel number corresponding to the pre-buried order; If it exists, read the preset first-level address management area according to the address of the preset first-level address management area, obtain the maximum order number of each corresponding preset second-level data storage area, and determine the insertion position of the pre-buried order based on the size relationship between the maximum order number and the order number of the pre-buried order; Using the insertion position to query the preset secondary data storage area address in the preset primary address management area, and reading the preset secondary data storage area based on the preset secondary data storage area address to obtain each target order number of the stored pre-buried order; Determine the address to be inserted of the pre-buried order based on the order of magnitude of each target order number, and store the pre-buried order in the preset secondary data storage area according to the address to be inserted; The method further comprises: When the front end deletes the pre-buried order, if there is a pre-buried order in the preset secondary data storage area, the address of the preset secondary data storage area is recycled to the preset address cache pool, so that the preset secondary address management area address can be reused when the front end applies for the address of the secondary address management area; When deleting the pre-buried order at the front end, if there are several pre-buried orders in the preset secondary data storage area, the pre-buried orders in the preset secondary data storage area are deleted according to the address to be inserted, and the remaining pre-buried orders in the preset secondary data storage area are rearranged, and the corresponding pre-buried orders after rearrangement are written into the preset secondary data storage area; The method further comprises: If the first-level address management area of ​​the next link does not exist in the preset first-level address management area, when the front end deletes the pre-buried order, the address of the preset first-level address management area is recycled to the preset address cache pool, so that the address of the preset first-level address management area can be reused when the front end applies for the address of the first-level address management area; If the first-level address management area of ​​the next link exists in the preset first-level address management area, and the first-level address management area of ​​the previous link does not exist, then when the front end deletes the pre-buried order, the address of the preset first-level address management area is recycled to the preset address cache pool, so that the front end can reuse the address of the preset first-level address management area when applying for the address of the first-level address management area, and write the address of the first-level address management area of ​​the next link into the preset FPGA internal address management; If the preset first-level address management area contains the first-level address management area of ​​the next link and the first-level address management area of ​​the previous link, and the first-level address management area of ​​the previous link is an address read from the non-preset FPGA internal address management, then when the front end deletes the pre-buried order, the address of the preset first-level address management area is recovered to the preset address cache pool, so that the preset first-level address management area address can be reused when the front end applies for the first-level address management area address, and the address of the first-level address management area of ​​the next link is written into the first address bit corresponding to the first-level address management area of ​​the previous link to eliminate invalid links.

2. The method for storing a pre-buying order according to claim 1, characterized in that: After querying, according to the order channel number corresponding to the pre-buried order, whether there is a preset first-level address management area address corresponding to the order channel number in the preset FPGA internal address management, the method further includes: If the preset first-level address management area address corresponding to the order channel number does not exist in the preset FPGA internal address management, a new first-level address management area and a second-level address management area are created to store the information of the pre-buried order.

3. The method for storing pre-buying orders according to claim 1, characterized in that: The step of determining the insertion position of the pre-buried order based on the size relationship between the maximum order number and the order number of the pre-buried order includes: If the order number of the pre-buried order is smaller than the maximum order number, the preset secondary data storage area corresponding to the maximum order number is determined as the insertion position of the pre-buried order.

4. The method for storing a pre-buying order according to claim 1, characterized in that: Also includes: If the number of addresses of the preset second-level address management area stored in the preset first-level address management area reaches a first quantity threshold, apply for a new first-level address management area, and store the new first-level address management area address corresponding to the new first-level address management area into the preset first-level address management area; If the number of pre-buried orders stored in the preset secondary address management area reaches the second quantity threshold, a new secondary address management area is applied for, and the new secondary address management area address corresponding to the new secondary address management area is stored in the current primary address management area.

5. The method for storing pre-buying orders according to claim 1, characterized in that: After storing the pre-buried order in the preset secondary data storage area according to the address to be inserted, the method further includes: If the number of pre-placed orders in the preset secondary data storage area reaches a third quantity threshold, a new secondary data storage area is reapplied for, and the order numbers in the preset secondary data storage area that meet the preset conditions are stored in the new secondary data storage area.

6. A pre-buried single storage device, characterized in that: include: The address query module is used to query whether there is a preset first-level address management area address corresponding to the order channel number in the preset FPGA internal address management when receiving the pre-buried order according to the order channel number corresponding to the pre-buried order; An insertion position determination module is used to read the preset first-level address management area according to the address of the preset first-level address management area, if it exists, obtain the maximum order number of each corresponding preset second-level data storage area, and determine the insertion position of the pre-buried order based on the relationship between the maximum order number and the order number of the pre-buried order; An order number acquisition module is used to query the preset secondary data storage area address in the preset primary address management area using the insertion position, and read the preset secondary data storage area based on the preset secondary data storage area address to obtain each target order number of the stored pre-buried order; A pre-buried order storage module, used for determining the address to be inserted of the pre-buried order based on the order of magnitude of each target order number, and storing the pre-buried order in the preset secondary data storage area according to the address to be inserted; The device is further configured to, when the front end deletes the pre-buried order, if there is a pre-buried order in the preset secondary data storage area, recycle the address of the preset secondary data storage area to a preset address cache pool, so that the preset secondary address management area address can be reused when the front end applies for the address of the secondary address management area; When deleting the pre-buried order at the front end, if there are several pre-buried orders in the preset secondary data storage area, the pre-buried orders in the preset secondary data storage area are deleted according to the address to be inserted, and the remaining pre-buried orders in the preset secondary data storage area are rearranged, and the corresponding pre-buried orders after rearrangement are written into the preset secondary data storage area; The device is further used for, if the first-level address management area of ​​the next link does not exist in the preset first-level address management area, then when the front end deletes the pre-buried order, recycling the address of the preset first-level address management area to the preset address cache pool, so that the front end can reuse the address of the preset first-level address management area when applying for the address of the first-level address management area; if the first-level address management area of ​​the next link exists in the preset first-level address management area, and the first-level address management area of ​​the previous link does not exist, then when the front end deletes the pre-buried order, recycling the address of the preset first-level address management area to the preset address cache pool, so that the front end can reuse the address of the preset first-level address management area when applying for the address of the first-level address management area, and write the address of the first-level address management area of ​​the next link into the preset FPGA internal address management; If the preset first-level address management area contains the first-level address management area of ​​the next link and the first-level address management area of ​​the previous link, and the first-level address management area of ​​the previous link is an address read from the non-preset FPGA internal address management, then when the front end deletes the pre-buried order, the address of the preset first-level address management area is recovered to the preset address cache pool, so that the preset first-level address management area address can be reused when the front end applies for the first-level address management area address, and the address of the first-level address management area of ​​the next link is written into the first address bit corresponding to the first-level address management area of ​​the previous link to eliminate invalid links.

7. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor is used to execute the computer program to implement the pre-buying order storage method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that: Used to store a computer program, wherein the computer program, when executed by a processor, implements the pre-buying order storage method as described in any one of claims 1 to 5.

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