Data access method and processor

Abstract

The present invention proposes a data access method and a processor. It relates to the field of data access technology. The data access method is executed in a processor with multiple cores, and the core processor executes writing data or reading data. It is characterized in that the method includes: when a core processor writes data to the system memory, the data is recorded in a historical access record table; when a core processor reads data, it checks whether there is corresponding data in the historical access record table. If the corresponding data is found, it is directly read from the historical record; if the required data is not found in the historical record table, the core processor reads the data from the system memory. By caching the data accessed by the core processor in the historical access record table, when the same data is requested again, it can be directly read from the historical record, avoiding repeated access to the system memory, thereby significantly improving the data access speed.

Description

Technical Field

[0001] The present invention relates to the technical field of data access, and in particular to a data access method and a processor. Background Art

[0002] In a processing system, such as a personal computer or similar digital device, the processor relies on a memory controller to manage access to memory resources. In a traditional system, when the memory controller receives memory access requests, it will first temporarily store these requests and process them according to certain priority rules.

[0003] In order to improve the efficiency of memory access, there is a technology that adjusts the scheduling order of memory access requests. This technology includes first sending the first memory access request to the memory controller, and then sending the second request based on the estimated completion time of the first request. This strategy aims to optimize the utilization of memory resources and reduce waiting time.

[0004] Another similar optimization method is that after the bus interface unit (the component responsible for receiving memory access requests) receives the first request, it does not forward it to the memory controller immediately, but sends the second request at a later time point and then processes the first request. The purpose of this is to balance the load of the memory controller by adjusting the timing of sending requests to avoid overload or uneven idleness.

[0005] Since system memory is mainly dynamic random access memory (DRAM), its access speed is much lower than the cache inside the processor. Whenever the processor needs to read data from the memory, the data needs to be transferred between the cache and the memory, which increases latency and affects processor performance. Therefore, in addition to directly improving the access speed of the memory, reducing the number of times data is transferred between the cache and the memory is also a key strategy to improve the overall efficiency of the system. By optimizing the scheduling and processing of memory access requests, memory resources can be used more effectively, improving the operating speed and responsiveness of the system. Summary of the invention

[0006] The present invention provides a data access method and a processor to solve the problems mentioned in the above background technology:

[0007] The present invention provides a data access method, which is executed in a processor having multiple cores, and the core processor executes writing data or reading data, and the method comprises:

[0008] When a core processor writes data to the system memory, the data is recorded in the historical access record table so that other cores can use the data in the future;

[0009] When a core processor reads data, it checks whether there is corresponding data in the historical access record table. If the corresponding data is found, it reads it directly from the historical record without accessing the system memory.

[0010] If the required data is not found in the history record table, the core processor reads the data from the system memory and simultaneously stores the read data in the history record table.

[0011] Furthermore, before the core processor reads the data, it first sends a signal to notify other core processors having the data to put the data back into the system memory. Subsequently, the core processor obtains the data and performs a write operation.

[0012] Furthermore, before the core processor reads the data, it first sends a signal to notify other core processors having the data to put the data back into the system memory, including:

[0013] Core processor A determines the address or identifier of the data to be read and checks whether the local cache (such as L1, L2 cache) already contains the data;

[0014] If the local cache misses, core processor A will further query the shared historical access record table and obtain the latest location and status information of the data;

[0015] Through the historical access record table, core processor A identifies all core processors that may hold the data (such as core processor B, core C, etc.), and core processor A asks these cores whether they hold the data through a lightweight communication mechanism (such as a signal in a cache consistency protocol);

[0016] If direct inquiry is fruitless or a more precise response is needed, the core processor A sends a detailed data rollback request signal to each potential data holder; the rollback request signal includes information such as the unique identifier of the data, the type of request (read), and the priority of the request;

[0017] Each core processor that receives the request, such as core processor B, checks its internal cache and registers to confirm whether it holds the requested data;

[0018] If the data is held, core processor B writes the data back to the appropriate location in the system memory, updates or clears the record of the data in the historical access record table, and sends a confirmation signal containing the new location of the data (system memory address) to the requester;

[0019] If core processor B does not hold the data or cannot respond to the request immediately, it sends a negative response to core processor A;

[0020] Core processor A receives the confirmation signal from the data holder through a timer or a waiting mechanism;

[0021] If no confirmation signal is received within the preset time, core processor A will resend the request, select another data source, or read the data directly from the system memory;

[0022] If a negative response or timeout is received, core processor A will record this event and adjust its subsequent data access strategy or notify the upper-layer application;

[0023] After confirming that the data has been rolled back to the system memory or cannot be obtained from other cores, core processor A directly reads the required data from the system memory; and uses the prefetch mechanism to simultaneously read the adjacent and related data of the data, and stores this information in the historical access record table and the local cache.

[0024] Furthermore, the core processor obtains these data and performs a write operation, including:

[0025] Before planning to write data, core processor A analyzes whether the data depends on data currently held by other cores (such as core processor B, core C, etc.) by checking the dependency graph between the data or using a version control mechanism;

[0026] If a dependency is found, core processor A sends a dependency notification to all related cores, requesting them to keep the data status unchanged or prepare for data rollback;

[0027] For data that needs to be rolled back, core processor A sends a rollback request to the core holding the data; the request includes a unique identifier of the data, a target address for rollback, and timestamp information;

[0028] The core holding the data (such as core processor B) performs a rollback operation, writes the data back to the specified location of the system memory, and updates the historical access record table; after completion, it sends a rollback confirmation signal to core processor A;

[0029] The core processor A receives all necessary rollback confirmations based on a preset waiting mechanism. If no confirmation is received within a timeout period, the core processor A will execute an error handling process, which includes retrying the request, selecting an alternate data source, or terminating the operation.

[0030] Core processor A checks the historical access record table to determine whether the required data already exists. If it does exist and is valid (i.e., not expired and not marked as invalid), it directly reads it from the historical record;

[0031] If the required data does not exist in the history record, core processor A will perform a system memory read operation. During the execution, the system memory manager pre-fetches adjacent and related data and tries to temporarily store them in the history storage record table;

[0032] Core processor A prepares the acquired data (including data read from system memory or historical records) for writing. This may include steps such as data verification, formatting or conversion. If the target write location is a shared resource, core processor A acquires the appropriate lock, including a mutex lock and a read-write lock.

[0033] Core processor A writes the prepared data to the target location, including writing the data to a specific area of ​​the system memory, updating a cache line, or writing to a hardware register. After the write operation is completed, core processor A obtains a write confirmation signal from the hardware or memory controller;

[0034] Regardless of whether the data is read from the historical record or from the system memory, core processor A updates the historical access record table after the write operation. If the write operation resolves the previous data dependency, core processor A will send a dependency release notification to all related cores, allowing them to continue to execute the blocked operation;

[0035] Core processor A broadcasts its write operations to other cores via a cache coherence protocol such as the MESI protocol.

[0036] Furthermore, when the system memory accesses data, adjacent and related data of the data are extracted together and temporarily stored in a historical storage record table.

[0037] Furthermore, extracting adjacent and related data of the data includes:

[0038] Before initiating a data access request, the core processor (core processor A) analyzes the needs of the application to determine whether it is necessary to extract adjacent and related data; this may require considering the access pattern of the data, the dependencies between the data, and the overall performance goals of the system;

[0039] Based on the demand analysis, core processor A formulates a data extraction strategy, including determining the data range, priority, and how to handle data conflicts, and constructs a detailed request containing the main data address, adjacent data range, related data identifiers, and extraction strategy;

[0040] Send the request to the system memory manager (or cache controller) and wait for a response. The system memory manager parses the request and understands the requirements and extraction strategy of core processor A.

[0041] Check whether the required primary data and its adjacent / related data already exist in the cache. If so, prepare the data directly; if not, proceed to the next step;

[0042] Read the master data from the system memory, determine the range of adjacent and related data to be extracted according to the extraction strategy, and extract the master data and its adjacent / related data from the memory;

[0043] Organize the extracted data into a data structure suitable for processing by the core processor A, such as a data block, an index table or a graph structure, temporarily store the organized data in a historical storage record table, and record relevant information of the data; the relevant information includes information such as data source, extraction time and validity period;

[0044] When temporarily storing data, check whether there is a data conflict (for example, different cores request different versions of the same data). If there is a conflict, handle it according to the conflict resolution strategy (such as version control, data merging, etc.); and optimize the data layout and replacement strategy in the cache based on historical access records and current system load;

[0045] The extracted and temporarily stored data is sent to the core processor A. After receiving the data, the core processor A performs corresponding processing, which includes verification, calculation or updating of internal state. The core processor A provides feedback to the system memory manager according to the processing result, such as the validity and usage frequency of the data, so that the system memory manager can adjust the cache strategy and optimize the data extraction strategy;

[0046] The system regularly monitors data access performance, including indicators such as cache hit rate, data extraction time, and conflict resolution efficiency, and optimizes relevant strategies based on the monitoring results. The relevant strategies include extraction strategy, cache strategy, and conflict resolution strategy.

[0047] The present invention proposes a processor, which includes multiple core processors, and the core processors are connected to the system memory and other core processors through an input / output block. The input / output block includes a historical access record table, and the historical storage record table is used to temporarily store the part obtained by each core processor from the system memory.

[0048] Furthermore, the historical access record table of the input / output block is connected to a consistency circuit and a memory controller, wherein the consistency circuit is connected to a core processor, and the memory controller is connected to the system memory.

[0049] Furthermore, the historical access record table is a cache memory queue, and the storage content of the historical storage record table includes number, read / write status, validity and data. The historical storage record table is used to record the historical records of each core accessing the system memory data.

[0050] Furthermore, the steps of storing the historical storage record table include:

[0051] When the system starts, the size of the historical storage record table, data structure (such as hash table, red-black tree or skip table, etc., to support fast search and insertion) and cleanup strategy (such as LRU, LFU or timestamp expiration, etc.) are initialized according to the hardware configuration and performance requirements;

[0052] Assign a unique identifier (CoreID) to each core processor and set a separate storage area or tag for each core in the historical storage record table;

[0053] Configure the parameters of the consistency circuit and the memory controller. When the core processor (core processor A) initiates a data access request, check whether the local cache (if any) contains the required data. If not, the core processor A sends the data access request to the memory controller through the input / output block.

[0054] The memory controller processes the request and reads the data from the system memory (if necessary). At the same time, the memory controller passes the relevant information of the access request (such as CoreID, address, size, access type, etc.) to the input / output block;

[0055] The input / output block checks the history storage record table to determine whether the same access request has already been recorded; this is done by searching for an entry that matches the CoreID, address, and size.

[0056] If a matching entry is found and its validity flag is valid, the input / output block directly reads data from the entry (if actual data is stored) or updates its access timestamp (if data reference is stored);

[0057] If no matching entry is found or the entry has expired, the input / output block creates a new history entry and fills it with information, including:

[0058] Number: Generates a unique identifier to distinguish between different history entries.

[0059] CoreID: Records the identifier of the core processor that initiated the access request.

[0060] Address: The target memory address of the access request.

[0061] Size: The size of the data being accessed.

[0062] Access type: read or write.

[0063] Data / Reference: Stores the actual data if storage space allows; otherwise, stores a reference (such as a pointer or offset) to the location of the data in memory.

[0064] Timestamp: records the time when the entry was created or last accessed.

[0065] Validity flag: marks whether the entry is valid.

[0066] Insert new entries into the history storage record table and check whether expired or no longer needed entries need to be deleted according to the configured cleanup strategy;

[0067] The consistency circuit monitors the interaction between the historical storage record table and the memory controller. When data conflicts or inconsistencies are detected, the consistency circuit takes appropriate measures (such as writing back to the cache, undoing operations, or executing cache consistency protocols) to resolve the problem.

[0068] The input / output block periodically interacts with the cache manager to synchronize the cache status and the contents of the historical storage record table. The system monitoring tool periodically collects performance indicators of the historical storage record table, such as hit rate, search time, insertion time, cleanup frequency, etc.

[0069] Based on the collected performance indicators, the performance bottlenecks and potential optimization points of the historical storage record table are analyzed, and based on the analysis results, the size, data structure, cleanup strategy or parameters of the consistency circuit of the historical storage record table are adjusted.

[0070] The beneficial effects of the present invention are as follows: the historical access record table can be used to temporarily store data that has been used before; in addition, since the probability of the previously used data being used again and the surrounding adjacent data being accessed is high, the use of the historical access record table can reduce the number of times the data moves between the cache and the system memory, thereby improving the performance of the processor. By caching the data accessed by the core processor in the historical access record table, when the same data is requested again, it can be directly read from the historical record, avoiding repeated access to the system memory and significantly improving the data access speed; adopting a reasonable cleaning strategy and data structure, the historical access record table can efficiently manage the cache space, avoid cache pollution and waste, and ensure a high hit rate; in the process of data writing and reading, through the monitoring and intervention of the consistency circuit and the communication mechanism between the cores, the consistent access to shared data between multiple core processors is ensured, improving the reliability and stability of the system; before writing data, by analyzing the dependencies between data and using the version control mechanism, data conflicts and unnecessary rollback operations are avoided. At the same time, secure access to shared resources is guaranteed through appropriate locking mechanisms; when reading data, not only the main data is obtained, but also adjacent and related data are extracted according to the strategy, reducing the delay in future access to this data and improving system performance; performance indicators of historical access record tables are collected through system monitoring tools, and dynamic analysis and optimization are performed based on these indicators, so that the system can adapt to different workloads and application requirements and maintain optimal performance; the overall power consumption of the system is reduced due to the reduced frequent access to system memory; the optimized data access method and processor architecture enable multiple core processors to work together more efficiently, improving the overall processing power and throughput of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] Figure 1 A schematic diagram of a processor architecture disclosed in an embodiment of the present invention;

[0072] Figure 2 A block diagram of a method for writing data into a non-existent historical access record table according to an embodiment of the present invention;

[0073] Figure 3 A block diagram showing a reading method for pre-fetching data and temporarily storing it in a historical access record table according to an embodiment of the present invention;

[0074] Figure 4 A block diagram showing a method for reading data stored in a historical access record table according to an embodiment of the present invention. DETAILED DESCRIPTION

[0075] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0076] One embodiment of the present invention, as Figure 1 As shown, the embodiment in the figure discloses that the processor 100 includes multiple cores 101, 102, 103, 104 such as C0, C1, C2...Cn, and each core 101~104 is respectively equipped with a cache (indicated by the "$" symbol in the figure). The processor 100 has an input / output block (I / O block) 120, and the I / O block 120 is connected to each of the cores 101~104. Secondly, the processor 100 is connected to the system memory 130 through the I / O block 120.

[0077] More specifically, the I / O block 120 includes a history access record table 121 connected to a multiplexer 122 , a consistency circuit unit 123 and a memory controller 126 . The consistency circuit 123 is connected to the core 101 , and the memory controller 126 is connected to a system memory 130 .

[0078] Furthermore, the input / output block 120 includes a first interface 124 and a second interface 125. The first interface 124 is connected to the historical access record table 121, the memory controller 126 and the multiplexer 122, and the input / output block 120 is connected to each of the cores 101-104 via the first interface 124. The second interface 125 is connected to the multiplexer 122 and the memory controller 126 and the system memory 130.

[0079] The historical access record table 121 is a memory queue similar to a high-speed cache, and its storage content includes serial number, read / write, validity and data, so as to record the historical records of each core 101-104 accessing the data of the system memory 130. According to the long-term accumulated usage data and experience analysis, most of the access behaviors, instructions and data of the system memory 130 are repeatedly executed, so the possibility of future access to the system memory 130 address can be predicted by using the historical access record table 121, and the data can be pre-read and stored in the historical access record table 121, so as to reduce the number of accesses to the system memory 130.

[0080] According to the above description, the data access method disclosed in the present invention may include but is not limited to the following situations:

[0081] Condition 1: Data does not exist in the historical access record table:

[0082] like Figure 2As shown, taking the data movement between core processor A and core processor B as an example, when core processor A wants to perform reading and writing of data S to the system memory, such as "write" shown in block 201; at this time, the core processor A first broadcasts a snoop, as shown in block 202; if the data S has been accessed or is being used by core processor B, the processing method needs to be further determined based on whether the data S has been changed, as shown in block 203; if the content of the data S has been changed, the core processor B writes the data back to the memory, and also leaves a copy in the record table, and the core processor B declares the state of the data S in its cache to be invalid, as disclosed in block 204; then, the core processor A can obtain the correct (latest) data S from the historical access record table to perform the predetermined write behavior, as disclosed in block 205.

[0083] After the judgment of the content disclosed in block 20, if the content of data S has not changed, core processor B declares the state of data S in its cache as invalid, as disclosed in block 206; then core processor A may Figure 3 Block 302 is shown and executed according to the process. Figure 3 Block 302 and subsequent processes will be described later.

[0084] Condition 2: Pre-fetch data and temporarily store it in the historical access record table:

[0085] like Figure 3 As shown, taking the core processor A reading data X as an example, when the core processor A wants to read specific data X in the system memory, as shown in block 301; the memory controller can fetch data X from the system memory, as shown in block 302; then, data X can be transmitted to the core processor A, as shown in block 303; after the core processor A completes accessing data X, or during the access process, data X is written into the historical access record table, as shown in block 304.

[0086] It is worth noting that if the data X is accessed by other cores again, the other cores can access the data X from the historical access record table; if the data X is not accessed by other cores as predicted, the data X will be replaced or terminated in the future.

[0087] In addition, according to the experience of accessing the system memory, when data is accessed, it is often accompanied by a high probability that the surrounding adjacent data will be accessed in the future. Therefore, in this embodiment, when data X is read and temporarily stored in the historical access record table, the surrounding adjacent or related data is also loaded and temporarily stored in the historical access record table, as shown in block 305.

[0088] Condition 3: Data has been stored in the historical access record table:

[0089] like Figure 4 As shown, core processor A executes to read data X, as shown in block 401; then checks the contents of the historical access record table, as shown in block 402; if data X exists in the historical access record table, it is directly retrieved from the historical access record table, as shown in block 403; if data X does not exist in the historical access record table, the reading method is based on Figure 3 Block 302 is shown and executed according to the process.

[0090] According to the access method of the processor architecture disclosed above, the historical access record table can be used to temporarily store the data that has been used, and when the core reads the data, it checks whether there is corresponding data in the historical access record table. If there is corresponding data in the historical access record table, the data is directly read from the historical access record, and the reading of data from the system memory is interrupted. In addition, since the probability of the data that has been used being used again and the surrounding adjacent data being accessed is high, the use of the historical access record table can reduce the number of times the data moves between the cache and the system memory, thereby improving the performance of the processor.

[0091] In one embodiment of the present invention, when a core ("write core") in a processor performs a write operation to write data into a system memory, the data is written into the system memory and is additionally recorded into a historical access record table. The record table may be a fast access storage area located inside or near the processor, such as a part of a cache or a dedicated storage structure. When another core ("read core") needs to read data, it first checks the historical access record table to see if the required data has been recorded therein by a previous write operation. If the required data is found in the historical record table (i.e., data hit), the read core will read the data directly from the historical record table without accessing the relatively slow system memory. If the required data is not found in the historical record table (i.e., data miss), the read core will read the data from the system memory. After reading the data from the system memory, the data will be simultaneously stored in the historical access record table.

[0092] By caching data in a historical access record table, the number of times the processor core directly accesses the system memory is reduced. Because the access speed of the system memory is much lower than the high-speed cache inside the processor, the cache mechanism can significantly reduce the delay of data access and improve the overall performance of the processor. When multiple core processors are processing similar or related data sets, the data access method can significantly improve the efficiency of data access. Once a core writes data into the system memory and updates it to the historical record table, other cores can quickly read the data from the historical record table without reloading it from the system memory. By intelligently managing the historical access record table, the utilization of the processor's internal storage resources can be optimized. For example, a predetermined strategy can be implemented to automatically eliminate data that has not been accessed for a long time to make room for new data. In a multi-core processor environment, the data access method can support efficient concurrent processing. Different cores can perform read and write operations in parallel, while using the historical access record table to reduce data access conflicts and waiting time; by introducing the historical access record table to cache data, the efficiency and performance of the multi-core processor in processing data are significantly improved.

[0093] In one embodiment of the present invention, when core processor A needs to read data, it first checks whether its local cache (such as L1, L2 cache) already contains the required data. Through the principle of cache locality, the most recent or most frequently used data can be quickly accessed. If the local cache does not hit, core processor A will further query the shared historical access record table. This record table contains the latest location and status information of the data, helping core processor A to determine which other cores may hold the data. Core processor A asks potential data holders (such as core processor B, core C, etc.) whether they hold the data through a lightweight communication mechanism (such as a signal in a cache consistency protocol). If the direct inquiry is fruitless or a more precise response is required, core processor A will send a detailed data rollback request signal. The signal contains information such as the unique identifier of the data, the request type (read), and the priority of the request. Each core (such as core processor B) that receives the request checks its internal cache and registers to confirm whether it holds the requested data. If it does, core processor B writes the data back to the system memory and updates or clears the record of the data in the historical access record table. Then, core processor B sends a confirmation signal containing the new location of the data (system memory address) to the requester (core processor A). If it does not hold the data or cannot respond immediately, core processor B sends a negative response; core processor A receives the confirmation signal from the data holder through a timer or waiting mechanism. If the confirmation signal is not received within the preset time, core processor A can choose to resend the request, select other data sources, or read the data directly from the system memory. If a negative response or timeout is received, core processor A will record this event and may adjust its subsequent data access strategy, such as increasing the frequency of direct reading from the system memory, or notifying the upper-level application to optimize its data access mode. After confirming that the data has been rolled back to the system memory or cannot be obtained from other cores, core processor A reads the required data directly from the system memory. At the same time, core processor A uses the prefetch mechanism to read the adjacent and related data of the data, and stores this information in the historical access record table and local cache to optimize future data access.

[0094] By ensuring that data is rolled back from other core caches to system memory before reading, this technical solution helps maintain data consistency and avoid errors caused by cache inconsistencies; through the collaborative work of the historical access record table and the local cache, and the application of the pre-fetch mechanism, this technical solution can more effectively utilize cache resources and improve the hit rate of data access; through a lightweight communication mechanism and a fast data rollback process, this technical solution can reduce data access latency and improve system responsiveness; through this technical solution, it supports multi-core processor environments and can expand with the increase in the number of cores to maintain efficient data access performance. By recording events and adjusting subsequent data access strategies, this technical solution provides the system with flexible data access management capabilities, which helps to cope with different workloads and data access patterns.

[0095] In one embodiment of the present invention, before planning to write data, core processor A will check the dependency graph between data or use a version control mechanism to determine whether the data depends on data currently held by other cores (such as core processor B, core C, etc.). Ensure that all relevant old data is in the correct state before writing new data; if a dependency is found, core processor A will send a dependency notification to all relevant cores, requesting them to keep the data state unchanged or prepare for data rollback. For data that needs to be rolled back, core processor A will send a rollback request to the core holding the data, and the request will include the data's unique identifier, the rollback target address, and timestamp information; the core holding the data (such as core processor B) will perform a rollback operation, write the data back to the specified location in the system memory, and update the historical access record table. After completion, a rollback confirmation signal is sent to core processor A. Core processor A receives all necessary rollback confirmations based on a preset waiting mechanism. If no confirmation is received within a timeout, the error handling process is executed; the timeout period can be dynamically adjusted using the following formula;

[0096]

[0097] in, , Indicates the average response time of historical data access; Indicates the standard deviation of network delay; represents the safety factor; represents the load level of the ith core; N represents the total number of cores; Indicates the maximum value of the timeout period; Indicates the minimum timeout value;

[0098] After confirming that all dependencies have been properly handled, core processor A checks the history access record table to determine whether the required data already exists and is valid. If it exists, it is read directly from the history record; if it does not exist, a system memory read operation is performed. The system memory manager pre-fetches adjacent and related data and tries to temporarily store them in the history access record table. Core processor A performs necessary processing on the acquired data, such as verification, formatting, or conversion, and obtains appropriate locks to ensure the atomicity of the write operation; core processor A writes the prepared data to the target location, including writing data to a specific area of ​​the system memory, updating a cache line, or writing to a hardware register. After the write operation is completed, core processor A obtains a write confirmation signal from the hardware or memory controller; regardless of whether the data is read from the history record or from the system memory, core processor A updates the history access record table after the write operation. If the write operation resolves the previous data dependency, core processor A sends a dependency release notification to all related cores, allowing them to continue to execute the blocked operation. Finally, core processor A broadcasts its write operation to other cores through a cache consistency protocol (such as the MESI protocol) to ensure that all cores can see the latest data status.

[0099] Through data dependency analysis and rollback mechanism, this technical solution can ensure that all relevant old data are in the correct state before writing new data, thereby improving data consistency; through the use of historical access record tables and pre-fetching of adjacent data, this technical solution can reduce the number of system memory accesses and optimize data access efficiency; the error handling process and dependency release notification mechanism enable the system to run more stably and recover in time even when abnormal situations occur; through the broadcast of the cache consistency protocol and the appropriate locking mechanism, this technical solution can support efficient concurrent processing, allowing multiple cores to process data simultaneously without interfering with each other; this technical solution supports multiple data dependency processing methods and can be expanded as needed to adapt to a larger number of cores and more complex data processing requirements. The above-mentioned timeout dynamic adjustment formula can adaptively adjust the timeout to cope with different system load conditions by considering the load level of each core (normalized and limited). When the system load is high, the timeout will increase to give the system more processing time; when the system load is low, the timeout will decrease accordingly to improve the system's response speed; by introducing the standard deviation and safety factor of network delay, the formula can predict and respond to potential fluctuations in network delay. It helps to maintain the stability and reliability of the system when network conditions are unstable; by adjusting parameters, system administrators or developers can optimize the calculation method of timeout according to specific application scenarios and system characteristics. ; By setting the maximum and minimum values ​​of the timeout, the formula can prevent the timeout from becoming too extreme. It helps to prevent system performance or stability problems caused by improper timeout settings; by dynamically adjusting the timeout, the system can use resources more efficiently and reduce resource waste caused by unnecessary waiting. At the same time, when the system is under high load or the network delay is high, the appropriate timeout setting can also help reduce the retry and error handling overhead caused by frequent timeouts; through reasonable timeout settings, the system can more accurately detect and respond to potential failures or delays. It helps to take timely measures to avoid or mitigate the impact of failures on system performance, thereby improving the reliability and availability of the system.

[0100] In one embodiment of the present invention, before initiating a data access request, the core processor (core processor A) first analyzes the needs of the application program to determine whether it is necessary to extract adjacent and related data. This includes the data access mode, the dependencies between the data, and the overall performance goals of the system. Based on the results of the needs analysis, the core processor A formulates a detailed data extraction strategy, including determining the data range, priority, and how to handle data conflicts. Subsequently, a detailed request including the main data address, the adjacent data range, the related data identifier, and the extraction strategy is constructed. The request is sent to the system memory manager (or cache controller) and waits for its response. The system memory manager parses the request and understands the needs and extraction strategy of the core processor A. The system memory manager first checks whether the required main data and its adjacent / related data already exist in the cache. If the data already exists in the cache, the data is prepared directly; if not in the cache, the main data is read from the system memory, and the range of the adjacent and related data to be extracted is determined according to the extraction strategy, and the data is extracted from the memory; the extracted data is organized into a data structure suitable for processing by the core processor A, such as a data block, an index table, or a graph structure, and the organized data is temporarily stored in the historical storage record table. At the same time, record relevant information about the data, such as data source, extraction time, and validity period. When temporarily storing data, check whether there is a data conflict (such as different cores requesting different versions of the same data). If there is a conflict, handle it according to the conflict resolution strategy (such as version control, data merging, etc.). In addition, based on historical access records and current system load, optimize the data layout and replacement strategy in the cache. Among them, the system load is obtained through the following formula:

[0101]

[0102] Wherein, L represents the system load; Indicates the current number of active users; Indicates the number of requests currently being processed; represents the number of data requests waiting to be processed; R represents the average processing time of each request; Indicates the input / output operation volume of the system; Indicates the system resource usage; Indicates the historical load average; , , , , , , , represents the weight coefficient of each factor; , , , , represents the parameter that controls the nonlinear relationship (usually set to a positive number, usually 2 or 3); , , It represents the equilibrium constant of each factor.

[0103] The extracted and temporarily stored data is sent to core processor A. After receiving the data, core processor A verifies, calculates, or updates the internal state, and provides feedback to the system memory manager based on the processing results, such as the validity of the data, the frequency of use, etc., so that the system memory manager can adjust the cache strategy and optimize the data extraction strategy. The system regularly monitors data access performance, where data access performance is calculated using the following formula:

[0104]

[0105] in, Indicates system access performance; represents the average response time; Table throughput; Indicates the cache hit rate; represents the error rate; , , , Represents the weight coefficient of each indicator, and the sum is 1.

[0106] Based on the monitoring results, relevant strategies are tuned to further improve system performance.

[0107] By extracting neighboring and related data in advance, the delay in subsequent data access is reduced and the efficiency of data access is improved. Through reasonable caching and replacement strategies, the data in the cache is closer to the needs of actual applications, improving the utilization and hit rate of the cache; through effective conflict resolution strategies, the conflicts caused by inconsistent data versions between different cores are reduced, and the stability and reliability of the system are improved. This technical solution supports the adjustment of data extraction strategies and caching strategies according to actual needs, has good flexibility and scalability, and can adapt to different application scenarios and performance requirements. Through regular performance monitoring and strategy tuning, the performance of the system can be continuously optimized to ensure that the system is always in the best state. The above system load formula can better simulate the nonlinear effects of active users, requests, and waiting requests on the system load by using power functions and logarithmic functions. For example, an increase in the number of active users may cause the load to increase in a square or cubic manner. By balancing the constant , , When the number of active users, requests, and waiting requests is low, it can avoid calculating excessively high load values ​​to ensure the stability of the model under low load; introduce historical load averages to consider the load conditions over the past period of time, so that the system can dynamically adjust according to historical performance to better cope with future load fluctuations; use logarithmic functions to process I / O operation volume, which can effectively reduce the impact of high I / O load on calculations and avoid distortion of the total load by extreme values; incorporate resource utilization into load calculations proportionally, so that the system can more sensitively reflect load changes when resources are tight. The above data access performance formula combines multiple performance indicators and can comprehensively reflect the system access performance, not just from a single perspective; by assigning weights to different indicators, the importance of each factor in the overall performance can be balanced; the performance indicator output by the formula is a specific value, which is convenient for comparison and analysis; the change of this value can be continuously monitored to evaluate the stability or change trend of system performance; the formula provides a clear optimization goal, that is, to improve the value of the performance indicator P; by analyzing each component, performance bottlenecks can be found to guide the formulation of optimization strategies; by optimizing each indicator in the formula, the overall performance of the system can be effectively improved; the improvement of system access performance is directly related to user experience, and faster response time and higher throughput can enhance user satisfaction; a high cache hit rate can reduce the number of accesses to system memory, thereby improving resource utilization; by monitoring and reducing error rates, system failures and interruptions can be reduced and system reliability can be improved; the formula provides a quantitative performance indicator that can help decision makers make decisions on resource allocation and system upgrades; the formula can help developers and operation and maintenance personnel identify performance bottlenecks and perform targeted tuning.

[0108] In one embodiment of the present invention, multiple core processors are connected through an input / output block (IOB) to achieve communication with the system memory and other core processors. This architecture enables each core processor to efficiently share data and instructions and work together to complete complex computing tasks. The historical access record table in the input / output block is a key component. As a high-speed cache memory queue, it is used to temporarily store data obtained by each core processor from the system memory, which can reduce frequent access to the system memory, improve data access speed, and reduce system power consumption. The historical access record table stores a wealth of information, including numbers (for uniquely identifying records), read / write status (indicating whether data is read or written), validity (marking whether data is still valid) and the data itself. This information helps the processor to efficiently manage and utilize historical data. The consistency circuit is connected to a core processor and is responsible for ensuring consistent access to shared data between multiple core processors. When a core processor modifies data, the consistency circuit notifies other core processors to update the data in their cache to avoid data inconsistency problems; the memory controller is connected to the system memory and is responsible for processing data transmission between the core processor and the system memory. Receives read and write requests from the core processor and controls the flow of data between the system memory and the core processor. When the core processor needs to access data, it first checks the historical access record table to see if the required data is temporarily stored in it. If the data exists and is valid, it is read directly from the historical access record table without accessing the system memory. If the data does not exist or is invalid, it is read from the system memory through the memory controller and stored in the historical access record table for later use.

[0109] By using the historical access record table to temporarily store data, the number of accesses to the system memory is reduced, thereby increasing the data access speed. This is particularly important for applications that need to frequently access the same data; reducing access to system memory also means reducing system power consumption, because accessing system memory is usually more power-consuming than accessing cache; the consistency circuit ensures consistent access to shared data between multiple core processors, avoiding data inconsistency problems and improving system reliability and stability; the design of the entire processor architecture enables various components to work together, improving the overall efficiency of the system. Communication between core processors is more efficient, and data access is faster and more accurate; due to the use of a multi-core processor architecture and the ability to efficiently share data and instructions between cores, the processor can support more complex computing tasks and meet the needs of modern applications for high-performance computing.

[0110] In one embodiment of the present invention, when the system starts, the historical storage record table is initialized according to the hardware configuration and performance requirements. This includes setting the size of the table, selecting a suitable data structure (such as a hash table, a red-black tree or a jump table) to support fast search and insertion, and configuring a cleanup strategy (such as LRU, LFU or timestamp expiration) to manage the cache space. A unique identifier (CoreID) is assigned to each core processor, and an independent storage area or tag is set for each core in the historical storage record table to distinguish and manage the data access history of different cores. When a core processor (such as core processor A) initiates a data access request, it first checks whether the local cache (if any) contains the required data. If not, a data access request is sent to the memory controller through the input / output block. The memory controller processes the request, reads the data from the system memory (if necessary), and passes the relevant information of the access request (such as CoreID, address, size, access type, etc.) to the input / output block. The input / output block checks the historical storage record table to determine whether the same access request has been recorded. This is achieved by searching for entries that match the CoreID, address and size. If a matching entry is found and its validity flag is valid, the data is directly read from the entry (if the actual data is stored) or its access timestamp is updated (if the data reference is stored). If no matching entry is found or the entry has expired, a new history entry is created and relevant information (such as number, CoreID, address, size, access type, data / reference, timestamp and validity flag) is filled. The new entry is inserted into the history storage record table, and the configured cleanup strategy is used to check whether the expired or no longer needed entry needs to be deleted. The consistency circuit monitors the interaction between the history storage record table and the memory controller to ensure data consistency between multiple core processors. When data conflicts or inconsistencies are detected, appropriate measures are taken to resolve the problem. The input / output block interacts with the cache manager regularly to synchronize the cache status and the contents of the history storage record table. The system monitoring tool collects performance indicators of the history storage record table, such as hit rate, search time, insertion time, cleanup frequency, etc. According to the collected performance indicators, analysis is performed to identify performance bottlenecks and potential optimization points, and the size, data structure, cleanup strategy or parameters of the consistency circuit of the history storage record table are adjusted accordingly.

[0111] By caching the results of data access requests in the historical storage record table, the need for repeated access to system memory is reduced and data access efficiency is improved; reasonable cleanup strategies and data structure selections enable effective use of cache space and avoid unnecessary cache pollution and waste; monitoring and intervention by consistency circuits ensure consistent access to shared data between multiple core processors, improving system reliability and stability; through performance monitoring and dynamic adjustment mechanisms, the system can automatically optimize the configuration of the historical storage record table based on actual conditions to adapt to different workloads and application requirements; the optimized historical storage record table works closely with components such as the cache manager and memory controller to improve the overall performance of the system, allowing multi-core processors to better exert their parallel processing capabilities.

[0112] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A data access method, wherein the data access method is executed in a processor having multiple cores, and the core processor executes writing data or reading data, characterized in that: The method comprises: When a core processor writes data to the system memory, the data is recorded in the historical access record table; When a core processor reads data, it checks whether there is corresponding data in the historical access record table. If the corresponding data is found, it reads it directly from the historical record; If the required data cannot be found in the historical access record table, the core processor reads the data from the system memory and simultaneously stores the read data in the historical access record table; Before the core processor reads the data, it first sends a signal to notify other core processors that have the data to put the data back into the system memory. Then, the core processor obtains the data and performs a write operation. The steps of the core processor acquiring data and performing a write operation include: Before planning to write data, core processor A analyzes whether the data depends on data currently held by other core processors by checking the dependency graph between the data or using a version control mechanism; If a dependency is found, core processor A sends a dependency notification to all related core processors, requesting them to keep the data status unchanged or prepare for data rollback; For data that needs to be rolled back, core processor A sends a rollback request to the core processor holding the data; The core holding the data performs a rollback operation, writes the data back to the specified location in the system memory, and updates the historical access record table; after completion, a rollback confirmation signal is sent to core processor A; The core processor A receives all necessary rollback confirmations based on a preset waiting mechanism. If no confirmation is received within a timeout period, the core processor A will execute an error handling process, which includes retrying the request, selecting an alternate data source, or terminating the operation. Core processor A checks the historical access record table to determine whether the required data already exists. If it exists and is valid, it is directly read from the historical record; If the required data does not exist in the historical record, core processor A will perform a system memory read operation. During the execution, the system memory manager pre-fetches adjacent and related data and temporarily stores them in the historical access record table; The core processor A prepares the acquired data for a write operation. If the target write location is a shared resource, the core processor A acquires an appropriate lock, which includes a mutex lock and a read-write lock. Core processor A writes the prepared data to the target location. After the write operation is completed, core processor A obtains a write confirmation signal from the hardware or memory controller; Core processor A updates the historical access record table after the write operation. If the write operation resolves the previous data dependency, core processor A will send a dependency release notification to all related core processors and continue to execute the blocked operation; Core processor A broadcasts its write operation to other core processors via the cache coherence protocol.

2. The data access method according to claim 1, characterized in that: Before the core processor reads the data, the steps of sending a signal to notify other core processors having the data to put the data back into the system memory include: Core processor A determines the address or identifier of the data to be read and checks whether the local cache already contains the data; If the local cache misses, core processor A will further query the shared historical access record table and obtain the latest location and status information of the data; Through the historical access record table, core processor A identifies all core processors that may hold the data, and core processor A asks these cores whether they hold the data through a lightweight communication mechanism; If direct inquiry is fruitless or a more precise response is needed, core processor A sends a detailed data rollback request signal to each potential data holder; Each core processor that receives the request checks its internal cache and registers to confirm whether it holds the requested data; If the data is held, core processor B writes the data back to the system memory, updates or clears the record of the data in the historical access record table, and sends a confirmation signal containing the new location of the data to the requester; If core processor B does not hold the data or cannot respond to the request immediately, it sends a negative response to core processor A; Core processor A receives the confirmation signal from the data holder through a timer or a waiting mechanism; If no confirmation signal is received within the preset time, core processor A will resend the request, select another data source, or read the data directly from the system memory; If a negative response or timeout is received, core processor A will record this event and adjust its subsequent data access strategy or notify the upper-layer application; After confirming that the data has been rolled back to the system memory or that the data cannot be obtained from other core processors, core processor A directly reads the required data from the system memory; and uses the prefetch mechanism to simultaneously read the adjacent and related data of the data, and stores this information in the historical access record table and the local cache.

3. The data access method according to claim 1, characterized in that: When the system accesses data, the adjacent and related data of the data are extracted and temporarily stored in the historical access record table.

4. The data access method according to claim 3, characterized in that: The step of extracting adjacent and related data of the data comprises: Before initiating a data access request, the core processor analyzes the application's needs to determine whether it needs to extract adjacent and related data; Based on the demand analysis, core processor A formulates a data extraction strategy and constructs a detailed request including the main data address, adjacent data range, related data identifiers, and extraction strategy; Send the request to the system memory manager and wait for a response. The system memory manager parses the request and analyzes the requirements and extraction strategy of core processor A. Check whether the required primary data and its adjacent / related data already exist in the cache. If so, prepare the data directly; if not, proceed to the next step; Read the master data from the system memory, determine the range of adjacent and related data to be extracted according to the extraction strategy, and extract the master data and its adjacent / related data from the memory; Organize the extracted data into a data structure processed by the core processor A, temporarily store the organized data in a historical access record table, and record relevant information of the data; When temporarily storing data, check whether there is a data conflict. If there is a conflict, handle it according to the conflict resolution strategy; and optimize the data layout and replacement strategy in the cache based on historical access records and current system load; The extracted and temporarily stored data is sent to the core processor A. After receiving the data, the core processor A performs corresponding processing, and the core processor A provides feedback to the system memory manager according to the processing result; The system regularly monitors data access performance and optimizes relevant strategies based on the monitoring results.

5. A processor, characterized in that: The processor includes a plurality of core processors, the core processors are connected to the system memory and other core processors through an input / output block, the input / output block includes a historical access record table, the historical access record table is used to temporarily store the part obtained by each core processor from the system memory; The historical access record table is a high-speed cache memory queue. The storage content of the historical access record table includes serial number, read / write status, validity and data. The historical access record table is used to record the historical records of each core accessing the system memory data. The steps of storing the historical access record table include: When the system starts, the size, data structure and cleanup strategy of the historical access record table are initialized according to the hardware configuration and performance requirements; Assign a unique identifier to each core processor and set a separate storage area or tag for each core in the historical access record table; Configure the parameters of the consistency circuit and the memory controller. When the core processor initiates a data access request, check whether the local cache contains the required data. If not, the core processor A sends a data access request to the memory controller through the input / output block. The memory controller processes the request and reads the data from the system memory. At the same time, the memory controller passes the relevant information of the access request to the input / output block; The input / output block checks the historical access record table to determine whether the same access request has been recorded; If a matching entry is found and its validity flag is valid, the input / output block directly reads data from the entry or updates its access timestamp; If no matching entry is found or the entry has expired, the input / output block creates a new history entry and fills it with information; Insert new entries into the historical access record table and check whether expired or no longer needed entries need to be deleted according to the configured cleanup strategy; The consistency circuit monitors the interaction between the historical access record table and the memory controller. When data conflict or inconsistency is detected, the consistency circuit takes appropriate measures to solve the problem. The input / output block periodically interacts with the cache manager to synchronize the cache status and the contents of the historical access record table, and the system monitoring tool periodically collects the performance indicators of the historical access record table; Based on the collected performance indicators, the performance bottlenecks and potential optimization points of the historical access record table are analyzed, and based on the analysis results, the size, data structure, cleanup strategy or parameters of the consistency circuit of the historical access record table are adjusted.

6. A processor according to claim 5, characterized in that: The historical access record table of the input / output block is connected to a consistency circuit and a memory controller, wherein the consistency circuit is connected to a core processor, and the memory controller is connected to the system memory.

Images