A bionic circuit for emotional associative memory based on memristor neural network

Abstract

The present invention discloses an emotion associative memory bionic circuit based on a memristor neural network, comprising: a signal input module, a fear emotion logic judgment module, a fear emotion synapse module, a disgust emotion logic judgment module, and a disgust emotion synapse module; the fear emotion logic judgment module is connected to the fear emotion synapse module, and the disgust emotion logic judgment module is connected to the disgust emotion synapse module; the signal input module is connected to the fear emotion logic judgment module and the disgust emotion logic judgment module. By adopting the technical solution of the present invention, different synapses between different emotion neurons are simulated by utilizing the differences between resistors and memristors, and different degrees of influence of these two different emotions on associative memory are simulated, so as to more comprehensively reflect the influence of human emotions on associative memory.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design, and in particular relates to an emotional associative memory bionic circuit based on a memristor neural network. Background Art

[0002] At present, neural network technology has developed rapidly, and brain-like intelligence has been widely studied and applied in recent years. However, the development of this network technology is based on software, which has high requirements for computing power and data processing, and will cause huge computing power loss. Memristor is a device with variable resistance value, which has the characteristics of low power consumption and fast response. Therefore, the use of memristor can solve this loss problem well.

[0003] Pavlov associative memory based on memristors has been widely studied, but in fact, human emotions will have an impact on associative memory, and different emotions have different effects on associative memory. Currently, there are few studies on the impact of emotions on associative memory. The invention with publication number CN202011483756 proposes a neural network circuit for emotional homeostasis regulation and associative memory to solve the problem that existing neural network circuits do not consider the characteristics of emotions themselves and their impact on memory.

[0004] However, the emotions considered in the above invention are single, collectively referred to as positive or negative emotions, and the degree of influence on associative memory is fixed and limited. Compared with a single emotion, people actually have multiple emotions, such as happiness, excitement, fear, disgust, and different emotions of people have different degrees of influence on associative memory. There is currently a lack of research on the influence of multiple emotions on associative memory. Summary of the invention

[0005] The technical problem to be solved by the present invention is an emotional associative memory bionic circuit based on a memristor neural network. The difference between resistors and memristors is used to simulate different synapses between neurons with different emotions, as well as the different degrees of influence of these two different emotions on associative memory, which can more comprehensively reflect the influence of human emotions on associative memory.

[0006] To achieve the above object, the present invention adopts the following technical solution:

[0007] An emotional associative memory bionic circuit based on a memristor neural network includes: a signal input module, a fear emotion logic judgment module, a fear emotion synapse module, a disgust emotion logic judgment module, and a disgust emotion synapse module; the fear emotion logic judgment module is connected to the fear emotion synapse module, and the disgust emotion logic judgment module is connected to the disgust emotion synapse module; the signal input module is connected to the fear emotion logic judgment module and the disgust emotion logic judgment module; wherein,

[0008] The fear emotion logic judgment module selects the corresponding function, i.e., the learning function or forgetting function of the fear emotion synapse module, by judging the activation state of the simulated fear language signal and the first simulated auditory signal in the signal input module, and changes the negative input voltage of the comparator COMP1 by changing the size of the memristor M1. When the input voltage is less than the fixed voltage V4 of the comparator COMP1, the comparator COMP1 outputs a positive voltage, and the fear emotion is activated.

[0009] The disgust emotion logic judgment module selects the corresponding function, that is, the learning function or forgetting function of the disgust emotion synapse module, by judging the activation state of the simulated disgust language signal and the second simulated auditory signal in the input module. The negative terminal voltage of the comparator COMP2 is changed by changing the size of the memristors M2 and M3. When the input voltage is less than the fixed voltage V8 of the comparator COMP2, the comparator COMP2 outputs a positive voltage and the disgust emotion is activated.

[0010] Preferably, the simulated fear language signal input terminal Vfear and the first simulated child auditory signal input terminal Va1 of the signal input module are connected to the fear emotion logic judgment module, and the simulated disgust language signal input terminal Vdisgust and the simulated child auditory input terminal Va2 of the signal input module are connected to the disgust emotion logic judgment module.

[0011] Preferably, the fear emotion logic judgment module is composed of a first AND gate AND1, a second AND gate AND2, a first OR gate OR1, a second OR gate OR2, a first NOT gate NOT1, and a second NOT gate NOT2; wherein the simulated fear language signal input terminal Vfear and the first simulated child auditory signal input terminal Va1 are respectively connected to the input terminal of the first OR gate OR1 and the input terminal of the first AND gate AND1, the output terminal of the first AND gate AND1 and the first simulated child auditory signal input terminal Va1 are connected to the input terminal of the second OR gate OR2, the simulated fear language signal input terminal Vfear is connected to the input terminal of the first NOT gate NOT1, the first simulated child auditory signal input terminal Va1 is connected to the input terminal of the second NOT gate NOT2, and the output terminal of the first NOT gate NOT1 and the output terminal of the second NOT gate NOT2 are connected to the input terminal of the second AND gate AND2.

[0012] Preferably, the fear emotion synapse module is composed of a first memristor M1, a first voltage-controlled switch S1, a second voltage-controlled switch S2, a third voltage-controlled switch S3, a fourth voltage-controlled switch S4, a first operational amplifier OP1, a second operational amplifier OP2, a first comparator COMP1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first constant voltage V1, a second constant voltage V2, a third constant voltage V3, a fourth constant voltage V4, a first digital operation unit ABM1, a second digital operation unit ABM2, and a third NOT gate NOT3; wherein,

[0013] The output end of the first voltage-controlled voltage S1 is connected to the output end of the first OR gate OR1, the output end of S1 is connected to the inverting input end of the first operational amplifier OP1, the output end of OP1 is connected to the input end of the first digital operation unit ABM1 and the 1 port of the second voltage-controlled voltage S2, the output end of the third NOT gate NOT3 is connected to the input end of the second voltage-controlled voltage S2, the output end of the first digital operation unit ABM1 is connected to the 1 port of the third voltage-controlled voltage S3, the 2 port of the second voltage-controlled voltage S2 and the 2 port of the third voltage-controlled voltage S3 are connected to the input end of the fixed resistor R4, the output end of R4 is connected to the positive input end of the first memristor M1, the inverting input end of M1 is connected to the inverting input end of the second operational amplifier OP2, the output end of OP2 and the output end of R4 are connected to the input end of the second digital operation unit ABM2, and the output end of the second digital operation unit ABM2 is connected to the inverting input end of the first comparator COMP1.

[0014] Preferably, the disgust emotion logic judgment module is composed of a third AND gate AND3, a fourth AND gate AND4, a third OR gate OR3, a fourth OR gate OR4, a fourth NOT gate NOT4, and a fifth NOT gate NOT5; wherein the simulated disgust language signal input terminal Vdisgust and the second simulated child auditory signal input terminal Va2 are respectively connected to the input terminal of the third OR gate OR3 and the input terminal of the third AND gate AND3, the output terminal of the third AND gate AND3 and the second simulated child auditory signal input terminal Va2 are connected to the input terminal of the fourth OR gate OR4, the simulated disgust language signal Vdisgust is connected to the input terminal of the fourth NOT gate NOT4, the second simulated child auditory signal input terminal Va2 is connected to the input terminal of the fifth NOT gate NOT5, and the output terminal of the fourth NOT gate NOT4 and the output terminal of the fifth NOT gate NOT5 are connected to the input terminal of the fourth AND gate AND4.

[0015] Preferably, the disgust emotion synapse module comprises a second memristor M2, a third memristor M3, a fifth voltage-controlled switch S5, a sixth voltage-controlled switch S6, a seventh voltage-controlled switch S7, an eighth voltage-controlled switch S8, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a fifth fixed voltage V5, a sixth fixed voltage V6, a seventh fixed voltage V7, an eighth fixed voltage V8, a third operational amplifier OP3, a fourth operational amplifier OP4, a second comparator COMP2, a third digital operation unit ABM3, a fourth digital operation unit ABM4, and a sixth NOT gate NOT6; wherein the output end of the fifth voltage-controlled voltage S5 is connected to the output end of the third OR gate OR3, the output end of S5 is connected to the reverse input end of the second memristor M2, and the forward input end of M2 is connected to the third The inverting input terminal of the operational amplifier OP3, the output terminal of OP3 is connected to the input terminal of the third digital operation unit ABM3 and the port 1 of the sixth voltage-controlled voltage S6, the output terminal of the sixth NOT gate NOT6 is connected to the input terminal of the sixth voltage-controlled voltage S6, the output terminal of the third digital operation unit ABM3 is connected to the port 1 of the seventh voltage-controlled voltage S7, the port 2 of the sixth voltage-controlled voltage S6 and the port 2 of the seventh voltage-controlled voltage S7 are connected to the input terminal of the fixed resistor R9, the output terminal of R9 is connected to the positive input terminal of the third memristor M3, the inverting input terminal of M3 is connected to the inverting input terminal of the fourth operational amplifier OP4, the output terminal of OP4 and the output terminal of R9 are connected to the input terminal of the fourth digital operation unit ABM4, and the output terminal of the fourth digital operation unit ABM4 is connected to the inverting input terminal of the second comparator COMP2.

[0016] By inputting the simulated fear language signal and the first simulated child auditory signal into the first OR gate OR1, the output voltage of the first OR gate OR1 is used to turn on the first voltage-controlled switch S1, and the fixed voltage V1 is output to the first operational amplifier OP1, and then output to the first digital operation unit ABM1 and the third voltage-controlled voltage S3 through the first operational amplifier OP1. After passing through the first digital operation unit ABM1, the output voltage value controls the change of the memristor value of the first memristor M1. The change of the resistance value of the first memristor M1 represents the change of the synaptic weight between the fear emotion and the fear language signal. Specifically, the smaller the resistance value of M1, the greater the synaptic weight. After passing through the second operational amplifier OP2 and the second digital operation unit ABM2, the output voltage of the second digital operation unit ABM2 is compared with the fourth fixed voltage V4 of the first comparator COMP1. According to the size of the COMP1 output voltage, the state of the child learning and forgetting the fear emotion is simulated.

[0017] By inputting the simulated disgusting language signal and the second simulated child auditory signal into the third OR gate OR3, that is, the simulated disgusting language signal input terminal and the child auditory signal input terminal are both at a high level. The output voltage of the third OR gate OR3 is at a high level, the fifth voltage-controlled switch S5 is turned on, and the output voltage Second Memristor The inverting input terminal is output through the operational amplifier OP4. Vout=- 。 The simulated disgust language signal input terminal and the child auditory signal input terminal are both high level, the third AND gate AND3 is high level, the fourth OR gate OR4 is high level, the output of OR4 passes through the sixth NOT gate to output a low level, S6 is not conducting, and the high level output of OR4 turns on S7. The output voltage Vout of OP3 passes through the third digital operation unit ABM3. Through S7, it is output to the positive input terminal of the memristor M3, causing the resistance of the memristor M3 to begin to decrease. When the negative terminal voltage value of the second comparator COMP2 is less than the voltage value of the positive port, the state of the child learning and forgetting disgust emotions is simulated.

[0018] By inputting the simulated fear language signal and the first simulated child auditory signal into the first OR gate OR1, the output voltage of the first OR gate OR1 is used to turn on the first voltage-controlled switch S1, and the fixed voltage V1 is output to the first operational amplifier OP1, and then output to the first digital operation unit ABM1 and the third voltage-controlled voltage S3 through the first operational amplifier OP1. After passing through the first digital operation unit ABM1, the output voltage value controls the change of the memristor value of the first memristor M1, and passes through the second operational amplifier OP2 and the second digital operation unit ABM2. The output voltage of the second digital operation unit ABM2 is compared with the fourth fixed voltage V4 of the first comparator COMP1, thereby simulating the state of a child learning and forgetting the fear emotion.

[0019] By inputting the simulated disgusting language signal and the second simulated child auditory signal into the third OR gate OR3, that is, the simulated disgusting language signal input terminal and the child auditory signal input terminal are both high level. The output voltage of the third OR gate OR3 is high level, the fifth voltage-controlled switch S5 is turned on, and the output voltage V5 is output to the inverting input terminal of the second memristor M3 through the operational amplifier OP4. Vout=- . The simulated disgust language signal input terminal and the child auditory signal input terminal are both high level, the third AND gate AND3 is high level, the fourth OR gate OR4 is high level, the output of OR4 passes through the sixth NOT gate to output a low level, S6 is not turned on, and the high level output of OR4 turns on S7. The output voltage Vout of OP3 passes through the third digital operation unit ABM3. Through S7, it is output to the positive input terminal of the memristor M3, causing the resistance of the memristor M3 to begin to decrease. When the voltage value of the negative terminal of the second comparator COMP2 is less than the voltage value of the positive port, the state of the child learning and forgetting disgust emotions is simulated.

[0020] By controlling the change in the resistance of the memristors M1, M2, and M3, the output of the entire circuit is controlled, thereby determining whether fear or disgust is generated.

[0021] The present invention can not only simulate the learning and forgetting process of the associative memory of a single emotion, but also effectively simulate the learning and forgetting process of the associative memory of similar emotions, and can effectively simulate the different degrees of influence of similar emotions on the learning and forgetting process of associative memory. The present invention takes fear and disgust as examples, has a simple structure and perfect functions, and is of great significance to the research on memristor bionic circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0023] Figure 1 It is a structural schematic diagram of the memristor bionic circuit of the emotional associative memory of the present invention;

[0024] Figure 2 Schematic diagram of IV characteristic curves of memristors M1, M2 and M3 of the present invention;

[0025] Figure 3 A schematic diagram of the PSPICE simulation results of the learning and forgetting of fear emotion of the present invention;

[0026] Figure 4 It is a schematic diagram of the PSPICE simulation results of the learning and forgetting of disgust emotion of the present invention;

[0027] Figure 5 A schematic diagram of PSPICE simulation results for comparing the learning and forgetting of two similar emotions according to the present invention. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] Embodiment 1:

[0031] like Figure 1 As shown, the embodiment of the present invention provides an emotional associative memory bionic circuit based on a memristor neural network, including: a signal input module, a fear emotion logic judgment module, a fear emotion synapse module, a disgust emotion logic judgment module, and a disgust emotion synapse module; the fear emotion logic judgment module is connected to the fear emotion synapse module, and the disgust emotion logic judgment module is connected to the disgust emotion synapse module; the signal input module is connected to the fear emotion logic judgment module and the disgust emotion logic judgment module; wherein,

[0032] The fear emotion logic judgment module selects the corresponding function, i.e., the learning function or forgetting function of the fear emotion synapse module, by judging the activation state of the simulated fear language signal and the first simulated auditory signal in the signal input module, and changes the negative input voltage of the comparator COMP1 by changing the size of the memristor M1. When the input voltage is less than the fixed voltage V4 of the comparator COMP1, the comparator COMP1 outputs a positive voltage, and the fear emotion is activated.

[0033] The disgust emotion logic judgment module selects the corresponding function, that is, the learning function or forgetting function of the disgust emotion synapse module, by judging the activation state of the simulated disgust language signal and the second simulated auditory signal in the input module. The negative terminal voltage of the comparator COMP2 is changed by changing the size of the memristors M2 and M3. When the input voltage is less than the fixed voltage V8 of the comparator COMP2, the comparator COMP2 outputs a positive voltage and the disgust emotion is activated.

[0034] like Figure 2 As shown, Figure 2 is the IV characteristic curve of the selected memristor M1, memristor M2, and memristor M3. Figure 2 It can be seen from the figure that the memristor's memristor value can decrease with the increase of voltage and increase with the decrease of voltage. Its maximum memristor value can reach , the minimum memristor value can be reached .

[0035] As an implementation mode of an embodiment of the present invention, the simulated fear language signal input terminal Vfear of the signal input module and the first simulated child auditory signal input terminal Va1 are connected to the fear emotion logic judgment module, and the simulated disgust language signal input terminal Vdisgust of the signal input module and the simulated child auditory input terminal Va2 are connected to the disgust emotion logic judgment module.

[0036] As an implementation mode of an embodiment of the present invention, the fear emotion logic judgment module is composed of a first AND gate AND1, a second AND gate AND2, a first OR gate OR1, a second OR gate OR2, a first NOT gate NOT1, and a second NOT gate NOT2; wherein the simulated fear language signal input terminal Vfear and the first simulated child auditory signal input terminal Va1 are respectively connected to the input terminal of the first OR gate OR1 and the input terminal of the first AND gate AND1, the output terminal of the first AND gate AND1 and the first simulated child auditory signal input terminal Va1 are connected to the input terminal of the second OR gate OR2, the simulated fear language signal input terminal Vfear is connected to the input terminal of the first NOT gate NOT1, the first simulated child auditory signal input terminal Va1 is connected to the input terminal of the second NOT gate NOT2, and the output terminal of the first NOT gate NOT1 and the output terminal of the second NOT gate NOT2 are connected to the input terminal of the second AND gate AND2.

[0037] As an implementation mode of an embodiment of the present invention, the fear emotion synapse module is composed of a first memristor M1, a first voltage-controlled switch S1, a second voltage-controlled switch S2, a third voltage-controlled switch S3, a fourth voltage-controlled switch S4, a first operational amplifier OP1, a second operational amplifier OP2, a first comparator COMP1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a fifth resistor R6, a first constant voltage V1, a second constant voltage V2, a third constant voltage V3, a fourth constant voltage V4, a first digital operation unit ABM1, a second digital operation unit ABM2, and a third NOT gate NOT3; wherein, the output end of the first voltage-controlled voltage S1 is connected to the output end of the first OR gate OR1, and the output end of S1 is connected to the first operational amplifier OP 1, the output end of OP1 is connected to the input end of the first digital operation unit ABM1 and the port 1 of the second voltage-controlled voltage S2, the output end of the third NOT gate NOT3 is connected to the input end of the second voltage-controlled voltage S2, the output end of the first digital operation unit ABM1 is connected to the port 1 of the third voltage-controlled voltage S3, the port 2 of the second voltage-controlled voltage S2 and the port 2 of the third voltage-controlled voltage S3 are connected to the input end of the fixed resistor R4, the output end of R4 is connected to the positive input end of the first memristor M1, the reverse input end of M1 is connected to the reverse input end of the second operational amplifier OP2, the output end of OP2 and the output end of R4 are connected to the input end of the second digital operation unit ABM2, and the output end of the second digital operation unit ABM2 is connected to the reverse input end of the first comparator COMP1.

[0038] As an implementation mode of an embodiment of the present invention, the disgust emotion logic judgment module is composed of a third AND gate AND3, a fourth AND gate AND4, a third OR gate OR3, a fourth OR gate OR4, a fourth NOT gate NOT4, and a fifth NOT gate NOT5; wherein the simulated disgust language signal input terminal Vdisgust and the second simulated child auditory signal input terminal Va2 are respectively connected to the input terminal of the third OR gate OR3 and the input terminal of the third AND gate AND3, the output terminal of the third AND gate AND3 and the second simulated child auditory signal input terminal Va2 are connected to the input terminal of the fourth OR gate OR4, the simulated disgust language signal Vdisgust is connected to the input terminal of the fourth NOT gate NOT4, the second simulated child auditory signal input terminal Va2 is connected to the input terminal of the fifth NOT gate NOT5, and the output terminal of the fourth NOT gate NOT4 and the output terminal of the fifth NOT gate NOT5 are connected to the input terminal of the fourth AND gate AND4.

[0039] As an implementation mode of an embodiment of the present invention, the disgust emotion synapse module is composed of a second memristor M2, a third memristor M3, a fifth voltage-controlled switch S5, a sixth voltage-controlled switch S6, a seventh voltage-controlled switch S7, an eighth voltage-controlled switch S8, a seventh resistor R8, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a fifth fixed voltage V5, a sixth fixed voltage V6, a seventh fixed voltage V7, an eighth fixed voltage V8, a third operational amplifier OP3, a fourth operational amplifier OP4, a second comparator COMP2, a third digital operation unit ABM3, a fourth digital operation unit ABM4, and a sixth NOT gate NOT6; wherein the output end of the fifth voltage-controlled voltage S5 is connected to the output end of the third OR gate OR3, the output end of S5 is connected to the reverse input end of the second memristor M2, and the forward input end of M2 The input end is connected to the inverting input end of the third operational amplifier OP3, the output end of OP3 is connected to the input end of the third digital operation unit ABM3 and the port 1 of the sixth voltage-controlled voltage S6, the output end of the sixth NOT gate NOT6 is connected to the input end of the sixth voltage-controlled voltage S6, the output end of the third digital operation unit ABM3 is connected to the port 1 of the seventh voltage-controlled voltage S7, the port 2 of the sixth voltage-controlled voltage S6 and the port 2 of the seventh voltage-controlled voltage S7 are connected to the input end of the fixed resistor R9, the output end of R9 is connected to the positive input end of the third memristor M3, the inverting input end of M3 is connected to the inverting input end of the fourth operational amplifier OP4, the output end of OP4 and the output end of R9 are connected to the input end of the fourth digital operation unit ABM4, and the output end of the fourth digital operation unit ABM4 is connected to the inverting input end of the second comparator COMP2.

[0040] The activation state of the fear emotion logic judgment module is controlled by simulating the fear language signal and the first simulated child auditory signal, the synaptic weight in the fear emotion synaptic module is changed by the activation state of the fear emotion logic judgment module, and whether the fear emotion is activated is judged by the voltage output by the fear emotion synaptic module. The activation state of the disgust emotion logic judgment module is controlled by simulating the disgust language signal and the second simulated child auditory signal, the synaptic weight in the disgust emotion synaptic module is changed by the activation state of the disgust emotion logic judgment module, and whether the disgust emotion is activated is judged by the voltage output by the disgust emotion synaptic module. The present invention can not only realize the function of learning and forgetting the fear emotion, but also realize the function of learning and forgetting the similar emotion, namely the disgust emotion, and can compare the influence of the two emotions on associative memory.

[0041] Furthermore, in the embodiment of the present invention, when a high level is input, it is used to simulate the occurrence of a fear language signal or a simulated disgust language fear signal or a child's auditory signal stimulation, and when a low level is input, it is used to simulate the occurrence of a fear language signal or a simulated disgust language fear signal or a child's auditory signal stimulation; the output signal high level simulates that the child has a fear emotion or a disgust emotion, and the output signal low level simulates that the child does not have a fear emotion or a disgust emotion. Assume that the initial test state of the memristors M1, M2, and M3 in each scenario is .

[0042] The present invention conducts example analysis on four scenarios: learning fear emotion, forgetting fear emotion, learning disgust emotion, and forgetting disgust emotion.

[0043] like Figure 3 The figure shows the simulation diagram of the learning process and forgetting process of fear emotion. The specific process is:

[0044] Fear emotion learning stage: Simulated fear language signal and child auditory signal are given at the same time. That is, the simulated fear language signal input terminal Vfear and the child auditory signal input terminal Va1 are both high level. The output voltage of the first OR gate OR1 is high level, the first voltage-controlled switch S1 is turned on, and the fixed value voltage V1 is output to the negative input port of the first operational amplifier OP1, and the operational amplifier OP1 outputs Vout=- V1 , where R2=150Ω, R3=100Ω, V1=15.5V, the analog fear language signal input terminal and the child auditory signal input terminal are both high level, the first AND gate AND1 is high level, the second OR gate OR2 is high level, the output of OR2 passes through the third NOT gate to output a low level, S2 is not conducting, and the high level output of OR2 turns on S3. The output voltage Vout of OP1 passes through the first digital operation unit ABM1 Vout= . It is output to the positive input terminal of memristor M1 through S3, causing the resistance of memristor M2 to begin to decrease. It is output through ABM2 The module outputs voltage to the negative terminal of the first comparator COMP1, and compares it with the voltage value of the positive terminal of the first comparator COMP1. When it is less than the voltage value of the positive terminal, it outputs a high level to generate fear emotion.

[0045] Fear emotion forgetting stage 1: only give the child an auditory signal. That is, the simulated fear language signal input terminal Vfear is low level, and the child's auditory input terminal Va1 is high level. The output voltage of the first OR gate OR1 is high level, the first voltage-controlled switch S1 is turned on, and the first fixed value voltage V1 is output to the first operational amplifier OP1, and the operational amplifier OP1 outputs Vout=- V1 , where R2=150Ω, R3=100Ω, V1=15.5V, the simulated fear language signal input is low level, and the child's auditory input is high level. Then the first AND gate AND1 is low level, the second OR2 output is low level, the third voltage-controlled switch S3 is closed, the third NOT gate NOT3 output is high level, the second voltage-controlled switch S2 is turned on, the output of OP1 passes through the second voltage-controlled switch S2 to the memristor M1, the resistance of the memristor increases, and the voltage output of OP2 is output through ABM2 , compared with the voltage of the positive terminal of the first comparator COMP1, when the positive input terminal is greater than the reverse input terminal, the forgetting of the fear emotion is completed.

[0046] Fear emotion forgetting stage 2: No stimulation is given to the simulated fear language signal and the child's auditory signal, that is, the simulated fear language input terminal Vfear and the child's auditory input terminal Va1 are both low level. The outputs of the first NOT gate NOT1 and the second NOT gate NOT2 are both high level, then the output high level of the second AND gate AND2 goes to the fourth voltage-controlled switch S4, and the output is a negative constant voltage V3, which goes to the positive input terminal of the memristor M1, increasing the resistance of the memristor M1. The voltage output of OP2 is output through ABM2 , compared with the voltage of the positive terminal of the first comparator COMP1, when the positive input terminal is greater than the reverse input terminal, the forgetting of the fear emotion is completed.

[0047] like Figure 4 The figure shows the simulation diagram of the learning process and forgetting process of disgust emotion. The specific process is:

[0048] Disgust emotion learning stage: Simulated disgust language signal and child auditory signal are given at the same time. That is, the simulated disgust language signal input terminal Vdisgust and the child auditory signal input terminal Va2 are both high level. The output voltage of the third OR gate OR3 is high level, the fifth voltage-controlled switch S5 is turned on, and the fifth fixed value voltage is output to the reverse input port of the memristor M2. The resistance of the memristor M2 increases, and the output is through the operational amplifier OP3. Vout=- , where R8=100Ω, V5=15.5V. As M2 increases, the absolute value of Vout decreases. The analog disgust language signal input terminal and the child auditory signal input terminal are both high level, the third AND gate AND3 is high level, the fourth OR gate OR4 is high level, the output of OR4 passes through the sixth NOT gate to output a low level, S6 is not conducting, and the high level output of OR4 turns on S7. The output voltage Vout of OP3 passes through the third ABM3 module Vout= . It is output to the positive input terminal of the memristor M3 through S7, so that the resistance of the memristor M3 begins to decrease. When the voltage value of the negative terminal of the second comparator COMP2 is less than the voltage value of the positive terminal, it outputs a high level, generating disgust emotion.

[0049] Disgust forgetting stage 1: Only give the child an auditory signal. That is, the analog disgust language signal input terminal Vdisgust is low level, and the child's auditory input terminal Va2 is high level. The output voltage of the third OR gate OR4 is high level, the fifth voltage-controlled switch S5 is turned on, and the fixed value voltage V is output to the reverse input terminal of the memristor M2, and then output through the third operational amplifier OP3. Vout=- , where R8=100Ω, V5=15.5V. The analog disgust language signal input terminal Vdisgust is low level, and the child's auditory input terminal Va2 is high level. Then the third AND gate AND3 is low level, the fourth OR gate OR4 output is low level, the seventh voltage-controlled switch S7 is closed, the sixth NOT gate NOT6 output is high level, the sixth voltage-controlled switch S6 is turned on, the output of OP3 passes through the sixth voltage-controlled switch S6 to the memristor M3, the resistance of the memristor increases, and the voltage output of OP4 is output through ABM4 , compared with the voltage of the positive terminal of the second comparator COMP2, when the positive input terminal is greater than the reverse input terminal, the forgetting of the fear emotion is completed.

[0050] Disgust emotion forgetting stage 2: No stimulation is given to the simulated disgust language signal and the child's auditory signal, that is, the simulated disgust language input terminal Vdisgust and the child's auditory input terminal Va2 are both low level. The outputs of the fourth NOT gate NOT4 and the fifth NOT gate NOT5 are both high level, then the output high level of the fourth AND gate AND4 is sent to the eighth voltage-controlled switch S8, and the negative fixed voltage V7 is output to the positive input terminal of the memristor M3, so that the resistance value of the memristor M3 increases. The voltage output of OP4 is output through ABM4 , compared with the voltage at the positive terminal of the second comparator COMP2, when the positive input terminal is greater than the reverse input terminal, the forgetting of the fear emotion is completed.

[0051] like Figure 5 The figure shows a simulation diagram comparing the learning process and forgetting process of fear emotion with the learning process and forgetting process of disgust emotion. The specific process is as follows:

[0052] Comparison between fear and disgust: When inputting voltage from the positive end of the memristor, the smaller the voltage value, the faster the resistance of the memristor will decrease. When inputting voltage from the reverse end of the memristor, the smaller the voltage value, the slower the resistance of the memristor will increase. It can be clearly seen from the figure that the memory speed of disgust is faster and the forgetting speed is slower. In the learning stage, the fixed resistors V1 and V5 given by the two emotion modules are equal in size, but in the disgust emotion, the core of the synaptic module between the neurons of the disgust emotion is the memristor M2 and M3. When the reverse access of M2 can input a positive voltage, the output of the operational amplifier OP3 is Vout=- , where R8=100Ω, V5=15.5V. The increase of memristor M2 can reduce the absolute value of Vout output by operational amplifier OP3, and the memristor can get a faster drop speed after flowing through memristor M3. In the forgetting stage, when the reverse access of M2 can input positive voltage, the output of operational amplifier OP3 is Vout=- , the reduction of memristor M2 can increase the absolute value of Vout output by operational amplifier OP3, and after flowing through memristor M3, the memristor can achieve a slower forgetting speed.

[0053] The embodiments described above are only descriptions of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. An emotional associative memory bionic circuit based on a memristor neural network, characterized in that: include: Signal input module, fear emotion logic judgment module, fear emotion synapse module, disgust emotion logic judgment module, disgust emotion synapse module; The fear emotion logic judgment module is connected to the fear emotion synapse module, and the disgust emotion logic judgment module is connected to the disgust emotion synapse module; the signal input module is connected to the fear emotion logic judgment module and the disgust emotion logic judgment module; wherein, The fear emotion logic judgment module selects the corresponding function, i.e., the learning function or forgetting function of the fear emotion synapse module, by judging the activation state of the simulated fear language signal and the first simulated auditory signal in the signal input module, and changes the negative input voltage of the comparator COMP1 by changing the size of the memristor M1. When the input voltage is less than the fixed voltage V4 of the comparator COMP1, the comparator COMP1 outputs a positive voltage, and the fear emotion is activated. The disgust emotion logic judgment module selects the corresponding function, i.e., the learning function or forgetting function of the disgust emotion synapse module, by judging the activation state of the simulated disgust language signal and the second simulated auditory signal in the input module. The negative terminal voltage of the comparator COMP2 is changed by changing the size of the memristors M2 and M3. When the input voltage is less than the fixed voltage V8 of the comparator COMP2, the comparator COMP2 outputs a positive voltage, and the disgust emotion is activated. The simulated fear language signal input terminal Vfear and the first simulated child hearing signal input terminal Va1 of the signal input module are connected to the fear emotion logic judgment module, and the simulated disgust language signal input terminal Vdisgust and the simulated child hearing input terminal Va2 of the signal input module are connected to the disgust emotion logic judgment module; The fear emotion logic judgment module is composed of a first AND gate AND1, a second AND gate AND2, a first OR gate OR1, a second OR gate OR2, a first NOT gate NOT1, and a second NOT gate NOT2; wherein the simulated fear language signal input terminal Vfear and the first simulated child auditory signal input terminal Va1 are respectively connected to the input terminal of the first OR gate OR1 and the input terminal of the first AND gate AND1, the output terminal of the first AND gate AND1 and the first simulated child auditory signal input terminal Va1 are connected to the input terminal of the second OR gate OR2, the simulated fear language signal input terminal Vfear is connected to the input terminal of the first NOT gate NOT1, the first simulated child auditory signal input terminal Va1 is connected to the input terminal of the second NOT gate NOT2, and the output terminal of the first NOT gate NOT1 and the output terminal of the second NOT gate NOT2 are connected to the input terminal of the second AND gate AND2; The fear emotion synapse module is composed of a first memristor M1, a first voltage-controlled switch S1, a second voltage-controlled switch S2, a third voltage-controlled switch S3, a fourth voltage-controlled switch S4, a first operational amplifier OP1, a second operational amplifier OP2, a first comparator COMP1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first constant voltage V1, a second constant voltage V2, a third constant voltage V3, a fourth constant voltage V4, a first digital operation unit ABM1, a second digital operation unit ABM2, and a third NOT gate NOT3; wherein the output end of the first voltage-controlled voltage S1 is connected to the output end of the first OR gate OR1, and the output end of S1 is connected to the inverting input end of the first operational amplifier OP1, The output end of OP1 is connected to the input end of the first digital operation unit ABM1 and the port 1 of the second voltage-controlled voltage S2, the output end of the third NOT gate NOT3 is connected to the input end of the second voltage-controlled voltage S2, the output end of the first digital operation unit ABM1 is connected to the port 1 of the third voltage-controlled voltage S3, the port 2 of the second voltage-controlled voltage S2 and the port 2 of the third voltage-controlled voltage S3 are connected to the input end of the fixed resistor R4, the output end of R4 is connected to the positive input end of the first memristor M1, the reverse input end of M1 is connected to the reverse input end of the second operational amplifier OP2, the output end of OP2 and the output end of R4 are connected to the input end of the second digital operation unit ABM2, and the output end of the second digital operation unit ABM2 is connected to the reverse input end of the first comparator COMP1; The disgust emotion logic judgment module is composed of a third AND gate AND3, a fourth AND gate AND4, a third OR gate OR3, a fourth OR gate OR4, a fourth NOT gate NOT4, and a fifth NOT gate NOT5; wherein the simulated disgust language signal input terminal Vdisgust and the second simulated child auditory signal input terminal Va2 are respectively connected to the input terminal of the third OR gate OR3 and the input terminal of the third AND gate AND3, the output terminal of the third AND gate AND3 and the second simulated child auditory signal input terminal Va2 are connected to the input terminal of the fourth OR gate OR4, the simulated disgust language signal Vdisgust is connected to the input terminal of the fourth NOT gate NOT4, the second simulated child auditory signal input terminal Va2 is connected to the input terminal of the fifth NOT gate NOT5, the output terminal of the fourth NOT gate NOT4 and the output terminal of the fifth NOT gate NOT5 are connected to the input terminal of the fourth AND gate AND4; The disgust emotion synapse module comprises a second memristor M2, a third memristor M3, a fifth voltage-controlled switch S5, a sixth voltage-controlled switch S6, a seventh voltage-controlled switch S7, an eighth voltage-controlled switch S8, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a fifth constant voltage V5, a sixth constant voltage V6, a seventh constant voltage V7, an eighth constant voltage V8, a third operational amplifier OP3, a fourth operational amplifier OP4, a second comparator COMP2, a third digital operation unit ABM3, a fourth digital operation unit ABM4, and a sixth NOT gate NOT6; wherein the output end of the fifth voltage-controlled voltage S5 is connected to the output end of the third OR gate OR3, the output end of S5 is connected to the reverse input end of the second memristor M2, and the forward input end of M2 is connected to the third operational amplifier OP4. The inverting input terminal of the amplifier OP3, the output terminal of OP3 is connected to the input terminal of the third digital operation unit ABM3 and the port 1 of the sixth voltage-controlled voltage S6, the output terminal of the sixth NOT gate NOT6 is connected to the input terminal of the sixth voltage-controlled voltage S6, the output terminal of the third digital operation unit ABM3 is connected to the port 1 of the seventh voltage-controlled voltage S7, the port 2 of the sixth voltage-controlled voltage S2 and the port 2 of the seventh voltage-controlled voltage S7 are connected to the input terminal of the fixed resistor R9, the output terminal of R9 is connected to the positive input terminal of the third memristor M3, the inverting input terminal of M3 is connected to the inverting input terminal of the fourth operational amplifier OP4, the output terminal of OP4 and the output terminal of R9 are connected to the input terminal of the fourth digital operation unit ABM4, and the output terminal of the fourth digital operation unit ABM4 is connected to the inverting input terminal of the second comparator COMP2.

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