A simulation system supporting fast large-scale brain simulation

Abstract

The application discloses a simulation system supporting fast large-scale brain simulation, and belongs to the technical field of brain simulation.The simulation system comprises a hardware device layer, which provides a plurality of hardware device resources; a data communication layer, which provides a plurality of types of communication modes between the computing nodes; an operation abstraction layer, which provides a plurality of types of neuron models, synapse models, connection rules and learning rules; an API layer, which provides an API interface and receives user requirements through the API interface; a hardware abstraction layer, which calls corresponding hardware kernels; and a network abstraction layer, which firstly records the topological structure of a brain simulation network, performs resource allocation and neuron cluster mapping, then creates the brain simulation network on the hardware device, and finally performs training or execution of the brain simulation network.The application fully utilizes cluster hardware resources to realize faster and larger-scale brain simulation, and solves the problems of lack of resource scheduling and resource allocation, insufficient utilization of device parallelism, too long communication time consumption, and limited support of hardware and interfaces.

Description

Technical Field

[0001] This invention belongs to the field of brain simulation technology, specifically relating to a simulation system that supports rapid large-scale brain simulation. Background Technology

[0002] The development of traditional artificial intelligence, represented by deep learning, has reached a bottleneck. It not only struggles to achieve general artificial intelligence similar to the human brain but also consumes vast amounts of energy. The human brain represents the pinnacle of biological intelligence. Brain simulation not only reflects the most advanced artificial intelligence but also inspires new developments in AI technology. Referencing the spiking neural networks of the human brain provides new insights into general artificial intelligence. The human brain contains approximately 86 billion neurons. To achieve brain-like artificial intelligence, a brain simulation of a similar scale is first needed. Creating and running large-scale brain models has become an important interdisciplinary research topic. However, there is currently a lack of effective simulation systems to support rapid, large-scale brain simulation, thus preventing the full utilization of computing resources to achieve faster and larger-scale brain simulations.

[0003] Several brain simulation systems have been proposed in the prior art: for example, the NEURON simulation system focuses on simulating biological neuron models, providing a powerful and flexible environment for realizing biological models of electrical and chemical signals in neurons and neuronal networks, attempting to simulate complex biological neuron models; the Brain simulation system emphasizes simplicity and flexibility, allowing the development of related models through equations and computational formulas, facilitating the development of complex neuron models and reducing the time spent on code writing; and the GeNN (GPU enhanced Neuronal Networks) simulation system implements a 4.13 × 10⁻⁶ macaque visual cortex on a single GPU by dynamically generating synapses. 6 Brain simulations at the neuron level; for example, the NEST (NEural Simulation Tool) simulation system focuses on the system dynamics and scale effects of spiking neural networks rather than complex neuron models, and can perform brain simulations on distributed clusters.

[0004] Among them, the NEURON and Brain simulation systems primarily focus on modeling neuronal models, facilitating researchers in neurobiology to develop complex neuronal models that more closely resemble biological neurons. However, both systems lack sufficient support for multithreading and multiprocessing, making large-scale brain simulations difficult. While the GeNN simulation system achieves brain simulations at the million-neuron level on a single GPU through dynamic synapse generation, it only supports brain simulations on a single GPU and does not support distributed computing clusters, hindering larger-scale brain simulations. Although the NEST simulation system supports brain simulations on distributed clusters, its network parallelism needs improvement, communication between cluster computing nodes is time-consuming, and it lacks support for resource allocation. Therefore, the NEST simulation system struggles to fully utilize hardware resources for rapid, large-scale brain simulations. Summary of the Invention

[0005] The purpose of this invention is to provide a simulation system that supports rapid large-scale brain simulation, making full use of cluster hardware resources to achieve faster and larger-scale brain simulation, and solving the problems of lack of resource scheduling and allocation, insufficient utilization of device parallelism, excessive communication time, and limited support hardware and interfaces in the prior art.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A simulation system supporting rapid large-scale brain simulation, the simulation system comprising a hardware device layer, a data communication layer, an operation abstraction layer, an API layer, a hardware abstraction layer, and a network abstraction layer, wherein:

[0008] The hardware device layer is used to provide multiple hardware device resources;

[0009] The data communication layer is used to provide multiple types of communication methods between the computing nodes of the brain simulation network;

[0010] The operational abstraction layer is used to provide multiple types of neuron models, synapse models, connection rules, and learning rules;

[0011] The API layer is used to provide predefined API interfaces to receive user requests.

[0012] The hardware abstraction layer is used to call the corresponding hardware kernel according to the hardware device specified in the user requirements;

[0013] The network abstraction layer is used to first record the topology of the brain simulation network provided in the user's requirements, and then allocate resources and map neuron clusters according to the information of the specified hardware device and the topology of the brain simulation network. Then, according to the neuron model, synapse model, connection rules, learning rules and communication method type specified in the user's requirements, the brain simulation network is created on the corresponding hardware device. Finally, the brain simulation network is trained or executed on the specified hardware device according to the user's requirements.

[0014] Several alternative methods are provided below, but they are not intended as additional limitations on the overall solution above. They are merely further additions or optimizations. Provided there are no technical or logical contradictions, each alternative method can be combined individually with respect to the overall solution above, or multiple alternative methods can be combined with each other.

[0015] Preferably, the hardware device resources provided by the hardware device layer include: central processing unit (CPU), graphics processing unit (GPU), and brain-like computing unit (BCU) type hardware devices.

[0016] Preferably, the communication method provided by the data communication layer is determined by communication rules, communication operators, and communication libraries.

[0017] Preferably, the types of the communication rules include All_Reduce, Broadcast, Reduce, All_Gather, Reduce_Scatter, All_To_All, and Point_To_Point;

[0018] The communication operator is used to encode the pulse information between computing nodes. The encoding methods are divided into dense encoding and sparse encoding.

[0019] The communication library supports both the MPI and NCCL communication libraries.

[0020] Preferably, the neuron model types include IF neuron model, LIF neuron model, HH neuron model and IZH neuron model;

[0021] The types of synaptic models include Static_synapse, Dynamic_synapse, and RealTime_synapse.

[0022] The connection rules include One_To_One connection, All_To_All connection, Fixed_Prob connection, Fixed_PreNum connection, Fixed_PostNum connection, and Fixed_Total_Number connection;

[0023] The learning rule is the STDP learning rule.

[0024] Preferably, the API interface includes a device-specified interface, a model networking interface, and a model running interface;

[0025] The device-specified interface is used by the user to specify the type and quantity of hardware devices.

[0026] The model networking interface is used for users to input the topology of the brain simulation network. The topology includes the neuron model of neurons in the neuron cluster, the number of neurons and the parameters of the neurons, and specifies the synapse model, connection rules and communication method type.

[0027] The model operation interface is used for users to input training parameters or execution parameters, and the training parameters include learning rules.

[0028] Preferably, the network abstraction layer is also used to initialize the specified hardware devices according to the type and quantity of hardware devices specified in the user requirements, and to read the storage space of each hardware device.

[0029] Preferably, the resource allocation and neuron cluster mapping based on the information of the specified hardware device and the topology of the brain simulation network includes:

[0030] Based on the storage space of each hardware device and the topology of the brain simulation network, tightly connected clusters of neurons in the brain simulation network are allocated to the same hardware device to complete resource allocation.

[0031] Based on resource allocation, a process ID is assigned to each neuron cluster, the neuron cluster is mapped to the specified hardware device, and proxy neurons are established for neurons connected by synapses across hardware devices.

[0032] Preferably, creating the brain simulation network on the corresponding hardware device includes:

[0033] If the user request does not call resource allocation, the brain simulation network will be created on the specified hardware device according to the recorded topology of the brain simulation network in a round-robin manner; if the user request calls resource allocation, the brain simulation network will be created on the specified hardware device according to the resource allocation and neuron cluster mapping, based on the recorded topology of the brain simulation network.

[0034] Preferably, when creating a brain simulation network on the corresponding hardware device, all hardware devices create neuron clusters and synaptic connections in parallel.

[0035] Preferably, the network abstraction layer is also used to draw a pulse firing diagram and / or a membrane voltage diagram based on the training or execution results of the brain simulation network, and output the pulse firing diagram and / or membrane voltage diagram through the API interface.

[0036] This invention provides a simulation system supporting rapid, large-scale brain simulation. The system supports computer cluster systems and resource scheduling, allowing neuronal clusters to be created and simulated on designated hardware devices. The simulation system separates model parameter / variable management from model construction to a certain extent, facilitating the actual creation of the brain simulation network on the hardware device after resource allocation, rather than creating the brain simulation network first, then allocating resources, and then creating the network again, which leads to redundant network creation. In resource allocation, closely connected neuronal clusters are assigned to the same hardware device, reducing communication between hardware devices and minimizing the overhead of cross-device synaptic connections, while ensuring load balancing across hardware devices, thereby achieving faster and larger-scale brain simulation. Attached Figure Description

[0037] Figure 1 This is a block diagram of a simulation system that supports rapid large-scale brain simulation according to the present invention;

[0038] Figure 2 This is a diagram showing the pulse output from the experiment of this invention. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0041] Existing simulation systems place too much emphasis on building up the neuron model and have limited support for large-scale brain simulation. They do not fully utilize the parallelism of cluster devices, waste storage space, and have excessively long communication times. Therefore, this embodiment proposes a simulation system that supports fast large-scale brain simulation. This simulation system supports computer cluster systems and resource scheduling, and neuron clusters can be created and simulated on designated hardware devices.

[0042] like Figure 1As shown in the figure, a simulation system supporting rapid large-scale brain simulation in this embodiment comprises: a hardware device layer, a data communication layer, an operation abstraction layer, an API layer, a hardware abstraction layer, and a network abstraction layer.

[0043] The hardware device layer provides hardware device resources for the simulation system; the data communication layer facilitates communication between computing nodes in the distributed cluster; the operation abstraction layer stores basic, indivisible operations, including neuron models and synapse models; the API layer provides users with predefined APIs (Application Program Interfaces); the hardware abstraction layer abstracts hardware resources and calls different hardware kernels based on user-specified hardware; the network abstraction layer encapsulates the abstracted operations, providing support for the API layer. This simulation system enables rapid, large-scale brain simulation. The following provides a detailed description of each layer in the simulation system.

[0044] (1) Hardware device layer, used to provide multiple hardware device resources.

[0045] The hardware resources in this embodiment can be independent hardware devices or hardware resources of a cluster system. Corresponding to common scenarios of brain simulation, the hardware device layer of this embodiment pre-sets hardware resources including: central processing unit (CPU), graphics processing unit (GPU), and brain-inspired computing unit (BCU) type hardware devices.

[0046] Users can actually create brain simulation networks on different hardware devices such as CPUs, GPUs, and BCUs to perform brain simulations. In addition, considering the expanded applications of the simulation system, the hardware device layer also supports intermediate representation (RI) files for hardware extension.

[0047] (2) Data communication layer, which provides various communication methods between computing nodes in the brain simulation network. The communication methods are determined by communication rules, communication operators and communication libraries.

[0048] (2.1) Communication rules: The types of communication rules executed by the simulation system include All_Reduce, Broadcast, Reduce, All_Gather, Reduce_Scatter, All_To_All and Point_To_Point, which are used to complete the communication of pulse delivery between hardware devices.

[0049] Communication rule All_Reduce: Reduce is a general term for a series of simple computational operations, and All_Reduce applies the same Reduce operation to all processes. All_Reduce operation can be completed through Reduce + Broadcast operation on a single node.

[0050] Broadcast: The Broadcast operation broadcasts the input of a node to other nodes. In distributed machine learning, it is often used for the initialization of network parameters.

[0051] Communication rule Reduce: Reduce, also known as reduction operation, is a collective term for a series of simple operations, which can be further subdivided into reduction operations such as SUM, MIN, MAX, PROD, LOR, etc. Reduce means to reduce / simplify, because its operation takes an array of input elements on each process, and after performing the operation, it will obtain fewer elements.

[0052] The All_Gather communication rule: The Gather operation collects data from multiple senders onto a single node. Gather can be understood as the reverse of Scatter. Instead of distributing data from one process to multiple processes, the Gather operation collects data from multiple processes onto a single process. This is often useful in many-to-many communication scenarios, where the All_Gather operation is needed. For a set of data distributed across all processes, All_Gather collects all data across all processes. At its most basic level, All_Gather is equivalent to a Gather operation followed by a Bcast operation.

[0053] Communication rule Reduce_Scatter: The Reduce_Scatter operation first sums the input of the process, then splits it in the 0th dimension according to the number of cards, and distributes the data to the corresponding cards.

[0054] The All_To_All communication rule: All_To_All is a full exchange operation. Through All_To_All communication, each node can obtain values ​​from other nodes. When using All_To_All, each process sends messages to any other process, and each process also receives messages from any other process. Each process's receive and send buffers are arrays divided into several data blocks. The specific operation of All_To_All is: process i sends the j-th block of data from its send buffer to process j, and process j places the received data block from process i into the i-th position of its own receive buffer.

[0055] Communication rule Point_To_Point: Point_To_Point is point-to-point communication, which is communication between two nodes.

[0056] It is easy to understand that the above are some of the more conventional communication rules provided in this embodiment. In practical applications, other communication rules can be selected as needed, such as Scatter, Gather, etc.

[0057] (2.2) Communication operators are used to encode pulse information between computing nodes. The encoding methods are divided into dense encoding and sparse encoding. In practical applications, the encoding method can be selected to reduce the amount of data transmitted and reduce communication time.

[0058] When the neuron firing rate is high, dense encoding is used. Dense encoding uses binary 0s and 1s to indicate whether the corresponding neuron has fired a pulse. A value of 1 indicates that the neuron corresponding to that bit has fired a pulse, and a value of 0 indicates that the neuron corresponding to that bit has not fired a pulse. When the neuron firing rate is low, sparse encoding is used. The index of the neuron indicates whether it has fired a pulse. If the index of the neuron is present in the data, it indicates that the neuron has fired a pulse; if the index is not present, it indicates that the neuron has not fired a pulse. This method completes the encoding and decoding of pulse data, facilitating its transmission.

[0059] (2.3) The communication library supports the MPI (Multi Point Interface) communication library and the NCCL (NVIDIA Collective Communications Library) communication library, and supports multiple communication interfaces such as infiniteband (“Infinite Bandwidth” technology, abbreviated as IB), PCIE (bus interface, PCI-Express), and NvLink.

[0060] (3) Operational abstraction layer, used to provide various types of neuron models, synapse models, connection rules and learning rules.

[0061] (3.1) The types of neuron models include IF (Integrate-and-Fire) neuron models, LIF (leaky-Integrate-and-Fire) neuron models, HH (Hodgkin-Huxley) neuron models, and IZH (Izhikevich) neuron models. In other embodiments, other types of neuron models may also be introduced, such as FHN (Fitzhugh-Nagumo) neuron models, ML (Morris-Lecar) neuron models, etc., or even custom neuron models.

[0062] (3.2) Synaptic models include Static_synapse, Dynamic_synapse, and RealTime_synapse. Static_synapses remain unchanged during brain simulation; Dynamic_synapses are mainly used for model training, where synaptic weights change continuously. RealTime_synapses are designed to reduce storage space consumption by synapses. Synapses are not generated in storage space but are generated and destroyed in real time as needed during simulation, thus reducing storage space consumption. RealTime_synapses only save the delay of synaptic connections in advance, not the weights. The weights are generated on demand during the execution of the brain simulation network. This on-demand generation can be based on the source neuron ID and target neuron ID of each synaptic connection during pulse propagation, with the weights being either truly random or pseudo-random numbers.

[0063] (3.3) The types of connection rules include One_To_One connection, All_To_All connection, Fixed_Prob connection, Fixed_PreNum connection, Fixed_PostNum connection and Fixed_Total_Number connection, which makes it convenient for users to establish connections between neuron clusters.

[0064] The connection function processes connections differently depending on the connection type. In One_To_One connection mode, connections are made one-to-one according to the neuron IDs in the source and target neuron clusters. In All_To_All connection mode, all neurons in both the source and target neuron clusters are traversed, and connections are made between each pair of neurons. In Fixed_Prob connection mode, the probability of each postsynaptic neuron forming a connection with a neuron in the presynaptic neuron cluster is fixed. In Fixed_PreNum connection mode, each neuron in the postsynaptic neuron cluster is randomly connected to a fixed number of neurons in the presynaptic neuron cluster. In Fixed_PostNum connection mode, each neuron in the presynaptic neuron cluster is randomly connected to a fixed number of neurons in the postsynaptic neuron cluster. In Fixed_Total_Number connection mode, the number of synaptic connections between the two neuron clusters is fixed; a fixed number of neuron IDs are randomly selected from the source and target neuron clusters and then connected one by one.

[0065] (3.4) The learning rule is the STDP (spike-timing dependent plasticity) learning rule. The system supports STDP learning rules such as Nearest-neighbour STDP and Temporal all-to-all STDP, and updates the synaptic weights during training.

[0066] (4) API layer, which provides predefined API interfaces to receive user requests. In this embodiment, the API interfaces include device specification interfaces, model networking interfaces, and model operation interfaces.

[0067] (4.1) Device specification interface, which is used by users to specify the type and quantity of hardware devices and provide users with hardware resource management capabilities.

[0068] (4.2) Model networking interface, used by users to input the topology of the brain simulation network. The topology includes the neuron model of the neurons in the neuron cluster, the number of neurons and the parameters of the neurons, and specifies the synapse model, connection rules, learning rules and communication methods.

[0069] When creating a neuron cluster, users need to specify the neuron model and number of neurons within the cluster, and set relevant neuron parameters, including resting potential, initial membrane voltage, and time constant. Users also need to set synapse models, specifically defining them as static, dynamic, or real-time synapses, excitatory or inhibitory synapses, specifying synaptic connections to and from neuron clusters, and defining connection rules. The connection rule parameters also need to be configured. Synaptic connections in the model network support slicing, allowing users to connect a portion of one neuron cluster to a portion of another, and also to a portion of the same neuron cluster itself. Users must specify the model's external input, either DC or Poisson input, and set the input parameters. Furthermore, users need to specify the communication rules, operators, and libraries for the communication method. Additionally, users can specify whether to invoke resource allocation.

[0070] (4.3) Model running interface, used by users to input training parameters or execution parameters. If the model needs to be trained, users can set the model's learning rules, training parameters, training time and other training parameters according to their needs to train the model; if the model does not need to be trained, users can set the model execution time and other execution parameters to start brain simulation directly.

[0071] The training time here refers to the number of training sessions (number of training cycles). The execution time also refers to the number of executions (number of execution cycles), which has a corresponding biological time in brain simulation. For example, one execution corresponds to a biological time of 0.1ms.

[0072] In addition, to visualize the model simulation results, the API layer also provides a result display and saving interface, through which the model simulation results can be output and displayed. Furthermore, to facilitate the application of the simulation system, this embodiment can also pre-import classic brain models previously established by relevant researchers and set up an existing model library including Microcircuit models, Macaque models, etc., so that users can directly call existing brain simulation models for training or execution through the model networking interface.

[0073] (5) Hardware Abstraction Layer (HAL), used to call the corresponding hardware kernel according to the hardware device specified in the user's requirements. The main components of the HAL include: CPU_Kernel (CPU kernel), GPU_Kernel (GPU kernel), BCU_Kernel (Neuro-inspired chip kernel), and IR (Intermediate Representation), which corresponds to the hardware device resources of the hardware device layer.

[0074] The Hardware Abstraction Layer (IR) calls different kernels for model creation and simulation based on the user-specified hardware device type. Furthermore, the IR framework supports extensions for different types of hardware, generating IR files to save the user-built network, facilitating model creation and simulation on various hardware types. IR is a hardware-independent intermediate representation; if hardware extension is needed, other hardware can simply parse the IR.

[0075] (6) Network abstraction layer, which mainly includes device management module, model parameter / variable management module, resource allocation module, model building module, executor, trainer, and plotting library.

[0076] (6.1) Device Management Module: Based on the hardware device type and number specified by the user in the API layer device specification, complete the initialization of the hardware devices and read the hardware device storage space.

[0077] (6.2) Model Parameter / Variable Management Module: This module records and saves the topology and input parameters of the user-defined brain simulation network in the API layer model networking interface. This module records and saves the parameters of each network but does not actually create the brain simulation network on the hardware. Network creation is very time-consuming; this approach avoids wasting resources by creating the brain simulation network on the hardware first, then allocating resources, and then creating it again after resource allocation. It also facilitates the transfer of network parameters to the resource allocation module, ensuring that resource allocation is completed before the brain simulation network is created on the hardware.

[0078] (6.3) Resource allocation module: Runs resource allocation algorithms and resource scheduling to allocate resources and map neuron clusters based on the information of specified hardware devices and the topology of the brain simulation network.

[0079] The resource allocation algorithm, based on the user-defined topology of the brain simulation network and the device's storage space, distributes tightly connected clusters of neurons to the same hardware device. This reduces communication between hardware devices, minimizes the overhead of cross-device synaptic connections, and ensures load balancing across all hardware devices, thereby enabling faster and larger-scale brain simulation. The resource allocation algorithm used in this embodiment is an existing method, such as the one mentioned in Chinese Patent Application No. CN2022116912007.

[0080] After running the resource allocation algorithm, neuron clusters are assigned to user-specified hardware devices. During resource scheduling, the process ID of the allocated hardware device is specified for each neuron cluster, mapping the cluster to the corresponding device, allowing the clusters to be created and simulated on the designated hardware. Furthermore, surrogate neurons are established for neurons connected by synapses across hardware devices, facilitating pulse transmission across devices during simulation. The resource scheduling serves two main purposes: firstly, it facilitates system support for computer clusters (multiple hardware devices performing brain simulation simultaneously); secondly, it supports the creation of specific neuron clusters on specific devices, enabling the actual creation of the brain simulation network based on the results of the resource allocation algorithm.

[0081] (6.4) Model Building Module: Based on the neuron model, synapse model, connection rules, learning rules, and communication method type specified in the user requirements, a brain simulation network is created on the corresponding hardware device. This embodiment separates model parameter / variable management and model building to a certain extent, facilitating the actual creation of the brain simulation network on the hardware device after resource allocation is completed.

[0082] When actually creating a brain simulation network, if the user does not invoke resource allocation, the network is actually created on the user-specified hardware device according to the network parameters saved in the model parameter / variable management module, using a polling method; if the user invokes resource allocation, the network is actually created on the user-specified device according to the result of resource allocation and the network parameters saved in the model parameter / variable management module.

[0083] In the actual creation of the brain simulation network, all devices create neuron clusters in parallel. For any hardware device 'a', assuming it has k neuron clusters, k threads are used to create a matrix of k neuron clusters. The neuron cluster matrix is ​​a pi*qi two-dimensional matrix, where pi represents the number of neurons in the i-th neuron cluster, and qi represents the number of parameters in each neuron. pi*qi threads are used to initialize the matrix values. Furthermore, all hardware devices create synaptic connections in parallel. For any hardware device 'a', the total number of synapses 's' to be created is determined according to the connection rules and parameters. s threads are used to complete the synapse creation, and a synaptic connection matrix is ​​generated based on the synapses. This embodiment uses multi-threaded parallelism to quickly complete model construction, completing the actual creation of the brain simulation network on the hardware devices. The system fully utilizes parallelism, simultaneously enabling multiple processes and threads to accelerate the brain simulation speed.

[0084] (6.5) Actuator: Relying on the brain simulation network that has been actually created, the brain simulation starts according to the execution time set by the user. The number of processes of the hardware device specified by the user are activated. All hardware devices perform brain simulation in parallel. For any hardware device a, the total number of threads of the total number of neurons of the hardware device are activated to update the neuron parameters. After updating the neuron parameters, it is determined whether the neuron fires a pulse. For all neurons that fire pulses, the synaptic connection matrix is ​​searched to determine the neurons to which the synapse is connected. The synapse transmits the pulse fired by the neuron. The brain simulation is performed in a loop.

[0085] (6.6) Trainer: Trains the brain simulation network according to the learning rules, training parameters and training time selected by the user, and updates the synaptic weights.

[0086] (6.7) Plotting library: used to plot pulse firing diagrams and / or membrane voltage diagrams based on the training or execution results of the brain simulation network, and supports outputting the pulse firing diagrams and / or membrane voltage diagrams through the result display and saving interface in the API interface, so that the simulation system of this embodiment can send the training or execution results to the web page in real time and display the simulation status on the web page.

[0087] To further illustrate the advantages of the simulation system that supports rapid large-scale brain simulation provided by the present invention, a specific example is given below.

[0088] The established simulation system was used to perform a large-scale brain simulation of 910 million units on a computer cluster with 22 hardware devices (NVIDIA A100), simulating four seconds of biological time. The information for each layer of the simulation system was set as follows:

[0089] Hardware device layer: The hardware device consists of 22 NVIDIA A100 GPUs.

[0090] Data communication layer: The communication rule is Point_To_Point; the communication operator is sparse coding; the communication library is the MPI library.

[0091] Operational abstraction layer: The neuron model is the LIF neuron model; the synapse model is the Static_synapse static synapse; the connection rule is the Fixed_PostNum connection.

[0092] API Layer: Device specification interface, specifying the hardware device as GPU, with a limit of 22 devices; Model networking interface, creating 20,000 neuron clusters, using LIF neuron models, and setting relevant LIF neuron parameters. Establishing connections between neuron clusters using the Fixed_PostNum rule, Static_synapse synapse model, setting relevant parameters, and configuring resource allocation; Model execution interface, where the model does not require training, setting the execution time to 4 seconds; Result display and saving interface, saving the spike firing data and spike firing map of the specified neuron clusters.

[0093] Hardware Abstraction Layer: Calls the GPU_Kernel kernel.

[0094] Network Abstraction Layer: Device Management Module: Initializes 22 NVIDIA A100 GPUs based on user-specified hardware devices and reads device storage space information; Model Parameter / Variable Management Module: Records, saves, and manages the user's brain simulation network; Resource Allocation Algorithm: Allocates resources based on device storage space information and brain simulation network information to obtain resource allocation results; Resource Scheduling: Maps neuron clusters to corresponding hardware devices based on resource allocation results; Model Building Module: Actually creates the brain simulation network on the hardware device; Executor: Enables multiple processes and threads to start brain simulation; Graphics Library: Draws pulse firing diagrams.

[0095] The pulse emission diagram output by the simulation system in the experiment is as follows: Figure 2 As shown. According to Figure 2 As can be seen, relying on the designed simulation system, large-scale brain simulations of 910 million units can be performed using 22 NVIDIA A100 GPUs, with a four-second biological simulation time of only 360.692 seconds. This demonstrates that the simulation system designed in this invention can effectively support rapid, large-scale brain simulations.

[0096] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A simulation system supporting rapid large-scale brain simulation, characterized in that, The simulation system supporting rapid large-scale brain simulation comprises a hardware device layer, a data communication layer, an operation abstraction layer, an API layer, a hardware abstraction layer, and a network abstraction layer, wherein: The hardware device layer is used to provide multiple hardware device resources; The data communication layer is used to provide multiple types of communication methods between the computing nodes of the brain simulation network; The operational abstraction layer is used to provide multiple types of neuron models, synapse models, connection rules, and learning rules; The API layer is used to provide predefined API interfaces to receive user requests. The hardware abstraction layer is used to call the corresponding hardware kernel according to the hardware device specified in the user requirements; The network abstraction layer is used to first record the topology of the brain simulation network provided in the user's requirements, and then perform resource allocation and neuron cluster mapping based on the information of the specified hardware device and the topology of the brain simulation network. Next, based on the neuron model, synapse model, connection rules, learning rules, and communication method type specified in the user's requirements, it creates the brain simulation network on the corresponding hardware device. Finally, it trains or executes the brain simulation network on the specified hardware device according to the user's requirements. The network abstraction layer is also used to initialize the specified hardware device according to the type and number of hardware devices specified in the user's requirements, and read the storage space of each hardware device. The step of allocating resources and mapping neuron clusters based on the information of the specified hardware device and the topology of the brain simulation network includes: Based on the storage space of each hardware device and the topology of the brain simulation network, tightly connected clusters of neurons in the brain simulation network are allocated to the same hardware device to complete resource allocation. Based on resource allocation, a process ID is assigned to each neuron cluster, the neuron cluster is mapped to the specified hardware device, and proxy neurons are established for neurons connected by synapses across hardware devices.

2. The simulation system supporting rapid large-scale brain simulation as described in claim 1, characterized in that, The hardware device resources provided by the hardware device layer include: central processing unit (CPU), graphics processing unit (GPU), and brain-like computing unit (BCU) type hardware devices.

3. The simulation system supporting rapid large-scale brain simulation as described in claim 1, characterized in that, The communication method provided by the data communication layer is determined by communication rules, communication operators, and communication libraries.

4. The simulation system supporting rapid large-scale brain simulation as described in claim 3, characterized in that, The types of communication rules include All_Reduce, Broadcast, Reduce, All_Gather, Reduce_Scatter, All_To_All, and Point_To_Point; The communication operator is used to encode the pulse information between computing nodes. The encoding methods are divided into dense encoding and sparse encoding. The communication library supports both the MPI and NCCL communication libraries.

5. The simulation system supporting rapid large-scale brain simulation as described in claim 1, characterized in that, The types of neuron models include IF neuron models, LIF neuron models, HH neuron models, and IZH neuron models; The types of synaptic models include Static_synapse, Dynamic_synapse, and RealTime_synapse. The connection rules include One_To_One connection, All_To_All connection, Fixed_Prob connection, Fixed_PreNum connection, Fixed_PostNum connection, and Fixed_Total_Number connection; The learning rule is the STDP learning rule.

6. The simulation system supporting rapid large-scale brain simulation as described in claim 1, characterized in that, The API interfaces include device-specific interfaces, model networking interfaces, and model operation interfaces; The device-specified interface is used by the user to specify the type and quantity of hardware devices. The model networking interface is used for users to input the topology of the brain simulation network. The topology includes the neuron model of neurons in the neuron cluster, the number of neurons and the parameters of the neurons, and specifies the synapse model, connection rules and communication method type. The model operation interface is used for users to input training parameters or execution parameters, and the training parameters include learning rules.

7. The simulation system supporting rapid large-scale brain simulation as described in claim 1, characterized in that, The creation of the brain simulation network on the corresponding hardware device includes: If the user request does not call resource allocation, the brain simulation network will be created on the specified hardware device according to the recorded topology of the brain simulation network in a round-robin manner; if the user request calls resource allocation, the brain simulation network will be created on the specified hardware device according to the resource allocation and neuron cluster mapping, based on the recorded topology of the brain simulation network.

8. The simulation system supporting rapid large-scale brain simulation as described in claim 1, characterized in that, When creating a brain simulation network on the corresponding hardware device, all hardware devices create neuron clusters and synaptic connections in parallel.

9. The simulation system supporting rapid large-scale brain simulation as described in claim 1, characterized in that, The network abstraction layer is also used to draw pulse firing diagrams and / or membrane voltage diagrams based on the training or execution results of the brain simulation network, and output the pulse firing diagrams and / or membrane voltage diagrams through the API interface.

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