A data reading circuit

Abstract

The present application provides a data reading circuit, including: a data conversion circuit, including a first parallel-to-serial circuit and a command control circuit, the first parallel-to-serial circuit is connected to a storage array to read the parallel data of the storage array; the command control circuit generates control signals with different trigger timings to the first parallel-to-serial circuit based on the control of a read command, processes the parallel data of the storage array, and the first parallel-to-serial circuit outputs the parallel data of the storage array serially in sequence within one timing cycle with reference to the timing of the control signal; a data selection circuit to control the output order of the serial data; a second parallel-to-serial circuit, which receives the serial data output by the data selection circuit and outputs the serial data after compressing it into a single data bit. The present application converts the data from parallel to serial through a parallel-to-serial circuit and compresses the serial data into a single data bit, reducing the use of half of the data lines.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a data reading circuit. Background Art

[0002] The data reading process of a dynamic random access memory (DRAM) chip involves multiple stages, including command transmission and decoding, row activation and column selection, data sensing and output, as well as data transfer and precharging. In a single DRAM chip, the width of the data bus is usually 16 bits, and multiple data bits can be transmitted simultaneously. The host sends a specific row address to the double data rate synchronous dynamic random access memory (DDR) through the address line. The row decoder inside the DDR memory decodes this address, and then all the memory cells in this row will be used for subsequent read and write operations. Immediately after row activation, the host sends a column address to the DDR memory. The DDR memory can transfer data twice within one clock cycle, doubling the data transfer rate compared to traditional single-data memories. Similar to the row address, the selection of the column address is also decoded by an internal decoder to precisely select a specific column. The transmission of the column address is accompanied by a read command, indicating that the memory starts to read data. As the column address is continuously switched, different data in the same row can be selected for reading.

[0003] Since the last 3 bits of the address signal in this column address-based data selection circuit decode 8-bit data, when selecting 1 data line for signal output, the matching difficulty of the signal and the circuit area in the chip need to be considered. Summary of the Invention

[0004] The present application provides a data reading circuit and method. The data is converted from parallel to serial through a first parallel-to-serial conversion circuit, and the serial data is compressed into a single-bit data through a second parallel-to-serial conversion circuit, reducing the use of half of the data lines and greatly reducing the circuit design area. At the same time, the column address-based data selection circuit makes data reading simpler and faster, greatly improving the working efficiency.

[0005] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0006] To achieve one or part or all of the above objects or other objects, the present invention provides a data reading circuit.

[0007] A data reading circuit includes:

[0008] A data conversion circuit, including a first parallel-to-serial circuit and a command control circuit. The first parallel-to-serial circuit is connected to a storage array to read the parallel data of the storage array. The command control circuit, based on the control of a read command, generates control signals with different trigger timings to the first parallel-to-serial circuit to process the parallel data of the storage array. The first parallel-to-serial circuit, referring to the timing of the control signals, outputs the parallel data of the storage array as serial data in sequence within one timing cycle.

[0009] A data selection circuit controls the output order of the serial data.

[0010] A second parallel-to-serial circuit receives the serial data output by the data selection circuit, compresses the serial data into a single data bit, and then outputs it.

[0011] Outputting the parallel data of the storage array as serial data in sequence within one timing cycle includes:

[0012] Grouping the parallel data input to the storage array and inputting it to the first parallel-to-serial circuit. The parallel data within each group is output in sequence according to the timing of the control signals to form serial data.

[0013] The command control circuit includes a read command circuit that outputs an input external read command as a read signal and multiple read commands with different trigger timings.

[0014] And a control signal generation circuit. An external address signal is input to an address signal circuit to generate an address signal 2. The address signal 2 and the read signal are input to the control signal generation circuit to generate multiple pairs of signals with the same trigger timing. Each pair of signals within each group has opposite trigger timings.

[0015] Each pair of signals within each group is respectively combined with two read commands to generate multiple control signals.

[0016] The control signal generation circuit generates two groups of pairs of signals with the same trigger timing.

[0017] The first parallel-to-serial circuit includes a logic selection circuit and a CMOS circuit. The logic selection circuits are grouped in pairs, and multiple groups are set according to the number of parallel data of the storage array.

[0018] The output terminals of two groups of logic selection circuits are respectively connected to the PMOS gate and the NMOS gate in a CMOS circuit. Each group of logic selection circuits within the two groups of logic selection circuits has the same input storage array data and control signals.

[0019] The stored array data input in each CMOS circuit is processed by the logic selection circuit and the CMOS circuit, and is alternately output according to the trigger start times of multiple control signals.

[0020] The number of the control signals is two.

[0021] The first parallel-to-serial circuit further includes a plurality of buffer units. The buffer units refer to the timing of the control signals and cache the serial data output by the parallel-to-serial circuit when the control signals end triggering.

[0022] The number of the buffer units is the same as the number of the first parallel-to-serial circuits.

[0023] The data selection circuit includes

[0024] a decoding circuit. An external address signal is input to the address signal circuit to generate an address signal 0 and an address signal 1, and the address signal 0 and the address signal 1 generate a plurality of decoding signals through the decoding circuit;

[0025] and a control circuit. Four registers of the control circuit form a group, and multiple groups are set according to the number of the serial data; the input ends of each group of registers are connected to the serial data in different orders, and the clock ends are connected to different decoding signals, and the output order of the serial data is determined according to the corresponding decoding signals.

[0026] The decoding circuit generates four decoding signals.

[0027] The second parallel-to-serial circuit includes

[0028] a clock misalignment circuit, which caches the serial data output in sequence by the data selection circuit in response to read commands with different trigger timings;

[0029] The clock misalignment circuit is provided with a plurality of clock misalignment units according to the number of the serial data. The clock misalignment units include N cascaded registers; different clock misalignment units are relatively staggered by half a clock cycle according to the corresponding input serial data, and the serial data output in sequence is combined into rising-edge data and falling-edge data;

[0030] and a data compression circuit, which compresses the rising-edge data and the falling-edge data into single-bit data in response to a clock signal and then outputs the data.

[0031] Compared with the prior art, the beneficial effects of the present invention mainly include:

[0032] The first parallel-to-serial circuit of the present application processes the parallel data of the storage array according to control signals with different trigger timings generated by the command control circuit. Referring to the timing of the control signals, the parallel data is converted into serial data and output to the data selection circuit; the second parallel-to-serial circuit receives the serial data in different orders output by the data selection circuit, compresses it into data with a single data bit, and then outputs it, reducing the use of half of the data lines and greatly reducing the design area of the circuit.

[0033] To make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0035] Figure 1 Schematic diagram of a data reading circuit module provided by an embodiment of the present application.

[0036] Figure 2 Schematic diagram of a data reading circuit provided by an embodiment of the present application.

[0037] Figure 3 Schematic diagram of a control signal generation circuit provided by an embodiment of the present application.

[0038] Figure 4 Schematic diagram of the first parallel-to-serial circuit provided by an embodiment of the present application Figure 1 。

[0039] Figure 5 Schematic diagram of the first parallel-to-serial circuit provided by an embodiment of the present application Figure 2 。

[0040] Figure 6 Schematic diagram of a decoding circuit provided by an embodiment of the present application.

[0041] Figure 7 Schematic diagram of a control circuit provided by an embodiment of the present application.

[0042] Figure 8 Schematic diagram of the correspondence between decoding signals provided by an embodiment of the present application.

[0043] Figure 9 Timing provided by an embodiment of the present application Figure 1 。

[0044] Figure 10The timing provided by the embodiments of the present application Figure 2 。 Detailed implementation manners

[0045] Regarding the foregoing and other technical contents, features and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the accompanying drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or rear, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0046] The present application provides a data reading circuit and method, which convert data from parallel to serial through a first parallel-to-serial conversion circuit, and compress the serial data into data of a single data bit through a second parallel-to-serial conversion circuit, reducing the use of half of the data lines and greatly reducing the design area of the circuit; at the same time, the data selection circuit based on the column address makes data reading simpler and faster, greatly improving the working efficiency.

[0047] The following will elaborate on the embodiments of the present application in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are provided for the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0048] Figure 1 Shown is a schematic diagram of a data reading circuit module provided by the embodiments of the present application.

[0049] As Figure 1 shown, a data reading circuit includes: a data conversion circuit, a data selection circuit, and a second parallel-to-serial conversion circuit;

[0050] Specifically, as Figure 2 shown,

[0051] The data conversion circuit includes a first parallel-to-serial conversion circuit and a command control circuit;

[0052] The first parallel-to-serial conversion circuit is connected to the storage array to read the parallel data of the storage array;

[0053] The command control circuit generates control signals with different trigger timings to the first parallel-to-serial conversion circuit based on the control of the read command;

[0054] The first parallel-to-serial conversion circuit processes the parallel data of the storage array, and according to the timing of the control signal, outputs the parallel data of the storage array as serial data in sequence within one timing cycle;

[0055] The data selection circuit controls the output order of the serial data;

[0056] The second parallel-to-serial circuit receives the serial data output by the data selection circuit, compresses the serial data into a single data bit, and then outputs it.

[0057] Specifically, the command control circuit includes a read command circuit that outputs an input external read command as a read signal and multiple read commands with different trigger timings.

[0058] The external address signal is input to the address signal circuit and generates address signal 2. Address signal 2 and the read signal are input to the control signal generation circuit.

[0059] As Figure 3 shown, the control signal generation circuit generates two pairs of signals with the same trigger timing. Signal A and signal B are a pair of signals, and signal C and signal D are a pair of signals. The pair of signals within each group have opposite trigger timings; the pair of signals within each group are respectively combined with read command 0 and read command 1 to generate control signal 0 and control signal 1.

[0060] Figure 9 shown is the timing provided by the embodiment of the present application Figure 1 .

[0061] As Figure 9 shown, when address signal 2 is low, with the read signal as the clock signal, after passing through two registers, the state of signal A is low, the state of signal B is high, the state of signal C is low, and the state of signal D is high. These four signals and read command <1:0> obtain control signal <1:0> through combinational logic. The pulse signal of control signal 0 comes first, and the pulse signal of control signal 1 comes later.

[0062] Figure 10 shown is the timing provided by the embodiment of the present application Figure 2 .

[0063] As Figure 10 shown, when address signal 2 is high, with the read signal as the clock signal, after passing through two registers, the state of signal A is high, the state of signal B is low, the state of signal C is high, and the state of signal D is low. These four signals and read command <1:0> obtain read control signal <1:0> through combinational logic. The pulse signal of control signal 0 comes later, and the pulse signal of control signal 1 comes first.

[0064] As Figure 4 shown, the first parallel-to-serial circuit includes a logic selection circuit and a CMOS circuit. Two logic selection circuits are in a group, and multiple groups are set according to the number of parallel data in the storage array.

[0065] The output terminals of two groups of logic selection circuits are respectively connected to the PMOS gate and the NMOS gate in a CMOS circuit. Each group of logic selection circuits in the two groups of logic selection circuits has the same input storage array data and control signals;

[0066] The input storage array data in each CMOS circuit is processed by the logic selection circuit and the CMOS circuit, and is alternately output according to the trigger start times of control signal 0 and control signal 1;

[0067] In addition, the first parallel-to-serial circuit further includes a plurality of buffer units. The buffer units refer to the timing of the control signals and cache the serial data output by the parallel-to-serial circuit when the triggering of control signal 0 and control signal 1 ends; the number of buffer units is the same as the number of the first parallel-to-serial circuits.

[0068] As Figure 5 shown, after the parallel data of the storage array is grouped and input into the first parallel-to-serial circuit, the parallel data within each group is output in sequence according to the timing of control signal 0 and control signal 1 to form serial data; the data on 8 data lines becomes 4 data lines after parallel-to-serial conversion for output. There are two bits of data on each data line. The control signal 0 and control signal 1 generated according to the state of address signal 2 determine whether to output the first four bits or the last four bits of the data first; that is, data 0 corresponds to data 4, data 1 corresponds to data 5, data 2 corresponds to data 6, and data 3 corresponds to data 7; if the first four bits are output, 0 is output first, and the output data combination can only be 0, 1, 2, 3; if the last four bits are output, 4 is output first, and the output data combination can only be 4, 5, 6, 7.

[0069] As Figure 6 shown, after the external address signal is input to the address signal circuit to generate address signal 0 and address signal 1, address signal 0 and address signal 1 generate four decoding signals through the decoding circuit, namely decoding 0, decoding 1, decoding 2, and decoding 3.

[0070] As Figure 7 shown, the control circuit has 4 registers in a group, and multiple groups are set according to the number of serial data; the input terminals of each group of registers are connected to the serial data in different orders, and the clock terminals are connected to different decoding signals, and the output order of the serial data is determined according to the corresponding decoding signals;

[0071] Specifically, determining which bit of data is preferentially output through the decoding of address signal <1:0> includes:

[0072] The 4 data lines of the serial data are connected to the control circuit in a specific order. Which data is preferentially output is determined by the decoding signal of address signal <1:0>. The corresponding table of the decoding signals is as Figure 8 shown;

[0073] For example, when the decoded signal is 0, the order of the output serial signals is 0123; when the decoded signal is 1, the order of the output serial signals is 1230; when the decoded signal is 2, the order of the output serial signals is 2301; when the decoded signal is 3, the order of the output serial signals is 3012.

[0074] As Figure 1 shown, the second parallel-to-serial circuit includes:

[0075] The clock misalignment circuit is provided with a plurality of clock misalignment units according to the number of serial data. Each clock misalignment unit includes N cascaded registers;

[0076] The clock misalignment circuit caches the serial data sequentially output by the data selection circuit in response to read commands with different trigger timings, and combines the cached data into rising-edge data and falling-edge data; each group of data contains two different clock misalignment units. The two clock misalignment units are relatively staggered by half a clock cycle according to the corresponding input serial data, and cache and combine the sequentially output serial data;

[0077] Specifically, serial data 1 and serial data 3 are a group of falling-edge data. The clock misalignment unit corresponding to serial data 3 has one more register than the clock misalignment unit corresponding to serial data 1. Thus, the clock misalignment unit corresponding to serial data 1 is relatively staggered by half a clock cycle. The clock misalignment unit corresponding to serial data 3 has three registers, and the clock misalignment unit corresponding to serial data 1 has two registers;

[0078] Serial data 0 and serial data 2 are a group of rising-edge data. The clock misalignment unit corresponding to serial data 2 has one more register than the clock misalignment unit corresponding to serial data 0. Thus, the clock misalignment unit corresponding to serial data 0 is relatively staggered by half a clock cycle. The clock misalignment unit corresponding to serial data 0 has one register, and the clock misalignment unit corresponding to serial data 2 has two registers.

[0079] It further includes a data compression circuit:

[0080] The falling-edge data of the data compression circuit is controlled by the #CLK signal, and the rising-edge data is controlled by the CLK signal;

[0081] The data compression circuit compresses the rising-edge data and the falling-edge data into single-bit data in response to the clock signal and then outputs it.

[0082] The first parallel-to-serial circuit of the present application processes the parallel data of the storage array according to control signals with different trigger timings generated by the command control circuit, and converts the parallel data into serial data for output to the data selection circuit with reference to the timing of the control signals; the second parallel-to-serial circuit receives the serial data in different orders output by the data selection circuit, compresses them into data with a single data bit and then outputs them, reducing the use of half of the data lines and greatly reducing the design area of the circuit.

[0083] Some common English nouns or letters used in the present invention for the convenience of clear description are only for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0084] It should also be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A data reading circuit, characterized in that: include: The data conversion circuit includes a first parallel-to-serial circuit and a command control circuit, wherein the first parallel-to-serial circuit is connected to a storage array and reads parallel data of the storage array; the command control circuit generates control signals with different trigger timings to the first parallel-to-serial circuit based on the control of the read command, and processes the parallel data of the storage array; the first parallel-to-serial circuit refers to the timing of the control signal and outputs the parallel data of the storage array as serial data in sequence within a timing cycle; A data selection circuit, controlling the output sequence of the serial data; A second parallel-to-serial circuit receives the serial data output by the data selection circuit, compresses the serial data into data of a single data bit, and then outputs the data; The command control circuit includes a read command circuit that outputs an input external read command as a read signal and a plurality of read commands with different trigger timings; and a control signal generating circuit, wherein an external address signal is input to the address signal circuit and generates an address signal 2, and the address signal 2 and the read signal are input to the control signal generating circuit to generate a plurality of pairs of signals having the same trigger timing, wherein the pairs of signals in each group have opposite trigger timings; The pair of signals in each group are respectively combined with two read commands to generate a plurality of control signals; The first parallel-to-serial circuit includes a logic selection circuit and a CMOS circuit, wherein two logic selection circuits form a group, and multiple groups are provided according to the number of parallel data in the storage array; The output ends of the two groups of logic selection circuits are respectively connected to a PMOS gate and an NMOS gate in a CMOS circuit, and each group of logic selection circuits in the two groups of logic selection circuits has the same input storage array data and control signal; The storage array data input into each CMOS circuit is processed by the logic selection circuit and the CMOS circuit, and is output alternately according to the trigger start time of multiple control signals.

2. A data reading circuit according to claim 1, characterized in that: Outputting the parallel data of the storage array as serial data in sequence within a timing cycle includes: The parallel data input into the storage array are grouped and input into the first parallel-to-serial circuit, and the parallel data in each group are output in sequence according to the timing of the control signal to form serial data.

3. The data reading circuit according to claim 1, characterized in that: The control signal generating circuit generates two sets of pair signals with the same trigger timing.

4. The data reading circuit according to claim 1, characterized in that: The number of the control signals is two.

5. The data reading circuit according to claim 1, characterized in that: The first parallel-to-series circuit further includes a plurality of cache units, which cache the serial data output by the parallel-to-series circuit with reference to the timing of the control signal when the control signal ends triggering; The number of the cache units is the same as the number of the first parallel-to-series circuits.

6. The data reading circuit according to claim 1, characterized in that: The data selection circuit comprises: A decoding circuit, an external address signal is input to the address signal circuit to generate address signal 0 and address signal 1, and the address signal 0 and address signal 1 are passed through the decoding circuit to generate a plurality of decoding signals; And a control circuit, wherein four registers form a group, and multiple groups are set according to the number of serial data; the input end of each group of registers is connected to serial data of different orders, and the clock end is connected to different decoding signals, and the output order of the serial data is determined according to the corresponding decoding signals.

7. The data reading circuit according to claim 6, characterized in that: The decoding circuit generates four decoded signals.

8. The data reading circuit according to claim 1, characterized in that: The second parallel-to-series circuit comprises: A clock misalignment circuit, in response to read commands with different trigger timings, caches the serial data sequentially output by the data selection circuit; The clock misalignment circuit is provided with a plurality of clock misalignment units according to the number of the serial data, and the clock misalignment units include N cascaded registers; different clock misalignment units are relatively staggered by half a clock cycle according to the corresponding input serial data, and the serial data output in sequence are merged into rising edge data and falling edge data; And a data compression circuit responds to the clock signal to compress the rising edge data and the falling edge data into data of a single data bit and then output it.

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