Read-only memory cell array and storage information reading method, system, computer device, storage medium and program product thereof

Abstract

The present invention provides a read-only memory cell array and a method, system, computer equipment, storage medium and program product for reading stored information thereof, belonging to the field of semiconductor technology. Among two adjacent switch tubes of the read-only memory cell array, the source of one of the switch tubes is electrically connected to the drain of the other switch tube; among all the switch tubes, the drain of the switch tube with an odd sequence number is electrically connected to any one of the bit lines through a through hole, and the source is electrically connected to any one of the power lines or ground lines through a through hole; each of the switch tubes is electrically connected to a word line; when a target word line is selected, the bit line electrically connected to the switch tube corresponding to the target word line outputs a number 0 or 1, and the bit line electrically connected to the switch tube not corresponding to the target word line outputs a number 1 or 0. For the same amount of stored information, the number of read-only memory cells is small, thereby reducing the area of ​​the read-only memory cell array and improving the storage density of the read-only memory cell.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a read-only memory cell array and a method, system, computer equipment, storage medium and program product thereof for reading stored information. Background Art

[0002] Mobile devices such as smartphones contain a processing chip that provides computing power. The security data of this chip is usually stored in a read-only memory (ROM) cell array. ROM has a simple structure, is easy to read, and the stored data is stable. The data will not change after power failure. It is often used to store various fixed programs and data, including the chip's security code, the processor chip's startup code, and the startup chip's configuration.

[0003] In the prior art, such as Figure 1 In the ROM cell shown, the source (or drain) of the first MOS tube is electrically connected to the bit line BL, the drain (or source) is grounded, the source and drain of the second MOS tube are electrically connected to the same bit line BL, and the source and drain of the third MOS tube are not electrically connected to any bit line; the gate of the first MOS tube is electrically connected to the first word line WL1, the gate of the second MOS tube is electrically connected to the second word line WL2, and the gate of the third MOS tube is electrically connected to the third word line WL3. When the first word line WL1 is turned on, the bit line BL outputs a low level, when the second word line WL2 is turned on, the bit line BL outputs a high level, and when the third word line WL3 is turned on, the bit line BL outputs a high level. The three storage cells can be arranged in sequence on the layout according to actual needs to meet the requirements of reading 0 / 1.

[0004] However, as processor chips become more and more complex, the size of various fixed programs and data may increase with the increase of processor chip versions. In the related art, the ROM cell array is implemented by hardware, which occupies space on the chip. Due to the limitation of process rules, the area of ​​the ROM cell array cannot be reduced in proportion to the process size, resulting in a larger storage area for unit information. Summary of the invention

[0005] The present invention provides a read-only memory cell array and a method, system, computer device, storage medium and program product for reading stored information thereof, so as to solve the problem in the related art that the area of ​​the ROM cell array cannot be reduced in proportion to the process size, resulting in a larger storage area for unit information.

[0006] In a first aspect, the present invention provides a read-only memory cell array, comprising a plurality of switch tubes electrically connected in sequence, a plurality of bit lines and at least one ground line or a power line; among two adjacent switch tubes, the source of one of the switch tubes is electrically connected to the drain of the other switch tube; among all the switch tubes, the drain of the switch tube with an odd sequence number is electrically connected to any one of the bit lines through a through hole, and the source is electrically connected to any one of the power lines or the ground line through a through hole; each of the switch tubes is electrically connected to a word line; when a target word line is selected, the bit line electrically connected to the switch tube corresponding to the target word line outputs a number 0 or 1, and the bit line electrically connected to the switch tube not corresponding to the target word line outputs a number 1 or 0.

[0007] Optionally, when the target word line is selected and each of the switch tubes is electrically connected to the ground line, the bit line electrically connected to the switch tube corresponding to the target word line outputs a digital 0, and the bit line not electrically connected to the switch tube corresponding to the target word line outputs a digital 1.

[0008] Optionally, when the target word line is selected and each of the switch tubes is electrically connected to a power line, the bit line electrically connected to the switch tube corresponding to the target word line outputs a digital 1, and the bit line not electrically connected to the switch tube corresponding to the target word line outputs a digital 0.

[0009] Optionally, all the switch tubes are P-channel metal oxide semiconductor (PMOS) transistors or N-channel metal oxide semiconductor (NMOS) transistors.

[0010] In a second aspect, the present invention provides a method for reading storage information of a read-only memory cell array as described in the first aspect, comprising:

[0011] Selecting a through hole corresponding to a target bit line;

[0012] Determine whether the through hole corresponding to the target bit line is electrically connected to the target switch tube;

[0013] If the through hole corresponding to the target bit line is electrically connected to the target switch tube, it is determined that the through hole corresponding to the target bit line outputs a digital 1 or 0;

[0014] If the through hole corresponding to the target bit line is not electrically connected to the target switch tube, it is determined that the through hole corresponding to the target bit line outputs a digital 0 or 1;

[0015] Traversing through holes corresponding to all bit lines to obtain storage information of the read-only memory cell;

[0016] All read-only memory cells are traversed to obtain storage information of the read-only memory cell array.

[0017] In a third aspect, the present invention provides a storage information reading system of a read-only memory cell array as described in the first aspect, comprising:

[0018] A selection module, used for selecting a through hole corresponding to a target bit line;

[0019] A judgment module, used to judge whether the through hole corresponding to the target bit line is electrically connected to the target switch tube;

[0020] A first determination module, configured to determine whether the through hole corresponding to the target bit line outputs a digital 1 or 0 when the judgment module determines that the through hole corresponding to the target bit line is electrically connected to the target switch tube;

[0021] A second determination module is used to determine whether the through hole corresponding to the target bit line outputs a digital 0 or 1 when the judgment module determines that the through hole corresponding to the target bit line is not electrically connected to the target switch tube;

[0022] A first traversal module is used to traverse the through holes corresponding to all bit lines to obtain storage information of the read-only memory cell;

[0023] The second traversal module is used to traverse all read-only memory cells to obtain storage information of the read-only memory cell array.

[0024] In a fourth aspect, the present invention provides a computer device comprising a processor and a memory; wherein, when the processor executes a computer program stored in the memory, the steps of the method for reading storage information of a read-only memory cell array described in the second aspect are implemented.

[0025] In a fifth aspect, the present invention provides a computer-readable storage medium for storing a computer program; when the computer program is executed by a processor, the steps of the method for reading storage information of a read-only memory cell array described in the second aspect are implemented.

[0026] In a sixth aspect, the present invention provides a computer program product, comprising computer executable instructions or a computer program, which, when executed by a processor, implements the steps of the method for reading storage information of a read-only memory cell array described in the second aspect.

[0027] The present invention provides a read-only memory cell array and a method, system, computer equipment, storage medium and program product for reading stored information thereof, wherein the read-only memory cell array includes a plurality of switch tubes electrically connected in sequence, a plurality of bit lines and at least one ground line or power line; among two adjacent switch tubes, the source of one of the switch tubes is electrically connected to the drain of the other switch tube; among all the switch tubes, the drain of the switch tube with an odd sequence number is electrically connected to any one of the bit lines through a through hole, and the source is electrically connected to any one of the power lines or ground lines through a through hole; each of the switch tubes is electrically connected to a word line; when a target word line is selected, the bit line electrically connected to the switch tube corresponding to the target word line outputs a digital 0 or 1, and the bit line electrically connected to the switch tube not corresponding to the target word line outputs a digital 1 or 0, and after traversing the bit lines and the read-only memory cells, the storage information of the read-only memory cell array is obtained. For the same amount of stored information, the present invention has a smaller number of read-only memory cells in the read-only memory cell array, thereby reducing the area of ​​the read-only memory cell array and improving the storage density of the read-only memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 It is a structural diagram of a ROM unit in the related art;

[0030] Figure 2 A schematic diagram of the structure of a read-only memory cell array provided by an embodiment of the present invention;

[0031] Figure 3 A schematic diagram of another structure of a read-only memory cell array provided by an embodiment of the present invention;

[0032] Figure 4 A schematic flow chart of a method for reading storage information of a read-only memory cell array provided in an embodiment of the present invention;

[0033] Figure 5 A schematic diagram of a structure of a read-only memory unit provided by an embodiment of the present invention;

[0034] Figure 6 A schematic diagram of another structure of a read-only memory unit provided by an embodiment of the present invention;

[0035] Figure 7 A schematic structural diagram of a storage information reading system of a read-only memory cell array provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Example 1

[0037] The present embodiment provides a read-only memory cell array, comprising a plurality of switch tubes electrically connected in sequence, a plurality of bit lines and at least one ground line or power line; among two adjacent switch tubes, the source of one switch tube is electrically connected to the drain of the other switch tube; among all switch tubes, the drain of the switch tube with an odd sequence number is electrically connected to any bit line through a through hole, and the source is electrically connected to any power line or ground line through a through hole; each switch tube is electrically connected to a word line; when a target word line is selected, the bit line electrically connected to the switch tube corresponding to the target word line outputs a digital 0 or 1, and the bit line electrically connected to the switch tube not corresponding to the target word line outputs a digital 1 or 0. In the present embodiment, only one switch tube is turned on in one cycle.

[0038] When the target word line is selected and each of the switch tubes is electrically connected to the ground line, the bit line electrically connected to the switch tube corresponding to the target word line outputs a digital 0, and the bit line not electrically connected to the switch tube corresponding to the target word line outputs a digital 1.

[0039] When the target word line is selected and each switch tube is electrically connected to the power line, the bit line electrically connected to the switch tube corresponding to the target word line outputs the number 1, and the bit line not electrically connected to the switch tube corresponding to the target word line outputs the number 0.

[0040] Exemplarily, in this embodiment, all the switch tubes are P-channel metal oxide semiconductor (PMOS) transistors or N-channel metal oxide semiconductor (NMOS) transistors.

[0041] like Figure 2As shown, this embodiment is described using four MOS transistors (the four MOS transistors are sequentially divided into MOS1, MOS2, MOS3 and MOS4), four word lines (WL1, WL2, WL3 and WL4 respectively), two bit lines (BL1 and BL2) and a ground line VSS as a read-only memory cell array. The gates of MOS1, MOS2, MOS3 and MOS4 are electrically connected to WL1, WL2, WL3 and WL4 respectively; the drain of MOS1 is electrically connected to BL1 through via00, or is electrically connected to BL2 through via20; the source of MOS1 is electrically connected to the ground line VSS through via10; the drain of MOS2 is electrically connected to the source of MOS1, and is electrically connected to the ground line VSS through via10; the source of MOS2 is electrically connected to BL1 through via01, or is electrically connected to BL2 through via21; the drain of MOS3 is electrically connected to the source of MOS2, and is electrically connected to BL1 through via01, or is electrically connected to BL2 through via21; the source of MOS3 is electrically connected to the ground line VSS through via11; the drain of MOS4 is electrically connected to the source of MOS3, and is electrically connected to the ground line VSS through via11; the source of MOS4 is electrically connected to BL1 through via02, or is electrically connected to BL2 through via22. Via via00, via via01, via via02, via via20, via via21 and via22 are respectively regarded as common node 200, common node 201, common node 202, common node 203, common node 204 and common node 205.

[0042] In this embodiment, the read-only memory cell array is programmed by arranging vias at common nodes 200-205. Taking via00 as an example, via00 makes BL1 electrically contact with common node 200. When WL1 is selected (i.e., a voltage that turns on the MOS tube is applied to the gate of MOS1), common node 200 forms a path with VSS, so that BL1 is discharged to the ground, and the voltage value of BL1 is detected as digital 0.

[0043] Continuing with the example, via00 is not selected, and via20 is selected. When WL1 is selected, common node 203 forms a path with VSS, while common node 200 does not form a path with VSS. Then the voltage value of BL1 is detected as digital 1, BL2 is discharged to the ground, and the voltage value of BL2 is detected as digital 0.

[0044] When the target word line is selected, the MOS tube corresponding to the target word line, the target bit line and the ground line form a loop, and the through hole on the target bit line in the loop outputs a digital 0 as the information stored in the read-only memory cell. The through hole on the target bit line that does not form a loop with the ground line outputs a digital 1 as the information stored in the read-only memory cell.

[0045] like Figure 3 As shown, in this embodiment, the ground line can be replaced by the power line VDD, and other settings remain unchanged. VDD can save the time of precharging the bit line. Taking the through hole via00 as an example, the through hole via00 makes BL1 electrically contact with the common node 200. When WL1 is selected (i.e., a voltage that turns on the MOS tube is applied to the gate of MOS1), the common node 200 forms a path with VDD, so that VDD charges BL1, and the voltage value of BL1 is detected as digital 1. If the through hole via00 is not selected and the through hole via20 is selected, when WL1 is selected, the common node 203 forms a path with VDD, and the common node 200 does not form a path with VDD, then the voltage value of BL1 is detected as digital 0, VDD charges BL2, and the voltage value of BL2 is detected as digital 1.

[0046] When the target word line is selected, the MOS tube corresponding to the target word line, the target bit line and the power line form a loop, and the through hole in the loop on the target bit line outputs a digital 1 as the information stored in the read-only memory cell. The through hole on the target bit line that does not form a loop with the ground line outputs a digital 0 as the information stored in the read-only memory cell.

[0047] In summary, the read-only memory cell array provided by this embodiment, in two adjacent switch tubes, the source of one of the switch tubes is electrically connected to the drain of the other switch tube; in all the switch tubes, the drain of the switch tube with an odd sequence number is electrically connected to any one of the bit lines through a through hole, and the source is electrically connected to any one of the power lines or ground lines through a through hole; each of the switch tubes is electrically connected to a word line; when the target word line is selected, the bit line electrically connected to the switch tube corresponding to the target word line outputs a digital 0 or 1, and the bit line electrically connected to the switch tube not corresponding to the target word line outputs a digital 1 or 0, and after traversing all bit lines and read-only memory cells, the storage information of the read-only memory cell array is obtained. In this implementation, programming is performed by setting the number of bit lines, the number of through holes, and the position of the through holes. For the same amount of stored information, the number of read-only memory cells in the read-only memory cell array provided by this implementation embodiment is reduced compared with the related art, thereby reducing the area of ​​the read-only memory cell array and improving the storage density of the read-only memory cell. Example 2

[0048] like Figure 4 As shown, this embodiment provides a method for reading storage information of a read-only memory cell array based on the embodiment 1, comprising:

[0049] Step 101, selecting a through hole corresponding to a target bit line.

[0050] Step 102, determining whether the through hole corresponding to the target bit line is electrically connected to the target switch tube.

[0051] Step 103: If the through hole corresponding to the target bit line is electrically connected to the target switch tube, it is determined that the through hole corresponding to the target bit line outputs a digital 1 or 0.

[0052] Step 104 : if the through hole corresponding to the target bit line is not electrically connected to the target switch tube, determine whether the through hole corresponding to the target bit line outputs a digital 0 or 1.

[0053] Step 105, traverse the through holes corresponding to all the bit lines to obtain the storage information of the read-only memory cell.

[0054] Step 106, traverse all read-only memory cells to obtain storage information of the read-only memory cell array.

[0055] In step 101-step 106, the level of the through hole reflects the voltage state of the through hole (i.e., a high level corresponds to a high voltage, and a low level corresponds to a low voltage). A given switch tube (such as the MOS tube in Example 1) can store bits by using a through hole to connect its source or drain to ground or to a power supply. For example, the through hole can connect the source or drain to ground, so that when the switch tube is turned on, it causes a low voltage (digital 0) to appear at the bit line, or the through hole is not electrically connected to the given switch tube, so that when the switch tube is turned on, a high voltage (digital 1) appears at the bit line. These through holes are placed during the manufacture of the processor chip so that the data stored by placing the through holes is considered to be read-only data after programming.

[0056] Exemplarily, the method for reading storage information of a read-only memory cell array provided in this embodiment includes:

[0057] Get the level on the target bit line when the target switch is turned on.

[0058] Determine whether the level on the target bit line is high when the target switch tube is turned on.

[0059] If it is a high level, it is determined whether the through hole corresponding to the target bit line is electrically connected to the target switch tube.

[0060] If the through hole corresponding to the target bit line is electrically connected to the target switch tube, it is determined that the through hole corresponding to the target bit line outputs a digital 1.

[0061] If the through hole corresponding to the target bit line is not electrically connected to the target switch tube, it is determined that the through hole corresponding to the target bit line outputs a digital 0.

[0062] If it is not a high level, it is determined whether the through hole corresponding to the target bit line is electrically connected to the target switch tube.

[0063] If the through hole corresponding to the target bit line is electrically connected to the target switch tube, it is determined that the through hole corresponding to the target bit line outputs a digital 0.

[0064] If the through hole corresponding to the target bit line is not electrically connected to the target switch tube, it is determined that the through hole corresponding to the target bit line outputs a digital 1.

[0065] The through holes corresponding to all the bit lines are traversed to obtain the storage information of the read-only memory cell.

[0066] like Figure 5 and Figure 6 As shown, a solid circle indicates that the bit line is electrically connected to the MOS tube, and a hollow circle indicates that the bit line is not electrically connected to the MOS tube. Figure 5 In the example, the source or drain of the MOS tube is grounded, the bit lines BL0, BL1 and BL3 are electrically connected to the MOS tube, and the bit line BL2 is not electrically connected to the MOS tube, then the storage information of the read-only memory cell is 0010; Figure 6 In the example, the source or drain of the MOS tube is connected to the power line, the bit lines BL0, BL1 and BL3 are electrically connected to the MOS tube, and the bit line BL2 is not electrically connected to the MOS tube, then the storage information of the read-only memory cell is 1101.

[0067] All read-only memory cells are traversed to obtain storage information of the read-only memory cell array. Example 3

[0068] Based on the same inventive concept as Example 2, this embodiment provides a storage information reading system based on the read-only memory cell array provided in Example 1. Since the principle of solving the problem by this system is similar to the storage information reading method provided in Example 2, the implementation of this system can refer to the implementation of the storage information reading method provided in Example 2.

[0069] like Figure 7 As shown, a storage information reading system of a read-only memory cell array comprises:

[0070] The selection module 10 is used to select a through hole corresponding to a target bit line.

[0071] The judgment module 20 is used to judge whether the through hole corresponding to the target bit line is electrically connected to the target switch tube.

[0072] The first determination module 30 is used to determine whether the through hole corresponding to the target bit line outputs a digital 1 or 0 when the judgment module determines that the through hole corresponding to the target bit line is electrically connected to the target switch tube.

[0073] The second determination module 40 is used to determine whether the through hole corresponding to the target bit line outputs a digital 0 or 1 when the judgment module determines that the through hole corresponding to the target bit line is not electrically connected to the target switch tube.

[0074] The first traversal module 50 is used to traverse the through holes corresponding to all the bit lines to obtain the storage information of the read-only memory cells.

[0075] The second traversal module 60 is used to traverse all read-only memory cells to obtain storage information of the read-only memory cell array.

[0076] For more specific working processes of the above modules, please refer to the corresponding contents disclosed in Example 2, which will not be repeated here. Example 4

[0077] This embodiment provides a computer device, including a processor and a memory; wherein the processor implements the steps of the storage information reading method described in Embodiment 2 when executing a computer program stored in the memory.

[0078] For more specific details of the above method, please refer to the corresponding contents disclosed in Example 2, which will not be repeated here. Example 5

[0079] This embodiment provides a computer-readable storage medium for storing a computer program; when the computer program is executed by a processor, the steps of the storage information reading method described in Embodiment 2 are implemented.

[0080] For more specific details of the above method, please refer to the corresponding contents disclosed in Example 2, which will not be repeated here. Example 6

[0081] This embodiment provides a computer program product, including computer executable instructions or a computer program. When the computer executable instructions or the computer program are executed by a processor, the steps of the storage information reading method described in Embodiment 2 are implemented.

[0082] For more specific details of the above method, please refer to the corresponding contents disclosed in Example 2, which will not be repeated here.

[0083] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the systems, devices, storage media, and computer program products disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0084] Those skilled in the art can clearly understand that the technology in the embodiments of the present invention can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the technical solution in the embodiments of the present invention can be essentially or partly contributed to the prior art in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present invention or certain parts of the embodiments.

[0085] In some embodiments, computer executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0086] As an example, computer-executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file storing other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0087] As an example, computer executable instructions may be deployed to be executed on one electronic device, or on multiple electronic devices located at one site, or on multiple electronic devices distributed at multiple sites and interconnected by a communication network.

[0088] The present invention has been described in detail above in conjunction with specific implementations and exemplary examples, but these descriptions cannot be understood as limiting the present invention. Those skilled in the art understand that, without departing from the spirit and scope of the present invention, a variety of equivalent substitutions, modifications or improvements may be made to the technical solution of the present invention and its implementation methods, all of which fall within the scope of the present invention. The scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A read-only memory cell array, characterized in that: The invention comprises a plurality of switch tubes, a plurality of bit lines and at least one ground line or power line which are electrically connected in sequence; among two adjacent switch tubes, the source of one of the switch tubes is electrically connected to the drain of the other switch tube; among all the switch tubes, the drain of the switch tube with an odd sequence number is electrically connected to at least one of the bit lines through a through hole, and the source is electrically connected to any power line or ground line through a through hole; each of the switch tubes is electrically connected to a word line; when a target word line is selected, the bit line electrically connected to the switch tube corresponding to the target word line outputs a digital 0 or 1, and the bit line electrically connected to the switch tube not corresponding to the target word line outputs a digital 1 or 0; When the target word line is selected and each of the switch tubes is electrically connected to the ground line, the bit line electrically connected to the switch tube corresponding to the target word line outputs a digital 0, and the bit line electrically connected to the switch tube not corresponding to the target word line outputs a digital 1; When the target word line is selected and each of the switch tubes is electrically connected to the power line, the bit line electrically connected to the switch tube corresponding to the target word line outputs a digital 1, and the bit line not electrically connected to the switch tube corresponding to the target word line outputs a digital 0.

2. The read-only memory cell array according to claim 1, wherein: All the switch tubes are P-channel metal oxide semiconductor (PMOS) transistors or N-channel metal oxide semiconductor (NMOS) transistors.

3. A method for reading storage information of a read-only memory cell array according to any one of claims 1 to 2, characterized in that: include: Selecting a through hole corresponding to a target bit line; Determine whether the through hole corresponding to the target bit line is electrically connected to the target switch tube; If the through hole corresponding to the target bit line is electrically connected to the target switch tube, it is determined that the through hole corresponding to the target bit line outputs a digital 1 or 0; If the through hole corresponding to the target bit line is not electrically connected to the target switch tube, it is determined that the through hole corresponding to the target bit line outputs a digital 0 or 1; Traversing through holes corresponding to all bit lines to obtain storage information of the read-only memory cell; All read-only memory cells are traversed to obtain storage information of the read-only memory cell array.

4. A storage information reading system of a read-only memory cell array as claimed in any one of claims 1 to 2, characterized in that: include: A selection module, used for selecting a through hole corresponding to a target bit line; A judgment module, used to judge whether the through hole corresponding to the target bit line is electrically connected to the target switch tube; A first determination module, configured to determine whether the through hole corresponding to the target bit line outputs a digital 1 or 0 when the judgment module determines that the through hole corresponding to the target bit line is electrically connected to the target switch tube; A second determination module is used to determine whether the through hole corresponding to the target bit line outputs a digital 0 or 1 when the judgment module determines that the through hole corresponding to the target bit line is not electrically connected to the target switch tube; A first traversal module is used to traverse the through holes corresponding to all bit lines to obtain storage information of the read-only memory cell; The second traversal module is used to traverse all read-only memory cells to obtain storage information of the read-only memory cell array.

5. A computer device, characterized in that: It comprises a processor and a memory; wherein, when the processor executes the computer program stored in the memory, the steps of the method for reading storage information of a read-only memory cell array as claimed in claim 3 are implemented.

6. A computer-readable storage medium, characterized in that: Used to store computer programs; when the computer programs are executed by a processor, the steps of the method for reading storage information of a read-only memory cell array as claimed in claim 3 are implemented.

7. A computer program product, characterized in that The method comprises computer executable instructions or a computer program, and when the computer executable instructions or the computer program are executed by a processor, the steps of the method for reading storage information of a read-only memory cell array as claimed in claim 3 are implemented.

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