A non-resonant all-region soft-switching DC-AC converter and its control circuit

Abstract

The present invention discloses a non-resonant full-range soft-switching DC-AC converter and its control circuit. The converter includes module A and module B with the same structure. The negative output terminals of module A and module B are connected, and the positive terminals are respectively connected to both ends of load R Ld ; Module A includes switching transistors Q 1a , Q 2a , Q 3a , Q 4a and their corresponding parasitic diodes and parasitic capacitors, main inductor L a , output filter capacitor C fa , output filter inductor L fa ; Q 1a , Q 2a conduct complementarily to form a bridge arm unit, and Q 3a , Q 4a conduct complementarily to form a bridge arm unit; Both ends of L a are connected to the midpoints of the bridge arm units formed by Q 1a , Q 2a and the midpoints of the bridge arm units formed by Q 3a , Q 4a . C fa is connected in parallel with the bridge arm unit of Q 3a , Q 4a . L fa is connected in series between C fa and Q 3a . The DC-AC conversion of the present invention has the characteristics of non-resonant full-range soft switching.

Description

Technical Field

[0001] The present invention belongs to the technical field of power converters, and particularly relates to a non-resonant all-region soft-switching DC-AC converter and its control circuit. Background Art

[0002] DC-AC converters are widely used in fields such as mobile power supplies, motor drives, and new energy power generation. With the continuous development of wide-bandgap semiconductor devices, power converters can achieve higher switching frequencies to realize higher power density and efficiency. On this basis, implementing soft-switching technology for power semiconductor devices can reduce switching losses, thereby improving the overall efficiency of the converter. At the same time, it also helps to reduce the volume of the radiator and lower electromagnetic interference.

[0003] Traditional soft-switching DC-AC converters such as Resonant DC Link Inverter and Resonant Pole Inverter are all resonant soft-switching converters. The realization of soft switching depends on the design and selection of passive devices, and factors such as parasitic parameters and temperature in the circuit have a greater impact on the operation of the converter. At the same time, during the resonance process, the voltage peak value and the effective value of the resonance current increase, the voltage stress of the switching tube increases, and the loss further increases. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a non-resonant all-region soft-switching DC-AC converter and its control circuit in view of the above-mentioned deficiencies of the prior art.

[0005] To achieve the above technical objectives, the technical solution adopted by the present invention is as follows:

[0006] A non-resonant all-region soft-switching DC-AC converter includes module A and module B. Module A and module B have the same structure, and the negative output terminals of module A and module B are connected, and the positive terminals are respectively connected to both ends of the load R Ld ; Module A includes switching tubes Q 1a , Q 2a , Q 3a , Q 4a and their corresponding parasitic diodes D 1a , D 2a , D 3a , D 4a , parasitic capacitors C 1a , C 2a , C 3a , C 4a , main inductor L a , output filter capacitor C fa , output filter inductor L fa ; Q 1a , Q 2aComplementary conduction forms a bridge arm unit, Q 3a and Q 4a Complementary conduction forms a bridge arm unit; The two ends of L a are respectively connected to the midpoint of the bridge arm unit composed of Q 1a and Q 2a and the midpoint of the bridge arm unit composed of Q 3a and Q 4a C is connected; C fa is in parallel with the bridge arm unit of Q 3a and Q 4a , and L fa is connected in series between C fa and Q 3a ; The voltage across the two ends of the bridge arm unit composed of Q 1a and Q 2a is the input voltage V in , and the voltage across the load R Ld is the output AC voltage v o .

[0007] To optimize the above technical solution, the specific measures taken also include:

[0008] The expression of the above v o is:

[0009]

[0010] Among them, the expression of the output voltage v A of module A is:

[0011]

[0012] The expression of the output voltage v B of module B is:

[0013]

[0014] V bias is the DC component, t is the time, U m is the effective value of the output voltage, and ω is the angular frequency of the output voltage.

[0015] A control circuit for a non-resonant all-region soft-switching DC-AC converter includes the control circuit modules A1, A2, and A3 of module A, the control circuit modules B1, B2, and B3 of module B, and the commutation control circuit module C; The module A1, A2, and A3 are respectively the same as the module B1, B2, and B3;

[0016] Module C uses the output current direction as the basis for power flow direction. By using comparator 9, comparator 10, CLK2a, NOT gate, delay circuit, AND gate, and RS flip-flop, it generates the strobe switch signals SW1 and SW2 for modules A1, A2, A3, B1, and B2, B3, realizing the commutation control of module A and module B; Module A1 uses a voltage regulator, comparator 1, clock signal CLK1a, and RS flip-flop 1 to generate the duty cycles of Q 1a , Q 2a , Q 3a , Q 4a ; Module A3 uses the phase shift angle generation circuit in PDCM mode, the phase shift angle calculation circuit in PCRM mode, diodes, comparator 4, and logic gate circuit to generate the falling edge signal CLK2a; Module A2 uses comparator 2, comparator 3, CLK1a, CLK2a, OR gate, and RS flip-flop to generate the turn-off signals of Q 1a , Q 2a , Q 3a , Q 4a , realizing valley current control.

[0017] In the above-mentioned module C, when the output voltage v o is in the positive half-cycle, the output current i o is positive, and the power flow direction is from the DC input terminal to the connection point A between L fa and C fa . The power flows forward. Comparator 9 outputs high. Through the subsequent NOT gate, delay circuit, and AND gate, the rising signal is extracted and AND logic operation is performed with CLK2a. When both are high, the output is high. Through the RS flip-flop, the output SW1 signal is high and the SW2 signal is low; when the output voltage v o is in the negative half-cycle, the output current i o is negative, and the power flow direction is from point A to the DC input terminal. The power flows backward. Comparator 10 outputs high. Through the subsequent NOT gate, delay circuit, and AND gate, the rising signal is extracted and AND logic operation is performed with CLK2a. When both are high, the output is high. Through the RS flip-flop, the output SW2 signal is high and the SW1 signal is low.

[0018] In the above-mentioned module A1, when the SW1 signal is high, the corresponding strobe switch closes, and the voltage regulator composed of operational amplifier EA1 takes effect. The output voltage sampling signal v oa is connected to the inverting terminal of the operational amplifier, and the given reference v refa is connected to the non-inverting terminal of the regulator. The modulation signal v errora generated by the regulator intersects with the sawtooth wave V saw through comparator 1, generating the duty cycle D 1a of Q y1a; When the SW2 signal is high, the corresponding gating switch closes, and the voltage regulator composed of operational amplifier EA2 comes into play to sample the output voltage v oa is connected to the non-inverting terminal of the regulator, and the given reference v refa is connected to the inverting terminal of the regulator. The modulation signal v errora generated by the regulator intersects with the sawtooth wave V saw through comparator 1 to generate the duty cycle D 3a of Q y3a , where CLK1a is the cycle start signal. When CLK1a arrives, Q 1a or Q 3a is turned on.

[0019] In the above-mentioned module B1, the given reference v refb is 180 degrees out of phase with the module A1v refa of module A1.

[0020] The phase-shift angle generation circuit in the above PDCM mode includes operational amplifier EA3, multiplier-division circuit, operational amplifier EA4 and peripheral circuits. The calculation formula of the phase-shift angle D θ_PDCM is as follows:

[0021] When the power flows forward:

[0022]

[0023] When the power flows backward:

[0024]

[0025] where D y1a is the duty cycle of Q 1a ;

[0026] v oa is the output voltage of module A;

[0027] D c_max is the minimum phase-shift angle that can achieve soft switching of all tubes within the full range.

[0028] The phase-shift angle calculation circuit in the above PCRM mode includes operational amplifiers EA5, EA6 and their peripheral circuits; when the power flows forward, EA5 and its peripheral circuits work, and the phase-shift angle calculation formula is:

[0029] D θ_PCRM1 (v oa ,i os )=av oa +bi os +V con1

[0030] where a and b are variables voa and i os The coefficients of, where i os is the output current sampling, i os is connected to the reverse terminal of EA5, V con1 is a fixed value;

[0031] When the power flows reversely, EA6 and its peripheral circuit work, and the calculation formula of its phase shift angle is:

[0032] D θ_PCRM2 (v oa , i os ) = cv oa + di os + V con2

[0033] Where c and d are the coefficients of variables v oa and i os , where d is negative, v oa is connected to the reverse terminal of EA6, and Vcon2 is a fixed value.

[0034] In the above-mentioned module A3, the phase shift angle amplitude signals generated in the PDCM and PCRM modes intersect through diodes, and the larger value makes the diodes conduct. The phase shift angle is generated by intersecting with the sawtooth wave through comparator 4, and the falling edge signal CLK2a is extracted through the subsequent logic gate circuit.

[0035] In the above-mentioned module A2, when the power flows forward, comparator 2 works. When the current of the main inductor L a drops below -I ZVS , a Q 3a turn-off signal is generated. The turn-off signal is OR-operated with CLK1a through an OR gate and then output to the R terminal of the RS flip-flop to ensure that no logic error occurs even if the current does not drop to -I ZVS within one cycle. At the same time, through CLK2a connected to the S terminal of the RS flip-flop, it is ensured that Q 4a is turned off when Q 3a is turned on; when the power flows reversely, comparator 3 works. When the current of the main inductor L a rises above I ZVS , a Q 1a turn-off signal is generated. The turn-off signal is OR-operated with CLK1a through an OR gate and then output to the R terminal of the RS flip-flop to ensure that no logic error occurs even if the current does not drop to -I ZVS within one cycle. At the same time, through CLK2a connected to the S terminal of the RS flip-flop, it is ensured that Q 2a is turned off when Q 1a is turned on.

[0036] The present invention has the following beneficial effects:

[0037] (1) It is possible to achieve soft switching of all switching tubes in a non-resonant manner, reduce the turn-on loss of the switching tubes, reduce the heat generation of the converter, and further improve the efficiency of the converter.

[0038] (2) The inductor current ripple is small, the value of the main power inductor is small, and the values of the output filter inductor and capacitor are small, which can further improve the power density of the converter. Description of the Drawings

[0039] Figure 1 It is the structural diagram of the single-channel four-switch Buck-Boost converter of the present invention;

[0040] Figure 2 It is the working waveform diagram of the quadrilateral current control of the FSBB converter of the present invention;

[0041] Figure 3 It is the structural diagram of the DC-AC converter of the present invention;

[0042] Figure 4 It is the output waveform diagram of the DC-AC converter of the present invention;

[0043] Figure 5 It is the control circuit block diagram of the DC-AC converter of the present invention;

[0044] Figure 6 It is the waveform of the output voltage of module A of the present invention and the output voltage and current of the entire converter;

[0045] Figure 7 It is the relationship surface between the phase shift angle at point A and the output voltage and output current in the PCRM mode when the power of the control circuit of the present invention flows forward;

[0046] Figure 8 It is the relationship surface between the phase shift angle at point A and the output voltage and output current in the PCRM mode when the power of the control circuit of the present invention flows backward. Detailed Embodiment

[0047] The following further describes the embodiments of the present invention in detail with reference to the drawings.

[0048] The power topology of the present invention is derived from a four-switch Buck-Boost converter. The structure of the single-channel four-switch Buck-Boost converter (hereinafter referred to as the FSBB converter) is as Figure 1 shown, where V in is the input voltage, V o is the output voltage, L c is the main inductor of the converter, and C o is the output filter capacitor. Q 1 , Q 2 , Q3 and Q 4 are switching transistors, D 1 , D 2 , D 3 and D 4 are the parasitic diodes of each switching transistor, C 1 , C 2 , C 3 and C 4 are the parasitic capacitors of each switching transistor.

[0049] The FSBB converter adopts quadrilateral current control, and its main working waveforms are as Figure 2 shown.

[0050] During the time period of 0 - t 1 , Q 1 , Q 4 transistors are turned on, and the voltage applied across the inductor is the input voltage V in , and the inductor current rises linearly;

[0051] At time t 1 , Q 4 is turned off, and Q 3 is turned on, ensuring that the current at point P is greater than the minimum current I ZVS for realizing soft switching, that is, the voltage across C 3 can be discharged to 0 within the dead time, thus realizing soft switching. At time t 1 - t 2 , Q 1 , Q 3 transistors are turned on, and the voltage applied across the inductor is (V in - V o ). When the input voltage is greater than the output voltage, the inductor current rises, and when the input voltage is lower than the output voltage, the inductor current drops;

[0052] At time t 2 , Q 1 is turned off, ensuring that the current at point Q is greater than I ZVS , that is, the soft switching of Q 1 transistor can be realized. During the time period of t 2 - t 3 , Q 2 , Q 3 transistors are turned on, and the voltage applied across the inductor is V o , and the inductor current drops linearly;

[0053] At time t 3 , when it is detected that the inductor current reaches - I ZVS , Q 3 is turned off, and Q 4 is turned on, that is, the soft switching of Q 4 transistor can be realized. At time t 3-t 4 Q within the time 2 and Q 4 conduct simultaneously, and the inductor current remains unchanged. When the next cycle arrives and Q 1 conducts, the current is still -I ZVS , and the soft switching of Q 1 can be achieved.

[0054] By connecting the negative output terminals of two four-switch Buck-Boost converters together, connecting the positive terminals to both ends of the load respectively, and adding filter inductors to each module, a four-switch Buck-Boost DC-AC converter can be obtained, and its structure is as Figure 3 shown. Define the left FSBB module as module A and the right FSBB module as module B respectively. Where V in is the input voltage, v o is the output AC voltage, L a is the main inductor of module A, L fa is the output filter inductor of module A, C fa is the output filter capacitor of module A. Q 1a and Q 2a and Q 3a and Q 4a are the switching tubes of module A, D 1a and D 2a and D 3a and D 4a are the parasitic diodes of each switching tube, C 1a and C 2a and C 3a and C 4a are the parasitic capacitors of each switching tube. L b is the main inductor of module B, L fb is the output filter inductor of module B, C fb is the output filter capacitor of module B. Q 1b and Q 2b and Q 3b and Q 4b are the switching tubes, D 1b and D 2b and D 3b and D 4b are the parasitic diodes of each switching tube, C 1b and C 2b and C 3b and C 4b are the parasitic capacitors of each switching tube, and R Ld is the load resistance.

[0055] When the converter is working, the total output voltage v o is composed of the output terminal voltages v A and v of the two modulesB Obtained by taking the difference. Since a single FSBB converter cannot output a negative voltage, a DC component V must be superimposed on the AC voltage bias so that the output voltage value is always positive. The output waveform of the converter is as Figure 4 shown.

[0056] Among them, the expression of the output voltage v A is:

[0057]

[0058] The expression of the output voltage v B is:

[0059]

[0060] The expression of the total output v o is:

[0061]

[0062] Next, the control circuit of the FSBB DC-AC converter will be introduced. The block diagram of its control circuit is as Figure 5 shown: Among them, the A1, A2, and A3 control modules are the control circuits of module A, the B1, B2, and B3 control modules are the control circuits of module B, and the C module is the commutation control circuit.

[0063] Next, the implementation method of the control circuit of the FSBB DC-AC converter will be introduced in detail.

[0064] (1) Commutation control C module

[0065] Due to the left-right symmetry of its structure, the FSBB converter can achieve bidirectional energy flow. Take the module A FSBB converter as an example. As Figure 6 shown, assuming that it works with a purely resistive load, when the output voltage v o is in the positive half-cycle, the output current direction is positive, and the power flow is from the DC input terminal to point A. When the output voltage v o is in the negative half-cycle, the output current direction is negative, and the power flow is from point A to the DC input terminal.

[0066] Since the control methods for different power flow directions are different, a commutation signal is required for control. The loads of the DC-AC converter are not all purely resistive. Because there is a phase difference between its output current and output voltage, the output current direction is used here as the basis for power flow. When the output current i oWhen it is positive, the output of comparator 9 is set high, and the rising signal is extracted through the subsequent NOT gate, delay circuit, and AND gate. This signal performs an AND logic operation with the clock signal CLK2a, and the output is high when both are high. Through the RS flip-flop, the SW1 signal can be made high and the SW2 signal can be made low. When the output current i o is negative, the output of comparator 10 is set high, and the subsequent circuit works in the same way as the upper circuit. Through the RS flip-flop, the SW2 signal can be made high and the SW1 signal can be made low.

[0067] (2) Voltage regulation modules A1 and B1

[0068] A1 and B1 are the voltage regulation circuits of two FSBB modules. Taking module A1 as an example, CLK1a is the start clock signal of the cycle. When the output current is in the positive half-cycle, the SW1 signal is high and the corresponding selection switch is closed. At this time, the voltage regulator composed of the upper operational amplifier EA1 comes into play, where v oa is the output voltage sampling signal, connected to the inverting terminal of the operational amplifier, and v refa is the given reference (a sine wave superimposed with a DC component), connected to the non-inverting terminal of the regulator. The modulation signal v errora generated by the regulator intersects with the sawtooth wave V saw to generate the duty cycle D 1a of Q y1a .

[0069] When the output current is in the negative half-cycle, the SW2 signal is high and the corresponding selection switch is closed. At this time, the voltage regulator composed of the lower operational amplifier EA2 comes into play. Since the power flow reverses, but still needs to control the voltage at point A as a sine wave, the regulator needs to work in reverse logic at this time, where v oa is the output voltage sampling signal, connected to the non-inverting terminal of the operational amplifier, and v refa is the given reference (a sine wave superimposed with a DC component), connected to the inverting terminal of the regulator. The modulation signal v errora generated by the regulator intersects with the sawtooth wave V saw to generate the duty cycle D 3a of Q y1a .

[0070] The working mode of module B1 is the same as above, where v refb and v refa are phase-shifted by 180 degrees.

[0071] (3) Phase-shift angle generation circuits A3 and B3

[0072] A3 and B3 are the phase-shift angle generation circuits of two FSBB modules. Taking module A3 as an example, EA3, the multiplier-division circuit, EA4, and the peripheral circuit form the phase-shift angle generation circuit in the PDCM mode.

[0073] The calculation formula for the PDCM downward phase angle is as follows:

[0074] When the power flows forward:

[0075]

[0076] When the power flows backward:

[0077]

[0078] EA5, EA6 and their peripheral circuits form a phase angle calculation circuit in the PCRM mode. When the power flows forward, EA5 and its peripheral circuits work. At this time, the output voltage at point A is an output quantity with a wide range. The relationship surface between its phase angle, output voltage and output current can be drawn as Figure 7 shown. It can be seen that it is a concave plane. Taking three points on it to form a plane as an approximate plane can simplify the control while ensuring that the actual phase angle is greater than the theoretical value, ensuring the realization of soft switching. The expression of the tangent plane is:

[0079] D θ_PCRM1 (v oa ,i os )=av oa +bi os +V con1

[0080] where a and b are the coefficients of variables v oa and i os . Among them, b is negative. Therefore, in the control circuit, i os is connected to the reverse end of EA5, and V con1 is a fixed value.

[0081] When the power flows backward, EA6 and its peripheral circuits work. The relationship surface between its phase angle, output voltage and output current can be drawn as Figure 8 shown. It can be seen that it is a concave plane. Taking 3 vertices to form a plane can obtain its approximate plane, which can simplify the control while ensuring that the actual phase angle is greater than the theoretical value, ensuring the realization of soft switching. The expression of the tangent plane is:

[0082] D θ_PCRM2 (v oa ,i os )=cv oa +di os +V con2

[0083] where c and d are the coefficients of variables voa and ios. Among them, c is negative. Therefore, in the control circuit, voa is connected to the reverse end of EA6, and Vcon2 is a fixed value.

[0084] The phase-shift angle amplitude signals generated in the PDCM and PCRM modes intersect through a diode. The larger value makes the diode conduct, and the phase-shift angle is generated by intersecting with a sawtooth wave through comparator 4. The falling-edge signal CLK2a is extracted through the subsequent logic gate circuit.

[0085] (4) Valley current control circuits A2 and B2

[0086] A2 and B2 are the valley current control circuits of two FSBB modules. Taking the A2 module as an example, when the power flows forward, comparator 2 functions. When the detected conduction current drops below -I ZVS a Q 3a turn-off signal is generated.

[0087] At the same time, the turn-off signal is OR-operated with CLK1a, which can ensure that no logic error occurs even if the current does not drop to -I within one cycle. ZVS

[0088] CLK2a is connected to the S terminal of the RS flip-flop, which can ensure that Q 4a turns off and Q 3a conducts. When the power flows reversely, comparator 3 functions. When the detected conduction current rises above I ZVS a Q 1a turn-off signal is generated, and the subsequent circuit is the same as when flowing forward.

[0089] The above is only the preferred embodiment of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the concept of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, several improvements and refinements made without departing from the principle of the present invention should be regarded as within the protection scope of the present invention.

Claims

1. A non-resonant global soft-switching DC-AC converter, characterized in that: It includes module A and module B. Module A and module B have the same structure. The negative output terminals of module A and module B are connected, and the positive output terminals are connected to the load R Ld The two ends of the module A include switch tube Q 1a , Q 2a , Q 3a , Q 4a and its corresponding parasitic diode D 1a , D 2a , D 3a , D 4a , parasitic capacitance C 1a , C 2a , C 3a , C 4a , main inductance L a , output filter capacitor C fa , output filter inductor L fa ; Switching tube Q 1a , Q 2a Complementary conduction forms a bridge arm unit, the switch tube Q 3a , Q 4a Complementary conduction, forming a bridge arm unit; the main inductor L a The two ends of the switch tube Q 1a , Q 2a The midpoint of the bridge arm unit and the switch tube Q 3a , Q 4a The midpoint connection of the bridge arm unit, the output filter capacitor C fa With the switch tube Q 3a , Q 4a The bridge arm units are connected in parallel, and the output filter inductor L fa Connected in series with the output filter capacitor C fa With the switch tube Q 3a Between; Switching tube Q 1a , Q 2a The voltage across the bridge arm unit is the input voltage V in , load R Ld The voltage across the two ends is the output AC voltage v o ; The control circuit of the non-resonant global soft-switching DC-AC converter comprises control circuit modules A1, A2, A3 of module A, control circuit modules B1, B2, B3 of module B, and commutation control circuit module C; the control circuit modules A1, A2, A3 are respectively the same as the control circuit modules B1, B2, B3; The commutation control circuit module C uses the output current direction as the basis for the power flow direction, and uses comparator 9, comparator 10, falling edge signal CLK2a, NOT gate, delay circuit, AND gate, and RS trigger to generate the selection switch signals SW1 and SW2 of the control circuit modules A1, A2, A3, B1, B2, and B3 to realize the commutation control of modules A and B; the control circuit module A1 uses the voltage regulator, comparator 1, clock signal CLK1a and RS trigger 1 to generate the switch tube Q 1a , Q 2a , Q 3a , Q 4a The control circuit module A3 uses the phase shift angle generating circuit in the PDCM mode, the phase shift angle calculating circuit in the PCRM mode, the diode, the comparator 4, and the logic gate circuit to produce the falling edge signal CLK2a; the control circuit module A2 uses the comparator 2, the comparator 3, the clock signal CLK1a, the falling edge signal CLK2a, the OR gate, and the RS trigger to generate the switch tube Q 1a , Q 2a , Q 3a , Q 4a The shutdown signal is used to realize valley current control.

2. A non-resonant global soft-switching DC-AC converter according to claim 1, characterized in that: The v o The expression is: Among them, the output voltage of module A is v A The expression is: The output voltage of module B is v B The expression is: V bias is the DC component, t is the time, U m is the effective value of the output voltage, and ω is the angular frequency of the output voltage.

3. The non-resonant global soft-switching DC-AC converter according to claim 1, characterized in that: In the module C, when the output AC voltage v o In the positive half cycle, the output current i o The direction is positive, and the power flows from the DC input to the output filter inductor L fa With the output filter capacitor C fa At the connection point A, power flows forward, the output of comparator 9 is set high, and the rising signal is extracted through the rear NOT gate, delay circuit and AND gate and the AND logic operation is performed with the falling edge signal CLK2a. When both are high at the same time, the output is high, and through the RS trigger, the output gate switch signal SW1 is high and the gate switch signal SW2 is low; when the output AC voltage v o In the negative half cycle, the output current i o The direction is negative, and the power flows from point A to the DC input terminal. The power flows negatively, and the output of comparator 10 is set high. The rising signal is extracted through the subsequent NOT gate, delay circuit and AND gate, and an AND logic operation is performed with the falling edge signal CLK2a. When both are high at the same time, the output is high. Through the RS trigger, the output selection switch signal SW2 is high and the selection switch signal SW1 is low.

4. The non-resonant global soft-switching DC-AC converter according to claim 1, characterized in that: In the control circuit module A1, when the selection switch signal SW1 is high, the corresponding selection switch is closed, the voltage regulator composed of the operational amplifier EA1 works, and the output voltage sampling signal v oa Connect to the reverse terminal of the op amp, given the reference v refa Connect to the same direction end of the regulator, the modulation signal v generated by the regulator errora Through comparator 1 and sawtooth wave V saw Intersection, generating switch tube Q 1a Duty cycle D y1a When the selection switch signal SW2 is high, the corresponding selection switch is closed, and the voltage regulator composed of the operational amplifier EA2 works to output the voltage sampling signal v oa Connect to the same direction terminal of the regulator, and give the reference v refa Connect to the reverse end of the regulator, the modulation signal v generated by the regulator errora Through comparator 1 and sawtooth wave V saw Intersection, generating switch tube Q 3a Duty cycle D y3a , where the clock signal CLK1a is the cycle start signal. When the clock signal CLK1a arrives, the switch tube Q is turned on. 1a or Q 3a .

5. The non-resonant global soft-switching DC-AC converter according to claim 4, characterized in that: The control circuit module B1 is given a reference v refb With the given reference v in the control circuit module A1 module refa The phases are staggered 180 degrees.

6. The non-resonant global soft-switching DC-AC converter according to claim 1, characterized in that: The phase shift angle generating circuit in the PDCM mode includes an operational amplifier EA3, a multiplier and divider, an operational amplifier EA4 and a peripheral circuit. θ_PDCM The calculation formula is as follows: When power flows in the forward direction: When power flows in the reverse direction: Where D y1a Q is the switch tube 1a Duty cycle; v oa is the output voltage of module A; D c_max To achieve the minimum phase shift angle for soft switching of all tubes within the full range.

7. The non-resonant global soft-switching DC-AC converter according to claim 1, characterized in that: The phase shift angle calculation circuit in the PCRM mode includes operational amplifiers EA5, EA6 and their peripheral circuits; When the power flows in the forward direction, EA5 and its peripheral circuits work, and the phase shift angle calculation formula is: D θ_PCRM1 (in oa ,i os )=av oa +bi os +V con1 Where a, b are variables v oa and i os The coefficient of os is the output current sampling, i os Connect to the reverse end of EA5, V con1 is a fixed value; When the power flows in the reverse direction, EA6 and its peripheral circuits work, and the phase shift angle calculation formula is: D θ_PCRM2 (v oa ,he os )cv oa +di os +V con2 Where c, d are variables v oa and i os The coefficient of , where d is a negative value, the variable v oa Connected to the reverse end of EA6, Vcon2 is a fixed value.

8. The non-resonant global soft-switching DC-AC converter according to claim 1, characterized in that: In the control circuit module A3, the phase shift angle amplitude signals generated in the PDCM and PCRM modes intersect through a diode, wherein the larger value causes the diode to conduct, and the phase shift angle is generated by intersecting with the sawtooth wave through the comparator 4, and the falling edge signal CLK2a is extracted through the subsequent logic gate circuit.

9. The non-resonant global soft-switching DC-AC converter according to claim 1, characterized in that: In the control circuit module A2, when the power flows in the forward direction, the comparator 2 works. a The current drops to less than -I ZVS When the switch tube Q 3a The shutdown signal is output to the R terminal of the RS trigger after being ORed with the clock signal CLK1a through the OR gate, ensuring that the current does not drop to -I within a cycle. ZVS No logic error will occur. At the same time, by connecting the falling edge signal CLK2a at the S end of the RS trigger, it is ensured that when the switch tube Q 4a When the switch is turned off, Q 3a When the power flows in the reverse direction, the comparator 3 works and the main inductor L a The current drops to greater than I ZVS When the switch tube Q 1a The shutdown signal is output to the R terminal of the RS trigger after being ORed with the clock signal CLK1a through the OR gate, ensuring that the current does not drop to -I within a cycle. ZVS No logic error will occur. At the same time, by connecting the falling edge signal CLK2a at the S end of the RS trigger, it is ensured that when the switch tube Q 2a When the switch is turned off, Q 1a On, I ZVS To achieve the minimum current value for soft switching.

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