A power-on detection circuit

Abstract

The present invention relates to the field of circuit protection technology, and specifically discloses a power-on detection circuit, including a first operational amplifier, a second trigger, a fourth field effect transistor, a fifth field effect transistor, a first resistor, a fifth resistor, a twentieth resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a third capacitor, a first connector, and a second connector; the first operational amplifier in-phase end, one end of the twentieth resistor, and the first connector end are connected, and the first operational amplifier inverting end is connected to one end of the twenty-third resistor and one end of the twenty-fourth resistor. The present invention can detect and reset the accuracy range based on the automatically constructed accuracy range, so as to prevent the logic error of the chip caused when the power supply signal is in an abnormal working state.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit protection, and in particular to a power-on detection circuit. Background Art

[0002] Some existing circuits can perform power-on detection. When the working circuit in the device obtains power supply signal feedback, it enters the reset state and stabilizes the power consumption after the power-on detection is completed. However, the circuit automatically constructs an accuracy range for detecting the power supply signal when the device is powered on and performs an accuracy range detection based on the automatically constructed accuracy range. When the power supply signal jumps and is not within the accuracy range during the power-on detection, it is impossible to keep the device in the reset state to prevent the working circuit in the device from entering the working state when the power supply signal is not within the accuracy range, causing a logical error in the chip, while limiting the self-reset of the detection circuit during this period. Summary of the invention

[0003] In view of the above technical problems, the present invention provides a power-on detection circuit, including a first operational amplifier U1, a second trigger U2, a fourth field effect transistor Q4, a fifth field effect transistor Q5, a first resistor R1, a fifth resistor R5, a twentieth resistor R20, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a third capacitor C3, a first connector P1, and a second connector P2;

[0004] The in-phase end of the first operational amplifier U1, one end of the twentieth resistor R20 and the first connector P1 are connected, the inverting end of the first operational amplifier U1 is connected to one end of the twenty-third resistor R23 and one end of the twenty-fourth resistor R24, the output end of the first operational amplifier U1 is connected to the gate of the fourth field effect transistor Q4, the gate of the fifth field effect transistor Q5, and the other end of the twenty-fourth resistor R24, the first pin of the second trigger U2, the fourth pin of the second trigger U2, one end of the first resistor R1, one end of the twenty-sixth resistor R26 and the power supply are connected, the second pin of the second trigger U2, one end of the fifth resistor R5 and the second connection The first terminal of the first resistor R1 is connected to the first electrode P2, the second trigger U2 is connected to the source of the fourth field effect transistor Q4 and one end of the twenty-second resistor R22, the fourth field effect transistor Q4 drain is connected to the drain of the fifth field effect transistor Q5, one end of the twenty-fifth resistor R25 and one end of the third capacitor C3, the source of the fifth field effect transistor Q5 is connected to the other end of the twenty-sixth resistor R26, the other end of the first resistor R1, the other end of the fifth resistor R5, the other end of the twentieth resistor R20, the other end of the twenty-second resistor R22, the other end of the twenty-third resistor R23, the other end of the twenty-fifth resistor R25, the other end of the third capacitor C3 and the ground terminal are connected.

[0005] Furthermore, it also includes a third operational amplifier U3, a first field effect transistor Q1, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, an eighteenth resistor R18, a nineteenth resistor R19, a second capacitor C2, and a first diode D1;

[0006] The in-phase end of the third operational amplifier U3 is connected to the source of the first field effect transistor Q1, one end of the fourteenth resistor R14, and one end of the second capacitor C2. The inverting end of the third operational amplifier U3 is connected to one end of the eighteenth resistor R18 and one end of the nineteenth resistor R19. The output end of the third operational amplifier U3 is connected to one end of the fifteenth resistor R15 and the anode of the first diode D1. The gate of the first field effect transistor Q1 is connected to the fifth pin of the second trigger U2. The drain of the first field effect transistor Q1 is connected to one end of the twelfth resistor R12 and one end of the thirteenth resistor R13. The cathode of the first diode D1 is connected to the third pin of the second trigger U2. The other end of the thirteenth resistor R13 and the other end of the eighteenth resistor R18 are connected to the power supply. The other end of the twelfth resistor R12, the other end of the fourteenth resistor R14, the other end of the fifteenth resistor R15, the other end of the nineteenth resistor R19, and the other end of the second capacitor C2 are connected to the ground.

[0007] Furthermore, it also includes a fourth operational amplifier U4, a fifth operational amplifier U5, a sixth operational amplifier U6, a second resistor R2, a third resistor R3, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10;

[0008] The in-phase end of the fourth operational amplifier U4, one end of the second resistor R2 and the end of the first connector P1 are connected, the inverting end of the fourth operational amplifier U4 is connected to one end of the sixth resistor R6, the output end of the fourth operational amplifier U4 is connected to the other end of the sixth resistor R6, the in-phase end of the fifth operational amplifier U5 and the in-phase end of the sixth operational amplifier U6 are connected, the inverting end of the fifth operational amplifier U5 is connected to one end of the third resistor R3 and one end of the seventh resistor R7, the output end of the fifth operational amplifier U5 is connected to the other end of the third resistor R3, the inverting end of the sixth operational amplifier U6 is connected to one end of the eighth resistor R8, the output end of the sixth operational amplifier U6 is connected to the other end of the eighth resistor R8 and one end of the ninth resistor R9, one end of the tenth resistor R10 is connected to the other end of the ninth resistor R9, the other end of the second resistor R2, the other end of the seventh resistor R7, the other end of the tenth resistor R10 and the ground are connected.

[0009] Furthermore, it also includes a seventh operational amplifier U7, an eighth operational amplifier U8, a ninth operational amplifier U9, a second field effect transistor Q2, a third field effect transistor Q3, a fourth resistor R4, and a first capacitor C1;

[0010] The in-phase end of the seventh operational amplifier U7 is connected to the end of the first connector P1, the inverting end of the seventh operational amplifier U7 is connected to one end of the fourth resistor R4, the output end of the seventh operational amplifier U7 is connected to the in-phase end of the eighth operational amplifier U8, the inverting end of the ninth operational amplifier U9, the other end of the fourth resistor R4, and one end of the first capacitor C1, the inverting end of the eighth operational amplifier U8 is connected to the output end of the fifth operational amplifier U5, the output end of the eighth operational amplifier U8 is connected to the gate of the third field effect transistor Q3, the in-phase end of the ninth operational amplifier U9 is connected to one end of the tenth resistor R10, the output end of the ninth operational amplifier U9 is connected to the gate of the second field effect transistor Q2, the drain of the second field effect transistor Q2 is connected to the drain of the third field effect transistor Q3 and the source of the first field effect transistor Q1, the source of the second field effect transistor Q2, the source of the third field effect transistor Q3, the other end of the first capacitor C1 and the ground end are connected.

[0011] Furthermore, a twenty-first resistor R21 is included;

[0012] One end of the twenty-first resistor R21 is connected to the gate of the fourth field effect transistor Q4, and the other end of the twenty-first resistor R21 is connected to the ground.

[0013] Furthermore, it also includes an eleventh resistor R11;

[0014] One end of the eleventh resistor R11 is connected to the gate of the first field effect transistor Q1 , and the other end of the eleventh resistor R11 is connected to the ground.

[0015] Furthermore, it also includes a sixteenth resistor R16;

[0016] One end of the sixteenth resistor R16 is connected to the gate of the third field effect transistor Q3, and the other end of the sixteenth resistor R16 is connected to the ground.

[0017] Furthermore, it also includes a seventeenth resistor R17;

[0018] One end of the seventeenth resistor R17 is connected to the gate of the second field effect transistor Q2, and the other end of the seventeenth resistor R17 is connected to the ground.

[0019] The beneficial effects of the present invention compared with the prior art are:

[0020] The present invention can automatically construct an accuracy range for detecting a power supply signal when the device is powered on and perform accuracy range detection based on the automatically constructed accuracy range. When the power supply signal jumps outside the accuracy range during power-on detection, the device can be continuously in a reset state to prevent the working circuit in the device from entering a working state when the power supply signal is not within the accuracy range, causing a logic error of the chip, while limiting the self-reset of the detection circuit during this period. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A schematic diagram of the circuit structure provided by the present invention. DETAILED DESCRIPTION

[0023] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0024] refer to Figure 1 The present invention discloses a power-on detection circuit, including a first operational amplifier U1, a second trigger U2, a fourth field effect transistor Q4, a fifth field effect transistor Q5, a first resistor R1, a fifth resistor R5, a twentieth resistor R20, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a third capacitor C3, a first connector P1, and a second connector P2;

[0025] The in-phase end of the first operational amplifier U1, one end of the twentieth resistor R20 and the first connector P1 are connected, the inverting end of the first operational amplifier U1 is connected to one end of the twenty-third resistor R23 and one end of the twenty-fourth resistor R24, the output end of the first operational amplifier U1 is connected to the gate of the fourth field effect transistor Q4, the gate of the fifth field effect transistor Q5, and the other end of the twenty-fourth resistor R24, the first pin of the second trigger U2, the fourth pin of the second trigger U2, one end of the first resistor R1, one end of the twenty-sixth resistor R26 and the power supply are connected, the second pin of the second trigger U2, one end of the fifth resistor R5 and the second connection The first terminal of the first resistor R1 is connected to the first electrode P2, the second trigger U2 is connected to the source of the fourth field effect transistor Q4 and one end of the twenty-second resistor R22, the fourth field effect transistor Q4 drain is connected to the drain of the fifth field effect transistor Q5, one end of the twenty-fifth resistor R25 and one end of the third capacitor C3, the source of the fifth field effect transistor Q5 is connected to the other end of the twenty-sixth resistor R26, the other end of the first resistor R1, the other end of the fifth resistor R5, the other end of the twentieth resistor R20, the other end of the twenty-second resistor R22, the other end of the twenty-third resistor R23, the other end of the twenty-fifth resistor R25, the other end of the third capacitor C3 and the ground terminal are connected.

[0026] Specifically, it also includes a third operational amplifier U3, a first field effect transistor Q1, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, an eighteenth resistor R18, a nineteenth resistor R19, a second capacitor C2, and a first diode D1;

[0027] The in-phase end of the third operational amplifier U3 is connected to the source of the first field effect transistor Q1, one end of the fourteenth resistor R14, and one end of the second capacitor C2. The inverting end of the third operational amplifier U3 is connected to one end of the eighteenth resistor R18 and one end of the nineteenth resistor R19. The output end of the third operational amplifier U3 is connected to one end of the fifteenth resistor R15 and the anode of the first diode D1. The gate of the first field effect transistor Q1 is connected to the fifth pin of the second trigger U2. The drain of the first field effect transistor Q1 is connected to one end of the twelfth resistor R12 and one end of the thirteenth resistor R13. The cathode of the first diode D1 is connected to the third pin of the second trigger U2. The other end of the thirteenth resistor R13 and the other end of the eighteenth resistor R18 are connected to the power supply. The other end of the twelfth resistor R12, the other end of the fourteenth resistor R14, the other end of the fifteenth resistor R15, the other end of the nineteenth resistor R19, and the other end of the second capacitor C2 are connected to the ground.

[0028] Specifically, it also includes a fourth operational amplifier U4, a fifth operational amplifier U5, a sixth operational amplifier U6, a second resistor R2, a third resistor R3, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10;

[0029] The in-phase end of the fourth operational amplifier U4, one end of the second resistor R2 and the end of the first connector P1 are connected, the inverting end of the fourth operational amplifier U4 is connected to one end of the sixth resistor R6, the output end of the fourth operational amplifier U4 is connected to the other end of the sixth resistor R6, the in-phase end of the fifth operational amplifier U5 and the in-phase end of the sixth operational amplifier U6 are connected, the inverting end of the fifth operational amplifier U5 is connected to one end of the third resistor R3 and one end of the seventh resistor R7, the output end of the fifth operational amplifier U5 is connected to the other end of the third resistor R3, the inverting end of the sixth operational amplifier U6 is connected to one end of the eighth resistor R8, the output end of the sixth operational amplifier U6 is connected to the other end of the eighth resistor R8 and one end of the ninth resistor R9, one end of the tenth resistor R10 is connected to the other end of the ninth resistor R9, the other end of the second resistor R2, the other end of the seventh resistor R7, the other end of the tenth resistor R10 and the ground are connected.

[0030] Specifically, it also includes a seventh operational amplifier U7, an eighth operational amplifier U8, a ninth operational amplifier U9, a second field effect transistor Q2, a third field effect transistor Q3, a fourth resistor R4, and a first capacitor C1;

[0031] The in-phase end of the seventh operational amplifier U7 is connected to the end of the first connector P1, the inverting end of the seventh operational amplifier U7 is connected to one end of the fourth resistor R4, the output end of the seventh operational amplifier U7 is connected to the in-phase end of the eighth operational amplifier U8, the inverting end of the ninth operational amplifier U9, the other end of the fourth resistor R4, and one end of the first capacitor C1, the inverting end of the eighth operational amplifier U8 is connected to the output end of the fifth operational amplifier U5, the output end of the eighth operational amplifier U8 is connected to the gate of the third field effect transistor Q3, the in-phase end of the ninth operational amplifier U9 is connected to one end of the tenth resistor R10, the output end of the ninth operational amplifier U9 is connected to the gate of the second field effect transistor Q2, the drain of the second field effect transistor Q2 is connected to the drain of the third field effect transistor Q3 and the source of the first field effect transistor Q1, the source of the second field effect transistor Q2, the source of the third field effect transistor Q3, the other end of the first capacitor C1 and the ground end are connected.

[0032] Specifically, it also includes a twenty-first resistor R21;

[0033] One end of the twenty-first resistor R21 is connected to the gate of the fourth field effect transistor Q4, and the other end of the twenty-first resistor R21 is connected to the ground.

[0034] Specifically, it also includes an eleventh resistor R11;

[0035] One end of the eleventh resistor R11 is connected to the gate of the first field effect transistor Q1 , and the other end of the eleventh resistor R11 is connected to the ground.

[0036] Specifically, it also includes a sixteenth resistor R16;

[0037] One end of the sixteenth resistor R16 is connected to the gate of the third field effect transistor Q3, and the other end of the sixteenth resistor R16 is connected to the ground.

[0038] Specifically, it also includes a seventeenth resistor R17;

[0039] One end of the seventeenth resistor R17 is connected to the gate of the second field effect transistor Q2, and the other end of the seventeenth resistor R17 is connected to the ground.

[0040] When the device is powered on, the power supply signal of the device is synchronously fed back to the first connector P1, the signal at the end of the first connector P1 is connected to the ground terminal through the twentieth resistor R20, the signal at the end of the twentieth resistor R20 is fed back to the in-phase terminal of the first operational amplifier U1, the signal at the output end of the first operational amplifier U1 is connected to the ground terminal through the twenty-fourth resistor R24 ​​and the twenty-third resistor R23, the signal at the end of the twenty-third resistor R23 is fed back to the inverting terminal of the first operational amplifier U1, the signal at the output end of the first operational amplifier U1 obtains gain, and the resistance value of the twenty-fourth resistor R24 ​​is adjusted to change the gain multiple. The higher the resistance value, the greater the gain. According to the use The resistance value of the twenty-fourth resistor R24 ​​is set as needed in the environment to prevent false detection of the power-on signal due to interference signals. The power signal is connected to the ground terminal through the twenty-sixth resistor R26, the source of the fifth field effect transistor Q5, the drain of the fifth field effect transistor Q5, and the twenty-fifth resistor R25. At the same time, the potential of the third capacitor C3 rises. When the first connector P1 obtains the power supply signal, the first operational amplifier U1 outputs, and the output signal of the first operational amplifier U1 is fed back to the gate of the fifth field effect transistor Q5 and the gate of the fourth field effect transistor Q4. The voltage difference between the gate of the fifth field effect transistor Q5 and the source of the fifth field effect transistor Q5 is higher than the conduction threshold. , the fifth field effect transistor Q5 is cut off, the voltage between the gate of the fourth field effect transistor Q4 and the source of the fourth field effect transistor Q4 is higher than the conduction threshold, the fourth field effect transistor Q4 is turned on, the twenty-first resistor R21 is used to discharge the parasitic capacitance of the gate of the fourth field effect transistor Q4 and the gate of the fifth field effect transistor Q5, the signal at the end of the third capacitor C3 is connected to the ground terminal through the drain of the fourth field effect transistor Q4, the source of the fourth field effect transistor Q4, and the twenty-second resistor R22, the signal at the end of the twenty-second resistor R22 is fed back to the 3rd pin of the second trigger U2, the power supply signal is connected to the ground terminal through the first resistor R1, and the signal at the end of the first resistor R1 is fed back to the second trigger At pin 4 of U2, the potential of the third capacitor C3 drops, pin 3 of the second trigger U2 obtains a high-level signal, pin 6 of the second trigger U2 feeds back a low-level signal, pin 5 of the second trigger U2 feeds back a high level, and the signal at pin 6 of the second trigger U2 is fed back to the working circuit in the device via the second connector P2. The working circuit is reset when it obtains a low-level signal, and at the same time, the signal at the end of the second connector P2 is connected to the ground end via the fifth resistor R5, and the signal at the end of the fifth resistor R5 is fed back to pin 2 of the second trigger U2, so that the working circuit in the device can be reset when the device is powered on.

[0041] The power signal passes through the thirteenth resistor R13 and the twelfth resistor R12 to the ground terminal. When the 5th pin of the second trigger U2 feeds back a high level, the signal is fed back to the gate of the first field effect tube Q1. The eleventh resistor R11 is used to discharge the parasitic capacitance of the gate of the first field effect tube Q1. The voltage difference between the gate of the first field effect tube Q1 and the source of the first field effect tube Q1 is higher than the conduction threshold. The first field effect tube Q1 is turned on. The signal at the end of the twelfth resistor R12 passes through the drain of the first field effect tube Q1, the source of the first field effect tube Q1, and the fourteenth resistor R14 to the ground terminal. At the same time, the potential of the second capacitor C2 rises. The signal at the end of the fourteenth resistor R14 is fed back to the in-phase terminal of the third operational amplifier U3. The power signal passes through the eighteenth resistor R18 and the nineteenth resistor R19 to the ground terminal. The signal amplitude at the end of the nineteenth resistor R19 is the time required for the device to reset. The signal amplitude between the first and second triggers is 0, 1, 2, 3, 4, 5, 6 and 8. The signal at the end of the nineteenth resistor R19 is fed back to the inverting end of the third operational amplifier U3. When the potential of the second capacitor C2 rises and its amplitude is higher than the signal amplitude at the end of the nineteenth resistor R19, the third operational amplifier U3 outputs, and the signal at the output end of the third operational amplifier U3 reaches the ground end through the fifteenth resistor R15. The signal at the end of the fifteenth resistor R15 is fed back to the 3 pin of the second trigger U2 after passing through the first diode D1. When the 3 pin of the second trigger U2 obtains the high level signal feedback again, the 6 pin of the second trigger U2 is high level, and the 5 pin of the second trigger U2 is low level. The reset circuit in the device stops resetting the internal circuit. At the same time, the first field effect tube Q1 is turned off, and the third operational amplifier U3 is turned off, so that the power-on detection circuit can reset itself after the device is reset.

[0042] The signal at the first connector P1 end is synchronously fed back to the in-phase end of the fourth operational amplifier U4, the second resistor R2 is a pull-down resistor at the in-phase end of the fourth operational amplifier U4, the output end of the fourth operational amplifier U4 is negatively feedback connected to the inverting end of the fourth operational amplifier U4 through the sixth resistor R6, the fourth operational amplifier U4 follows and outputs the signal at the first connector P1 end to prevent signal interference from the lower-level circuit, the output end signal of the fourth operational amplifier U4 is fed back to the in-phase end of the fifth operational amplifier U5, the output end signal of the fifth operational amplifier U5 is grounded through the third resistor R3 and the seventh resistor R7, the signal at the third resistor R3 end is fed back to the inverting end of the fifth operational amplifier U5, the fifth operational amplifier U5 gain outputs the output end signal of the fourth operational amplifier U4, the resistance value of the third resistor R3 is adjusted to change the gain multiple, the higher the resistance value, the greater the gain, the output of the fourth operational amplifier U4 The terminal signal is synchronously fed back to the in-phase terminal of the sixth operational amplifier U6, the output terminal of the sixth operational amplifier U6 is fed back to the inverting terminal of the sixth operational amplifier U6 through the eighth resistor R8, the sixth operational amplifier U6 follows and outputs the output terminal signal of the fourth operational amplifier U4, the output terminal signal of the sixth operational amplifier U6 is looped to the ground terminal through the ninth resistor R9 and the tenth resistor R10, the terminal signal of the tenth resistor R10 is the output terminal gain reduction signal of the fourth operational amplifier U4, the resistance value of the ninth resistor R9 is adjusted to change the gain reduction multiple, the higher the resistance value, the greater the gain reduction, the resistance values ​​of the third resistor R3 and the ninth resistor R9 are set as needed so that the output terminal signal of the fifth operational amplifier U5 and the terminal signal of the tenth resistor R10 constitute the detection accuracy range of the power supply signal, thereby automatically constructing the accuracy range of the power supply signal during the power-on detection so as to facilitate the subsequent circuit to perform accuracy range detection on the power supply signal.

[0043] The signal at the first connector P1 end is synchronously fed back to the in-phase end of the seventh operational amplifier U7. The output end of the seventh operational amplifier U7 is negatively feedback connected to the inverting end of the seventh operational amplifier U7 through the fourth resistor R4. The seventh operational amplifier U7 follows and outputs the signal at the first connector P1 end to prevent signal interference from the lower circuit. At the same time, the signal at the output end of the seventh operational amplifier U7 is fed back to the first capacitor C1. The charging and discharging of the first capacitor C1 causes the output end signal of the seventh operational amplifier U7 to lag behind the signal at the first connector P1 end. The output end signal of the seventh operational amplifier U7 is fed back to the in-phase end of the eighth operational amplifier U8 and the inverting end of the ninth operational amplifier U9. The output end signal of the fifth operational amplifier U5 is fed back to the inverting end of the eighth operational amplifier U8. The signal at the end of the tenth resistor R10 is fed back to the in-phase end of the ninth operational amplifier U9. When the device is powered on, the signal at the first connector P1 end jumps to make it above the constructed accuracy range, the ninth operational amplifier U9 outputs, and the output end signal of the ninth operational amplifier U9 is fed back to the gate of the second field effect transistor Q2. The seventeenth resistor R17 is used to discharge the parasitic capacitance of the gate of the second field effect transistor Q2. The second field effect transistor Q2 The voltage difference between the gate and the source of the second field effect tube Q2 is higher than the conduction threshold, the second field effect tube Q2 is turned on, and the signal at the second capacitor C2 end passes through the drain of the second field effect tube Q2 and the source of the second field effect tube Q2 to the ground end, and the potential of the second capacitor C2 drops to zero potential. When the device is powered on, the signal at the first connector P1 end jumps to make it below the constructed accuracy range, the eighth operational amplifier U8 outputs, and the output signal of the eighth operational amplifier U8 is fed back to the gate of the third field effect tube Q3. The sixteenth resistor R16 is used to discharge the parasitic capacitance of the gate of the third field effect tube Q3. The third The voltage difference between the gate of the field effect transistor Q3 and the source of the third field effect transistor Q3 is higher than the conduction threshold, the third field effect transistor Q3 is turned on, and the signal at the second capacitor C2 end passes through the drain of the third field effect transistor Q3 and the source of the third field effect transistor Q3 to the ground end, and the potential of the second capacitor C2 drops to zero potential, so that when the power supply signal is not within the accuracy range during the power-on detection period, the device can be continuously in a reset state to prevent the working circuit in the device from entering the working state when the power supply signal is not within the accuracy range, causing a logic error of the chip and limiting the self-reset of the detection circuit during this period.

[0044] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A power-on detection circuit, characterized in that: It includes a first operational amplifier, a second trigger, a fourth field effect transistor, a fifth field effect transistor, a first resistor, a fifth resistor, a twentieth resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a third capacitor, a first connector, and a second connector; The in-phase end of the first operational amplifier and one end of the twentieth resistor are connected to the first connector end, the inverting end of the first operational amplifier is connected to one end of the twenty-third resistor and one end of the twenty-fourth resistor, the output end of the first operational amplifier is connected to the gate of the fourth field effect tube, the gate of the fifth field effect tube, and the other end of the twenty-fourth resistor, the first pin of the second trigger, the fourth pin of the second trigger, one end of the first resistor, one end of the twenty-sixth resistor and the power supply are connected, the second pin of the second trigger, one end of the fifth resistor are connected to the second connector end, the third pin of the second trigger is connected to the source of the fourth field effect tube and one end of the twenty-second resistor, the drain of the fourth field effect tube is connected to the drain of the fifth field effect tube, one end of the twenty-fifth resistor, and one end of the third capacitor, the source of the fifth field effect tube is connected to the other end of the twenty-sixth resistor, and the other end of the first resistor, the other end of the fifth resistor, the other end of the twentieth resistor, the other end of the twenty-second resistor, the other end of the twenty-third resistor, the other end of the twenty-fifth resistor, and the other end of the third capacitor are connected to the ground end; and also includes a third operational amplifier, a first field effect tube, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, an eighteenth resistor, a nineteenth resistor, a second capacitor, and a first diode; The in-phase end of the third operational amplifier is connected to the source of the first field effect tube, one end of the fourteenth resistor, and one end of the second capacitor, the inverting end of the third operational amplifier is connected to one end of the eighteenth resistor and one end of the nineteenth resistor, the output end of the third operational amplifier is connected to one end of the fifteenth resistor and the anode of the first diode, the gate of the first field effect tube is connected to the fifth pin of the second trigger, the drain of the first field effect tube is connected to one end of the twelfth resistor and one end of the thirteenth resistor, the cathode of the first diode is connected to the third pin of the second trigger, the other end of the thirteenth resistor and the other end of the eighteenth resistor are connected to the power supply, and the other end of the twelfth resistor, the other end of the fourteenth resistor, the other end of the fifteenth resistor, the other end of the nineteenth resistor, and the other end of the second capacitor are connected to the ground; also includes a fourth operational amplifier, a fifth operational amplifier, a sixth operational amplifier, a second resistor, a third resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor; The fourth operational amplifier non-inverting end, one end of the second resistor and the first connector end are connected, the fourth operational amplifier inverting end and one end of the sixth resistor are connected, the fourth operational amplifier output end and the other end of the sixth resistor, the fifth operational amplifier non-inverting end and the sixth operational amplifier non-inverting end are connected, the fifth operational amplifier inverting end and one end of the third resistor and one end of the seventh resistor are connected, the fifth operational amplifier output end and the other end of the third resistor are connected, the sixth operational amplifier inverting end and one end of the eighth resistor are connected, the sixth operational amplifier output end and the other end of the eighth resistor and one end of the ninth resistor are connected, one end of the tenth resistor and the other end of the ninth resistor are connected, and the other end of the second resistor, the other end of the seventh resistor, the other end of the tenth resistor and the ground end are connected.

2. The power-on detection circuit according to claim 1, characterized in that: It also includes a seventh operational amplifier, an eighth operational amplifier, a ninth operational amplifier, a second field effect transistor, a third field effect transistor, a fourth resistor, and a first capacitor; The non-inverting end of the seventh operational amplifier is connected to the first connector end, the inverting end of the seventh operational amplifier is connected to one end of the fourth resistor, the output end of the seventh operational amplifier is connected to the non-inverting end of the eighth operational amplifier, the inverting end of the ninth operational amplifier, the other end of the fourth resistor, and one end of the first capacitor, the inverting end of the eighth operational amplifier is connected to the output end of the fifth operational amplifier, the output end of the eighth operational amplifier is connected to the gate of the third field effect tube, the non-inverting end of the ninth operational amplifier is connected to one end of the tenth resistor, the output end of the ninth operational amplifier is connected to the gate of the second field effect tube, the drain of the second field effect tube is connected to the drain of the third field effect tube and the source of the first field effect tube, and the source of the second field effect tube, the source of the third field effect tube, the other end of the first capacitor and the ground end are connected.

3. The power-on detection circuit according to claim 1, characterized in that: Also included is a twenty-first resistor; One end of the twenty-first resistor is connected to the gate of the fourth field effect transistor, and the other end of the twenty-first resistor is connected to the ground.

4. The power-on detection circuit according to claim 1, characterized in that: An eleventh resistor is also included; One end of the eleventh resistor is connected to the gate of the first field effect transistor, and the other end of the eleventh resistor is connected to the ground.

5. The power-on detection circuit according to claim 2, characterized in that: Also included is a sixteenth resistor; One end of the sixteenth resistor is connected to the gate of the third field effect transistor, and the other end of the sixteenth resistor is connected to the ground end.

6. The power-on detection circuit according to claim 3, characterized in that: Also included is a seventeenth resistor; One end of the seventeenth resistor is connected to the gate of the second field effect transistor, and the other end of the seventeenth resistor is connected to the ground.

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