ClassAB output stage control and compensation circuit
By introducing differential differential amplifiers and resistor capacitor networks into the Class_AB output stage circuit, precise current control and stability compensation for the Class_AB output stage is achieved, quiescent current control and stability problems are solved, and the efficiency and stability of the operational amplifier are improved.
Patent Information
- Application Number
- CN202510268050.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-07
- Publication Date
- 2025-07-25
AI Technical Summary
In the existing Class_AB output stage circuit, quiescent current cannot be accurately controlled and stability compensation is difficult, making it difficult to meet the application needs of low power consumption, high efficiency and high stability.
The folded casubar amplifier module, Class_AB output stage bias module, Class_AB output stage control module and Class_AB output stage compensation module are adopted to realize the negative feedback structure through a differential amplifier, accurately control the gate voltage of the output stage transistor, and frequency compensation is performed through the resistor and capacitance network to ensure system stability.
It realizes accurate current control of the Class_AB output stage and improves stability over a wide frequency range, reduces static power consumption, improves power rejection ratio and dynamic response performance, has strong adaptability, low cost and good compatibility.
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Figure CN120377833A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of analog integrated circuits, and particularly to a Class_AB output stage control and compensation circuit. Background Art
[0002] The output stage circuit of an operational amplifier usually includes three types: Class_A, Class_B, and Class_AB (push-pull output stage). The Class_A output stage remains conducting throughout the entire operating cycle, having high linearity, but its static power consumption is large and the energy utilization rate is low; the Class_B output stage uses complementary transistors to amplify the positive and negative half-cycles of the signal respectively. Although the efficiency is high, there is crossover distortion at the zero crossover point, which affects the signal quality. In the design of operational amplifiers that need to drive large capacitors or low-impedance loads, the Class_AB output stage is usually preferred to balance power consumption, efficiency, and distortion control. The operating state of the Class_AB output stage is between Class_A and Class_B. Its characteristic is that the push-pull structure is used to keep both transistors conducting to a certain extent in the small-signal range, thereby effectively reducing the crossover distortion in the Class_B output stage. At the same time, under large-signal conditions, this structure can provide high output capability, enhance the driving ability, and improve the overall efficiency. Compared with the Class_A output stage, the Class_AB output stage can significantly reduce the static power consumption and avoid the problem of continuous high energy consumption; compared with the Class_B output stage, it overcomes the deficiency of crossover distortion and improves the signal quality. Therefore, the Class_AB output stage has been widely used in the design of operational amplifiers with low power consumption, high linearity, and high driving ability, especially suitable for application scenarios with high requirements for power consumption, output stability, and signal integrity.
[0003] However, the prior art has the following problems: it is difficult to accurately control the static current of the Class_AB output stage with a wide range of load currents and to compensate for stability. Summary of the Invention
[0004] The object of the present invention is to provide a Class_AB output stage control and compensation circuit to solve the technical problems that it is difficult to accurately control the static current of the Class_AB output stage with a wide range of load currents and to compensate for stability, and to improve the Class_AB output stage circuit technically to meet the application requirements of low power consumption, high efficiency, and high stability.
[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:
[0006] A Class-AB output stage control and compensation circuit, comprising: a folded cascode amplifier module, a Class-AB output stage bias module, a Class-AB output stage control module, and a Class-AB output stage compensation module. The folded cascode amplifier module is used to provide gain for the loop to ensure the loop gain of the negative feedback system and the accuracy of the output voltage; the Class-AB output stage bias module is used to generate the bias reference voltage of the output power transistors and provide the reference value of the static current; the Class-AB output stage control module generates the gate voltage of the output power transistors through a differential difference amplifier to control their static and dynamic currents; the Class-AB output stage compensation module is used to compensate for the loop stability to ensure the stability of the loop under a wide range of output currents. The entire circuit adopts a negative feedback structure so that the gate voltage of the output stage transistors can be dynamically adjusted following the magnitude of the output current. At the same time, the gate of the pull-up transistor PMOS and the gate of the pull-down transistor can always ensure a constant voltage difference through the action of the Class-AB output stage control module, and can accurately control the short-circuit current of the Class-AB output stage, improving the current efficiency of the Class-AB output stage.
[0007] Optionally, the folded cascode amplifier module (2) may include an amplifier input pair of transistors with equal areas, namely Q1 and Q2. In this design, common-gate transistors are connected above the output pair of transistors to increase the output impedance, and the common-gate transistors are M3 and M4. Further, the output end is designed for differential-to-single-ended output, and the load transistor M6 is connected through a diode. In addition, the common-gate transistors at the PMOS end are divided into two paths, which are composed of M8 and M9, M10 and M11 respectively. Among them, the gate voltages of M8 and M11 are controlled by the positive output terminal (VBPP) of the differential difference amplifier (DDA) of the Class AB output stage control module (4), while the gate voltages of M9 and M10 are controlled by the negative output terminal (VBPM) of the differential difference amplifier (DDA) of the Class AB output stage control module (4).
[0008] Optionally, the two in-phase output terminals of the folded cascode amplifier module (2) are respectively the gate (VPG) of the PMOS power transistor and the gate (VNG) of the NMOS power transistor. Among them, VPG is simultaneously connected to the negative input terminal of the differential difference amplifier (DDA) of the Class AB output stage control module (4), while VNG is simultaneously connected to the positive input terminal of this module. Through this design, effective control and regulation of the power transistors can be achieved to ensure the stability and linearity of the output performance.
[0009] Optionally, in the design of the Class AB output stage bias module (1), the width-to-length ratio of the PMOS tube M1 is equal to that of the PMOS output power tube M17, and the number of M1 connected in parallel is 1 / N1 of that of the PMOS tube M17; meanwhile, the width-to-length ratio of the NMOS tube M2 is equal to that of the NMOS tube M18, and the number of M1 connected in parallel is 1 / N2 of that of the NMOS tube M18. In order to ensure the balance of current, the gate-source voltage difference VGS between the PMOS tube M1 and the PMOS output power tube M17 is equal, and the gate-source voltage difference VGS between the NMOS tube M2 and the NMOS tube M18 is also equal. When the Class AB output stage is unloaded, the current of M1 is provided by the fixed current source IB1, and the current flowing through the PMOS tube M17 is N1 times that of the fixed current source IB1; similarly, the current of M2 is provided by the fixed current source IB2, and the current flowing through the NMOS tube M18 is N2 times that of the fixed current source IB2, wherein IB1 is equal to IB2, and N1 is equal to N2. This design effectively provides bias current, thus ensuring stable operation of the Class AB output stage.
[0010] Optionally, the Class AB output stage control module (4) uses a differential differential amplifier (DDA) embedded between two common-gate transistors on one side of the output end of the folded common-source common-gate amplifier module (2). The differential differential amplifier has four output ports and two groups of output pairs of transistors, one group of output pairs of transistors is M21 and M22, and the input ports are VNG and VNB respectively; the other group of output pairs of transistors is M23 and M24, and the input ports are VPG and VPB respectively. Tail current source transistors M25 and M27 are used to provide stable current, while M26 is used as a common-gate transistor to increase the impedance of the tail current source tube output. In addition, M19 and M20 can effectively protect the output pair of transistors M21 and M22 to prevent their drain-source voltage difference from exceeding a safe range. M17 and M18 are diode-connected loads to ensure the stable operation of the module. The output terminals VBPP and VBPM are respectively connected to the common-gate transistor Gate terminal of the main operational amplifier to ensure the stability of the output voltage.
[0011] Optionally, the Class AB output stage compensation module (3) is optimized using a resistor-capacitor network. A resistor-capacitor network is connected between the gate and the output end of the output power tubes M17 and M18. The network is composed of a capacitor C2 connected in series with a resistor R1 and connected in parallel with the network of capacitor C1 to form a resistor-capacitor network at the pull-up end; similarly, a capacitor C3 is connected in series with a resistor R2 and connected in parallel with the network of capacitor C4 to form a resistor-capacitor network at the pull-down end. After the two groups of resistor-capacitor networks are connected in parallel, they are connected in series with R3. Through the design of this compensation network, the frequency response and stability of the system can be effectively improved, ensuring that the Class AB output stage maintains stable output performance within a wider operating frequency range.
[0012] The control circuit and compensation circuit of the Class-AB output stage of the present invention have the following beneficial effects compared with the prior art:
[0013] The core of the Class-AB output stage control circuit proposed by the present invention is to bias the gate voltage of the output stage transistor by using a differential difference amplifier connected in a negative feedback structure, and to achieve precise control and regulation by controlling the gate voltage difference to be equal to the target voltage difference. Compared with the traditional transconductance linear loop structure, the technology adopted by the present invention effectively avoids the influence of the floating current source channel length modulation effect, and can adjust the bias current of the output stage more stably and precisely. When dealing with power supply voltage fluctuations, this design significantly reduces the amplitude of the static current of the output stage transistor changing with the power supply voltage, thereby effectively improving the power supply rejection ratio (PSRR) of the operational amplifier. At the same time, the design of the present invention maintains a small number of devices, and the circuit structure is simple and efficient, which not only reduces costs but also ensures good compatibility, enabling it to operate stably in a variety of different application environments.
[0014] The core of the Class-AB output stage compensation circuit proposed by the present invention is to introduce multiple pairs of zeros and poles close to each other in position, to ensure that the system gain rolls off appropriately while maintaining a high phase margin in a wide frequency range, thereby effectively offsetting the unstable influence brought by the change of the output pole. Compared with the traditional frequency compensation scheme, it can significantly improve the stability and dynamic response performance of the operational amplifier in a wide load range.
[0015] The application scope of the Class-AB output stage control and compensation circuit of the present invention is not limited to the Class-AB output stage operational amplifier circuit exemplified in this article. In fact, the control circuit designed by the present invention can be widely applied to the independent biasing of two nodes that are separated in direct current and short-circuited in alternating current. The compensation circuit involved in the present invention can be widely applied to complex compensation problems where the pole position moves in a wide frequency range, with strong adaptability and universality, and can meet the needs of different fields, providing an efficient, low-cost and highly reliable solution. Brief Description of the Drawings
[0016] Figure 1 is a schematic diagram of a Class-AB output stage control and compensation circuit of the present invention;
[0017] Figure 2 is a schematic diagram of a Class-AB compensation network module of the present invention.
[0018] Reference Numerals: 1. Class-AB output stage biasing module; 2. Folded cascode amplifier module; 3. Class-AB output stage compensation module; 4. Class-AB output stage control module. Detailed implementation manners
[0019] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0020] Before describing the embodiments of the present invention, some related technologies of the present invention are described as follows:
[0021] The basic idea of the push-pull structure is to combine two output stages with output transistors composed of PMOS and NMOS respectively, and achieve complementarity of the signal truncation part by allowing each of the two output stages to occupy a part of the conduction angle. Taking the class B output stage as an example, by paralleling a PMOS source follower and an NMOS source follower, a simple push-pull class B output stage can be obtained. According to the level of the input signal, the two MOS transistors will conduct alternately to drive the output. That is, for each transistor, the conduction time is only half, so its energy efficiency is relatively high. However, there is a "dead zone" where both transistors are not conducting in the circuit. That is, when the output voltage approaches the input voltage, the VGS of both transistors will be less than VTH (both are not conducting), and at this time, the driving ability of the output stage almost disappears, resulting in a dead zone error between the output voltage and the input voltage, introducing additional nonlinear distortion. To solve the dead zone problem, an additional biasing structure (usually two diode-connected MOS transistors) can be used to separate the gate voltages of the two output transistors and bias them respectively in the critical conduction state. At this time, the conduction time of the two transistors will be greater than 50%, so this output stage belongs to class AB, and its energy efficiency is slightly lower than that of class B. However, the class AB push-pull output stage implemented based on the source follower still cannot avoid the problem of output swing limitation. That is, since the gate voltage of the follower cannot be higher than the power supply voltage (or cannot be lower than the ground voltage), the output amplitude of the follower is always limited within the range of the power supply rail minus two VTHs. To achieve rail-to-rail output swing, a common-source configuration needs to be used to implement the class AB push-pull stage output. For the class AB push-pull output stage implemented by the common-source configuration, the requirements that its control circuit needs to meet are to independently bias the gate voltages of the upper and lower output transistors to be separated in DC and short-circuited in AC. DC separation can ensure static current biasing for the upper and lower output transistors respectively, ensuring that the static current is not too large; while AC short-circuit can ensure that the gate voltages can rise and fall together, so that when the current of one transistor increases, the current of the other transistor will decrease, improving the output efficiency.
[0022] The differential difference amplifier (DDA) has two differential input ports, namely (VNG - VNB) and (VPG - VPB). Then the expression for the fully differential output terminal is VBPP = -VBPM = A[(VPG - VPB) - (VNG - VNB)]. When connected in a negative feedback form, the following relationship will be satisfied: VPG - VNG = VPB - VNB. Therefore, by connecting the differential difference amplifier in a negative feedback form, the gate voltages of the two output transistors can approximately meet the static bias requirement of a constant difference.
[0023] The stability and transient response performance of an operational amplifier (op-amp) largely depend on the design of the frequency compensation network. To effectively improve the phase margin and system stability of the op-amp, the compensation network usually adopts a resistor-capacitor (RC) network structure. In the existing RC compensation network design, the key components include capacitors C1, C2 and resistors R1, R2, and their working principles and functions are described as follows. C2 is usually used as a Miller capacitor, and its capacitance value is larger than that of C1. In the low-frequency band, the impedance of C1 is high and can be regarded as an open circuit. C2 is connected across the Class AB output stage, and its main function is to shift the main pole of the system to the low-frequency region, thereby improving the low-frequency stability. Resistor R2 introduces a zero point in this network to enhance the phase margin of the system. When the operating frequency gradually increases, the impedance of C2 decreases. When the impedance of C2 decreases to be equal to the resistance value of R2, the system reaches the angular frequency ω = 1 / (R2C2). At this time, the impedance of the series branch composed of R2 and C2 is mainly dominated by R2, and C2 can be regarded as a short circuit, and the system introduces a zero point, and the compensation effect appears. As the frequency continues to rise, the impedance of C1 begins to decrease. When the frequency reaches ω = 1 / (R2C1), the impedance of C1 is less than R2. At this time, the impedance of this parallel network is dominated by C1, and the system impedance continues to decrease with the increase of frequency. Finally, when the frequency further increases to ω = 1 / (R1C1), the impedance of C1 decreases to be less than R1, and the impedance of the entire RC network is dominated by R1, and the system impedance remains unchanged. Through the above design, the RC network introduces two poles and two zero points, forming an effective frequency compensation mechanism. The advantage of this compensation method is that the change range of the output stage current of the op-amp is large, resulting in significant fluctuations in the output impedance, and further causing the output pole to fluctuate between multiple orders of magnitude, which may lead to the problem of insufficient phase margin. By introducing multiple zero points and poles, this compensation network not only ensures the appropriate roll-off of the system gain, but also maintains a high phase margin in a wide frequency range, thereby effectively offsetting the unstable influence brought by the change of the output pole and significantly improving the stability and dynamic response performance of the op-amp.
[0024] Embodiment:
[0025] Please refer to Figure 1 , this embodiment provides a Class_AB output stage control and compensation circuit.
[0026] The folded cascode amplifier module (2) is mainly used to provide gain for the loop to ensure the loop gain of the negative feedback system and the accuracy of the output voltage. The working principle of this module depends on the input pair transistors Q1 and Q2, which have equal areas and are controlled by the input signal VIP at their input terminals. The output terminals of Q1 and Q2 are respectively connected to the cascode transistors M3 and M4 to form the output stage of the amplifier, and the output is carried out through the load transistor M6. The function of the cascode transistors M3 and M4 is to increase the output impedance to ensure a stable output.
[0027] The signal VIP at the input terminal is input through Q1 and Q2, and the corresponding output signal is transmitted through M3 and M4. The output signal is converted from differential to single-ended output, and the load transistor M6 is connected in diode form to transmit the output signal to the subsequent module. The cascode transistors at the PMOS side are divided into two paths: M8 and M9, M10 and M11. Among them, the gate voltages of M8 and M11 are controlled by the positive output terminal (VBPP) of the differential difference amplifier (DDA) of the Class-AB output stage control module (4), and the gate voltages of M9 and M10 are controlled by the negative output terminal (VBPM) of the DDA.
[0028] The two in-phase output terminals of the folded cascode amplifier module (2) are respectively the gate (VPG) of the PMOS power transistor and the gate (VNG) of the NMOS power transistor. VPG is connected to the negative input terminal of the DDA of the Class-AB output stage control module (4), and VNG is connected to the positive input terminal of the DDA of the Class-AB output stage control module (4), thus establishing a feedback relationship between the output stage modules.
[0029] The Class-AB output stage bias module (1) provides a reference value for the static current by generating a bias reference voltage for the output power transistors. This module consists of the PMOS transistor M1 and the PMOS output power transistor M17. The width-to-length ratios of M1 and M17 are equal, and the parallel number is 1 / N1 of M17. The width-to-length ratios of the NMOS transistor M2 and the NMOS transistor M18 are also equal, and the parallel number is 1 / N2 of M18. The gate-source voltage difference VGS between the PMOS transistor M1 and M17 is equal to the gate-source voltage difference VGS between the NMOS transistor M2 and M18.
[0030] The fixed current source IB1 provides current for M1, and the current of IB1 flows through M17 with a current N1 times that of IB1; similarly, the fixed current source IB2 provides current for M2, and the current of IB2 flows through M18 with a current N2 times that of IB2. Through this design, the Class-AB output stage bias module (1) realizes the precise biasing of the output power transistors.
[0031] The Class-AB output stage control module (4) controls the gate voltage of the output power transistors through a differential difference amplifier (DDA), thereby precisely controlling their static and dynamic currents. On one side of the output terminal of the folded cascode amplifier module (2), the DDA module is embedded between two pairs of common-gate transistors M21, M22 and M23, M24.
[0032] The input ports of the differential difference amplifier are VNG, VNB (corresponding to the inputs of M21 and M22) and VPG, VPB (corresponding to the inputs of M23 and M24) respectively. The tail current source transistors M25 and M27 of the DDA provide a stable current, and M26 acts as a common-gate transistor to increase the output impedance of the tail current source transistors. M19 and M20 play a protective role to prevent the drain-source voltage difference of the output pair transistors M21 and M22 from exceeding the safe range.
[0033] The output terminals of the DDA are VBPP and VBPM, which are respectively connected to the Gate terminals of the common-gate transistors of the main op-amp, thereby achieving precise control of the output voltage.
[0034] Please refer to Figure 2 , this embodiment provides a Class_AB compensation network module. The Class-AB output stage compensation module (3) is used to compensate for the loop stability to ensure the stability of the loop under a wide range of output currents. The key to the compensation module lies in the connection of the resistor-capacitor network. Between the gates and the output terminals of the output power transistors M17 and M18, two resistor-capacitor networks are connected.
[0035] The resistor-capacitor network at the upper pull end is formed by connecting capacitor C2 in series with resistor R1 and then in parallel with capacitor C1; the resistor-capacitor network at the lower pull end is formed by connecting capacitor C3 in series with resistor R2 and then in parallel with capacitor C4. After these two resistor-capacitor networks are connected in parallel, they are then connected in series with resistor R3, finally achieving effective compensation for the loop frequency response. Through this design, the stability of the system can be improved to ensure that the loop can remain stable under a wide range of output currents.
[0036] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and supplements can still be made, and these improvements and supplements should also be regarded as the protection scope of the present invention.
Claims
1. A Class_AB output stage control and compensation circuit, characterized in that The control and compensation circuit includes: a Class_AB output stage biasing module (1), a folded cascode amplifier module (2), a Class_AB output stage compensation module (3), and a Class_AB output stage control module (4).
2. The Class_AB output stage control and compensation circuit according to claim 1, wherein The folded cascode amplifier module (2) is used to provide gain for the loop, thereby providing the loop gain of the negative feedback system and stabilizing the output voltage.
3. The Class_AB output stage control and compensation circuit according to claim 1, wherein The Class_AB output stage biasing module (1) is used to generate the bias reference voltage of the output power transistors to provide a reference value for the static current.
4. A Class_AB output stage control and compensation circuit according to claim 1, characterized in that, The Class_AB output stage control module (4) is used to generate the gate voltage of the output power transistors through a differential difference amplifier to control the static current and dynamic current of the power transistors.
5. A Class_AB output stage control and compensation circuit according to claim 1, characterized in that, The Class_AB output stage compensation module (3) is used to compensate for the loop stability, so that the loop can operate stably under the output current within a preset range.
6. The Class_AB output stage control and compensation circuit according to claim 2, characterized in that, The amplifier input pair transistors of the folded cascode amplifier module (2) are composed of transistors Q1 and Q2 with equal areas; the amplifier output pair transistors of the folded cascode amplifier module (2) are connected with common-gate transistors M3 and M4 to increase the impedance; the output end of the folded cascode amplifier module (2) outputs in a differential-to-single-ended manner, and the load transistor M6 is diode-connected; the common-gate transistors at the PMOS end of the folded cascode amplifier module (2) are each divided into two paths, namely M8 and M9, M10 and M11, where the gate voltages of M8 and M11 are controlled by the positive output end of the differential difference amplifier of the Class_AB output stage control module (4), and the gate voltages of M9 and M10 are controlled by the negative output end of the differential difference amplifier of the Class_AB output stage control module (4); the two in-phase output ends of the folded cascode amplifier module (2) are VPG and VNG respectively, and VPG is also connected to a negative input end of the differential difference amplifier of the Class_AB output stage control module (4), and VNG is also connected to a positive input end of the differential difference amplifier of the Class_AB output stage control module (4).
7. A Class_AB output stage control and compensation circuit according to claim 3, characterized in that, The aspect ratio of PMOS transistor M1 in the Class_AB output stage bias module (1) is equal to that of PMOS output power transistor M17, and the number of parallel connections is 1 / N1 of PMOS transistor M17; the aspect ratio of NMOS transistor M2 in the Class_AB output stage bias module (1) is equal to that of NMOS transistor M18, and the number of parallel connections is 1 / N2 of NMOS transistor M18; the gate-source voltage difference VGS of PMOS transistor M1 is equal to that of PMOS output power transistor M17, and the gate-source voltage difference VGS of NMOS transistor M2 is equal to that of NMOS transistor M18; when the output stage of the Class_AB output stage control and compensation circuit is unloaded, the current flowing through M1 is provided by the fixed current source IB1, and then the current flowing through PMOS transistor M17 is N1 times that of the fixed current source IB1, where N is the ratio of the aspect ratio of M17 to M1; the current flowing through M2 is provided by the fixed current source IB2, and then the current flowing through NMOS transistor M18 is N2 times that of the fixed current source IB2, where N2 is the ratio of the aspect ratio of M2 to M18; where IB1 = IB2 and N1 = N2.
8. A Class_AB output stage control and compensation circuit according to claim 4, characterized in that, The Class_AB output stage control module (4) embeds a differential difference amplifier between two common-gate transistors on one side of the output terminal of the folded cascode amplifier module (2). The differential difference amplifier includes: a total of four output ports, two groups of output pairs of transistors. One group of output pairs of transistors is M21 and M22, and the corresponding input ports are VNG and VNB respectively. The other group of input pairs of transistors is M23 and M24, and the corresponding input ports are VPG and VPB respectively; M25 and M27 are tail current source transistors, M26 is a common-gate transistor for increasing the output impedance of the tail current source transistor, and M19 and M20 are used to protect the drain-source voltage difference of the output pairs of transistors M21 and M22 from exceeding a preset safety range; M17 and M18 are diode-connected loads; the output terminals are VBPP and VBPM, which are respectively connected to the Gate terminals of the common-gate transistors of the main op-amp.
9. The Class_AB output stage control and compensation circuit according to claim 5, wherein The Class_AB output stage compensation module (3) connects a resistor-capacitor network between the gates and output terminals of output power transistors M17 and M18 respectively. The resistor-capacitor network includes: a network where capacitor C2 is in parallel with the network of resistor R1 in series with capacitor C1 to form the resistor-capacitor network of the pull-up end, and a network where capacitor C3 is in parallel with the network of resistor R2 in series with capacitor C4 to form the resistor-capacitor network of the pull-down end. After the two groups of resistor-capacitor networks are in parallel, they are then in series with R3.
Citation Information
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