Wireless ad hoc network communication methods, devices, storage media and nodes

Abstract

The present application discloses a wireless ad hoc network communication method, device, storage medium and node, which relates to the field of communication technology. The nodes in the wireless ad hoc network can: determine the service data packet length that matches the interruption interval and modulation coding strategy according to the service data recommended packet length table; generate a fixed-length control sequence part in the physical layer frame format, and the fixed-length control sequence part includes a leading sequence and a control sequence; process the service data according to the service data packet length and the modulation coding strategy through a chip to generate a variable-length service data part; start a direct memory access controller to move the modulated data to the transceiver interface and send it in the wireless ad hoc network, and the modulated data consists of a fixed-length control sequence part and a variable-length service data part. The present application can realize the good application of chips using accelerators based on mobile communication standard protocols in wireless ad hoc networks, and maximize the throughput capacity of such chips in wireless ad hoc networks.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a wireless ad hoc network communication method, device, storage medium and node. Background Art

[0002] Many functions of the accelerators included in some chips are based on mobile communication standard protocols (such as LTE protocols), which are based on centralized networking communication protocols, that is, a central node similar to a base station is required to schedule resources for access terminals. These chips have the advantages of low power consumption and high bandwidth with the assistance of a large number of accelerators based on mobile communication standard protocol functions. If they can be applied to nodes in decentralized wireless ad hoc networks, they will have the advantages of low node power consumption and high bandwidth.

[0003] However, in order to adapt to mobile communication networks with fixed time frame structures scheduled by central base stations (such as LTE networks), these chips use DMA (Direct Memory Access) to move data, and their handling methods are strongly related to the fixed time frame structure. However, wireless ad hoc networks are decentralized, and their network topology often changes with the changes in the wireless environment. Their services are often bursty, and they compete for channel resources in time according to the actual volume of services. This means that these chips that adapt to fixed time frame structures cannot currently be well applied to decentralized wireless ad hoc networks. Summary of the invention

[0004] The embodiment of the present application provides a wireless ad hoc network communication solution, which can realize the good application of chips using accelerators based on mobile communication standard protocols in wireless ad hoc networks and improve the throughput capacity of such chips in wireless ad hoc networks.

[0005] The embodiments of the present application provide the following technical solutions:

[0006] According to one embodiment of the present application, a wireless ad hoc network communication method is applied to a node in a wireless ad hoc network, the method comprising: determining a service data packet length that matches an interruption interval and a modulation and coding strategy according to a service data recommended packet length table, wherein the interruption interval is the time interval between output interruptions when the chip uses a direct memory access controller to move data, and the modulation and coding strategy is a modulation and coding strategy for service data; generating a fixed-length control sequence portion in a physical layer frame format, the fixed-length control sequence portion comprising a leading sequence and a control sequence, the leading sequence being used for receiving synchronization and channel estimation of a physical frame, the control sequence comprising the service data packet length and the modulation and coding strategy; processing service data according to the service data packet length and the modulation and coding strategy through the chip to generate a variable-length service data portion in the physical layer frame format; starting the direct memory access controller to move the modulated data to a transceiver interface and send it in the wireless ad hoc network, the modulated data consisting of the fixed-length control sequence portion and the variable-length service data portion.

[0007] In some embodiments of the present application, before determining the service data packet length that matches the interruption interval and the modulation and coding strategy according to the service data recommended packet length table, the method also includes: calculating the time length of the orthogonal frequency division multiplexing symbol occupied by the fixed-length control sequence part in the physical layer frame format to obtain a first time length; calculating the time length of the orthogonal frequency division multiplexing symbol occupied by the target data length under the modulation and coding strategy adopted by the service rate gear according to the number of available subcarriers of the orthogonal frequency division multiplexing symbol to obtain a second time length; calculating the sum of the first time length and the second time length to obtain the total time length; if the difference between the total time length and the interruption interval is less than the length of an orthogonal frequency division multiplexing symbol, recording the matching relationship between the service rate gear and the target data length in the service data recommended packet length table.

[0008] In some embodiments of the present application, determining the service data packet length that matches the interruption interval and the modulation and coding strategy based on the service data recommended packet length table includes: determining the service rate gear where the modulation and coding strategy is located in the service data recommended packet length table; determining the target data length corresponding to the service rate gear where the modulation and coding strategy is located as the service data packet length that matches the interruption interval and the modulation and coding strategy.

[0009] In some embodiments of the present application, the chip processes the service data according to the service data packet length and the modulation and coding strategy to generate a variable-length service data portion in the physical layer frame format, including: calling a coding accelerator on the second core processor of the chip to perform bit-level processing on the service data to obtain coded data according to the service data packet length and the modulation and coding strategy, and sending an interrupt message to the first core processor of the chip; and starting an scrambling accelerator to perform symbol-level processing on the coded data in response to the interrupt message by the first core processor to obtain a variable-length service data portion in the physical layer frame format.

[0010] In some embodiments of the present application, the calling of the coding accelerator to perform bit-level processing on the service data to obtain the encoded data includes: calling the coding accelerator to perform cyclic redundancy check, code block segmentation, encoding and rate matching on the bit stream of the service data to obtain the encoded data; correspondingly, the starting of the scrambling accelerator to perform symbol-level processing on the encoded data to obtain the variable-length service data portion in the physical layer frame format, including: starting the scrambling accelerator to scramble the encoded data to obtain the scrambled data; performing orthogonal frequency division multiplexing modulation on the scrambled data with the number of orthogonal frequency division multiplexing symbols contained in the interruption interval as the granularity to obtain the variable-length service data portion in the physical layer frame format.

[0011] In some embodiments of the present application, the method also includes: receiving data sent in a wireless self-organizing network to obtain received data; using the first core processor in the chip to perform time-frequency synchronization and equalization processing on the fixed-length control sequence portion in the received data to obtain the service data packet length and modulation and coding strategy in the received data, and calculating demodulation information based on the service data packet length and modulation and coding strategy in the received data; using the second core processor in the chip to demodulate the variable-length service data portion in the received data according to the demodulation information, and decode the demodulated data obtained by demodulation to obtain a service data bit stream.

[0012] In some embodiments of the present application, the demodulation information includes the number of divisions of the coding code block and the number of orthogonal frequency division multiplexing symbols contained in each coding code block; the variable-length business data part in the received data is demodulated according to the demodulation information, and the demodulated data is decoded to obtain a business data bit stream, including: according to the number of orthogonal frequency division multiplexing symbols contained in each coding code block, the coding code blocks in the variable-length business data part are demodulated in turn and decoded using a decoding accelerator until the demodulation and decoding of the divided number of coding code blocks are completed to obtain the business data bit stream.

[0013] According to one embodiment of the present application, a wireless ad hoc network communication device is applied to a node in a wireless ad hoc network, the device comprising: a determination module, used to: determine a service data packet length that matches an interruption interval and a modulation and coding strategy according to a service data recommended packet length table, wherein the interruption interval is the time interval between output interruptions when the chip uses a direct memory access controller to move data, and the modulation and coding strategy is a modulation and coding strategy for service data; a first generation module, used to: generate a fixed-length control sequence portion in a physical layer frame format, the fixed-length control sequence portion includes a leading sequence and a control sequence, the leading sequence is used for receiving synchronization and channel estimation of a physical frame, and the control sequence includes the service data packet length and the modulation and coding strategy; a second generation module, used to: process service data according to the service data packet length and the modulation and coding strategy through the chip, and generate a variable-length service data portion in the physical layer frame format; a sending module, used to: start the direct memory access controller to move the modulated data to the transceiver interface and send it in the wireless ad hoc network, the modulated data consists of the fixed-length control sequence portion and the variable-length service data portion.

[0014] In some embodiments of the present application, before determining the service data packet length that matches the interruption interval and the modulation and coding strategy based on the service data recommended packet length table, the device also includes a search module, which is used to: calculate the time length of the orthogonal frequency division multiplexing symbol occupied by the fixed-length control sequence part in the physical layer frame format to obtain a first time length; calculate the time length of the orthogonal frequency division multiplexing symbol occupied by the target data length under the modulation and coding strategy adopted by the service rate gear according to the number of available subcarriers of the orthogonal frequency division multiplexing symbol to obtain a second time length; calculate the sum of the first time length and the second time length to obtain the total time length; if the difference between the total time length and the interruption interval is less than the length of an orthogonal frequency division multiplexing symbol, then record the matching relationship between the service rate gear and the target data length in the service data recommended packet length table.

[0015] In some embodiments of the present application, the determination module is used to: determine the service rate gear where the modulation and coding strategy is located in the service data recommended packet length table; determine the target data length corresponding to the service rate gear where the modulation and coding strategy is located as the service data packet length that matches the interruption interval and the modulation and coding strategy.

[0016] In some embodiments of the present application, the second generation module is used to: call the coding accelerator on the second core processor of the chip to perform bit-level processing on the business data to obtain coded data according to the service data packet length and the modulation and coding strategy, and send an interrupt message to the first core processor of the chip; respond to the interrupt message through the first core processor, start the scrambling accelerator to perform symbol-level processing on the coded data, and obtain the variable-length service data part in the physical layer frame format.

[0017] In some embodiments of the present application, the second generation module is used to: call the encoding accelerator to perform cyclic redundancy check, code block segmentation, encoding and rate matching on the bit stream of the service data to obtain the encoded data; start the scrambling accelerator to scramble the encoded data to obtain scrambled data; perform orthogonal frequency division multiplexing modulation on the scrambled data with the number of orthogonal frequency division multiplexing symbols contained in the interruption interval as the granularity to obtain the variable length service data part in the physical layer frame format.

[0018] In some embodiments of the present application, the device also includes a receiving module, which is used to: receive data sent in a wireless self-organizing network to obtain received data; use the first core processor in the chip to perform time-frequency synchronization and equalization processing on the fixed-length control sequence part in the received data to obtain the service data packet length and modulation and coding strategy in the received data, and calculate demodulation information based on the service data packet length and modulation and coding strategy in the received data; use the second core processor in the chip to demodulate the variable-length service data part in the received data according to the demodulation information, and decode the demodulated data obtained by demodulation to obtain a service data bit stream.

[0019] In some embodiments of the present application, the demodulation information includes the number of divisions of the coded code block and the number of orthogonal frequency division multiplexing symbols contained in each coded code block; the receiving module is used to: demodulate the coded code blocks in the variable-length service data part in turn according to the number of orthogonal frequency division multiplexing symbols contained in each coded code block, and decode them using a decoding accelerator until the demodulation and decoding of the divided number of coded code blocks are completed to obtain the service data bit stream.

[0020] According to another embodiment of the present application, a storage medium stores a computer program thereon, and when the computer program is executed by a processor of a node, the node executes the method described in the embodiment of the present application.

[0021] According to another embodiment of the present application, a node may include: a memory storing a computer program; and a processor reading the computer program stored in the memory to execute the method described in the embodiment of the present application.

[0022] According to another embodiment of the present application, a computer program product or a computer program includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in various optional implementations described in the embodiments of the present application.

[0023] In an embodiment of the present application, for a node in a wireless ad hoc network, the method includes: determining a service data packet length that matches an interruption interval and a modulation and coding strategy according to a service data recommended packet length table, wherein the interruption interval is the time interval between output interruptions when the chip uses a direct memory access controller to move data, and the modulation and coding strategy is a modulation and coding strategy for service data; generating a fixed-length control sequence portion in a physical layer frame format, wherein the fixed-length control sequence portion includes a leading sequence and a control sequence, wherein the leading sequence is used for receiving synchronization and channel estimation of a physical frame, and wherein the control sequence includes the service data packet length and the modulation and coding strategy; processing service data according to the service data packet length and the modulation and coding strategy through the chip to generate a variable-length service data portion in the physical layer frame format; starting the direct memory access controller to move the modulated data to a transceiver interface and send it in the wireless ad hoc network, wherein the modulated data consists of the fixed-length control sequence portion and the variable-length service data portion.

[0024] In this way, the service data packet length that matches the interruption interval and the modulation and coding strategy is determined according to the service data recommended packet length table, the interruption interval is the time interval between output interruptions when the chip uses a direct memory access controller to move data, and the modulation and coding strategy is the modulation and coding strategy of the service data. Furthermore, the service data can be processed by the chip according to the service data packet length and the modulation and coding strategy, thereby generating a variable-length service data part in the physical layer frame format that matches the interruption interval and the modulation and coding strategy. The modulated data consisting of the variable-length service data part and the fixed-length control sequence part is moved to the transceiver interface through the direct memory access controller and sent in the wireless ad hoc network. Taking into account the characteristics of the chip and the wireless ad hoc network, the chip using an accelerator based on the mobile communication standard protocol can be well applied to the wireless ad hoc network, thereby maximizing the throughput capacity of such chips in the wireless ad hoc network. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A flow chart of a wireless ad hoc network communication method according to an embodiment of the present application is shown.

[0027] Figure 2 A schematic diagram of chip data transfer interruption according to an example of the present application is shown.

[0028] Figure 3 A schematic diagram of a waveform physical frame format of an ad hoc network according to an example of the present application is shown.

[0029] Figure 4 A schematic diagram comparing the physical frame format of an ad hoc network waveform and chip interruption according to an example of the present application is shown.

[0030] Figure 5 A schematic diagram comparing the physical frame format of a self-organizing network waveform and chip interruption in the related art is shown.

[0031] Figure 6 A flowchart of searching for recommended length according to an embodiment of the present application is shown.

[0032] Figure 7 A schematic diagram of a multi-frame transmission processing data flow according to an embodiment of the present application is shown.

[0033] Figure 8 A schematic diagram of a multi-frame receiving and processing data flow according to an embodiment of the present application is shown.

[0034] Fig. 9 A block diagram of a wireless ad hoc network communication device according to an embodiment of the present application is shown.

[0035] Fig.10 A block diagram of a node according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0036] The present disclosure is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the embodiments provided herein are only used to explain the present disclosure and are not intended to limit the present disclosure. In addition, the embodiments provided below are partial embodiments for implementing the present disclosure, rather than providing all embodiments for implementing the present disclosure. In the absence of conflict, the technical solutions recorded in the embodiments of the present disclosure can be implemented in any combination.

[0037] It should be noted that, in the embodiments of the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a method or apparatus including a series of elements includes not only the elements explicitly recorded, but also includes other elements not explicitly listed, or also includes elements inherent to the implementation of the method or apparatus. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other related elements in the method or apparatus including the element (such as a step in the method or a unit in the apparatus, for example, a unit may be a part of a circuit, a part of a processor, a part of a program or software, etc.).

[0038] For example, the wireless ad hoc network communication method provided by the embodiment of the present disclosure includes a series of steps, but the wireless ad hoc network communication method provided by the embodiment of the present disclosure is not limited to the recorded steps. Similarly, the wireless ad hoc network communication device provided by the embodiment of the present disclosure includes a series of units, but the device provided by the embodiment of the present disclosure is not limited to including the units explicitly recorded, and may also include units required to obtain relevant information or perform processing based on information.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0040] It is understandable that in the specific implementation of this application, relevant data is involved. When the embodiments in this application are applied to specific products or technologies, user permission or consent is required, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0041] Figure 1 The flowchart of the wireless ad hoc network communication method according to an embodiment of the present application is schematically shown. The execution subject of the wireless ad hoc network communication method can be any node in the wireless ad hoc network, such as a television, a computer, a mobile phone, a smart watch, and a home appliance. In a specific embodiment of the present application, the node in the wireless ad hoc network is specifically a drone.

[0042] Nodes in wireless ad hoc networks can perform the following operations: Figure 1 The steps shown are as follows Figure 1 The wireless ad hoc network communication method shown may include steps S110 to S140.

[0043] Step S110, determining the service data packet length that matches the interruption interval and the modulation and coding strategy according to the service data recommended packet length table, wherein the interruption interval is the time interval between output interruptions when the chip uses a direct memory access controller to move data, and the modulation and coding strategy is the modulation and coding strategy of the service data; Step S120, generating a fixed-length control sequence part in the physical layer frame format, wherein the fixed-length control sequence part includes a leading sequence and a control sequence, wherein the leading sequence is used for receiving synchronization and channel estimation of the physical frame, and the control sequence includes the service data packet length and the modulation and coding strategy; Step S130, processing the service data according to the service data packet length and the modulation and coding strategy through the chip, and generating a variable-length service data part in the physical layer frame format; Step S140, starting the direct memory access controller to move the modulated data to the transceiver interface and send it in the wireless ad hoc network, wherein the modulated data consists of the fixed-length control sequence part and the variable-length service data part.

[0044] Many functions of the accelerators included in some chips are based on mobile communication standard protocols (such as LTE protocols). This protocol is based on a centralized networking communication protocol. In order to adapt to mobile communication networks with fixed time frame structures scheduled by central base stations (such as LTE networks), these chips use DMA (Direct Memory Access) controllers to move data. The way they move data is strongly related to the fixed time frame structure. That is, an interrupt is output each time data is moved, and the time interval between two interrupts (that is, the interrupt interval) is a fixed time length. For example, Figure 2 As shown, in one example the interruption interval is 1 ms.

[0045] Nodes in wireless ad hoc networks can determine the service data packet length that matches the interruption interval and modulation and coding strategy based on the service data recommended packet length table. The service data packet length is the packet length used to send service data. The interruption interval is the time interval between output interrupts when the chip in the node uses a direct memory access controller to move data. The modulation and coding strategy is the modulation method and coding rate for the current service data in the node. Therefore, the determined service data packet length takes into account the characteristics of the chip and the node.

[0046] For further information, see Figure 3 In the embodiment of the present application, the physical layer frame format is designed as follows Figure 3 As shown, the physical layer frame format includes a fixed-length control sequence part and a variable-length service data part. The fixed-length control sequence part is also a fixed-length part, and the variable-length service data part is a part whose length can be changed with the length of the service data packet.

[0047] The fixed-length control sequence part includes a preamble sequence and a control sequence. The preamble sequence is used for receiving synchronization and channel estimation of the physical frame. The control sequence may include at least necessary receiving and demodulating information such as the service data packet length and the modulation and coding strategy. The fixed-length control sequence part may be generated according to the service data packet length and the modulation and coding strategy.

[0048] Through the chip, the current business data in the node can be processed according to the business data packet length and the modulation and coding strategy to generate a variable-length business data part in the physical layer frame format, and the variable-length business data part will match the interrupt interval of the chip.

[0049] Furthermore, by starting the direct memory access (DMA) controller, the modulated data consisting of a fixed-length control sequence part and a variable-length service data part can be moved to the transceiver interface through direct memory access (DMA) and sent in the wireless ad hoc network, so that it can be received by the nodes in the wireless ad hoc network. Specifically, starting the direct memory access (DMA) controller can move the modulated data to the RF transceiver interface and transmit it from the node via the antenna. When the chip is a chip using an accelerator based on a mobile communication standard protocol, the throughput capacity of the wireless ad hoc network can be effectively improved.

[0050] In this way, the service data packet length that matches the interruption interval and the modulation and coding strategy is determined according to the service data recommended packet length table, the interruption interval being the time interval between output interruptions when the chip uses a direct memory access controller to move data, and the modulation and coding strategy is the modulation and coding strategy of the service data. Furthermore, the service data can be processed by the chip according to the service data packet length and the modulation and coding strategy, thereby generating a variable-length service data portion in the physical layer frame format that matches the interruption interval and the modulation and coding strategy. The modulated data consisting of the variable-length service data portion and the fixed-length control sequence portion is moved to the transceiver interface through the direct memory access controller and sent in the wireless ad hoc network. Taking into account the characteristics of the chip and the wireless ad hoc network, the chip using an accelerator based on a mobile communication standard protocol can be well applied to the wireless ad hoc network, thereby maximizing the throughput capacity of such chips in the wireless ad hoc network.

[0051] Described below Figure 1 When wireless ad hoc network communication is performed under the embodiment, further optional specific embodiments are provided under each step performed.

[0052] In one embodiment, before determining the service data packet length matching the interruption interval and the modulation and coding strategy according to the service data recommended packet length table, the method may further include:

[0053] Calculate the time length of the orthogonal frequency division multiplexing symbol occupied by the fixed-length control sequence part in the physical layer frame format to obtain a first time length; calculate the time length of the orthogonal frequency division multiplexing symbol occupied by the target data length under the modulation and coding strategy adopted by the service rate gear according to the number of available subcarriers of the orthogonal frequency division multiplexing symbol to obtain a second time length; calculate the sum of the first time length and the second time length to obtain a total time length; if the difference between the total time length and the interruption interval is less than the length of an orthogonal frequency division multiplexing symbol, then record the matching relationship between the service rate gear and the target data length in the service data recommended packet length table.

[0054] Orthogonal Frequency Division Multiplexing (OFDM) is a modulation technology used in digital communications. It divides the data stream into multiple subcarriers for transmission. Orthogonal frequency division multiplexing technology can be used in wireless ad hoc networks to transmit modulated data. The modulated data consists of a fixed-length control sequence part in the physical layer frame format and a variable-length service data part.

[0055] The length of the fixed-length control sequence part in the physical layer frame format is fixed, and the time length of the orthogonal frequency division multiplexing symbol (OFDM symbol) occupied by the fixed-length control sequence part can be calculated to obtain the first time length T1.

[0056] Furthermore, in the orthogonal frequency division multiplexing technology, the data stream is divided into multiple subcarriers for transmission, wherein there is a specified interval between the subcarriers, and the number of subcarriers with multiple intervals included in one orthogonal frequency division multiplexing symbol is the number of available subcarriers. According to the number of available subcarriers of the orthogonal frequency division multiplexing symbol, the time length of the orthogonal frequency division multiplexing symbol occupied by the target data length under the modulation and coding strategy adopted by the service rate gear can be calculated to obtain the second time length. For example, the time length of the orthogonal frequency division multiplexing symbol occupied by the target data length j under the modulation and coding strategy adopted by the service rate gear i can be calculated to obtain the second time length T2.

[0057] Furthermore, the sum of the first time length and the second time length is calculated to obtain the total time length; if the difference between the total time length and the interruption interval is less than the length of an orthogonal frequency division multiplexing symbol, it means that the target time length matches the interruption interval and the modulation and coding strategy adopted under the service rate gear, and the matching relationship between the service rate gear and the target data length can be recorded in the service data recommended packet length table.

[0058] Different modulation and coding strategies are used under different service rate gears. For different service rate gears, the corresponding matching relationship can be calculated and saved in the service data recommended packet length table. Furthermore, according to the matching relationship in the service data recommended packet length table, the target data length matching the current modulation and coding strategy in the node can be accurately determined as the service data packet length matching the chip interruption interval and the current modulation and coding strategy in the node.

[0059] Furthermore, determining the service data packet length that matches the interruption interval and the modulation and coding strategy based on the service data recommended packet length table may include: determining the service rate gear where the modulation and coding strategy is located in the service data recommended packet length table; and determining the target data length corresponding to the service rate gear where the modulation and coding strategy is located as the service data packet length that matches the interruption interval and the modulation and coding strategy.

[0060] In this way, after determining the service data packet length that matches the interruption interval and the modulation coding strategy according to the service data recommended packet length table, when a frame of modulated data is transmitted multiple times through a direct memory access (DMA) controller through steps S120 to S140, an interrupt is output each time the data is moved and the time interval between two interruptions (i.e., the interruption interval) is a fixed time length. However, if Figure 4 As shown, the time of the last interruption is closely aligned with the end of the frame of modulated data, which does not waste air interface time resources and improves the air interface time utilization efficiency of the system.

[0061] In the related art, see Figure 5 As shown in the figure, the last interruption time is far beyond the end of the modulated data frame. At this time, there will be a Figure 5 The idle time period shown in the figure wastes air interface time resources and reduces the air interface time utilization efficiency of the system.

[0062] For further information, see Figure 6 , calculate the time length of the orthogonal frequency division multiplexing symbol occupied by the fixed-length control sequence part in the physical layer frame format to obtain a first time length; according to the number of available subcarriers of the orthogonal frequency division multiplexing symbol, calculate the time length of the orthogonal frequency division multiplexing symbol occupied by the target data length under the modulation and coding strategy adopted by the service rate gear to obtain a second time length; calculate the sum of the first time length and the second time length to obtain the total time length; if the difference between the total time length and the interruption interval is less than the length of an orthogonal frequency division multiplexing symbol, then record the matching relationship between the service rate gear and the target data length in the service data recommended packet length table, which may specifically include steps S210 to S270.

[0063] Step S210, divide N service rate gears: each service rate gear corresponds to a modulation and coding strategy, the modulation and coding strategy includes a modulation mode and a coding rate, and different service rate gears adopt different modulation and coding strategies, that is, each service rate gear is determined by a combination of different modulation modes and coding rates. The modulation modes include but are not limited to the set {BPSK, QPSK, 16QAM, 64QAM, 256QAM, 1024QAM}; the coding rates include but are not limited to the set {1 / 3, 1 / 2, 2 / 3, 3 / 4, 5 / 6}. Different modulation modes and coding rates are combined in pairs to form N service rate gears, such as {BPSK, 1 / 2}, {QPSK, 1 / 2}, and {QPSK, 3 / 4}, which constitute three service rate gears, and so on to obtain other N service rate gears.

[0064] Step S220, calculate the length of the fixed part and set the initial data: calculate the time length of the orthogonal frequency division multiplexing symbol (OFDM symbol) occupied by the fixed-length control sequence part in the physical layer frame format, obtain the first time length L1, and set the sequence number of the service rate gear i=0, and the target data length j=1.

[0065] Step S230, calculate the variable part length and the total time length: according to the number of available subcarriers of the orthogonal frequency division multiplexing symbol, calculate the time length of the orthogonal frequency division multiplexing symbol occupied by the target data length j under the modulation and coding strategy adopted by the service rate gear i, and obtain the second time length L2; and, calculate the sum of the first time length L1 and the second time length L2 to obtain the total time length T.

[0066] Step S240, match and store the target data length j according to the difference between the total time length T and the intermediate interval G: if the difference between the total time length T and the interruption interval G is less than the length of an orthogonal frequency division multiplexing symbol, then the i-th row List[i] in the service data recommended packet length table List records the matching relationship between the service rate gear i and the target data length j; otherwise, the target data length j is not saved in the service data recommended packet length table, and the target data length j=j+1.

[0067] Step S250, determining whether the target data length j is less than the maximum allowable length M of a single frame; if so, returning to re-execute step S230; if not, executing step S260.

[0068] Step S260, searching for the recommended packet length of the next service rate gear: let service rate gear i=i+1, target data length j=1.

[0069] Step S270, determine whether the service rate gear i is less than the total number of rate gears N; if so, complete the search for recommended packet lengths under all N service rate gears, and obtain a recommended packet length table List of service data for all N service rate gears; if not, return to step S230 and start re-executing the search for service rate gear i=i+1.

[0070] In one embodiment, the chip processes the service data according to the service data packet length and the modulation and coding strategy to generate a variable-length service data portion in the physical layer frame format, which may include: calling a coding accelerator on the second core processor of the chip to perform bit-level processing on the service data to obtain coded data according to the service data packet length and the modulation and coding strategy, and sending an interrupt message to the first core processor of the chip; and starting an scrambling accelerator to perform symbol-level processing on the coded data in response to the interrupt message by the first core processor to obtain a variable-length service data portion in the physical layer frame format.

[0071] See also Figure 7 In the case of random burst services with indefinite frame lengths in wireless ad hoc networks, the two cores of the device work in parallel. For each frame, one core CP1 is responsible for "bit-level processing" and one core CP0 is responsible for "symbol-level processing", thus streamlining the physical layer processing under services with indefinite frame lengths. In the application scenario of wireless ad hoc networks with contention-based burst services, the chip processing performance is further improved to the maximum extent.

[0072] Specifically, according to the service data packet length and modulation and coding strategy, the coding accelerator is called on the second core processor CP1 of the chip to perform bit-level processing on the service data to obtain encoded data, and an interrupt message is sent to the first core processor CP0 of the chip; the first core processor CP0 responds to the interrupt message, starts the scrambling accelerator to perform symbol-level processing on the encoded data, and obtains the variable-length service data part in the physical layer frame format.

[0073] In one embodiment, calling a coding accelerator to perform bit-level processing on service data to obtain coded data may include: calling a coding accelerator to perform cyclic redundancy check, code block segmentation, encoding, and rate matching on the bit stream of the service data to obtain the coded data; correspondingly, starting a scrambling accelerator to perform symbol-level processing on the coded data to obtain a variable-length service data portion in the physical layer frame format, including: starting a scrambling accelerator to scramble the coded data to obtain scrambled data; performing orthogonal frequency division multiplexing modulation on the scrambled data with the number of orthogonal frequency division multiplexing symbols contained in the interruption interval as the granularity to obtain a variable-length service data portion in the physical layer frame format.

[0074] Specifically, on the second core processor CP1, the coding accelerator (such as Turbo code accelerator) is called to perform cyclic redundancy check (CRC check), code block segmentation, coding (such as Turbo coding) and rate matching on the bit stream of the service data to obtain the coded data. Then, on the first core processor CP0, the scrambling accelerator is started to scramble the coded data to obtain the scrambled data; the scrambled data is modulated by orthogonal frequency division multiplexing (OFDM) with the number of orthogonal frequency division multiplexing symbols contained in the interrupt interval as the granularity to obtain the variable length service data part in the physical layer frame format.

[0075] In this way, at the transmitting end of the chip, the second core processor CP1 is used to handle the transmission processing of the fixed part of the data, and the coding accelerator is called to perform CRC check, code block segmentation, encoding, and rate matching on the service data. The first core processor CP0 modulates the encoded data after the coding accelerator to realize the pipelining of CP0 and CP1. In the wireless self-organizing network non-fixed frame format time slot system, it is further beneficial to improve the system processing capability.

[0076] Furthermore, a node in the wireless ad hoc network can receive modulated data generated and sent by other nodes in the aforementioned manner to obtain received data, and the node can further demodulate the received data to obtain service data sent by other nodes.

[0077] Specifically, in one embodiment, the method may also include: receiving data sent in a wireless ad hoc network to obtain received data; using the first core processor in the chip to perform time-frequency synchronization and equalization processing on the fixed-length control sequence portion in the received data to obtain the service data packet length and modulation and coding strategy in the received data, and calculating demodulation information based on the service data packet length and modulation and coding strategy in the received data; using the second core processor in the chip to demodulate the variable-length service data portion in the received data according to the demodulation information, and decoding the demodulated data obtained by demodulation to obtain a service data bit stream.

[0078] See also Figure 8 After receiving the received data, the node inputs it into the first core processor CP0 in the chip. The first core processor CP0 performs time-frequency synchronization and equalization processing, symbol-level processing (including channel estimation, equalization, demodulation and decoding) to obtain the service data packet length and modulation and coding strategy; then, the second core processor CP1 is used to perform bit-level processing (including demodulation and decoding) to obtain the service data bit stream.

[0079] In this way, at the receiving end of the chip, CP0 is used for time-frequency synchronization and equalization processing, symbol-level processing (including channel estimation, equalization, demodulation and decoding), and CP1 is used for bit-level processing (including demodulation and decoding), further realizing the pipeline processing of received data in the wireless ad hoc network system and further improving the system processing capability.

[0080] Specifically, after receiving the received data, the node inputs it into the first core processor CP0 in the chip, and the first core processor CP0 in the chip is used to perform time-frequency synchronization and equalization processing, which may include: using a correlation accelerator to perform correlation operations on the received data to find the frame start position in the received data of the current frame, extracting the synchronization training sequence in the received data according to the frame start position to perform frequency offset estimation, and using this to perform frequency offset compensation on the data after the synchronization training sequence in the received data of the current frame. Then the first core processor CP0 performs symbol-level processing (including channel estimation, equalization, demodulation and decoding), which may include: extracting the leading sequence of the fixed-length control sequence part after frequency offset compensation for channel estimation of the control sequence to obtain a channel estimation value, and then using the channel estimation value to equalize the data in the control sequence, and demodulating the data in the equalized control sequence to obtain demodulated control domain data, and calling a decoding accelerator (such as a viterbi accelerator) to decode the demodulated control domain data to obtain the service data packet length and modulation and coding strategy; and, based on the service data packet length and modulation and coding strategy in the received data, calculating the demodulation information of the service data, and notifying the demodulation information to the second core processor CP1 in the form of a message.

[0081] Furthermore, using the second core processor CP1 to perform bit-level processing (including demodulation and decoding) may include: demodulating the variable-length service data portion in the received data according to the demodulation information, and decoding the demodulated data to obtain a service data bit stream.

[0082] In one embodiment, the demodulation information includes the number P of segmentation of the coding code block and the number of orthogonal frequency division multiplexing symbols contained in each coding code block; the variable-length service data part in the received data is demodulated according to the demodulation information, and the demodulated data is decoded to obtain a service data bit stream, which may include: according to the number of orthogonal frequency division multiplexing symbols contained in each coding code block, the coding code blocks in the variable-length service data part are demodulated in turn and decoded using a decoding accelerator until the demodulation and decoding of the segmented number of coding code blocks are completed to obtain the service data bit stream.

[0083] The second core processor CP1 sequentially demodulates the coded code blocks (e.g., Turbo code blocks) of the variable-length service data portion of the received data, and starts the decoding accelerator (e.g., Turbo accelerator) for decoding each time the demodulation of a coded code block is completed. After the decoding accelerator completes the decoding, it outputs the bit stream of the coded code block to the designated storage space. The second core processor CP1 determines whether the demodulation and decoding of P coded code blocks have been completed. If so, the bit stream of P coded code blocks (i.e., the service data bit stream) is obtained.

[0084] In order to facilitate better implementation of the wireless ad hoc network communication method provided in the embodiment of the present application, the embodiment of the present application also provides a wireless ad hoc network communication device based on the wireless ad hoc network communication method. The meanings of the terms are the same as those in the wireless ad hoc network communication method, and the specific implementation details can refer to the description in the method embodiment. Fig. 9 A block diagram of a wireless ad hoc network communication device according to an embodiment of the present application is shown.

[0085] like Fig. 9 As shown, the wireless ad hoc network communication device 300 may include: a determination module 310 may be used to: determine the service data packet length that matches the interruption interval and the modulation and coding strategy according to the service data recommended packet length table, wherein the interruption interval is the time interval between output interruptions when the chip uses a direct memory access controller to move data, and the modulation and coding strategy is the modulation and coding strategy of the service data; a first generation module 320 may be used to: generate a fixed-length control sequence part in the physical layer frame format, the fixed-length control sequence part includes a leading sequence and a control sequence, the leading sequence is used for receiving synchronization and channel estimation of the physical frame, and the control sequence includes the service data packet length and the modulation and coding strategy; a second generation module 330 may be used to: process the service data according to the service data packet length and the modulation and coding strategy through the chip, and generate a variable-length service data part in the physical layer frame format; a sending module 340 may be used to: start the direct memory access controller to move the modulated data to the transceiver interface and send it in the wireless ad hoc network, and the modulated data consists of the fixed-length control sequence part and the variable-length service data part.

[0086] In some embodiments of the present application, before determining the service data packet length that matches the interruption interval and the modulation and coding strategy based on the service data recommended packet length table, the device also includes a search module, which is used to: calculate the time length of the orthogonal frequency division multiplexing symbol occupied by the fixed-length control sequence part in the physical layer frame format to obtain a first time length; calculate the time length of the orthogonal frequency division multiplexing symbol occupied by the target data length under the modulation and coding strategy adopted by the service rate gear according to the number of available subcarriers of the orthogonal frequency division multiplexing symbol to obtain a second time length; calculate the sum of the first time length and the second time length to obtain the total time length; if the difference between the total time length and the interruption interval is less than the length of an orthogonal frequency division multiplexing symbol, then record the matching relationship between the service rate gear and the target data length in the service data recommended packet length table.

[0087] In some embodiments of the present application, the determination module is used to: determine the service rate gear where the modulation and coding strategy is located in the service data recommended packet length table; determine the target data length corresponding to the service rate gear where the modulation and coding strategy is located as the service data packet length that matches the interruption interval and the modulation and coding strategy.

[0088] In some embodiments of the present application, the second generation module is used to: call the coding accelerator on the second core processor of the chip to perform bit-level processing on the business data to obtain coded data according to the service data packet length and the modulation and coding strategy, and send an interrupt message to the first core processor of the chip; respond to the interrupt message through the first core processor, start the scrambling accelerator to perform symbol-level processing on the coded data, and obtain the variable-length service data part in the physical layer frame format.

[0089] In some embodiments of the present application, the second generation module is used to: call the encoding accelerator to perform cyclic redundancy check, code block segmentation, encoding and rate matching on the bit stream of the service data to obtain the encoded data; start the scrambling accelerator to scramble the encoded data to obtain scrambled data; perform orthogonal frequency division multiplexing modulation on the scrambled data with the number of orthogonal frequency division multiplexing symbols contained in the interruption interval as the granularity to obtain the variable length service data part in the physical layer frame format.

[0090] In some embodiments of the present application, the device also includes a receiving module, which is used to: receive data sent in a wireless self-organizing network to obtain received data; use the first core processor in the chip to perform time-frequency synchronization and equalization processing on the fixed-length control sequence part in the received data to obtain the service data packet length and modulation and coding strategy in the received data, and calculate demodulation information based on the service data packet length and modulation and coding strategy in the received data; use the second core processor in the chip to demodulate the variable-length service data part in the received data according to the demodulation information, and decode the demodulated data obtained by demodulation to obtain a service data bit stream.

[0091] In some embodiments of the present application, the demodulation information includes the number of divisions of the coded code block and the number of orthogonal frequency division multiplexing symbols contained in each coded code block; the receiving module is used to: demodulate the coded code blocks in the variable-length service data part in turn according to the number of orthogonal frequency division multiplexing symbols contained in each coded code block, and decode them using a decoding accelerator until the demodulation and decoding of the divided number of coded code blocks are completed to obtain the service data bit stream.

[0092] It should be noted that, although several modules or units of the equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units.

[0093] In addition, the present application embodiment also provides a node, such as Fig.10 As shown, Fig.10 A block diagram of a node according to an embodiment of the present application is shown, specifically:

[0094] The node may include one or more processing core processors 401, one or more computer-readable storage media memories 402, a power supply 403, an input unit 404 and other components. Those skilled in the art will appreciate that Fig.10 The node structure shown in the figure does not constitute a limitation on the node, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0095] The processor 401 is the control center of the node, and uses various interfaces and lines to connect various parts of the entire computer device. By running or executing software programs and / or modules stored in the memory 402, and calling data stored in the memory 402, the processor 401 performs various functions of the computer device and processes data, thereby monitoring the node as a whole. Optionally, the processor 401 may include one or more processing cores; preferably, the processor 401 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user pages and application programs, etc., and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 401.

[0096] The memory 402 can be used to store software programs and modules. The processor 401 executes various functional applications and data processing by running the software programs and modules stored in the memory 402. The memory 402 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 402 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices. Accordingly, the memory 402 may also include a memory controller to provide the processor 401 with access to the memory 402.

[0097] The node also includes a power supply 403 for supplying power to each component. Preferably, the power supply 403 can be logically connected to the processor 401 through a power management system, so as to manage charging, discharging, and power consumption through the power management system. The power supply 403 can also include one or more DC or AC power supplies, recharging systems, power failure detection circuits, power converters or inverters, power status indicators, and other arbitrary components.

[0098] The node may further include an input unit 404, which may be used to receive input digital or character information and generate keyboard, mouse, joystick, optical or trackball signal input related to user settings and function control.

[0099] Although not shown, the node may also include a display unit, etc., which will not be described in detail here. Specifically in this embodiment, the processor 401 in the node will load the executable file corresponding to the process of one or more computer programs into the memory 402 according to the following instructions, and the processor 401 will run the computer program stored in the memory 402, so as to realize various functions in the aforementioned embodiments of the present application, such as the processor 401 can perform the following steps:

[0100] According to the recommended packet length table of business data, determine the business data packet length that matches the interruption interval and the modulation and coding strategy, wherein the interruption interval is the time interval between output interruptions when the chip uses a direct memory access controller to move data, and the modulation and coding strategy is the modulation and coding strategy of the business data; generate a fixed-length control sequence part in the physical layer frame format, the fixed-length control sequence part includes a leading sequence and a control sequence, the leading sequence is used for receiving synchronization and channel estimation of the physical frame, and the control sequence includes the business data packet length and the modulation and coding strategy; through the chip, process the business data according to the business data packet length and the modulation and coding strategy, and generate a variable-length business data part in the physical layer frame format; start the direct memory access controller to move the modulated data to the transceiver interface and send it in the wireless ad hoc network, and the modulated data consists of the fixed-length control sequence part and the variable-length business data part.

[0101] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be completed by a computer program, or by controlling related hardware through a computer program. The computer program may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0102] To this end, an embodiment of the present application further provides a storage medium, in which a computer program is stored. The computer program can be loaded by a processor to execute the steps in any method provided in the embodiment of the present application.

[0103] The storage medium may be a computer-readable storage medium, and the storage medium may include: a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0104] Since the computer program stored in the storage medium can execute the steps in any method provided in the embodiments of the present application, the beneficial effects that can be achieved by the method provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0105] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the embodiments disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application.

[0106] It should be understood that the present application is not limited to the embodiments that have been described above and shown in the accompanying drawings, but various modifications and changes may be made without departing from the scope thereof.

Claims

1. A wireless ad hoc network communication method, characterized in that: Applied to a node in a wireless ad hoc network, the method comprises: According to the recommended packet length table of service data, determine the service data packet length that matches the interruption interval and the modulation and coding strategy, wherein the interruption interval is the time interval between output interruptions when the chip uses a direct memory access controller to move data, and the modulation and coding strategy is the modulation and coding strategy of the service data; Generate a fixed-length control sequence part in a physical layer frame format, wherein the fixed-length control sequence part includes a preamble sequence and a control sequence, wherein the preamble sequence is used for receiving synchronization and channel estimation of a physical frame, and the control sequence includes the service data packet length and the modulation and coding strategy; By means of the chip, the service data is processed according to the service data packet length and the modulation and coding strategy to generate a variable-length service data portion in the physical layer frame format; Starting the direct memory access controller to move the modulated data to the transceiver interface and transmit it in the wireless ad hoc network, wherein the modulated data consists of the fixed-length control sequence part and the variable-length service data part; The chip processes the service data according to the service data packet length and the modulation and coding strategy to generate a variable-length service data portion in the physical layer frame format, including: According to the service data packet length and the modulation and coding strategy, calling a coding accelerator on the second core processor of the chip to perform bit-level processing on the service data to obtain coded data, and sending an interrupt message to the first core processor of the chip; In response to the interrupt message, the first core processor starts a scrambling accelerator to perform symbol-level processing on the encoded data to obtain a variable-length service data portion in the physical layer frame format.

2. The method according to claim 1, characterized in that: Before determining the service data packet length matching the interruption interval and the modulation and coding strategy according to the service data recommended packet length table, the method further includes: Calculate the time length of the orthogonal frequency division multiplexing symbol occupied by the fixed-length control sequence part in the physical layer frame format to obtain a first time length; According to the number of available subcarriers of the orthogonal frequency division multiplexing symbol, calculate the time length of the orthogonal frequency division multiplexing symbol occupied by the target data length under the modulation and coding strategy adopted by the service rate gear, and obtain a second time length; Calculate the sum of the first time length and the second time length to obtain a total time length; If the difference between the total time length and the interruption interval is less than the length of an orthogonal frequency division multiplexing symbol, the matching relationship between the service rate gear and the target data length is recorded in the service data recommended packet length table.

3. The method according to claim 2, characterized in that Determining the service data packet length matching the interruption interval and the modulation and coding strategy according to the service data recommended packet length table includes: In the service data recommended packet length table, determining the service rate gear where the modulation and coding strategy is located; The target data length corresponding to the service rate gear of the modulation and coding strategy is determined as the service data packet length matching the interruption interval and the modulation and coding strategy.

4. The method according to claim 1, characterized in that: The calling of the coding accelerator to perform bit-level processing on the service data to obtain coded data includes: Invoking a coding accelerator to perform cyclic redundancy check, code block segmentation, coding, and rate matching on a bit stream of the service data to obtain the coded data; Accordingly, the startup scrambling accelerator performs symbol-level processing on the encoded data to obtain a variable-length service data portion in the physical layer frame format, including: Starting a scrambling accelerator to scramble the encoded data to obtain scrambled data; The scrambled data is subjected to OFDM modulation with the number of OFDM symbols contained in the interruption interval as the granularity to obtain a variable-length service data portion in the physical layer frame format.

5. The method according to claim 1, characterized in that The method further comprises: Receiving data sent in the wireless ad hoc network to obtain received data; Using the first core processor in the chip, performing time-frequency synchronization and equalization processing on the fixed-length control sequence part in the received data to obtain the service data packet length and modulation and coding strategy in the received data, and calculating demodulation information based on the service data packet length and modulation and coding strategy in the received data; The second core processor in the chip is used to demodulate the variable-length service data portion in the received data according to the demodulation information, and decode the demodulated data to obtain a service data bit stream.

6. The method according to claim 5, characterized in that The demodulation information includes the number of divisions of the coded code block and the number of orthogonal frequency division multiplexing symbols contained in each coded code block; The step of demodulating the variable-length service data portion in the received data according to the demodulation information, and decoding the demodulated data to obtain a service data bit stream includes: According to the number of orthogonal frequency division multiplexing symbols contained in each coded code block, the coded code blocks in the variable-length service data part are demodulated in turn and decoded using a decoding accelerator until the demodulation and decoding of the divided number of coded code blocks are completed to obtain the service data bit stream.

7. A wireless ad hoc network communication device, characterized in that: Applied to a node in a wireless ad hoc network, the device comprises: A determination module, used to: determine the service data packet length that matches the interruption interval and the modulation and coding strategy according to the service data recommended packet length table, wherein the interruption interval is the time interval between output interruptions when the chip uses a direct memory access controller to move data, and the modulation and coding strategy is the modulation and coding strategy of the service data; A first generating module is used to: generate a fixed-length control sequence part in a physical layer frame format, wherein the fixed-length control sequence part includes a leading sequence and a control sequence, wherein the leading sequence is used for receiving synchronization and channel estimation of a physical frame, and wherein the control sequence includes the service data packet length and the modulation and coding strategy; The second generation module is used to: process the service data according to the service data packet length and the modulation and coding strategy through the chip to generate a variable-length service data part in the physical layer frame format; the processing of the service data according to the service data packet length and the modulation and coding strategy through the chip to generate a variable-length service data part in the physical layer frame format includes: calling a coding accelerator on the second core processor of the chip to perform bit-level processing on the service data to obtain coded data according to the service data packet length and the modulation and coding strategy, and sending an interrupt message to the first core processor of the chip; and starting a scrambling accelerator to perform symbol-level processing on the coded data in response to the interrupt message through the first core processor to obtain a variable-length service data part in the physical layer frame format; The sending module is used to start the direct memory access controller to move the modulated data to the transceiver interface and send it in the wireless ad hoc network, wherein the modulated data consists of the fixed-length control sequence part and the variable-length service data part.

8. A storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor of a node, the node is caused to execute the method according to any one of claims 1 to 6.

9. A node, characterized in that: include: a memory storing a computer program; A processor reads a computer program stored in a memory to execute the method according to any one of claims 1 to 6.

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