Semiconductor structure manufacturing method and semiconductor structure

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure, relating to the field of semiconductor technology. The method for manufacturing the semiconductor structure includes: providing a substrate, on which bitline structures are formed, the bitline structures being spaced apart, and adjacent bitline structures being separated by trenches; forming a first doped semiconductor layer in the trenches, wherein an exposed air gap is formed in the first doped semiconductor layer; filling the exposed air gap to form a second doped semiconductor layer, wherein the doping concentration of the first doped semiconductor layer is different from the doping concentration of the second doped semiconductor layer; and the first doped semiconductor layer and the second doped semiconductor layer jointly forming a contact plug. In the present disclosure, the exposed air gap in the first doped semiconductor layer is filled with the second doped semiconductor layer, and the top surface of the contact plug formed in the trench is planar, thereby preventing the exposed air gap from affecting the top surface profile of the contact plug, thereby improving the electrical transmission performance and yield rate of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] In semiconductor manufacturing processes, conductive structures are often formed that electrically connect metal layers to semiconductor layers. The direct connection between the metal and semiconductor layers results in high contact resistance, necessitating the formation of a metal silicide layer between the semiconductor and metal layers to reduce the contact resistance. However, during the formation of the semiconductor layer, air gaps may form within the semiconductor layer. These air gaps may be exposed during the etching step, causing the metal silicide layer to fill the exposed air gaps when forming the metal silicide layer on the surface of the semiconductor layer. This results in the absence of a metal silicide layer on the surface of the semiconductor layer (e.g., CoSi2 missing), increasing the contact resistance between the semiconductor and metal layers and potentially leading to single-bit failures (SBIT FAIL). Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] A first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0006] Providing a substrate, on which bit line structures are formed, wherein the bit line structures are arranged at intervals, and adjacent bit line structures are separated by trenches;

[0007] forming a first doped semiconductor layer in the trench, wherein an exposed air gap is formed in the first doped semiconductor layer;

[0008] The exposed air gap is filled to form a second doped semiconductor layer, wherein the doping concentration of the first doped semiconductor layer is different from the doping concentration of the second doped semiconductor layer; the first doped semiconductor layer and the second doped semiconductor layer jointly form a contact plug.

[0009] Optionally, the doping concentration of the first doped semiconductor layer is greater than the doping concentration of the second doped semiconductor layer; and / or,

[0010] The first doped semiconductor layer and the second doped semiconductor layer have the same conductive doping type.

[0011] Optionally, the doping concentration of the first doped semiconductor layer is 15×e20 at / cm 3 -20×e 20 at / cm 3 The doping concentration of the second doped semiconductor layer is 6.6×e 20 at / cm 3 -7.6×e 20 at / cm 3 .

[0012] Optionally, forming a first doped semiconductor layer in the trench includes:

[0013] forming an initial first doped semiconductor layer, wherein the initial first doped semiconductor layer at least fills the trench, and an air gap is formed in the initial first doped semiconductor layer located in the trench;

[0014] A portion of the initial first doped semiconductor layer located in the trench is removed by etching, and the remaining initial first doped semiconductor layer located in the trench serves as the first doped semiconductor layer, which exposes the air gap.

[0015] Optionally, filling the exposed air gap to form a second doped semiconductor layer comprises:

[0016] forming an initial second doped semiconductor layer, wherein the initial second doped semiconductor layer at least fills the exposed air gap;

[0017] A portion of the initial second doped semiconductor layer is etched away to expose a top surface of the first doped semiconductor layer, the remaining initial second doped semiconductor layer serves as the second doped semiconductor layer, and the exposed air gap formed in the first doped semiconductor layer is filled with the second doped semiconductor layer.

[0018] Optionally, during the process of etching and removing the initial second doped semiconductor layer, the etching conditions are controlled so that the initial second doped semiconductor layer has a high etching ratio relative to the first doped semiconductor layer.

[0019] Optionally, the method for manufacturing the semiconductor structure further includes:

[0020] forming an insulating material layer, wherein the insulating material layer covers the surface of the bit line structure exposed by the contact plug and covers the top surface of the contact plug;

[0021] A portion of the insulating material layer is removed by etching to expose the top surface of the contact plug.

[0022] Optionally, the method for manufacturing the semiconductor structure further includes:

[0023] A contact layer is formed, the contact layer covering a top surface of the contact plug.

[0024] Optionally, forming a contact layer comprises:

[0025] forming a first metal material layer, wherein the first metal material layer at least covers the top surface of the contact plug;

[0026] forming a first diffusion barrier layer, wherein the first diffusion barrier layer covers the first metal material layer;

[0027] heat-treating the first metal material layer so that the first metal material layer and the contact plug react at a contact interface between the first metal material layer and the contact plug to form the contact layer on a top surface of the contact plug;

[0028] The first diffusion barrier layer and the unreacted first metal material layer are removed to expose the top surface of the contact layer.

[0029] Optionally, the method for manufacturing the semiconductor structure further includes:

[0030] A metal conductive layer is formed, the metal conductive layer covers the contact layer, and the metal conductive layer is connected to the contact plug through the contact layer.

[0031] A second aspect of the present disclosure provides a semiconductor structure, comprising:

[0032] a substrate, on which bit line structures are formed, wherein the bit line structures are arranged at intervals, and adjacent bit line structures are separated by trenches;

[0033] a contact plug disposed in each of the trenches, the contact plug comprising a first doped semiconductor layer and a second doped semiconductor layer, wherein the first doped semiconductor layer is sealed with an air gap and / or a second doped semiconductor layer is formed to fill the air gap;

[0034] The doping concentration of the first doped semiconductor layer is different from the doping concentration of the second doped semiconductor layer.

[0035] Optionally, the doping concentration of the first doped semiconductor layer is greater than the doping concentration of the second doped semiconductor layer; and / or,

[0036] The first doped semiconductor layer and the second doped semiconductor layer have the same conductive doping type.

[0037] Optionally, the doping concentration of the first doped semiconductor layer is 15×e 20 at / cm 3 -20×e 20 at / cm 3The doping concentration of the second doped semiconductor layer is 6.6×e 20 at / cm 3 -7.6×e 20 at / cm 3 .

[0038] Optionally, the semiconductor structure further includes:

[0039] A contact layer covers a top surface of the contact plug.

[0040] Optionally, the semiconductor structure further includes:

[0041] A metal conductive layer covers the contact layer, and the metal conductive layer is connected to the contact plug through the contact layer.

[0042] In the semiconductor structure manufacturing method and semiconductor structure provided by the embodiments of the present disclosure, the exposed air gap of the first doped semiconductor layer is filled with the second doped semiconductor layer, thereby preventing the air gap from being exposed to the process environment during subsequent processes; at the same time, the doping concentrations of the first doped semiconductor layer and the second doped semiconductor layer are controlled to be different, and the top surfaces of the contact plugs formed by the first doped semiconductor layer and the second doped semiconductor layer in the trench are flat, thereby preventing the exposed air gap from affecting the top surface profile of the contact plug, ensuring that a metal silicide layer is formed on the top surface of the contact plug in subsequent processes, and greatly improving the SBIT fail problem. In addition, the different doping concentrations of the first doped semiconductor layer and the second doped semiconductor layer will reduce the resistance of the contact plug to a certain extent, improve the electrical transmission performance, increase the sensing margin test yield, and improve the electrical transmission performance and yield of the semiconductor structure.

[0043] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings, which are incorporated into and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, not all embodiments. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0045] Figure 1 The figure is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0046] Figure 2 FIG. 1 is a schematic diagram showing a bit line structure disposed on a substrate according to an exemplary embodiment.

[0047] Figure 3 FIG. 1 is a schematic diagram illustrating a state after an initial first doped semiconductor layer is formed according to an exemplary embodiment.

[0048] Figure 4 FIG. 1 is a schematic diagram illustrating a state after etching the initial first doped semiconductor layer to expose a portion of the air gap according to an exemplary embodiment.

[0049] Figure 5 FIG. 1 is a schematic diagram illustrating a state after an initial second doped semiconductor layer is formed according to an exemplary embodiment.

[0050] Figure 6 FIG. 1 is a schematic diagram showing a state after forming a contact plug according to an exemplary embodiment.

[0051] Figure 7 FIG. 1 is a schematic diagram showing a state after an insulating material layer is formed according to an exemplary embodiment.

[0052] Figure 8 FIG. 1 is a schematic diagram showing a state after a portion of the insulating material layer is removed to expose the top surface of the contact layer according to an exemplary embodiment.

[0053] Figure 9 FIG. 1 is a schematic diagram showing a state after a first metal material layer is formed according to an exemplary embodiment.

[0054] Figure 10 FIG. 1 is a schematic diagram illustrating a state after a first diffusion barrier layer is formed according to an exemplary embodiment.

[0055] Figure 11 is a schematic diagram showing a state after a contact layer is formed according to an exemplary embodiment.

[0056] Figure 12 FIG. 1 is a schematic diagram illustrating a state after a second diffusion barrier layer is formed according to an exemplary embodiment.

[0057] Figure 13 FIG. 1 is a schematic diagram showing a state after a second metal material layer is formed according to an exemplary embodiment.

[0058] Figure 14 FIG. 1 is a schematic diagram showing a state after a metal conductive layer is formed according to an exemplary embodiment.

[0059] Reference numerals:

[0060] 1. Substrate; 11. Active area; 12. Isolation structure; 2. Bit line structure; 21. Bit line contact layer; 22. Bit line barrier layer; 23. Bit line conductive layer; 24. Bit line dielectric layer; 3. Insulating layer; 31. First insulating layer; 32. Second insulating layer; 33. Third insulating layer; 4. Trench; 51. First doped semiconductor layer; 51a. Initial first doped semiconductor layer; 52. Second doped semiconductor layer; 52a. Initial second doped semiconductor layer; 501. Air gap; 6. Contact plug; 7. Contact layer; 71. First metal material layer; 72. First diffusion barrier layer; 8. Metal conductive layer; 81. Second diffusion barrier layer; 82. Second metal material layer; 9. Insulating material layer. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that, in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0062] In existing methods for fabricating semiconductor structures, the process for forming a capacitor contact structure typically involves filling the trenches between adjacent bitline structures with a semiconductor dopant material and then etching the semiconductor dopant material in the trenches to form the capacitor contact structure. To ensure good electrical performance for the capacitor structure, the deposited semiconductor dopant material is doped with a high concentration of conductive ions. However, the higher the doping concentration of the semiconductor dopant material, the larger the air gap formed by the semiconductor dopant material in the trenches, which affects the electrical transmission performance of the semiconductor structure. Furthermore, during the etching process, some of the air gaps may be exposed. During the step of forming a metal silicide layer on the surface of the capacitor contact structure, the metal silicide layer may fill the exposed air gaps, resulting in a situation where the metal silicide layer is absent from the surface of the capacitor contact structure. This increases the resistance between the capacitor contact structure and the subsequently formed metal layer (M0), reducing the electrical performance of the semiconductor structure and resulting in a decrease in the yield of the semiconductor structure. Depositing a semiconductor dopant material with a low doping concentration to fill the trenches can reduce the size of the air gap formed in the trenches. However, the low doping concentration of the semiconductor dopant material has poor conductivity, which directly increases the resistance of the capacitor contact structure and also detrimentally affects the electrical transmission performance of the semiconductor structure.

[0063] To mitigate the adverse effects of air gaps formed by semiconductor doping materials in trenches on semiconductor structures, related solutions involve first depositing a layer of semiconductor doping material with a high doping concentration in the trench, followed by a layer of semiconductor doping material with a low doping concentration. After the trench is completely filled, the semiconductor material in the trench is etched to form a capacitive contact structure. This approach can reduce the size of the air gaps formed in the trench, but the air gaps still exist and are partially exposed during the etching process, resulting in a situation where the metal silicide layer is absent from the surface of the capacitive contact structure, affecting the electrical performance and yield of the semiconductor structure.

[0064] In view of this, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps: providing a substrate, on which bit line structures are formed, the bit line structures being arranged at intervals, and adjacent bit line structures being separated by trenches; forming a first doped semiconductor layer in the trenches, wherein an exposed air gap is formed in the first doped semiconductor layer; filling the exposed air gap to form a second doped semiconductor layer, wherein the doping concentration of the first doped semiconductor layer is different from the doping concentration of the second doped semiconductor layer; and the first doped semiconductor layer and the second doped semiconductor layer jointly forming a contact plug.

[0065] In an exemplary embodiment of the present disclosure, the exposed air gap of the first doped semiconductor layer is filled with the second doped semiconductor layer, thereby preventing the air gap from being exposed to the process environment during subsequent processes; at the same time, the doping concentrations of the first doped semiconductor layer and the second doped semiconductor layer are controlled to be different, and the top surfaces of the contact plugs formed by the first doped semiconductor layer and the second doped semiconductor layer in the trench are flat, thereby preventing the exposed air gap from affecting the top surface profile of the contact plug, ensuring that a metal silicide layer is formed on the top surface of the contact plug in subsequent processes, and greatly improving the SBIT fail problem. In addition, the different doping concentrations of the first doped semiconductor layer and the second doped semiconductor layer will reduce the resistance of the contact plug to a certain extent, improve the electrical transmission performance, increase the sensing margin test yield, and improve the electrical transmission performance and yield of the semiconductor structure.

[0066] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. Figure 1 As shown, Figure 1 FIG2 shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure. Figure 2-14 The schematic diagram of each stage of the semiconductor structure manufacturing method is shown below. Figure 2-14 The fabrication method of semiconductor structures is introduced.

[0067] This embodiment does not limit the semiconductor structure. The semiconductor structure will be described below using a dynamic random access memory (DRAM) as an example, but this embodiment is not limited thereto. The semiconductor structure in this embodiment may also be other structures.

[0068] like Figure 1 As shown, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0069] Step S110: providing a substrate, on which bit line structures are formed. The bit line structures are arranged at intervals, and adjacent bit line structures are separated by trenches.

[0070] Reference Figure 2 As shown, the substrate 1 includes a plurality of independently arranged active regions 11 and an isolation structure 12. The plurality of active regions 11 are arranged parallel to each other and spaced apart from each other, and the isolation structure 12 is arranged between adjacent active regions 11. The material of the active region 11 includes a semiconductor material. For example, the semiconductor material may include one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds. In this embodiment, the material of the active region 11 includes silicon. The material of the isolation structure 12 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. Each active region 11 includes a first doping region and a second doping region, and the first doping region and the second doping region are arranged at two ends of the active region 11 relative to each other. The first doping region is one of the source region or the drain region, and the second doping region is the other of the source region or the drain region.

[0071] In some embodiments, the isolation structure 12 further covers the top surface of the active region 11 to protect the active region 11 and prevent the active region 11 from being exposed to a process environment and naturally oxidized, thereby preventing electrical degradation of the active region 11 .

[0072] Reference Figure 2 As shown, each bitline structure 2 extends along a predetermined direction on the substrate 1. The bitline structure 2 and the active area 11 intersect at an angle. Multiple bitline structures 2 are arranged in parallel on the substrate 1, and each bitline structure 2 covers the central region of each active area 11 arranged along its extension direction. In some embodiments, each bitline structure 2 includes a bitline contact layer 21, a bitline barrier layer 22, a bitline conductive layer 23, and a bitline dielectric layer 24, which are sequentially stacked on the substrate 1. The material of the bitline contact layer 21 can include a semiconductor material such as polysilicon, the bitline barrier layer 22 can include titanium or titanium nitride, the bitline conductive layer 23 can include a metal material with good conductivity such as tungsten or copper, and the bitline dielectric layer 24 can include an insulating medium such as silicon nitride, but is not limited thereto.

[0073] Reference Figure 2As shown, in some embodiments, a portion of the bit line contact layer 21 in each bit line structure 2 is disposed on the substrate 1 , and another portion of the bit line contact layer 21 extends into the middle region of each active region 11 intersecting therewith.

[0074] Reference Figure 2 As shown, the surface of the bitline structure 2 is covered by an insulating layer 3. The insulating layer 3 forms trenches 4 between adjacent bitline structures 2. The trenches 4 expose the first and second doped regions of the active area 11. The insulating layer 3 may be made of at least one of silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the insulating layer 3 has a stacked structure and includes a first insulating layer 31, a second insulating layer 32, and a third insulating layer 33, which sequentially cover the surface of the bitline structure 2.

[0075] In some embodiments, a plurality of word lines (not shown in the figure) may be provided in the substrate 1 at intervals. The extension direction of the word lines is perpendicular to the extension direction of the bit line structure. Each word line runs through each active area located in its extension direction. The top surface of the word line is lower than the top surface of the active area 11. The word line is a buried word line (BWL) provided in the substrate 1.

[0076] Step S120: forming a first doped semiconductor layer in the trench, wherein an exposed air gap is formed in the first doped semiconductor layer.

[0077] In this embodiment, the first doped semiconductor layer is formed in the trench by the following implementation methods:

[0078] Step S121: forming an initial first doped semiconductor layer, wherein the initial first doped semiconductor layer at least fills the trench, and an air gap is formed in the initial first doped semiconductor layer in the trench.

[0079] like Figure 3 As shown, refer to Figure 2The initial first doped semiconductor layer 51a can be formed by any one of chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), or sputtering, or a combination of these deposition processes. The initial first doped semiconductor layer 51a covers the surface of the insulating layer 3. When filling the trench 4, air gaps 501 are formed in the initial first doped semiconductor layer 51a due to the influence of the aspect ratio of the trench 4 and the doping concentration of the initial first doped semiconductor layer 51a on the deposition process. The air gaps 501 are sealed within the trench 4. The initial first doped semiconductor layer 51a can include a semiconductor material containing silicon or germanium, for example, polycrystalline silicon. The initial first doped semiconductor layer 51a is doped with conductive ions. The conductive doping type of the initial first doped semiconductor layer 51a can be P-type or N-type, for example, phosphorus (P).

[0080] In one embodiment, an initial first doped semiconductor layer 51 a is formed, which fills the trench 4 and covers the top surface of the bit line structure 2 , and an air gap 501 is formed in the initial first doped semiconductor layer 51 a in the trench 4 .

[0081] The initial first doped semiconductor layer 51a covering the top surface of the bit line structure 2 and the initial first doped semiconductor layer 51a partially located in the trench 4 are etched away, and the initial first doped semiconductor layer 51a retained in the trench 4 serves as the first doped semiconductor layer 51a, which exposes the air gap 501.

[0082] Step S122: etching and removing a portion of the initial first doped semiconductor layer in the trench, and the remaining initial first doped semiconductor layer in the trench serves as the first doped semiconductor layer, and the air gap is exposed in the first doped semiconductor layer.

[0083] like Figure 4 As shown, refer to Figure 2 、 Figure 3 The initial first doped semiconductor layer 51a covering the top surface of the insulating layer 3 is removed by etching, and the initial first doped semiconductor layer 51a in the trench 4 is etched to a predetermined height. The initial first doped semiconductor layer 51a retained in the trench 4 serves as the first doped semiconductor layer 51, exposing the air gap 501. In this embodiment, the initial first doped semiconductor layer 51a can be etched using a dry process or a wet process.

[0084] It is understood that a plurality of trenches 4 are provided on the substrate 1, and the size and shape of the air gaps 501 formed in each trench 4 by the initial first doped semiconductor layer 51a filling each trench 4 may be the same or different. Therefore, after etching the initial first doped semiconductor layer 51a to form the first doped semiconductor layer 51, the air gaps 501 in some trenches 4 are exposed by the first doped semiconductor layer 51, while the air gaps 501 in other trenches 4 are sealed in the first doped semiconductor layer 51. Of course, in some embodiments, the air gaps 501 in all trenches 4 may be exposed by the first doped semiconductor layer 51.

[0085] Step S130: filling the exposed air gap to form a second doped semiconductor layer, wherein the doping concentration of the first doped semiconductor layer is different from the doping concentration of the second doped semiconductor layer; the first doped semiconductor layer and the second doped semiconductor layer together form a contact plug.

[0086] In this embodiment, the exposed air gaps are filled to form the second doped semiconductor layer. The following implementations may be used:

[0087] Step S131: forming an initial second doped semiconductor layer, wherein the initial second doped semiconductor layer at least fills the exposed air gaps.

[0088] like Figure 5 As shown, refer to Figure 4 The initial second doped semiconductor layer 52a can be formed by in-situ doping of a semiconductor material using a low-pressure chemical vapor deposition (LPCVD) process. The initial second doped semiconductor layer 52a completely fills the exposed air gap 501 and also covers the top surface of the first doped semiconductor layer 51 and the walls of the trench 4 exposed by the first doped semiconductor layer 51. To ensure that the initial second doped semiconductor layer 52a completely fills the exposed air gap 501, the thickness of the deposited initial second doped semiconductor layer 52a in this embodiment is greater than 3 nm. The initial second doped semiconductor layer 52a can include a semiconductor material containing silicon or germanium, for example, the initial second doped semiconductor layer 52a can include polycrystalline silicon. The initial second doped semiconductor layer 52a is doped with conductive ions, and the conductive doping type of the initial second doped semiconductor layer 52a can be P-type or N-type, for example, phosphorus (P).

[0089] It can be understood that the first doped semiconductor layer 51 and the initial second doped semiconductor layer 52a can include the same material. For example, the first doped semiconductor layer 51 and the initial second doped semiconductor layer 52a can both include polycrystalline silicon. The difference between the first doped semiconductor layer 51 and the initial second doped semiconductor layer 52a is only the different doping concentrations of conductive ions. During the etching process, a high etching selectivity can be achieved for the first doped semiconductor layer 51 and the initial second doped semiconductor layer 52a with different doping concentrations by controlling the etching conditions.

[0090] Step S132: etching and removing a portion of the initial second doped semiconductor layer to expose the top surface of the first doped semiconductor layer, the remaining initial second doped semiconductor layer serves as the second doped semiconductor layer, and the exposed air gap formed in the first doped semiconductor layer is filled with the second doped semiconductor layer.

[0091] like Figure 6 As shown, refer to Figure 2 The initial second doped semiconductor layer 52a can be etched using a dry process. During the process of etching and removing the initial second doped semiconductor layer 52a, the etching conditions are controlled so that the initial second doped semiconductor layer 52a has a high etching ratio relative to the first doped semiconductor layer 51. The initial second doped semiconductor layer 52a covering the top surface of the first doped semiconductor layer 51 and the initial second doped semiconductor layer 52a covering the groove wall exposed by the first doped semiconductor layer 51 are etched and removed, exposing the top surface of the first doped semiconductor layer. The remaining initial second doped semiconductor layer 52a serves as the second doped semiconductor layer 52, and the exposed air gap formed in the first doped semiconductor layer is filled with the second doped semiconductor layer. The second doped semiconductor layer 52 and the first doped semiconductor layer 51 together form a contact plug 6.

[0092] The first doped semiconductor layer 51 and the second doped semiconductor layer 52 have different doping concentrations. In some examples, the doping concentration of the second doped semiconductor layer 52 is greater than the doping concentration of the first doped semiconductor layer 51. In other examples, the doping concentration of the second doped semiconductor layer 52 is less than the doping concentration of the first doped semiconductor layer 51.

[0093] According to an exemplary embodiment, this embodiment is an explanation of the above embodiment. In this embodiment, the doping concentration of the first doped semiconductor layer 51 is greater than the doping concentration of the second doped semiconductor layer 52; and / or, the first doped semiconductor layer 51 and the second doped semiconductor layer 52 have the same conductive doping type.

[0094] like Figure 5 、 Figure 6 As shown, refer to Figure 2The first doped semiconductor layer 51 has a higher doping concentration, better conductivity, and lower resistance. Forming the first doped semiconductor layer 51 first in the trench 4 increases the proportion of the first doped semiconductor layer 51 in the contact plug 6, thereby reducing the resistance of the contact plug 6 and improving the electrical transmission performance of the contact plug 6. The second doped semiconductor layer 52 has a lower doping concentration, resulting in better deposition uniformity. The second doped semiconductor layer 52 is less affected by the irregular edges of the air gap 501, and the second doped semiconductor layer 52 can completely fill the exposed air gap 501.

[0095] The first doped semiconductor layer 51 and the second doped semiconductor layer 52 have the same conductive doping type, resulting in a semiconductor structure with lower resistance, which can improve the electrical transmission performance and yield of the semiconductor structure. For example, the first doped semiconductor layer 51 and the second doped semiconductor layer 52 are both P-type conductive doping types, or the first doped semiconductor layer 51 and the second doped semiconductor layer 52 are both N-type conductive doping types. In one embodiment, the doping element is phosphorus (P).

[0096] In some embodiments, the doping concentration of the first doped semiconductor layer 51 is 15×e 20 at / cm 3 -20×e 20 at / cm 3 The doping concentration of the second doped semiconductor layer 52 is 6.6×e 20 at / cm 3 -7.6×e 20 at / cm 3 .

[0097] The higher the doping concentration of the first doped semiconductor layer 51, the better the conductivity of the first doped semiconductor layer 51, the larger the size of the air gap 501 formed in the trench 4 by the first doped semiconductor layer 51 filling the trench 4, and the greater the adverse effect of the air gap 501 on the contact plug 6. In this embodiment, the doping concentration of the first doped semiconductor layer 51 is defined as 15×e 20 at / cm 3 -20×e 20 at / cm 3 The contact resistance of the formed contact plug 6 can be ensured to be small, the contact plug 6 has good conductivity, and the adverse effect of the air gap 501 on the contact plug 6 can be reduced. For example, the doping concentration of the first doped semiconductor layer 51 can be 15×e 20 at / cm 3 、15.5×e 20 at / cm 3 、16×e 20 at / cm 3 、17×e20 at / cm 3 、18×e 20 at / cm 3 、19×e 20 at / cm 3 or 20×e 20 at / cm 3 .

[0098] The lower the doping concentration of the second doped semiconductor layer 52, the better the filling effect of the exposed air gap 501. However, if the doping concentration of the second doped semiconductor layer 52 is reduced, the resistance of the second doped semiconductor layer 52 will increase, resulting in an increase in the total resistance of the contact plug 6, which will affect the electrical transmission performance of the semiconductor structure. In this embodiment, the doping concentration of the second doped semiconductor layer 52 is defined as 6.6×e 20 at / cm 3 -7.6×e 20 at / cm 3 The second doped semiconductor layer 52 can fill the exposed air gap 501, and it is also beneficial to reduce the resistance of the contact plug 6 and improve the electrical performance of the contact plug 6. For example, the doping concentration of the second doped semiconductor layer 52 can be 6.6×e 20 at / cm 3 、6.8×e 20 at / cm 3 、7×e 20 at / cm 3 、7.2×e 20 at / cm 3 , 7.4×e 20 at / cm 3 、7.5×e 20 at / cm 3 or 7.6×e 20 at / cm 3 In this embodiment, the doping concentration of the first doped semiconductor layer 51 is 15×e 20 at / cm 3 The doping concentration of the second doped semiconductor layer 52 is 7.6×e 20 at / cm 3 .

[0099] According to an exemplary embodiment, this embodiment is an explanation of the above embodiment. The method for manufacturing a semiconductor structure in this embodiment further includes the following steps:

[0100] Step S140 : forming an insulating material layer, where the insulating material layer covers the surface of the bit line structure exposed by the contact plug and covers the top surface of the contact plug.

[0101] This step is performed after step S130. During the process of etching the initial first doped semiconductor layer 51a and forming the first doped semiconductor layer 51 in the trench 4, part of the insulating layer 3 may be consumed, resulting in a reduction in the thickness of the insulating layer 3 covering the surface of the bit line structure 2, thereby reducing the isolation effect of the insulating layer 3.

[0102] like Figure 7 As shown, refer to Figure 6 In this embodiment, after forming the second doped semiconductor layer 52 to fill the exposed air gap 501, any one of the deposition processes including the atomic layer deposition process, the chemical vapor deposition process, and the physical vapor deposition process can be used to deposit and form an insulating material layer 9. The insulating material layer 9 covers the top surface of the contact plug 6 and the insulating layer 3 on the surface of the bit line structure 2 exposed by the contact plug 6. The insulating material layer 9 fills the consumed portion of the insulating layer 3.

[0103] Step S150 : etching and removing a portion of the insulating material layer to expose the top surface of the contact plug.

[0104] like Figure 8 As shown, refer to Figure 7 Dry etching or wet etching can be used to remove the insulating material layer 9 on the top surface of the contact plug 6, and the retained insulating material layer 9 fills the consumed portion of the insulating layer 3. The combination of the insulating material layer 9 and the insulating layer 3 further improves the isolation effect of the semiconductor structure, reduces the risk of leakage caused by short circuits of adjacent semiconductor devices, and improves the electrical performance and yield of the semiconductor structure.

[0105] According to an exemplary embodiment, which is an explanation of the above embodiment, the method for manufacturing a semiconductor structure further includes the following steps:

[0106] Step S160 : forming a contact layer, where the contact layer covers the top surface of the contact plug.

[0107] This step is performed after step S150. In this embodiment, the contact layer may be formed using the following implementation methods. The steps of forming the contact layer include:

[0108] Step S161: forming a first metal material layer, wherein the first metal material layer at least covers the top surface of the contact plug;

[0109] like Figure 9 As shown, refer to Figure 8The first metal material layer 71 can be formed by depositing a first metal material layer 71 using any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering processes. The first metal material layer 71 covers the top surface of the contact plug 6 and the surface of the insulating layer 3. The material of the first metal material layer 71 includes at least one of manganese (Mn), titanium (Ti), zirconium (Zr), tantalum (Ta), tungsten (W), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), and yttrium (Y). In this embodiment, the material of the first metal material layer 71 includes cobalt.

[0110] Step S162 : forming a first diffusion barrier layer, where the first diffusion barrier layer covers the first metal material layer.

[0111] like Figure 10 As shown, refer to Figure 9 Any of the above deposition processes can be used to deposit the first diffusion barrier layer 72. The first diffusion barrier layer 72 covers the top surface of the first metal material layer 71 to prevent the material in the first metal material layer 71 from diffusing into other film layers or devices during subsequent heat treatment, causing contamination. The material of the first diffusion barrier layer 72 can include titanium (Ti) or a titanium compound, or tantalum (Ta) or a tantalum compound.

[0112] Step S163 : thermally treating the first metal material layer. At a contact interface between the first metal material layer and the contact plug, the first metal material layer and the contact plug react to form a contact layer on a top surface of the contact plug.

[0113] Reference Figure 10 、 Figure 11 As shown, the semiconductor structure is thermally annealed to diffuse the material in the first metal material layer 71 into the contact plug 6 , and the material in the first metal material layer 71 reacts with the semiconductor material in the contact plug 6 to form a metal compound, thereby forming a contact layer 7 on the top surface of the contact plug 6 .

[0114] In this embodiment, the material of contact plug 6 includes polysilicon, and the material of contact layer 7 includes metal silicide. The metal component of the metal silicide is selected from at least one of the following materials: manganese, titanium, zirconium, tantalum, tungsten, palladium, platinum, cobalt, nickel, and yttrium. For example, the material of contact layer 7 may include at least one of cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), or tungsten silicide (WSi), but is not limited thereto. In this embodiment, the material of contact layer 7 includes cobalt silicon.

[0115] Step S164 : removing the first diffusion barrier layer and the unreacted first metal material layer to expose the top surface of the contact layer.

[0116] like Figure 11 As shown, refer to Figure 10 The first diffusion barrier layer 72 and the remaining first metal material layer 71 may be removed by etching using a dry process or a wet process.

[0117] In the method for manufacturing the semiconductor structure of this embodiment, the top surface of the contact plug is a flat and uniform plane, and there are no exposed air gap defects on the top surface of the contact plug. A uniform first metal material layer can be deposited on the top surface of the contact plug, and a contact layer is formed on the top surface of the contact plug after heat treatment, ensuring that the top surface of the contact plug is completely covered by the contact layer, thereby avoiding the situation where metal silicide fills the air gap, the top surface of the contact plug is missing the contact layer, or the contact layer cannot fully cover the top surface of the contact plug.

[0118] According to an exemplary embodiment, which is an explanation of the above embodiment, the method for manufacturing a semiconductor structure further includes the following steps:

[0119] Step S170: forming a metal conductive layer, wherein the metal conductive layer covers the contact layer, and the metal conductive layer is connected to the contact plug via the contact layer.

[0120] In this embodiment, the metal conductive layer may be formed by the following methods:

[0121] like Figure 12 As shown, first, any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering deposition processes can be used to form a second diffusion barrier layer 81. The second diffusion barrier layer 81 covers the contact layer 7 and the insulating material layer 9 and the insulating layer 3 exposed by the contact layer 7. The material of the second diffusion barrier layer 81 may include titanium (Ti) or a titanium compound, tantalum (Ta) or a tantalum compound.

[0122] like Figure 13 As shown, any of the above deposition processes can then be used to deposit and form a second metal material layer 82. The second metal material layer 82 covers the second diffusion barrier layer 81 and fills the unfilled area of ​​the trench 4. The material of the second metal material layer 82 can include at least one of Cu (Cu) or a copper compound, Al (Al) or an aluminum compound, and W (Tungsten) or a tungsten compound.

[0123] Reference Figure 14 As shown, the second metal material layer 82 and the second diffusion barrier layer 81 are patterned, and a metal conductive layer 8 is formed on each contact layer 7. The metal conductive layer 8 includes the second diffusion barrier layer 81 and the second metal material layer 82 sequentially covering the contact layer 7. The metal conductive layer 8 is electrically connected to the contact plug 6 through the contact layer 7.

[0124] The method for manufacturing the semiconductor structure of this embodiment uses a second doped semiconductor layer with a lower doping concentration to fill the exposed air gap, so that the top surface of each contact plug formed is flat. A contact layer with uniform thickness can be formed on the top surface of the contact plug, and a metal conductive layer is formed on the contact layer. The metal conductive layer is electrically connected to the contact plug through the contact layer, thereby reducing the contact resistance between the metal conductive layer and the contact plug, improving the electrical transmission performance and yield of the semiconductor structure, and avoiding the adverse effects of direct contact between the metal conductive layer and the top surface of the contact plug, which would increase the resistance of the semiconductor structure.

[0125] According to an exemplary embodiment, this embodiment provides a semiconductor structure, referring to Figure 6 、 Figure 11 or Figure 14 As shown, the semiconductor structure includes a substrate 1 and a contact plug 6. Bit line structures 2 are formed on the substrate 1. The bit line structures 2 are arranged at intervals. Adjacent bit line structures 2 are separated by trenches 4 (see FIG. Figure 2 ) are separated. The contact plugs 6 are provided in each trench 4 (refer to Figure 2 ), the contact plug 6 includes a first doped semiconductor layer 51 and a second doped semiconductor layer 52. An air gap 501 is sealed in the first doped semiconductor layer 51 and / or a second doped semiconductor layer 52 is formed to fill the air gap 501 (the second doped semiconductor layer 52 fills the air gap 501, that is, the contact plug 6 does not expose the air gap 501). The doping concentration of the first doped semiconductor layer 51 is different from the doping concentration of the second doped semiconductor layer 52. In some examples, the doping concentration of the second doped semiconductor layer 52 is greater than the doping concentration of the first doped semiconductor layer 51. In other examples, the doping concentration of the second doped semiconductor layer 52 is less than the doping concentration of the first doped semiconductor layer 51.

[0126] In some embodiments, reference Figure 6 、 Figure 11 or Figure 14 As shown, the doping concentration of the first doped semiconductor layer 51 is greater than the doping concentration of the second doped semiconductor layer 52; and / or the first doped semiconductor layer 51 and the second doped semiconductor layer 52 have the same conductive doping type. For example, the first doped semiconductor layer 51 and the second doped semiconductor layer 52 are both P-type conductive doping types, or the first doped semiconductor layer 51 and the second doped semiconductor layer 52 are both N-type conductive doping types. In one embodiment, the doping element is phosphorus (P).

[0127] In some embodiments, reference Figure 6 、 Figure 11 or Figure 14 As shown, the doping concentration of the first doped semiconductor layer 51 is 15×e 20 at / cm 3-20×e 20 at / cm 3 The doping concentration of the second doped semiconductor layer 52 is 6.6×e 20 at / cm 3 -7.6×e 20 at / cm 3 .

[0128] In some embodiments, reference Figure 11 or Figure 14 As shown, the semiconductor structure further includes a contact layer 7, which covers the top surface of the contact plug 6. The material of the contact layer 7 includes a metal silicide, wherein the metal component of the metal silicide is selected from at least one of the following materials: manganese (Mn), titanium (Ti), zirconium (Zr), tantalum (Ta), tungsten (W), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), and yttrium (Y). For example, the material of the contact layer 7 may include at least one of cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), or tungsten silicide (WSi), but is not limited thereto. In this embodiment, the material of the contact layer 7 includes cobalt silicon.

[0129] In some embodiments, reference Figure 14 As shown, the semiconductor structure further includes a metal conductive layer 8, which covers the contact layer 7 and is connected to the contact plug 6 via the contact layer 7. In some embodiments, the metal conductive layer 8 includes a second diffusion barrier layer 81 and a second metal material layer 82 sequentially covering the contact layer 7.

[0130] The semiconductor structure of this embodiment can be applied to dynamic random access memory (DRAM). However, it can also be applied to static random access memory (SRAM), flash EPROM, ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PRAM), etc.

[0131] In the semiconductor structure provided by the embodiment of the present disclosure, the exposed air gap of the first doped semiconductor layer is filled with the second doped semiconductor layer, thereby preventing the air gap from being exposed to the process environment and entering the subsequent process; at the same time, the doping concentrations of the first doped semiconductor layer and the second doped semiconductor layer are controlled to be different, and the top surfaces of the contact plugs formed by the first doped semiconductor layer and the second doped semiconductor layer in the trench are flat, thereby preventing the exposed air gap from affecting the top surface profile of the contact plug, ensuring that a metal silicide layer is formed on the top surface of the contact plug in the subsequent process, and greatly improving the SBIT fail problem. In addition, the different doping concentrations of the first doped semiconductor layer and the second doped semiconductor layer will reduce the resistance of the contact plug to a certain extent, improve the electrical transmission performance, increase the sensing margin test yield, and improve the electrical transmission performance and yield of the semiconductor structure.

[0132] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0133] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0134] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0135] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present disclosure.

[0136] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0137] In one or more of the accompanying drawings, identical elements are represented by similar reference numerals. For clarity, many parts in the accompanying drawings are not drawn to scale. In addition, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be described in a single figure. Many specific details of the present disclosure, such as device structure, materials, dimensions, processing techniques, and technologies, are described below to facilitate a clearer understanding of the present disclosure. However, as will be appreciated by those skilled in the art, the present disclosure may be practiced without following these specific details.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The method for manufacturing the semiconductor structure comprises: Providing a substrate, on which bit line structures are formed, wherein the bit line structures are arranged at intervals, and adjacent bit line structures are separated by trenches; forming a first doped semiconductor layer in the trench, wherein an exposed air gap is formed in the first doped semiconductor layer; The exposed air gap is filled to form a second doped semiconductor layer, wherein the doping concentration of the first doped semiconductor layer is different from the doping concentration of the second doped semiconductor layer, and the doping concentration of the first doped semiconductor layer is 15×e 20 at / cm 3 -20×e 20 at / cm 3 The doping concentration of the second doped semiconductor layer is 6.6×e 20 at / cm 3 -7.6×e 20 at / cm 3 ; The first doped semiconductor layer and the second doped semiconductor layer together form a contact plug.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The first doped semiconductor layer and the second doped semiconductor layer have the same conductive doping type.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: forming a first doped semiconductor layer in the trench, comprising: forming an initial first doped semiconductor layer, wherein the initial first doped semiconductor layer at least fills the trench, and an air gap is formed in the initial first doped semiconductor layer located in the trench; A portion of the initial first doped semiconductor layer located in the trench is removed by etching, and the remaining initial first doped semiconductor layer located in the trench serves as the first doped semiconductor layer, which exposes the air gap.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: Filling the exposed air gap to form a second doped semiconductor layer, comprising: forming an initial second doped semiconductor layer, wherein the initial second doped semiconductor layer at least fills the exposed air gap; A portion of the initial second doped semiconductor layer is etched away to expose a top surface of the first doped semiconductor layer, the remaining initial second doped semiconductor layer serves as the second doped semiconductor layer, and the exposed air gap formed in the first doped semiconductor layer is filled with the second doped semiconductor layer.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: During the process of etching and removing the initial second doped semiconductor layer, the etching conditions are controlled so that the initial second doped semiconductor layer has a high etching ratio relative to the first doped semiconductor layer.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: The method for manufacturing the semiconductor structure further includes: forming an insulating material layer, wherein the insulating material layer covers the surface of the bit line structure exposed by the contact plug and covers the top surface of the contact plug; A portion of the insulating material layer is removed by etching to expose the top surface of the contact plug.

7. The method for manufacturing a semiconductor structure according to any one of claims 1 to 6, wherein: The method for manufacturing the semiconductor structure further includes: A contact layer is formed, the contact layer covering a top surface of the contact plug.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein: forming a contact layer, comprising: forming a first metal material layer, wherein the first metal material layer at least covers the top surface of the contact plug; forming a first diffusion barrier layer, wherein the first diffusion barrier layer covers the first metal material layer; heat-treating the first metal material layer so that the first metal material layer and the contact plug react at a contact interface between the first metal material layer and the contact plug to form the contact layer on a top surface of the contact plug; The first diffusion barrier layer and the unreacted first metal material layer are removed to expose the top surface of the contact layer.

9. The method for manufacturing a semiconductor structure according to claim 7, wherein: The method for manufacturing the semiconductor structure further includes: A metal conductive layer is formed, the metal conductive layer covers the contact layer, and the metal conductive layer is connected to the contact plug through the contact layer.

10. A semiconductor structure, characterized in that The semiconductor structure comprises: a substrate, on which bit line structures are formed, wherein the bit line structures are arranged at intervals, and adjacent bit line structures are separated by trenches; a contact plug disposed in each of the trenches, the contact plug comprising a first doped semiconductor layer and a second doped semiconductor layer, wherein the first doped semiconductor layer is sealed with an air gap and / or a second doped semiconductor layer is formed to fill the air gap; The doping concentration of the first doped semiconductor layer is different from the doping concentration of the second doped semiconductor layer. The doping concentration of the first doped semiconductor layer is 15×e 20 at / cm 3 -20×e 20 at / cm 3 The doping concentration of the second doped semiconductor layer is 6.6×e 20 at / cm 3 -7.6×e 20 at / cm 3 .

11. The semiconductor structure according to claim 10, wherein: The first doped semiconductor layer and the second doped semiconductor layer have the same conductive doping type.

12. The semiconductor structure according to any one of claims 10 to 11, wherein: The semiconductor structure further comprises: A contact layer covers a top surface of the contact plug.

13. The semiconductor structure according to claim 12, wherein: The semiconductor structure further comprises: A metal conductive layer covers the contact layer, and the metal conductive layer is connected to the contact plug through the contact layer.

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