Method of manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure provides a preparation method of a semiconductor structure, relates to the technical field of semiconductors, and aims to solve the technical problem of substrate loss. The preparation method of the semiconductor structure comprises the following steps: providing a substrate, wherein the substrate has a groove; performing nitriding treatment on the substrate exposed in the groove; forming a precursor layer covering the inner wall of the groove; and oxidizing the precursor layer by an in-situ water vapor growth process to form a dielectric layer. The present disclosure is used for blocking the combination of oxygen atoms and silicon atoms in the substrate, avoiding the oxidation of the substrate, reducing the loss of the substrate, and thus improving the yield of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a preparation method of a semiconductor structure. BACKGROUND

[0002] In the process of a semiconductor structure, a patterning process is usually used to form a trench in a substrate, and then an oxidation process is used to form a dielectric layer covering the inner wall of the trench. For example, a gate trench is formed in an active region of the substrate by using a patterning process, and then a gate dielectric layer is formed in the gate trench. However, the process of forming the gate dielectric layer will oxidize part of the thickness of the substrate, causing loss of the substrate and reducing the yield of the semiconductor structure. SUMMARY

[0003] In view of the above problems, embodiments of the present disclosure provide a preparation method of a semiconductor structure for reducing the loss of the substrate and improving the yield of the semiconductor structure.

[0004] Embodiments of the present disclosure provide a preparation method of a semiconductor structure, which comprises the following steps:

[0005] providing a substrate having a trench in the substrate;

[0006] nitriding the substrate exposed in the trench;

[0007] forming a precursor layer covering the inner wall of the trench, and oxidizing the precursor layer by an in-situ water vapor growth process to form a dielectric layer.

[0008] In some embodiments, at a preset temperature, nitrogen-containing gas is introduced into the trench, and the substrate exposed in the trench is nitrided by a plasma process.

[0009] In some embodiments, the nitrogen ion concentration in the surface of the substrate close to the precursor layer is greater than the nitrogen ion concentration in the interior of the substrate.

[0010] In some embodiments, the step of nitriding the substrate exposed in the trench further comprises:

[0011] forming a barrier layer covering the inner wall of the trench.

[0012] In some embodiments, the nitrogen-containing gas comprises at least one of ammonia, nitrogen, and nitrous oxide.

[0013] In some embodiments, the flow rate of the nitrogen-containing gas is 0.5 L / min-5 L / min.

[0014] In some embodiments, the pressure of the nitrogen-containing gas is 3 torr-10 torr.

[0015] In some embodiments, the preset temperature is 700-800℃.

[0016] In some embodiments, the step of forming the precursor layer covering the inner wall of the trench comprises: forming a precursor layer on the inner wall of the trench by a deposition process, and a material of the precursor layer comprises amorphous silicon.

[0017] In the method for manufacturing the semiconductor structure provided by the embodiments of the present disclosure, the substrate exposed in the trench is subjected to a nitriding treatment, so that the substrate has nitrogen ions; when the precursor layer is oxidized by the in-situ water vapor growth process subsequently, the nitrogen ions have a blocking function, which can block the combination of oxygen atoms and silicon atoms in the substrate, so as to avoid the oxidation of the substrate and reduce the loss of the substrate, thereby improving the yield of the semiconductor structure.

[0018] In addition, the nitriding treatment on the substrate exposed in the trench also improves the uniformity of the deposited precursor layer, reduces or even avoids the formation of pin-holes in the precursor layer, and can prevent the formation of holes in the dielectric layer when the precursor layer is oxidized to form the dielectric layer by the in-situ water vapor growth process subsequently, thereby reducing the risk of electric leakage and improving the yield of the semiconductor structure.

[0019] In addition to the technical problems solved by the embodiments of the present disclosure described above, the technical features constituting the technical solutions, and the beneficial effects brought by these technical features, the other technical problems solved by the method for manufacturing the semiconductor structure provided by the embodiments of the present disclosure, the other technical features included in the technical solutions, and the beneficial effects brought by these technical features will be further described in detail in the specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, a brief introduction will be given below to the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without any creative effort.

[0021] Figure 1 Process flow chart of the method for manufacturing the semiconductor structure provided by the embodiments of the present disclosure;

[0022] Figure 2 Schematic diagram of forming the trench in the method for manufacturing the semiconductor structure provided by the embodiments of the present disclosure;

[0023] Figure 3 Schematic diagram of forming the nitriding treatment substrate in the method for manufacturing the semiconductor structure provided by the embodiments of the present disclosure Figure 1 ​

[0024] Figure 4 Schematic diagram of forming a nitridation treatment substrate in the method for manufacturing a semiconductor structure provided in the embodiments of the present disclosure Figure 2 ;

[0025] Figure 5 Schematic diagram of forming a barrier layer in the method for manufacturing a semiconductor structure provided in the embodiments of the present disclosure Figure 1 ;

[0026] Figure 6 Schematic diagram of forming a barrier layer in the method for manufacturing a semiconductor structure provided in the embodiments of the present disclosure Figure 2 ;

[0027] Figure 7 Schematic diagram of forming a precursor layer in the method for manufacturing a semiconductor structure provided in the embodiments of the present disclosure Figure 1 ;

[0028] Figure 8 Schematic diagram of forming a precursor layer in the method for manufacturing a semiconductor structure provided in the embodiments of the present disclosure Figure 2 ;

[0029] Figure 9 Schematic diagram of forming a dielectric layer in the method for manufacturing a semiconductor structure provided in the embodiments of the present disclosure Figure 1 ;

[0030] Figure 10 Schematic diagram of forming a dielectric layer in the method for manufacturing a semiconductor structure provided in the embodiments of the present disclosure Figure 2 ;

[0031] Figure 11 Schematic diagram of forming a gate structure in the method for manufacturing a semiconductor structure provided in the embodiments of the present disclosure.

[0032] Reference signs:

[0033] 100: substrate; 110: trench; 200: barrier layer; 300: precursor layer; 400: dielectric layer; 500: gate structure; 510: barrier layer; 520: conductive layer. DETAILED DESCRIPTION

[0034] As described in the background section, in related technologies, when forming a dielectric layer on the inner wall of a trench, part of the substrate is oxidized, causing damage to the substrate. The inventors have discovered that this problem arises because the formation process of the dielectric layer mainly includes the following steps: first, a precursor layer of a certain thickness is formed on the inner wall of the trench; then, the precursor layer is oxidized through an oxidation process to form the dielectric layer. However, when the precursor layer is introduced, silicon atoms in the precursor layer can epitaxially form an epitaxial layer of a certain thickness on the surface of the substrate; or, during the oxidation process, not only the precursor layer but also the substrate is oxidized. This increases the damage to the substrate, for example, shortening the distance between adjacent active regions, increasing the risk of leakage current in adjacent active regions, and reducing the yield of the semiconductor structure.

[0035] To address the aforementioned technical problems, this disclosure provides a method for fabricating a semiconductor structure. By nitriding the substrate exposed in the trench, nitrogen ions are introduced into the substrate. When the precursor layer is subsequently oxidized using an in-situ water vapor growth process, the nitrogen ions have a blocking function, preventing oxygen atoms from combining with silicon atoms in the substrate, thus avoiding substrate oxidation, reducing substrate loss, and thereby improving the yield of the semiconductor structure.

[0036] Furthermore, nitriding the substrate exposed in the trench improves the uniformity of the deposited precursor layer, reduces or even eliminates pinholes in the precursor layer, and prevents voids in the dielectric layer during the subsequent in-situ water vapor growth process to oxidize the precursor layer, thereby reducing the risk of leakage and improving the yield of the semiconductor structure.

[0037] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0038] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0039] Please refer to the attached document. Figure 1 The present disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0040] Step S100: Provide a substrate having grooves within it.

[0041] Please refer to the attached drawings Figure 2 The substrate 100 is used to support semiconductor devices arranged thereon. The substrate 100 can be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate, etc.

[0042] In the embodiment, the substrate 100 can include an array region and a peripheral region. The array region is used to arrange a plurality of memory cells and data lines (e.g., bit line structures and word line structures). Each memory cell can include a transistor and a capacitor connected to the transistor, and the capacitor is used to store data. Exemplarily, the transistor includes a gate, a source and a drain, and the source and the drain are respectively located on both sides of the gate. The gate of the transistor is connected to the word line structure, one of the source and the drain is connected to the bit line structure, and the other of the source and the drain is connected to the capacitor, for example, the source is connected to the bit line structure, and correspondingly, the drain is connected to the capacitor. The voltage signal on the word line structure can control the opening or closing of the transistor, and then the data information stored in the capacitor is read through the bit line structure, or the data information is written into the capacitor through the bit line structure for storage.

[0043] In addition, the peripheral region is provided with a logic circuit, and the logic circuit is used to be electrically connected with the data lines in the array region to realize the storage or reading of data information.

[0044] The substrate 100 has a trench 110, and the depth direction of the trench 110 is perpendicular to the substrate 100. In the embodiment, the trench 110 can be used as an isolation trench, and a shallow trench isolation structure is formed in the isolation trench to divide the substrate 100 into active regions independent of each other. It should be noted that in the embodiment, the shallow trench isolation structure can be an “ONO” structure, that is, the shallow trench isolation structure includes a silicon oxide layer, a silicon nitride layer and a silicon oxide layer arranged in layers. In addition, the shallow trench isolation structure can also be a single silicon oxide layer, or a single silicon nitride layer.

[0045] The trench 110 can also be used as a gate trench, and the gate trench can be formed in the active region, and then the gate structure or the word line structure is formed in the trench 110. In order to facilitate the description of the preparation method of the semiconductor structure, the following embodiment will be described in detail taking the trench 110 as the gate trench as an example.

[0046] Exemplarily, a mask layer (not shown in the figure) is formed on the substrate 100, and a part of the thickness of the substrate 100 is removed by a patterning process to form the trench 110 in the substrate 100. The depth direction of the trench 110 is perpendicular to the substrate 100. It should be noted that the mask layer in the embodiment can be a photoresist layer, or a combination of a photoresist layer and a hard mask layer. The hard mask layer can be a single film layer, or a laminated structure, for example, the hard mask layer can include a spin on hard mask (SOH) layer and a silicon oxynitride layer which are arranged in a stack. When the hard mask layer is a laminated structure, the accuracy of the pattern transfer process can be improved, and thus the accuracy of the trench 110 can be improved.

[0047] After the hard mask layer is formed, an anti-reflection layer (not shown in the figure) is formed on the surface of the hard mask layer away from the substrate 100. The material of the anti-reflection layer can include nitride. For example, the material of the anti-reflection layer includes silicon nitride or silicon oxynitride, but is not limited thereto. The anti-reflection layer can alleviate or eliminate the standing wave effect of the photoresist layer, so that the accuracy of transferring the mask pattern from the mask plate to the photoresist layer can be increased, and thus the accuracy in the pattern transfer process can be improved.

[0048] In the embodiment, the patterning process can be a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.

[0049] Step S200: Nitriding treatment is performed on the substrate exposed in the trench.

[0050] Please refer to the accompanying drawings Figure 3 and the accompanying drawings Figure 4 At a preset temperature, nitrogen-containing gas is introduced into the trench 110, and at least the substrate 100 exposed in the trench 110 is subjected to nitriding treatment by a plasma treatment process.

[0051] It should be noted that the accompanying drawings Figure 3 show the structure along the cross-sectional view perpendicular to the extension direction of the trench 110; the accompanying drawings Figure 4 show the structure along the cross-sectional view along the extension direction of the trench 110.

[0052] For example, a nitrogen-containing gas is introduced into the reaction chamber, and the nitrogen-containing gas is ionized or dissociated under the action of radio frequency power (power of the plasma source) to form a nitrogen-containing plasma or nitrogen ions. The nitrogen-containing plasma or nitrogen ions move towards the exposed substrate 100 to perform nitridation on at least the substrate 100 exposed in the trench 110. The nitrogen-containing plasma or nitrogen ions can penetrate into the substrate 100 or react with silicon in the substrate 100 to form a barrier layer. In this way, the nitrogen-containing plasma or nitrogen ions can be used to increase the trapping ability of the top surface of the substrate 100. For example, the nitrogen ions or nitrogen-containing plasma can trap oxygen ions to prevent the oxygen ions from penetrating into the substrate 100, thereby preventing the substrate 100 from being oxidized and damaged.

[0053] In an example, the nitrogen-containing plasma or nitrogen ions can penetrate into the substrate 100 to make the substrate 100 contain nitrogen ions. The nitrogen ions can increase the trapping ability of the surface of the substrate 100. For example, the nitrogen ions can trap oxygen ions to prevent the oxygen ions from penetrating into the substrate 100, thereby preventing the substrate 100 from being oxidized and damaged.

[0054] The concentration of the nitrogen ions in the substrate 100 can be uniform or have other options. For example, the concentration of the nitrogen ions on the surface of the substrate 100 exposed in the trench 110 is greater than the concentration of the nitrogen ions in the substrate 100. For example, the substrate 100 is shown in the orientation. Figure 3 In the orientation shown, the concentration of the nitrogen ions in the substrate 100 gradually decreases from the direction of the top surface of the substrate 100 pointing to the bottom surface, i.e., from the direction of the bottom wall of the trench 110 pointing to the bottom surface of the substrate 100. The concentration of the nitrogen ions on the surface of the substrate 100 can be ensured to be large enough, thereby ensuring the trapping ability of the surface of the substrate 100. For example, the nitrogen ions can trap oxygen ions to prevent the oxygen ions from penetrating into the substrate 100, thereby preventing the substrate 100 from being oxidized and damaged.

[0055] At the same time, the concentration of the nitrogen ions in the substrate 100 gradually decreases from the direction of one of the trenches 110 pointing to another of the trenches 110, i.e., the direction corresponding to the side wall of the trench 110. In other words, the concentration of the nitrogen ions in the substrate 100 gradually decreases in the direction perpendicular to the substrate 100 or in the horizontal direction. In this way, the concentration of the nitrogen ions on the surface of the substrate 100 can be ensured to be large enough as much as possible, thereby ensuring the trapping ability of the surface of the substrate 100. For example, the nitrogen ions can trap oxygen ions to prevent the oxygen ions from penetrating into the substrate 100, thereby preventing the substrate 100 from being oxidized and damaged.

[0056] In addition, the penetration of excessive nitrogen ions into the substrate 100 can be prevented, the conductivity of the active region of the substrate 100 can be improved, and the performance of the semiconductor structure can be improved.

[0057] Please refer to the accompanying drawings Figure 5 and the accompanying drawings Figure 6 In another example, a barrier layer is formed, and the barrier layer covers the inner wall of the trench.

[0058] Illustratively, the nitrogen ions react with silicon in the substrate 100 to form a barrier layer 200, and the barrier layer 200 covers the inner wall of the trench 110. The material of the barrier layer 200 can include any one of silicon nitride and silicon oxynitride. The material of the barrier layer 200 can also be a mixture of silicon nitride and silicon oxynitride.

[0059] In this embodiment, by forming the barrier layer 200 on the inner wall of the trench 110, the barrier layer 200 covers the inner wall of the trench 110, and the exposed substrate 100 is shielded by the barrier layer 200, avoiding the interface between the barrier layer 200 and the substrate 100 from being oxidized, thereby improving the breakdown voltage of the active region and improving the yield of the semiconductor structure.

[0060] In this embodiment, the thickness of the barrier layer 200 is 1-10 nm, and illustratively, the thickness of the barrier layer 200 is 5 nm. In this way, the barrier ability of the barrier layer 200 can be ensured, and excessive reaction of nitrogen ions with silicon in the substrate 100 can be avoided, thereby avoiding excessive consumption of the substrate 100 and improving the yield of the semiconductor structure.

[0061] Step S300: Form a precursor layer covering the inner wall of the trench, and oxidize the precursor layer by an in-situ water vapor growth process to form a dielectric layer.

[0062] Please refer to the accompanying drawings Figure 7 and the accompanying drawings Figure 8 Illustratively, the precursor layer 300 is formed by a deposition process, for example, by a chemical vapor deposition (CVD), a physical vapor deposition (PVD), or an atomic layer deposition (ALD) process, etc. The precursor layer 300 is formed on the inner wall of the trench 110. The material of the precursor layer 300 includes amorphous silicon.

[0063] It should be noted that when the inner wall of the trench 110 has the barrier layer 200, the precursor layer 300 covers the barrier layer 200, that is, the precursor layer 300 and the barrier layer 200 are stacked, and the precursor layer 300 is disposed on the side of the barrier layer 200 away from the substrate 100.

[0064] In this embodiment, since the surface of the substrate 100 is subjected to a nitridation treatment and the precursor layer 300 is deposited, the precursor layer 300 is not easy to crystallize, on the one hand, the thickness of each region of the precursor layer 300 is substantially the same, and the step coverage is high, so as to prevent the formation of pinholes in the precursor layer 300; on the other hand, the gap between adjacent crystals is reduced, which can prevent the gap between adjacent crystals from being enlarged in subsequent etching or other processes, and reduce or even avoid the formation of pinholes in the precursor layer 300. In this way, the risk of leakage of the semiconductor structure can be reduced, and the yield of the semiconductor structure is improved.

[0065] After the precursor layer 300 is formed, please refer to the following description of the embodiment and the accompanying drawings. Figure 9 and the accompanying drawings. Figure 10 The precursor layer 300 is oxidized by an in-situ water vapor growth process to form a dielectric layer 400. The material of the dielectric layer 400 includes silicon oxide, but is not limited thereto.

[0066] For example, the reaction gas is introduced into the reaction chamber, and the reaction gas generates a large number of oxidizing gas-phase active radicals, which react with the precursor layer 300 to form the dielectric layer 400.

[0067] When the material of the dielectric layer 400 is silicon oxide, the reaction gas can be a mixture of hydrogen and oxygen. When the mixture of hydrogen and oxygen as the reaction gas is transported into the reaction chamber, as the temperature rises, the hydrogen and oxygen react to generate a large number of oxidizing gas-phase active radicals, including active oxygen atoms, atomic oxygen, water molecules, and hydroxyl groups. Subsequently, these radicals participate in the oxidation process of the silicon material of the precursor layer 300.

[0068] In this embodiment, the temperature in the reaction chamber is first raised to a relatively low temperature, for example, less than 600°C, so as to reduce the generation rate of surface oxygen radicals of the precursor layer 300 to some extent, thereby reducing the reaction rate of oxygen radicals with silicon material, providing sufficient reaction time for oxygen radicals and silicon material, and ensuring that the entire precursor layer 300 is oxidized to form the dielectric layer 400. The dielectric layer 400 has high thickness uniformity, so that the structure of the dielectric layer 400 is compact, and the dielectric layer 400 has high breakdown resistance, for example, the breakdown field strength is increased to 13 MV / cm, which greatly improves the performance of the semiconductor structure.

[0069] Please refer to the following description of the embodiment and the accompanying drawings. Figure 8 After the precursor layer 300 is formed, the thickness of the region of the substrate 100 corresponding to the bottom wall of the trench 110 is denoted as D1. Please refer to the following description of the embodiment and the accompanying drawings. Figure 10After the precursor layer 300 is oxidized to form the dielectric layer 400 through the in-situ water vapor growth process, the thickness of the substrate 100 corresponding to the region of the bottom wall of the trench 110 can be denoted as D2.

[0070] After the surface of the substrate 100 exposed in the trench 110 is subjected to the nitridation treatment, the surface of the substrate 100 has nitrogen ions, which have a blocking function and can block the interface state electrons in the substrate 100 from being captured, prevent oxygen atoms from combining with silicon atoms in the substrate 100, and make D1 and D2 substantially equal. In this way, the substrate 100 can be prevented from being oxidized, the loss of the substrate 100 can be reduced, the step coverage of the dielectric layer 400 can be improved, the breakdown voltage of the dielectric layer 400 can be improved, and the stability of the electrical parameters of the semiconductor structure can be ensured, for example, the stability of the threshold voltage can be ensured and the leakage current can be reduced to improve TTDB, and the service life and reliability of the semiconductor structure can be improved.

[0071] It should be noted that in the present embodiment, D1 and D2 are substantially equal, which can be understood as D1 and D2 being strictly equal, or D1 and D2 being approximately equal, for example, the difference between D1 and D2 is within the process error, for example, the difference between D1 and D2 is within 5%.

[0072] The dielectric layer 400 is not pure silicon oxide, but can also be doped with nitrogen elements. For example, the nitrogen elements account for 20% of all elements in the dielectric layer 400. At this time, the nitrogen ions can block boron ions and phosphorus ions from diffusing to the channel region in the subsequent heat treatment process, thereby improving the conductivity of the subsequently formed gate structure.

[0073] The nitrogen ions can also increase the dielectric constant of the dielectric layer 400. The dielectric layer 400 with a high dielectric constant can increase the physical thickness of the dielectric layer 400 while keeping the gate capacitance unchanged, thereby reducing the risk of dielectric current leakage of the dielectric layer 400 and improving the reliability of the semiconductor structure. In the present embodiment, by performing the nitridation treatment on the substrate 100 exposed in the trench 110, the breakdown strength of the dielectric layer 400 can be increased to 13 Mv / cm.

[0074] In a possible implementation, the nitrogen-containing gas includes at least one of ammonia, nitrogen, and nitrous oxide. That is, the nitrogen-containing gas can be one of the above-mentioned gases alone, or a mixture of ammonia, nitrogen, and nitrous oxide. The proportion of each gas in ammonia, nitrogen, and nitrous oxide can be designed according to actual needs, which will not be described in detail herein.

[0075] For example, at a preset temperature of 700°C-800°C, such as 750°C, at least one of ammonia, nitrogen, and nitrous oxide is introduced into the reaction chamber to ensure that the reaction chamber is at a suitable temperature. This arrangement ensures that as many nitrogen ions as possible penetrate into the substrate 100, or forms the barrier layer 200 as uniformly as possible, improving the substrate 100's ability to trap interface state electrons and preventing oxygen atoms from combining with silicon atoms in the substrate 100, making D1 and D2 essentially equal. This avoids oxidizing the substrate 100, reducing excessive wear on the substrate 100, and also improves the step coverage of the dielectric layer 400, increasing the breakdown voltage of the dielectric layer 400, thereby ensuring the stability of the electrical parameters of the semiconductor structure.

[0076] In one possible implementation, nitrogen gas is continuously introduced into the reaction chamber at a flow rate of 0.5 L / min to 5 L / min under a pressure of 3 torr to 10 torr in the reaction chamber or at a pressure of nitrogen-containing gas. This forms a precursor layer 300 of a predetermined thickness on the inner wall of the trench 110, ensuring that the thickness of the subsequently formed dielectric layer 400 can be controlled. This allows the trench width to be kept at its maximum, and the device power-on power increases due to the increased trench width, resulting in greater signal resolution and improved semiconductor structure performance.

[0077] It should be noted that, in this embodiment, the substrate 100 exposed in the trench 110 can be nitrided for about two hours. This allows as many nitrogen ions as possible to penetrate into the substrate 100, or to form the barrier layer 200 as uniformly as possible. This improves the substrate 100's ability to capture interface state electrons, prevents oxygen atoms from combining with silicon atoms in the substrate 100, and makes D1 and D2 essentially equal.

[0078] In one possible implementation, after the steps of forming a precursor layer covering the inner wall of the trench and oxidizing the precursor layer by an in-situ water vapor growth process to form a dielectric layer, the semiconductor structure fabrication method further includes:

[0079] Please refer to the attached document. Figure 11 A gate structure 500 is formed in the trench 110, and the top surface of the gate structure 500 is lower than the top surface of the substrate 100.

[0080] The regions on both sides of the trench 110 are source region and drain region. The source region and the drain region can be formed by ion doping or ion diffusion process, so that the formed transistor is NMOS transistor or PMOS transistor. In an example, the conductive type of the source region and the conductive type of the drain region are both P type. For example, the source region and the drain region can be doped with P type doping ions, such as boron B or gallium Ga, etc. group III element ions, so that the formed transistor is PMOS transistor. In another example, the conductive type of the source region and the conductive type of the drain region are both N type. For example, the source region and the drain region can be doped with N type doping ions, such as phosphorus P or arsenic As, etc. group V element ions, so that the formed transistor is NMOS transistor.

[0081] In the embodiment, the top surface of the gate structure 500 is lower than the top surface of the substrate 100, which can reduce the area of the overlapping region between the gate structure 500 and the source region and the drain region, so that the gate-induced drain leakage current at the junction of the gate structure and the source region and the drain region is small, the on-current of the semiconductor structure is improved, the sensitivity of the semiconductor structure is improved, and the performance of the semiconductor structure is improved.

[0082] In a possible implementation, the gate structure 500 includes a blocking layer 510 and a conductive layer 520 which are arranged in a stack, and the conductive layer 520 fills the region surrounded by the blocking layer 510.

[0083] For example, the blocking material layer and the conductive material layer can be formed on the surface of the dielectric layer 400 by using atomic layer deposition process, the top surface of the blocking material layer and the top surface of the conductive material layer are flush, and are higher than the top surface of the dielectric layer 400. In the embodiment, the atomic layer deposition process is used to form the blocking material layer and the conductive material layer, so that the thickness uniformity of the blocking material layer and the conductive material layer can be ensured.

[0084] Then, the top surfaces of the blocking material layer and the conductive material layer can be flattened by using chemical mechanical polishing (CMP) process, so that the top surfaces of the blocking material layer and the conductive material layer are flush with the top surface of the dielectric layer 400.

[0085] Then, the etching process, such as dry etching process or wet etching process, is used to remove part of the blocking material layer and the conductive material layer in the trench 110, and the remaining blocking material layer forms the blocking layer 510, and the remaining conductive material layer forms the conductive layer 520. The blocking layer 510 and the conductive layer 520 form the gate structure 500. The top surface of the gate structure 500 is lower than the upper surface of the substrate 100, so that a groove is formed between the gate structure 500 and the top surface of the substrate 100, to facilitate the subsequent formation of the gate protection layer in the groove. The material of the gate protection layer can include silicon nitride, but is not limited thereto.

[0086] In the embodiment, the material of the blocking layer 510 can include conductive materials such as titanium nitride, which can prevent the conductive material in the conductive layer 520 from penetrating between the substrate 100 while also having conductivity, thereby ensuring the performance of the semiconductor structure. The material of the conductive layer 520 can include tungsten.

[0087] It should be noted that the above-mentioned gate structure 500 is not limited to the above structure, and can also include a first conductive layer, a blocking layer and a second conductive layer which are stacked, wherein the material of the first conductive layer includes polysilicon, and the material of the second conductive layer includes tungsten.

[0088] Please refer to the accompanying drawings Figure 11 The semiconductor structure is prepared by the preparation method of the semiconductor structure in any of the above embodiments.

[0089] When the dielectric layer 400 of the semiconductor structure is formed, the surface of the substrate 100 exposed in the trench 110 is treated by nitriding in advance, so that the surface of the substrate 100 has nitrogen ions, which have a blocking function and can block the interface state electrons in the substrate 100 from being captured, prevent the combination of oxygen atoms and silicon atoms in the substrate 100, and make D1 and D2 substantially equal. In this way, the oxidation of the substrate 100 can be avoided, the excessive loss of the substrate 100 can be reduced, the step coverage of the dielectric layer 400 can be improved, the breakdown voltage of the dielectric layer 400 can be improved, and the stability of the electrical parameters of the semiconductor structure can be ensured, such as the stability of the threshold voltage and the reduction of the leakage current to improve TTDB, thereby improving the service life of the semiconductor structure.

[0090] The embodiments or implementations in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0091] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0092] In the present specification, the exemplary expressions of the above terms do not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in an appropriate manner.

[0093] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate with a trench formed therein; nitriding the substrate exposed in the trench to form a barrier layer covering the inner wall of the trench; forming a precursor layer covering the inner wall of the trench, the precursor layer conformally covering the barrier layer, and oxidizing the precursor layer by an in-situ water vapor growth process to form a dielectric layer with a breakdown field strength of 13 MV / cm; after forming the precursor layer and before forming the dielectric layer, the thickness of the region of the substrate corresponding to the bottom wall of the trench is D1, and after forming the dielectric layer, the thickness of the region of the substrate corresponding to the bottom wall of the trench is D2, wherein the D1 is equal to the D2; forming a gate structure in the trench, the top surface of the gate structure being lower than the top surface of the substrate.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: introducing a nitrogen-containing gas into the trench at a preset temperature, and nitriding the substrate exposed in the trench by a plasma process.

3. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: The nitrogen ion concentration in the surface of the substrate close to the precursor layer is greater than the nitrogen ion concentration in the interior of the substrate.

4. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: The nitrogen-containing gas comprises at least one of ammonia, nitrogen, and nitrous oxide.

5. The method of producing a semiconductor structure according to any one of claims 2 to 4, wherein The flow rate of the nitrogen-containing gas is 0.5 L / min-5 L / min.

6. The method of producing a semiconductor structure according to any one of claims 2 to 4, wherein The pressure of the nitrogen-containing gas is 3 torr-10 torr.

7. The method of producing a semiconductor structure according to any one of claims 2 to 4, wherein The preset temperature is 700°C-800°C.

8. The method of claim 1-4, wherein The step of forming the precursor layer covering the inner wall of the trench comprises: forming the precursor layer on the inner wall of the trench by a deposition process, the material of the precursor layer comprising amorphous silicon.

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