Audio interface reverse power supply circuit and power supply method

Abstract

The present invention discloses an audio interface reverse power supply circuit and a power supply method, comprising an identification unit, a conversion unit and a power-on unit. The identification unit inputs a power supply start signal through a Port_4 port, inputs a power supply voltage required by an RC receiver load through a Port_3 port, and outputs an identification signal through a Port_1 port. After receiving the identification signal, the conversion unit converts the power supply into a power supply voltage and outputs it to the Port_3 port. At the same time, the power-on unit detects the power-on state through the Port_1 port, and feeds back a signal to the conversion unit through a Port_2 port. The conversion unit starts progress detection, and outputs a power supply start signal to the Port_4 port after the detection is completed. The identification unit starts the power supply of the RC receiver load.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply regulation, and in particular to an audio interface reverse power supply circuit and a power supply method. Background Art

[0002] USB can be used as a standard audio interface for data and power transmission between electronic devices. Different versions of the interface have different power supply voltages. For example, the power extension introduced by USB3.1 can support a maximum charging power of 100W, which can greatly increase the charging efficiency while transmitting audio data. Higher versions of USB data cables, in addition to being compatible with the TYPE-C interface, can support a maximum of 48V fast charging. There are many types of devices on the market that can be connected via USB, and the supported USB versions are also different. When using USB data cables to interconnect Bluetooth speakers, mobile phones, laptops and other electronic devices, it is necessary to check the reverse withstand voltage and power supply parameters between the sending device and the receiving device. If they are too high, the reverse power supply function needs to be turned off to avoid damage to the low-voltage side equipment caused by overvoltage. Summary of the invention

[0003] In view of the above technical problems, the purpose of the present invention is to provide an audio interface reverse power supply circuit, including an identification unit, a conversion unit, and a power-on unit. The identification unit inputs a power supply start signal through the Port_4 port, inputs the power supply voltage required by the RC receiver load through the Port_3 port, and outputs the identification signal through the Port_1 port. After receiving the identification signal, the conversion unit converts the power supply into the power supply voltage and outputs it to the Port_3 port. At the same time, the power-on unit detects the power-on status through the Port_1 port, and the feedback signal is input to the conversion unit through the Port_2 port. The conversion unit starts progress detection and outputs a power supply start signal to the Port_4 port after the detection is completed. The identification unit starts the power supply of the RC receiver load.

[0004] Further, the conversion unit includes a second operational amplifier U2, a third digital potentiometer U3, a fourth AND gate U4, a first transistor Q1, a second transistor Q2, a third field effect transistor Q3, a fourth thyristor Q4, a fifth thyristor Q5, a first resistor R1, a third resistor R3, a fourth resistor R4, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11;

[0005] The collector of the first transistor Q1, the collector of the second transistor Q2, the source of the third field effect transistor Q3, one end of the first resistor R1, one end of the third resistor R3, the first pin of the third digital potentiometer U3, the eighth pin of the third digital potentiometer U3 and the power supply are connected, the base of the first transistor Q1 is connected to Port_2, the emitter of the first transistor Q1 is connected to the anode of the fourth thyristor Q4 and the anode of the fifth thyristor Q5, the emitter of the second transistor Q2 is connected to the control electrode of the fourth thyristor Q4 and one end of the seventh resistor R7, the base of the second transistor Q2 is connected to the second pin of the third digital potentiometer U3, the gate of the third field effect transistor Q3, the output end of the second operational amplifier U2 and one end of the tenth resistor R10, the drain of the third field effect transistor Q3 is connected to one end of the fourth resistor R4 and the control electrode of the fifth thyristor Q5, the cathode of the fourth thyristor Q4 is connected to the first connection end of the fourth AND gate U4 and one end of the eleventh resistor R11 The cathode of the fifth thyristor Q5 is connected to the second connection end of the fourth AND gate U4 and one end of the ninth resistor R9, the in-phase end of the second operational amplifier U2, the other end of the first resistor R1 and the Port_1 end, and the first connector P1 end are connected, the inverting end of the second operational amplifier U2, the other end of the third resistor R3, the third pin of the third digital potentiometer U3 and the Port_3 end, and the first connector P1 end are connected, the seventh pin of the third digital potentiometer U3, the output end of the fourth AND gate U4, one end of the eighth resistor R8 and the Port_4 end, and the first connector P1 end are connected, the fourth pin of the third digital potentiometer U3, the fifth pin of the third digital potentiometer U3, the sixth pin of the third digital potentiometer U3, the other end of the fourth resistor R4, the other end of the seventh resistor R7, the other end of the eighth resistor R8, the other end of the ninth resistor R9, the other end of the tenth resistor R10, the other end of the eleventh resistor R11 and the ground end are connected.

[0006] Further, the another conversion unit includes a fifth operational amplifier U5, a sixth operational amplifier U6, a seventh digital potentiometer U7, a seventh transistor Q7, a twelfth resistor R12, a thirteenth resistor R13, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, and a first capacitor C1;

[0007] The collector of the seventh transistor Q7, one end of the sixteenth resistor R16, one end of the seventeenth resistor R17, the first pin of the seventh digital potentiometer U7, the eighth pin of the seventh digital potentiometer U7 and the power supply are connected, the base of the seventh transistor Q7 is connected to the Port_2 end, the emitter of the seventh transistor Q7 is connected to one end of the twelfth resistor R12, the in-phase end of the fifth operational amplifier U5 is connected to the other end of the twelfth resistor R12, one end of the thirteenth resistor R13, and one end of the first capacitor C1, the output end of the fifth operational amplifier U5, the seventh pin of the seventh digital potentiometer U7, one end of the nineteenth resistor R19 and the Port_4 end and the first connector P1 end are connected, and the sixth operational amplifier U5 is connected to the output end of the fifth operational amplifier U5, the seventh pin of the seventh digital potentiometer U7, one end of the nineteenth resistor R19 and the Port_4 end and the first connector P1 end. The in-phase end of the amplifier U6, the other end of the sixteenth resistor R16 are connected to the Port_1 end and the first connector P1 end, the inverting end of the sixth operational amplifier U6, the third pin of the seventh digital potentiometer U7 are connected to the Port_3 end and the first connector P1 end, the output end of the sixth operational amplifier U6 is connected to the second pin of the seventh digital potentiometer U7 and one end of the eighteenth resistor R18, the fourth pin of the seventh digital potentiometer U7, the fifth pin of the seventh digital potentiometer U7, the sixth pin of the seventh digital potentiometer U7, the other end of the thirteenth resistor R13, the other end of the eighteenth resistor R18, the other end of the nineteenth resistor R19, the other end of the first capacitor C1 and the ground end are connected.

[0008] Furthermore, the identification unit includes a sixth field effect transistor Q6 and a sixth resistor R6;

[0009] The gate of the sixth field effect transistor Q6, the drain of the sixth field effect transistor Q6, one end of the sixth resistor R6 are connected to the first connector P1 end, and the source of the sixth field effect transistor Q6 and the other end of the sixth resistor R6 are connected to the first connector P1 end via RC.

[0010] Further, the power-on unit includes a first operational amplifier U1;

[0011] The output terminal of the first operational amplifier U1 is connected to the Port_2 terminal, and the inverting terminal of the first operational amplifier U1 is connected to the Port_1 terminal.

[0012] Furthermore, the power-on unit further includes a second resistor R2 and a fifth resistor R5;

[0013] One end of the second resistor R2 is connected to the power supply, the other end of the second resistor R2 is connected to one end of the fifth resistor R5 and the in-phase terminal of the first operational amplifier U1, and the other end of the fifth resistor R5 is connected to the ground.

[0014] Furthermore, the conversion unit further includes a fourteenth resistor R14 and a fifteenth resistor R15;

[0015] One end of the fourteenth resistor R14 is connected to the power supply, the other end of the fourteenth resistor R14 is connected to one end of the fifteenth resistor R15 and the inverting end of the fifth operational amplifier U5, and the other end of the fifteenth resistor R15 is connected to the ground.

[0016] The present invention also provides an audio interface reverse power supply method, comprising the following steps:

[0017] S1: Obtain the information of the reverse powered device through the identification resistor;

[0018] S2: After power-on, sample the resistance value of the identification resistor and convert the power supply voltage into the power supply voltage required by the receiver load based on the resistance value;

[0019] S3: Monitor the conversion process to avoid overvoltage, and stop sampling the resistance value of the identification resistor and the power supply voltage after the conversion is completed.

[0020] S4: Check the power-on status and reset the conversion progress after power failure.

[0021] Compared with the prior art, the present invention can automatically convert the power supply voltage into the power supply voltage required by the receiver load according to the identification resistor after power-on, and avoid overvoltage faults within an adjustable range.

[0022] In addition, the progress of the conversion can be detected to avoid power supply failure during the conversion process and secondary regulation of the receiver load voltage drop after power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 The present invention provides an overall structural diagram.

[0025] Figure 2 This is a schematic diagram of the reverse power supply circuit provided by the present invention.

[0026] Figure 3 This is another schematic diagram of a reverse power supply circuit provided by the present invention. DETAILED DESCRIPTION

[0027] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0028] In the present invention, the identification unit is a user-side audio interface, the power-on unit and the conversion unit are power supply and audio interfaces, and the two sides are connected by an audio line through the first connector P1. After the audio line is plugged in, the two ends of the first connector P1 are connected, the power-on unit and the conversion unit sample the connection voltage of the Port_1 port, and the conversion unit converts the VCC power supply into the power supply voltage required by the user side based on its connection end voltage and inputs it to the sixth field effect transistor Q6 power supply end of the identification unit through the Port_4 port. At the same time, the power-on unit feeds back a power-on signal to the conversion unit through the Port_2 port to start conversion progress detection. After the conversion is completed, the conversion unit inputs a power supply start signal and feeds back to the sixth field effect transistor Q6 of the identification unit through the Port_3 port to start power supply, thereby avoiding power supply before the conversion process, and stopping self-regulation at the same time, thereby avoiding secondary regulation of the receiver load voltage drop after power supply. After the power supply is disconnected, the power-on unit feeds back a signal to the conversion unit through the Port_2 port to reset the conversion progress.

[0029] The sixth resistor R6 in the identification unit is an identification resistor, and its resistance value is factory set according to the power supply voltage required by the user-side receiver load. The sixth field effect transistor Q6 is a power switch used to start power supply, and RC is the receiver load; the first resistor R1 in the conversion unit is a matching resistor, which is used to cooperate with the sixth resistor R6 for sampling. The resistance value of the first resistor R1 is an integer and fixed, and the value of the sixth resistor R6 is Y / [(XY) / R1], where X is the power supply voltage of the power supply, and Y is the voltage required by the user-side receiver load. For example, the power supply is 12V, and the user side requires 3.3V power supply. The first resistor R1 is 10K, then the resistance value of the sixth resistor R6 = 3.3 / [(12-3.3) / 10]; the in-phase terminal of the first operational amplifier U1 in the power-on unit is used to set the power-on reference signal, and the signal amplitude is close to and lower than the power supply voltage, and higher than the maximum required power supply voltage required by the user side. After detection, the first operational amplifier U1 outputs a signal to the base of the first transistor Q1 of the conversion unit.

[0030] In one embodiment, a conversion method is provided to avoid overvoltage power supply, and the smaller the voltage required by the receiver load is from the power supply voltage, the faster the startup is, wherein the conversion unit supplies power to the user side through the connection end of the third digital potentiometer U3 and the third resistor R3, the in-phase end of the second operational amplifier U2 is used to sample the voltage at the connection end of the first resistor R1 and the sixth resistor R6, the inverting end of the second operational amplifier U2 is used to sample the voltage at the connection end of the third digital potentiometer U3 and the third resistor R3, and the control signal is fed back to the second pin of the third digital potentiometer U3, and the fifth pin of the third digital potentiometer U3 is adjusted from the third pin or the sixth pin, so as to improve the The voltage between the third pin of the third digital potentiometer U3 and the connection end of the third resistor R3 is changed. During the adjustment conversion process and the initial state, the sixth field effect transistor Q6 is not powered. At the same time, the output end signal of the second operational amplifier U2 is also input to the gate of the third field effect transistor Q3 and the base of the second transistor Q2. Assuming that the current user-side power supply voltage is lower than the conversion voltage adjusted by the current third resistor R3 and the third pin connection end of the third digital potentiometer U3 after power-on, the second operational amplifier U2 outputs, the third field effect transistor Q3 is turned off, and the second transistor Q2 is turned on (conversely, the third field effect transistor Q3 is turned on and the second transistor Q2 is turned off), and the second transistor Q 2 is turned on, the power supply is fed back to the control electrode of the fourth thyristor Q4 through the collector, emitter, seventh resistor R7 and grounding loop of the second triode Q2, and the signal of the connecting terminal of the seventh resistor R7 and the second triode Q2 emitter is fed back to the control electrode of the fourth thyristor Q4, and there is current from the control electrode of the fourth thyristor Q4 to the cathode and the fourth thyristor Q4 is turned on after passing through the loop of the eleventh resistor R11, and the signal of the terminal of the eleventh resistor R11 is fed back to the fourth AND gate U4, and after the third digital potentiometer U3 is adjusted to convert the power supply voltage of the third pin of the third digital potentiometer U3 and the connecting terminal of the third resistor R3 to the power supply voltage required by the user side, the second operational amplifier U2 is turned off, the third field effect transistor Q3 is turned on, and the power supply is turned on. Through the source of the third field effect transistor Q3, the fourth resistor R4, and the ground loop, the voltage at the terminal of the fourth resistor R4 is input to the control electrode of the fifth thyristor Q5, the fifth thyristor Q5 is turned on, and the signal at the terminal of the ninth resistor R9 is fed back to the fourth AND gate U4. The output signal of the fourth AND gate U4 is fed back to the gate of the sixth field effect transistor Q6 via P7, the sixth field effect transistor Q6 is turned on for power supply, and the other signal is input to the seventh pin of the third digital potentiometer U3, the third digital potentiometer U3 stops regulating, and when the audio line plugged into the first connector P1 is disconnected, the first operational amplifier U1 detects and stops outputting, the first transistor Q1 is disconnected, and the third digital potentiometer U3 is reset.

[0031] In one embodiment, another conversion method is provided, which is lower in cost than the first method. When the first connector P1 is plugged in, the first operational amplifier U1 outputs a signal to the base of the seventh transistor Q7, and the collector power supply of the seventh transistor Q7 is pulled up through the twelfth resistor R12 and the first capacitor C1, and the power supply of the converted voltage is delayed. During the delay process, the seventh digital potentiometer U7 is regulated by the sixth operational amplifier U6. The in-phase terminal of the sixth operational amplifier U6 collects the voltage at the connection terminal of the sixteenth resistor R16 and the sixth resistor R6, and feeds back the control signal to the second pin of the seventh digital potentiometer U7. The fifth pin of the seventh digital potentiometer U7 is adjusted from the third pin or the sixth pin to change the third pin of the seventh digital potentiometer U7. The voltage at the connection terminal of the pin and the seventeenth resistor R17, during the adjustment conversion process and the initial state, the sixth field effect tube Q6 is cut off and no power is supplied, and a delayed reference signal is set at the inverting terminal of the fifth operational amplifier U5. When the voltage at the first capacitor C1 terminal sampled at the inverting terminal of the fifth operational amplifier U5 is greater than the delayed reference signal set at the inverting terminal, the output signal of the fifth operational amplifier U5 is fed back to the seventh pin of the seventh digital potentiometer U7 in one way, and is input to the gate of the sixth field effect tube Q6 through the first connector P1 in the other way. After the sixth field effect tube Q6 is turned on, it supplies power to the RC receiver load. In addition to the voltage division setting, the reference voltage set at the inverting terminal of the first operational amplifier U1 and the inverting terminal of the fifth operational amplifier U5 can also be provided by the upper signal. It should be noted that the startup speed can also be set by the initial voltage. The initial voltage shown in the attached figure is the VCC power supply voltage or 0V. When the startup speed needs to be increased, the output of the first operational amplifier U1 in the power-on unit can be controlled by controlling the conversion switch (not shown in the attached figure), wherein the common end of the conversion switch is connected to the inverting end of the sixth operational amplifier U6, and one of the other two ends is normally connected to Port_3, and the other end is connected to the initial voltage. The initial voltage can be applied to both conversion modes.

[0032] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. An audio interface reverse power supply circuit, characterized in that: It includes an identification unit, a conversion unit, and a power-on unit. The identification unit inputs a power supply start signal through a Port_4 port, inputs a power supply voltage required by an RC receiver load through a Port_3 port, and outputs an identification signal through a Port_1 port. After receiving the identification signal, the conversion unit converts the power supply into a power supply voltage and outputs it to a Port_3 port. At the same time, the power-on unit detects the power-on state through a Port_1 port, and inputs a feedback signal to the conversion unit through a Port_2 port. The conversion unit starts progress detection, and outputs a power supply start signal to a Port_4 port after the detection is completed. The identification unit starts the power supply of the RC receiver load. The conversion unit includes a second operational amplifier, a third digital potentiometer, a fourth AND gate, a first transistor, a second transistor, a third field effect transistor, a fourth thyristor, a fifth thyristor, a first resistor, a third resistor, a fourth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor. The collector of the first triode, the collector of the second triode, the source of the third field effect transistor, one end of the first resistor, one end of the third resistor, the first pin of the third digital potentiometer, the eighth pin of the third digital potentiometer and the power supply are connected, the base of the first triode is connected to the Port_2 end, the emitter of the first triode is connected to the anode of the fourth thyristor and the anode of the fifth thyristor, the emitter of the second triode is connected to the control electrode of the fourth thyristor and one end of the seventh resistor, the base of the second triode is connected to the second pin of the third digital potentiometer, the gate of the third field effect transistor, the output end of the second operational amplifier and one end of the tenth resistor, the drain of the third field effect transistor is connected to one end of the fourth resistor and the control electrode of the fifth thyristor, and the cathode of the fourth thyristor is connected to the first connection end of the fourth AND gate and one end of the eleventh resistor , the cathode of the fifth thyristor is connected to the second connection end of the fourth AND gate and one end of the ninth resistor, the in-phase end of the second operational amplifier, the other end of the first resistor, the Port_1 end, and the first connector end are connected, the inverting end of the second operational amplifier, the other end of the third resistor, the third pin of the third digital potentiometer, the Port_3 end, and the first connector end are connected, the seventh pin of the third digital potentiometer, the output end of the fourth AND gate, one end of the eighth resistor, the Port_4 end, and the first connector end are connected, the fourth pin of the third digital potentiometer, the fifth pin of the third digital potentiometer, the sixth pin of the third digital potentiometer, the other end of the fourth resistor, the other end of the seventh resistor, the other end of the eighth resistor, the other end of the ninth resistor, the other end of the tenth resistor, the other end of the eleventh resistor and the ground end are connected.

2. The audio interface reverse power supply circuit according to claim 1, characterized in that: The conversion unit includes a fifth operational amplifier, a sixth operational amplifier, a seventh digital potentiometer, a seventh transistor, a twelfth resistor, a thirteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, and a first capacitor; The collector of the seventh transistor, one end of the sixteenth resistor, one end of the seventeenth resistor, the first pin of the seventh digital potentiometer, and the eighth pin of the seventh digital potentiometer are connected to the power supply, the base of the seventh transistor is connected to the Port_2 end, the emitter of the seventh transistor is connected to one end of the twelfth resistor, the in-phase end of the fifth operational amplifier is connected to the other end of the twelfth resistor, one end of the thirteenth resistor, and one end of the first capacitor, the output end of the fifth operational amplifier, the seventh pin of the seventh digital potentiometer, one end of the nineteenth resistor, the Port_4 end, and the first connector end, the in-phase end of the sixth operational amplifier, the other end of the sixteenth resistor, the Port_1 end, and the first connector end, the inverting end of the sixth operational amplifier, the third pin of the seventh digital potentiometer, the Port_3 end, and the first connector end, the output end of the sixth operational amplifier is connected to the second pin of the seventh digital potentiometer and one end of the eighteenth resistor, the fourth pin of the seventh digital potentiometer, the fifth pin of the seventh digital potentiometer, the sixth pin of the seventh digital potentiometer, the other end of the thirteenth resistor, the other end of the eighteenth resistor, the other end of the nineteenth resistor, the other end of the first capacitor, and the ground end.

3. The audio interface reverse power supply circuit according to claim 1, characterized in that: The identification unit includes a sixth field effect transistor and a sixth resistor; The gate of the sixth field effect tube, the drain of the sixth field effect tube, one end of the sixth resistor and the first connector end are connected, and the source of the sixth field effect tube and the other end of the sixth resistor are connected to the first connector end via RC.

4. The audio interface reverse power supply circuit according to claim 1, characterized in that: The power-on unit includes a first operational amplifier; The output terminal of the first operational amplifier is connected to the Port_2 terminal, and the inverting terminal of the first operational amplifier is connected to the Port_1.

5. The audio interface reverse power supply circuit according to claim 4, characterized in that: The power-on unit further includes a second resistor and a fifth resistor; One end of the second resistor is connected to the power supply, the other end of the second resistor is connected to one end of the fifth resistor and the in-phase terminal of the first operational amplifier, and the other end of the fifth resistor is connected to the ground terminal.

6. The audio interface reverse power supply circuit according to claim 2, characterized in that: The conversion unit further includes a fourteenth resistor and a fifteenth resistor; One end of the fourteenth resistor is connected to the power supply, the other end of the fourteenth resistor is connected to one end of the fifteenth resistor and the inverting end of the fifth operational amplifier, and the other end of the fifteenth resistor is connected to the ground.

7. A method for reverse power supply of an audio interface, using the reverse power supply circuit of the audio interface according to any one of claims 1 to 6, characterized in that: The steps include: S1: Obtain the information of the reverse powered device through the identification resistor; S2: After power-on, sample the resistance value of the identification resistor and convert the power supply voltage into the power supply voltage required by the receiver load based on the resistance value; S3: Monitor the conversion process to avoid overvoltage, and stop sampling the resistance value of the identification resistor and the power supply voltage after the conversion is completed; S4: Check the power-on status and reset the conversion progress after power failure.

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