Flash memory data processing method, device, equipment and storage medium

Abstract

The embodiments of the present disclosure provide a flash memory data processing method, device, equipment and storage medium. The method includes: based on the data processing task to be executed, sending a corresponding first data processing command to a first flash memory connected to the SOC chip, then switching the flash memory connected to the SOC chip based on an analog switch, and sending a corresponding data processing command to the switched flash memory, and then repeatedly switching the flash memory and sending data processing commands to the switched flash memory until all data processing commands corresponding to the data processing task are completed. The technical solution of the embodiments of the present disclosure solves the problem in the related art that data processing based on flash memory needs to wait for data interaction between the flash memory cache and the storage array, which makes the embedded system data processing efficiency low, and improves the working efficiency of the embedded system.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing technology, and in particular to a flash memory data processing method, device, equipment and storage medium. Background Art

[0002] In the field of embedded systems, combining an embedded system chip SOC (hereinafter referred to as SOC chip) with SPI NAND flash memory (hereinafter referred to as flash memory) to complete data processing (such as data reading, writing and storage) is a very common hardware configuration method for embedded systems. Among them, the system files and important program data in the embedded system will be stored in the flash memory. When the embedded system starts, the SOC chip will send a control command to the flash memory to read data from the flash memory or write data to the flash memory to complete the system startup or system update.

[0003] In the related technologies, data processing based on SOC chips and flash memory requires transferring data to the cache of the flash memory, and then transferring it from the cache to the destination (such as the storage array inside the flash memory or the data address in the SOC chip). This process involves waiting for data to be transferred between the cache and the storage array inside the flash memory. During this process, the SOC chip cannot perform other operations, and the waiting time can only be wasted, resulting in low data processing efficiency of the system. Summary of the invention

[0004] The embodiments of the present disclosure provide a flash memory data processing method, apparatus, device and storage medium to solve the problem in the related art that flash memory-based data processing needs to wait for data interaction between the flash memory cache and the storage array, resulting in low embedded system data processing efficiency.

[0005] In a first aspect, an embodiment of the present disclosure provides a flash memory data processing method, which is applied to an embedded system, wherein the embedded system includes a SOC chip, an analog switch, and a flash memory, wherein the flash memory includes a first flash memory and a second flash memory, and the SOC chip is connected to the first flash memory and the second flash memory respectively through the analog switch;

[0006] The flash memory data processing method includes:

[0007] Based on the data processing task to be executed, sending a corresponding first data processing command to a first flash memory that is in a connected state with the SOC chip, wherein the data processing task includes a data processing command, and the data processing command includes a first data processing command corresponding to the first flash memory and a second data processing command corresponding to the second flash memory;

[0008] Based on the analog switch, switching the flash memory that is in a connected state with the SOC chip, and sending a corresponding data processing command to the switched flash memory, wherein the switched flash memory is used to represent the flash memory that is in a connected state with the SOC chip after the analog switch is switched;

[0009] Repeat switching the flash memory and sending data processing commands to the switched flash memory until all data processing commands corresponding to the data processing task are completed.

[0010] In a second aspect, an embodiment of the present disclosure provides a flash memory data processing device, which is applied to an embedded system. The embedded system includes a SOC chip, an analog switch, and a flash memory. The flash memory includes a first flash memory and a second flash memory. The SOC chip is connected to the first flash memory and the second flash memory respectively through the analog switch.

[0011] The flash memory data processing device comprises:

[0012] A first sending module is used to send a corresponding first data processing command to a first flash memory that is connected to the SOC chip based on a data processing task to be executed, wherein the data processing task includes a data processing command, and the data processing command includes a first data processing command corresponding to the first flash memory and a second data processing command corresponding to the second flash memory;

[0013] A switching module, used for switching the flash memory connected to the SOC chip based on the analog switch, and sending a corresponding data processing command to the switched flash memory, wherein the switched flash memory is used to indicate the flash memory connected to the SOC chip after the analog switch is switched;

[0014] The processing module is used for repeatedly switching the flash memory and sending data processing commands to the switched flash memory until all data processing commands corresponding to the data processing task are completed.

[0015] In a third aspect, an embodiment of the present disclosure further provides a control device, the control device comprising:

[0016] at least one processor;

[0017] and a memory communicatively coupled to the at least one processor;

[0018] The memory stores commands that can be executed by at least one processor, and the commands are executed by at least one processor to enable the control device to execute the flash memory data processing method as described in the first aspect of the present disclosure.

[0019] In a fourth aspect, an embodiment of the present disclosure further provides a flash memory data processing system, comprising: a SOC chip, at least two flash memory memories;

[0020] The SOC chip includes a built-in processor, and the built-in processor is used to execute the flash memory data processing method according to the first aspect of the present disclosure;

[0021] Flash storage consists of interconnected controllers, caches, and storage arrays.

[0022] In a fifth aspect, an embodiment of the present disclosure further provides a computer-readable storage medium, in which computer execution commands are stored. When the computer execution commands are executed by a processor, they are used to implement the flash memory data processing method as in the first aspect of the present disclosure.

[0023] In a sixth aspect, an embodiment of the present disclosure further provides a computer program product, which includes computer execution commands, and when the computer execution commands are executed by a processor, they are used to implement the flash memory data processing method as in the first aspect of the present disclosure.

[0024] The flash memory data processing method, device, equipment and storage medium provided by the embodiments of the present disclosure send a corresponding first data processing command to a first flash memory connected to a SOC chip based on a data processing task to be executed, and then switch the flash memory connected to the SOC chip based on an analog switch, and send a corresponding data processing command to the switched flash memory, and then repeatedly switch the flash memory and send the data processing command to the switched flash memory until all data processing commands corresponding to the data processing task are completed. Thus, multiple flash memories can be used to jointly complete the writing and reading of data, and when the current flash memory executes a data processing command, it directly switches to another flash memory and sends a corresponding data processing command to another flash memory, significantly reducing the time for data to be transferred between the cache and the storage array inside the flash memory while waiting for the flash memory to execute the data processing command, thereby significantly improving the efficiency of data reading and writing, and thus enabling the embedded system based on the SOC chip and the flash memory to quickly complete actions such as device startup and device update, thereby improving the working efficiency of the embedded system. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0026] Figure 1 An application scenario diagram of the flash memory data processing method provided by the embodiment of the present disclosure;

[0027] Figure 2A flowchart of a flash memory data processing method provided by an embodiment of the present disclosure;

[0028] Figure 3a A flowchart of a flash memory data processing method provided by another embodiment of the present disclosure;

[0029] Figure 3b for Figure 3a A flow chart of a method for determining the status of a flash memory provided in the illustrated embodiment;

[0030] Figure 4a A flowchart of a flash memory data processing method provided by another embodiment of the present disclosure;

[0031] Figure 4b for Figure 4a A flow chart of a method for determining a data processing command provided in the illustrated embodiment;

[0032] Figure 5a A flowchart of a flash memory data processing method provided by another embodiment of the present disclosure;

[0033] Figure 5b for Figure 5a A flow chart of a method for determining a data processing command in a data reading task provided in the illustrated embodiment;

[0034] Figure 6a A flowchart of a flash memory data processing method provided by another embodiment of the present disclosure;

[0035] Figure 6b for Figure 6a A flow chart of a method for determining a data erase command provided in the illustrated embodiment;

[0036] Figure 6c for Figure 6a A flow chart of a method for determining a starting storage address provided in the illustrated embodiment;

[0037] Figure 7 A schematic diagram of the structure of a flash memory data processing device provided by yet another embodiment of the present disclosure;

[0038] Figure 8 A schematic diagram of the structure of a control device provided by an embodiment of the present disclosure;

[0039] Fig. 9 A schematic diagram of the structure of a flash memory data processing system provided by yet another embodiment of the present disclosure.

[0040] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0041] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0042] The technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0043] The following is an explanation of the nouns involved in the embodiments of the present disclosure:

[0044] SOC chip: The corresponding English name of SOC is System on chip, which means system on chip. In the embodiments of the present disclosure, SOC chip is used to represent a chip for installing an embedded system. The SOC chip contains a processor and can run the embedded system.

[0045] Flash memory: In the embodiments of the present disclosure, it is a memory used for long-term storage of system files of the embedded system and important data related to the embedded system. Common flash memory such as SSD hard disk.

[0046] SPI NAND flash memory: SPI NAND flash memory is a type of flash memory with the advantages of large storage capacity and low manufacturing cost. It is suitable for embedded systems. In the embodiment of the present disclosure, it is a memory that interacts with the SOC chip and stores system files of the embedded system.

[0047] In the field of embedded systems, combining an embedded system chip SOC (hereinafter referred to as SOC chip) with a SPI NAND flash memory (hereinafter referred to as flash memory) to complete data processing (such as data reading, writing and storage) is a very common hardware configuration method for embedded systems. Among them, by taking advantage of the large storage capacity and low manufacturing cost of flash memory, system files and important program data in the embedded system can be stored in the flash memory. When the embedded system starts, the SOC chip will send a control command to the flash memory to read data from the flash memory or write data to the flash memory to complete the system startup or system update.

[0048] In the related technologies, data processing based on SOC chips and flash memory requires transferring data to the cache of the flash memory, and then transferring it from the cache to the destination (such as the storage array inside the flash memory or the data address in the SOC chip). This process involves waiting for data to be transferred between the cache inside the flash memory and the storage array. During this process, the SOC chip cannot perform other operations. Since the reading speed of the flash memory is relatively slow (the process of transferring data from the cache to the storage array consumes a long time), the waiting time can only be wasted, resulting in low data processing efficiency of the system.

[0049] In order to solve this problem, an embodiment of the present disclosure provides a flash memory data processing method, which connects a SOC chip to multiple flash memory chips and decomposes the data processing task to each flash memory chip, which is completed alternately by each flash memory chip, thereby significantly reducing the process of waiting for data processing by a single flash memory chip. While taking advantage of the low cost of SPI NAND flash memory, the data processing efficiency of the embedded system is significantly improved.

[0050] The application scenarios of the embodiments of the present disclosure are explained below:

[0051] Figure 1 This is an application scenario diagram of the flash memory data processing method provided by the embodiment of the present disclosure. Figure 1 As shown, during the data processing of the embedded system, the SOC chip 110 communicates with two flash memories 130 respectively through the analog switch 120 to complete operations such as writing, reading and erasing data.

[0052] It should be noted that Figure 1 In the scenario shown, only one or a specific number of SOC chips, SOC chip boxes, and flash memory are used as examples for illustration, but the present disclosure is not limited to this, that is, the number of SOC chips, SOC chip boxes, and flash memory can be arbitrary.

[0053] The flash memory data processing method provided by the present disclosure is described in detail below through specific embodiments.

[0054] Figure 2 The following is a flow chart of a flash memory data processing method provided by an embodiment of the present disclosure. Figure 2 As shown, the flash memory data processing method provided in this embodiment is applied to an embedded system, the embedded system includes a SOC chip, an analog switch and a flash memory, the flash memory includes a first flash memory and a second flash memory, the SOC chip is connected to the first flash memory and the second flash memory respectively through the analog switch; it includes the following steps:

[0055] Step S201: Based on the data processing task to be executed, a corresponding first data processing command is sent to a first flash memory connected to the SOC chip.

[0056] The data processing task includes a data processing command, and the data processing command includes a first data processing command corresponding to the first flash memory and a second data processing command corresponding to the second flash memory.

[0057] Specifically, the data processing task is the task that the SOC chip needs to perform. For example, if the task of starting the embedded system is to execute the data reading task from the flash memory (i.e., SPI NAND flash memory, hereinafter referred to as flash memory) to read the system files stored in the flash memory (i.e., other important data, hereinafter collectively referred to as system files for the sake of simplicity); if the task of updating the embedded system is to write the updated system files to the corresponding storage locations in the flash memory to overwrite the system files at the corresponding storage locations in the flash memory, i.e., the data writing task; before updating the embedded system, it is usually necessary to erase the original files at the corresponding storage locations in the flash memory, i.e., the data erasing task.

[0058] These data processing tasks can be completed through data processing commands, such as data write commands, data read commands, etc.

[0059] In the case where the embedded system includes multiple flash memories (at least two, described as two in this embodiment), each flash memory stores a part of the system file. Therefore, whether it is a data reading task, a data writing task or a data erasing task, it can be decomposed into each flash memory to obtain the corresponding data processing command that needs to be executed by each flash memory. That is, the data processing commands corresponding to each flash memory will be different, for example, the data to be stored in the data storage command is different.

[0060] When starting to execute a data processing task, the SOC chip will first send a corresponding data processing command (ie, a first data processing command) to a flash memory (ie, a first flash memory, hereinafter referred to as the first flash memory) connected thereto.

[0061] In some embodiments, the first data processing command usually includes multiple commands. The SOC chip can continuously send multiple first data processing commands, such as write enable commands, data receive commands, etc., to the first flash memory (or the second flash memory, hereinafter referred to as the second flash memory). The first flash memory processes these data processing commands faster. Therefore, multiple first data processing commands can be sent continuously instead of switching immediately after sending a single first data processing command.

[0062] In some embodiments, the data processing commands that support continuous sending are commands that do not involve modifying the data in the cache of the flash memory and / or the data in the storage array, such as a write enable command, which is a command that switches the flash memory to a state that supports data writing. This command does not require cache and storage array actions in the flash memory. Therefore, after sending this command, subsequent data processing commands can continue to be sent.

[0063] In some embodiments, if the data processing command is a command involving modifying data in the flash memory cache and / or data in the storage array, when such data processing command is sent to the flash memory, the SOC chip will switch the flash memory connected to the SOC chip through the analog switch. Because such commands take a long time to process in the flash memory, it is possible to directly switch to other flash memories and send the corresponding data processing command to other flash memories, thereby saving the time of waiting for the flash memory to execute the data processing command and improving the execution efficiency of the data processing task.

[0064] Step S202: based on the analog switch, switch the flash memory connected to the SOC chip, and send a corresponding data processing command to the switched flash memory.

[0065] The switched flash memory is used to indicate the flash memory that is connected to the SOC chip after the analog switch is switched.

[0066] Specifically, after sending the corresponding first data processing command to the first flash memory, the SOC chip can send a corresponding signal to the analog switch to make the analog switch switch the flash memory connected to the SOC chip (from the first flash memory to the second flash memory), and then send the corresponding data processing command (such as the second data processing command) to another flash memory (such as the second flash memory). When the second flash memory needs to wait to complete the data processing command, it switches to the next flash memory (such as the first flash memory) through the analog switch and sends the corresponding data processing command.

[0067] Thus, the waiting time of the flash memory in the process of completing the data processing command can be fully utilized, and the time required to wait for the flash memory to complete the data processing command can be reduced. At the same time, by decomposing the data processing tasks to be executed by different flash memories respectively, the time required for each flash memory to complete the corresponding data processing task is reduced, thereby significantly reducing the time required for data processing tasks as a whole, and significantly improving the data processing efficiency of the embedded system based on the flash memory.

[0068] Step S203: Repeat switching the flash memory and sending data processing commands to the switched flash memory until all data processing commands corresponding to the data processing task are completed.

[0069] Specifically, after sending the second data processing command to the second flash memory, while the second flash memory executes the corresponding second data processing command, the SOC can switch again through the analog switch to send a new first data processing command to the first flash memory after the first flash memory completes the corresponding first data processing command.

[0070] Furthermore, the data processing command includes a corresponding execution order. Thus, the implementation method of sending the corresponding data processing command to each flash memory is as follows: based on the execution order between the data processing commands, each flash memory sends the corresponding data processing command in turn until each flash memory completes all data processing commands corresponding to the data processing task.

[0071] Since the commands corresponding to data processing tasks such as data reading, writing, and erasing usually involve continuous processing of files and addresses (such as reading, writing, erasing, and other processing actions), it is necessary to ensure that the data processing commands received by each flash memory follow their corresponding order, which can ensure the continuity of the actions performed by each flash memory (such as reading files in continuous storage addresses in sequence), facilitate the subsequent operations of the SOC chip after the flash memory completes data processing (such as splicing and sorting data read based on the flash memory), improve the efficiency of data processing, and ensure that each flash memory can effectively complete the corresponding data processing tasks.

[0072] The flash memory data processing method provided by the embodiment of the present disclosure sends a corresponding first data processing command to a first flash memory connected to a SOC chip based on a data processing task to be executed, and then switches the flash memory connected to the SOC chip based on an analog switch, and sends a corresponding data processing command to the switched flash memory, and then repeatedly switches the flash memory and sends the data processing command to the switched flash memory until all data processing commands corresponding to the data processing task are completed. Thus, multiple flash memories can be used to jointly complete the writing and reading of data, and when the current flash memory executes a data processing command, it directly switches to another flash memory and sends a corresponding data processing command to the other flash memory, significantly reducing the time for data to be transferred between the cache and the storage array inside the flash memory while waiting for the flash memory to execute the data processing command, thereby significantly improving the efficiency of data reading and writing, and thus enabling the embedded system based on the SOC chip and the flash memory to quickly complete actions such as device startup and device update, thereby improving the working efficiency of the embedded system.

[0073] Figure 3a The following is a flow chart of a flash memory data processing method provided by an embodiment of the present disclosure. Figure 3a As shown, the flash memory data processing method provided in this embodiment includes the following steps:

[0074] Step S301: Based on the data processing task to be executed, a corresponding first data processing command is sent to a first flash memory connected to the SOC chip.

[0075] Specifically, this embodiment mainly further describes the content that the SOC chip sends data processing commands to different flash memories based on analog switches.

[0076] This step and Figure 2 The corresponding steps in the illustrated embodiment are the same in content and will not be described again here.

[0077] Step S302: Based on the analog switch, switch the flash memory connected to the SOC chip.

[0078] Specifically, when the first flash memory is in the process of executing the first data processing command, according to the prior art, it is necessary to wait for the first flash memory to complete the currently executing first data processing command before sending subsequent first data processing instructions to the first flash memory, thereby wasting time waiting for the first flash memory to process the execution of the first data processing command.

[0079] In this solution, after sending the first data processing command to the first flash memory, the SOC chip will switch the flash memory connected to the SOC chip through an analog switch, that is, switch to connecting to the second flash memory, so as to use the time when the first flash memory executes the first data processing command to send the corresponding second data processing command to the second flash memory, so that the second flash memory and the first flash memory are both in the process of executing the corresponding data processing commands, thereby improving the processing efficiency of data processing tasks.

[0080] Furthermore, the specific implementation method of switching the flash memory is: switching the level signal input by the SOC chip to the analog switch, wherein the analog switch is used to determine the flash memory connected to the SOC chip based on the level signal.

[0081] Specifically, the SOC chip is connected to the analog switch through the SPI interface to output data processing commands and receive data returned by the flash memory. The SOC chip is also connected to the analog switch through the GPIO interface to control the flash memory connected to the SOC chip by sending different signals.

[0082] When there are two flash memories connected to the SOC chip through the analog switch, the signal sent through the GPIO interface is a level signal, wherein the high level and the low level correspond to different flash memories respectively.

[0083] In some embodiments, if there are more than two flash memories connected to the SOC chip through the analog switch, the signal sent through the GPIO interface may be a signal of a type other than a level signal, so as to switch the flash memory connected to the SOC chip by sending different types of signals.

[0084] Step S303: determine that the switched flash memory is not in a state of executing a data processing command.

[0085] Specifically, before sending the corresponding data processing command to the switched flash memory, it is necessary to ensure that the flash memory is not in a state of executing the data processing command, so as to ensure that the switched flash memory can receive and execute the new data processing command.

[0086] Furthermore, if Figure 3b As shown, it is a flow chart of a method for determining the status of a flash memory, which includes the following steps:

[0087] Step S3031, sending a status query command to the switched flash memory.

[0088] Specifically, after the flash memory connected to the SOC chip is switched through the analog switch, a status query command is first sent to the switched flash memory. When the controller in the flash memory receives the status query command, it will feedback its own status to the SOC chip through the analog switch (that is, send feedback information) according to the working status in the flash memory.

[0089] Step S3032: Based on the feedback information of the switched flash memory, determine that the switched flash memory is in a state of not executing the data processing command.

[0090] Specifically, when the SOC chip receives the feedback information sent by the switched flash memory, it can determine the state of the flash memory according to the feedback information, such as the state of not executing the data processing command or the state of executing the data processing command.

[0091] Step S304: Send a corresponding data processing command to the switched flash memory.

[0092] Specifically, depending on whether the switched flash memory is the first flash memory or the second flash memory, the SOC chip will send a corresponding data processing command to the switched flash memory through the analog chip. If the switched flash memory is the second flash memory, it will send a corresponding second data processing command.

[0093] Step S305: determine whether the switched flash memory is in a state of executing a data processing command.

[0094] Specifically, in another case, if it is determined through feedback information that the switched flash memory is still in the state of executing data processing commands, new data processing commands cannot be sent directly to the flash memory, and it is necessary to determine when the switched flash memory can complete the data processing commands, or to switch the flash memory connected to the SOC chip again until it is determined that the flash memory connected to the SOC chip can accept and process new data processing commands. In this way, the waiting time in the flash memory processing data processing commands can be maximized, thereby improving the data processing efficiency of the entire embedded system.

[0095] Steps S305 to S307 are optional steps parallel to steps S303 to S304. Those skilled in the art may select corresponding steps to execute according to actual conditions, and no limitation is made here.

[0096] Step S306: Based on the analog switch, switch the flash memory connected to the SOC chip.

[0097] Specifically, since the action of switching the flash memory connected to the SOC chip through the analog switch itself also requires a certain amount of time to execute (this time is usually much shorter than the time required for the flash memory to execute the data processing command), when it is determined that the switched flash memory is still in a state of executing the data processing command, the flash memory that is connected to the SOC chip can be switched again, and it can be determined that the flash memory after switching again has completed executing the previous data processing command and can receive a new data processing command.

[0098] Step S307, repeatedly sending a status query command to the switched flash memory until it is determined that the switched flash memory is in a state where the data processing command is not executed.

[0099] Specifically, in addition to directly switching the flash memory that is connected to the SOC chip again, you can also directly poll the flash memory that is currently connected to the SOC chip. This is because the flash memory that is currently connected to the SOC chip usually receives data processing commands before the memory before switching. Therefore, the moment it completes executing the data processing command is usually before the moment the memory before switching completes executing the corresponding data processing command. Therefore, you can directly poll the switched flash memory until the received feedback information indicates that the switched flash memory is in a state of not executing data processing commands.

[0100] Step S307 is an optional step parallel to step S306. Those skilled in the art may select a corresponding step to perform according to actual conditions, and no limitation is made here.

[0101] Step S308, repeatedly switching the flash memory and sending data processing commands to the switched flash memory until all data processing commands corresponding to the data processing task are completed.

[0102] Specifically, this step is the same as the corresponding step in the above embodiment and will not be described again here.

[0103] The flash memory data processing method provided by the embodiment of the present disclosure sends a corresponding first data processing command to the first flash memory, switches to the second flash memory through an analog switch, and sends a status query command to the second flash memory. When it is determined that the second flash memory is not in a state of executing the data processing command, the corresponding second data processing command is sent to the second flash memory, and the execution action of the data processing command is completed by repeating this process. Thus, the corresponding data processing command can be sent alternately to each flash memory through the cooperation of the SOC chip and the analog switch, significantly reducing the time waiting for the flash memory to process the data processing command, and the data processing command corresponding to the data processing task can be jointly executed by multiple flash memories, significantly improving the execution efficiency of the data processing task.

[0104] Figure 4a The following is a flow chart of a flash memory data processing method provided by an embodiment of the present disclosure. Figure 4a As shown, the flash memory data processing method provided in this embodiment includes the following steps:

[0105] Step S401, determining a data processing command corresponding to a data writing task.

[0106] Specifically, the disclosed embodiments and subsequent embodiments are used to further illustrate specific data processing instructions and their execution processes in different types of data processing tasks on the basis of the aforementioned embodiments. Among them, this embodiment is used to further illustrate the corresponding flash memory data processing method based on the data writing task in the data processing task.

[0107] In this embodiment, the flash memory includes a controller, a cache, and a storage array that cooperate with each other.

[0108] In the data writing task, the SOC chip needs to transfer the file to be written to the cache of the flash memory through data processing commands, and then the flash memory controller transfers the data stored in the cache to the storage array for storage.

[0109] Furthermore, if Figure 4b As shown, it is a flow chart of a method for determining a data processing command, which includes the following steps:

[0110] Step S4011, determining the file to be written corresponding to the data writing task.

[0111] Specifically, in a data writing task, the storage space of the SOC chip (such as the built-in cache) will store the files to be written corresponding to the data writing task, such as the system file update package of the embedded system. Since the cache capacity of the flash memory is limited, it can only receive files of its capacity at a time and transfer them to the storage array inside the memory. Therefore, when actually processing the data writing task, it is necessary to first determine the files to be written, and then divide the files to be written to obtain the sub-files corresponding to the files to be written, so as to determine the corresponding data processing commands according to the sub-files to be written, so that the flash memory can transfer the divided sub-files to be written to the storage array according to the data processing commands.

[0112] Step S4012: based on the capacity of the cache of the flash memory, the file to be written is divided into sizes corresponding to the capacity to obtain divided sub-files to be written.

[0113] Specifically, after the file to be written is determined, it can be divided according to the cache capacity of the flash memory, and the files obtained by the division are the sub-files to be written.

[0114] Each sub-file to be written obtained by segmentation has the same size, that is, the same as the cache capacity of the flash memory (such as 2kb). If the end of a file to be written obtained during the segmentation process is less than the size corresponding to the flash cache capacity, it should be padded to that size.

[0115] Furthermore, if the size of the sub-file to be written after the division is smaller than the capacity, a spacer is added to the sub-file to be written until the size of the sub-file to be written is equal to the capacity.

[0116] Step S4013, determining the sequence number of the sub-file to be written according to the position of the sub-file to be written in the file to be written.

[0117] Specifically, after the sub-files to be written are divided, it is necessary to add sequence numbers to them according to the order of their storage positions in the file to be written, so that they can be written into the flash memory in sequence, and it is also convenient to read them from the flash memory in sequence during subsequent processing.

[0118] Step S4014: based on the number of flash memory devices, determine the sequence number of the sub-file to be written corresponding to each flash memory device.

[0119] Specifically, the flash memories connected to the SOC chip have the same configuration, so the data processing speed (such as data writing speed) of each flash memory is the same. Therefore, the sub-files to be written are usually evenly distributed to each flash memory (if they cannot be evenly distributed, they are distributed to individual flash memories in order).

[0120] Step S4015: determining at least one data processing command that needs to be executed by each flash memory based on the sequence number of the to-be-written sub-file corresponding to each flash memory.

[0121] Specifically, based on the sequence number of the to-be-written sub-file corresponding to each flash memory, a data processing command corresponding to each flash memory may be generated so as to be sent to the controller of the flash memory so that the flash memory completes the corresponding data writing action.

[0122] Furthermore, the data processing command obtained by the above method is also a data writing command, and the data writing command is used to send the subfile of the set number of the file to be written and the storage address of the subfile to the flash memory. The flash memory is used to receive the subfile of the set number into the cache, and the flash memory is also used to store the subfile of the set number into the storage address corresponding to the storage array based on the data writing command, and the set number includes a first set number corresponding to the first data processing command and a second set number corresponding to the second data processing command.

[0123] Furthermore, in the data writing task, in addition to the data writing command, the data processing commands include: a write enable command, which is used to switch the flash memory to a state that supports writing operations before sending the data writing command; a data transmission command, which is used to notify the flash memory to receive the data writing command; and a write enable turn off command, which is used to switch the flash memory to a state that does not support writing operations when the transmission of the data writing command corresponding to the file to be written is completed.

[0124] Specifically, in actual processing, the SOC chip does not directly send a data write command to the flash memory, because the flash memory is not always in a state where it can receive and write data. It is necessary to switch the working state of the flash memory through a write enable command, and inform the flash memory to start receiving the sub-file to be written through a data transfer command, and then send a data write command to the flash memory, so that the flash memory writes the sub-file to be written with the set number in the data write command to the storage address corresponding to the storage array in the flash memory. After completing the transmission of all data write commands, it is also necessary to turn off the write enable command to switch the flash memory back to a state that does not support write operations, so as to ensure the security of the data stored in the flash memory.

[0125] Step S402: Based on the data processing task to be executed, a corresponding first data processing command is sent to a first flash memory connected to the SOC chip.

[0126] Step S403: based on the analog switch, switch the flash memory connected to the SOC chip, and send a corresponding data processing command to the switched flash memory.

[0127] Step S404, repeatedly switching the flash memory and sending data processing commands to the switched flash memory until all data processing commands corresponding to the data processing task are completed.

[0128] Specifically, steps S402 to S404 are the same as the corresponding steps in the aforementioned embodiment and are not described again here.

[0129] The following is an example based on the previous steps. In this example, there are two flash memories. In this example, the data input task is implemented through the following steps:

[0130] First, determine a file to be written, such as a kernel file in an embedded system.

[0131] The SOC chip (hereinafter referred to as SOC in this example) first divides the kernel file into several small files (ie, sub-files to be written) of the same size (eg, 2KB) as the cache of the SPI NAND flash memory (hereinafter referred to as SPI NAND in this example).

[0132] Determine the sequence number of the sub-files to be written, that is, number them in the order of small files, where if the size of the last file is less than 2KB, the end data is padded with 0xFF to make up 2KB.

[0133] Then, it is necessary to determine the sequence number and data processing command of the sub-file to be written corresponding to each flash memory (the above content corresponds to step S401).

[0134] Then transfer file number 1 to the cache of SPI NAND1 by the following operations:

[0135] Step A1, SOC first pulls up the GPIO interface (input high level) to switch the analog switch mode, so that the SPI interface of SOC and SPINAND1 is connected.

[0136] Step A2: The SOC transmits a write enable command (06h) through the SPI interface (the SPI interface is an interface for transmitting data processing commands) to enable a write operation to the SPI NAND 1.

[0137] Step A3, SOC transmits a data transmission command (32h) through the SPI interface to notify SPI NAND 1 that data transmission is about to begin, so that the content of file 1 can be sent in sequence through the SPI interface in the subsequent time.

[0138] After the SOC sends the data, the data will exist in the cache of SPI NAND1.

[0139] SOC sends a data write command (10h) to SPI NAND1. Under the control of the controller, SPI NAND 1 writes data from the cache to address 1 specified by the 10h command. The execution of this command will consume a certain amount of time, and this solution will switch to SPI NAND 2 for new operations during this extra time gap. Then, the file number 2 is transferred to the cache of SPI NAND2 through the following operations (the contents of the above steps A1 to A3 correspond to step S402).

[0140] Step A4, the SOC first pulls down the GPIO interface (outputs low level) to switch the analog switch mode, so that the SOC chip and the SPI interface of the SPI NAND2 are connected.

[0141] Step A5: The SOC transmits a write enable command (06h) through the SPI interface to enable the write operation to the SPI NAND 2.

[0142] Step A6, SOC transmits a data transmission command (32h) through the SPI interface to notify SPI NAND 2 that data transmission is about to begin, so that the content of file 2 can be sent in sequence through the SPI interface through a data write command in a subsequent period of time.

[0143] After the SOC sends the data, the data will exist in the cache of SPI NAND 2.

[0144] Step A7, SOC sends a data write command (10h) to SPI NAND2. Under the control of the controller, SPI NAND 2 writes the data from the cache to address 2 specified by the 10h command. The execution of this command will consume a certain amount of time (the contents of the above steps A4 to A7 correspond to step S403).

[0145] Similarly, while SPI NAND 2 is running data transfer in the background, we continue to switch back to SPI NAND1 for new operations.

[0146] At this time, we pull up GPIO to a high level again. During the data transmission to SPI NAND 2, SPINAND 1 continues to execute the data write command (10h). At this time, we send a status query command (0Fh) to confirm that the operation has been completed. If it has not been completed, the query command (0Fh) is executed repeatedly until the operation is confirmed to be completed. At this time, file 1 has entered the storage array of SPI NAND 1.

[0147] Then we repeat the above operation and write file 3 into the cache of SPI NAND 1; then cut GPIO to low. During the data transmission to SPI NAND 1, SPI NAND 2 continues to execute the data write command (10h). At this time, we send a status query command (0Fh) to confirm that the operation has been completed. If it has not been completed, the status query command (0Fh) is executed repeatedly until the operation is confirmed to be completed. At this time, file 2 has entered the storage array of SPI NAND 2.

[0148] The above operation is repeated until all files are stored in the two SPI NANDs respectively. After the writing is completed, a write operation is completed by sending a close write enable command (04h) (corresponding to step S404).

[0149] Therefore, during the process of transferring the cache data of the two SPI NANDs to the storage column, the SOC is not in a state of waiting, but switches to another SPI NAND to start a new write operation. In the above example, the time required to write 10MB of data using the dual SPI NAND acceleration method is: 1030ms, and the time required to write 10MB of data using the traditional method is: 1250ms, and the performance is improved by about 17.5%.

[0150] The flash memory data processing method provided by the embodiment of the present disclosure divides and numbers the files to be written corresponding to the data writing task, and determines the sub-files to be written and the corresponding data processing commands corresponding to each flash memory accordingly, and then sends the corresponding data processing commands to each flash memory in turn. In this way, the data writing task can be completed by multiple flash memories together, which significantly saves the time of waiting for data transmission inside the flash memory, thereby improving the data transmission efficiency based on the flash memory.

[0151] Figure 5a The following is a flow chart of a flash memory data processing method provided by an embodiment of the present disclosure. Figure 5a As shown, the flash memory data processing method provided in this embodiment includes the following steps:

[0152] Step S501, determining a data processing command in a data reading task.

[0153] Specifically, the embodiments of the present disclosure are used to further illustrate the data reading tasks and related data processing commands in the data processing tasks based on the aforementioned embodiments.

[0154] Furthermore, if Figure 5b As shown, it is a flow chart of a method for determining a data processing command in a data reading task, which includes the following steps:

[0155] Step S5011, determining the storage address of the to-be-read sub-file corresponding to the data reading task in the corresponding flash memory.

[0156] Specifically, the data reading task is used to read pre-stored data from the storage array of the flash memory. It is frequently used during the startup process of the embedded system. At this time, the system files of the embedded system are stored in the flash memory. Through the data reading task, the system files can be loaded into the SOC chip to start the embedded system.

[0157] Furthermore, the data processing command includes a page read command and a data read command, the page read command includes a set address, the data read command is used to enable the flash memory to transfer the data corresponding to the set address in the storage array to the cache of the flash memory, the data read command is used to enable the flash memory to send the data in the cache to the SOC chip, and the set address includes a first set address corresponding to the first data processing command and a second set address corresponding to the second data processing command.

[0158] Therefore, when determining the data processing command in the data reading task, it is first necessary to determine the storage address (ie, the set address) of the data to be read in the flash memory.

[0159] Step S5012: determining a page read command and a data read command corresponding to each flash memory based on the set address.

[0160] Specifically, the page read command and the data read command are related to the set address of the sub-file to be read. There is a page read command and a data read command corresponding to each set address of data. Therefore, each sub-file to be read is stored in each flash memory respectively. Therefore, it is necessary to combine the set address and the corresponding flash memory to determine the page read command and data read command corresponding to each flash memory.

[0161] Step S502: Based on the data processing task to be executed, a corresponding first data processing command is sent to a first flash memory connected to the SOC chip.

[0162] Specifically, in actual execution, the first data processing command and the second data processing command both include multiple page read commands and multiple data read commands. For each data at a set address, a page read command is usually sent to the flash memory first, and then a corresponding data read command is sent to the same flash memory.

[0163] Since the execution time of the page read command is relatively long, when sending the first data processing command to the first flash memory, only one page read command may be sent. During the process of the first flash memory executing the page read command, it is directly switched to connect with the second flash memory through the analog switch. After sending the corresponding data processing command to the second flash memory, it is switched back to the first flash memory through the analog switch. After the first flash memory completes executing the page read command, the corresponding data read command is sent again.

[0164] Step S503: based on the analog switch, switch the flash memory connected to the SOC chip, and send a corresponding data processing command to the switched flash memory.

[0165] Specifically, this step is the same as the corresponding step in the above embodiment and will not be described again here.

[0166] Step S504, repeatedly switching the flash memory and sending data processing commands to the switched flash memory until all corresponding data processing commands are sent to the flash memory.

[0167] Specifically, the page read command and the data read command of the corresponding set address are repeatedly sent to each flash memory until the first flash memory completes all corresponding first data processing commands and the second flash memory completes all corresponding second data processing commands.

[0168] Step S505: splice the data received in the SOC chip to obtain complete data corresponding to the data reading task.

[0169] Specifically, after all the data are transferred to the SOC chip, the data need to be spliced ​​according to their sequential numbers to obtain a complete file.

[0170] The sequence number is usually stored in the SOC chip and corresponds to its set address. It is predetermined when determining its corresponding data processing command. Therefore, the file splicing can be completed only according to the sequence number recorded in the SOC chip.

[0171] The following is an example based on the above steps in this embodiment:

[0172] For a file (such as a kernel file), follow Figure 2 The operations of the corresponding examples in the illustrated embodiment have been divided into several small blocks and stored in two SPI NANDs, so we can read them out according to the following steps (the action of determining the data processing command is omitted in this example).

[0173] Step B1, SOC first pulls up GPIO to switch the analog switch mode, so that the SPI interface of SOC and SPI NAND1 is connected; SOC sends a page read command (13h) through the SPI interface, and the control of SPI NAND 1 transfers the 2kB data starting with the address (address 1) transmitted by 13h to the cache of SPI NAND1 (corresponding to step S502).

[0174] This command will be executed in the background for a period of time. During this period, the SOC will no longer wait for the output of the storage array to be transferred to the cache to complete the operation, and can start a new operation.

[0175] Step B2, SOC pulls down GPIO to switch the analog switch mode, so that the SPI interface of SOC and SPI NAND2 is connected, SOC reads the command (13h) through the SPI interface page, and the controller of SPI NAND 2 transfers the 2kB data starting with the address (address 2) transmitted by 13h to the cache of SPI NAND2. This command will be executed in the background for a period of time (corresponding to step S503).

[0176] Step B3: The SOC pulls up the GPIO to switch the analog switch mode, so that the SPI interface of the SOC and the SPI NAND1 are connected.

[0177] Step B4: query whether SPI NAND1 has completed the operation of writing into the cache through the status query command (0Fh). If it has been completed, continue to execute downwards. If it has not been completed, repeat the sending until the cache is confirmed to be written.

[0178] Step B5: Send a data read command (6Bh), and SPI NAND1 transfers the data in the cache to the SOC through the SPI interface.

[0179] Step B6, SOC reads the command (13h) through the SPI interface page, and the control of SPI NAND 1 transfers the 2kB data starting from the address (address 3) transmitted by 13h to the cache of SPI NAND1. This command will be executed in the background for a period of time. During this period of time, SOC will no longer continue to wait for the completion of the operation of transmitting the output of the storage array to the cache, and can start a new operation.

[0180] Step B7, the SOC pulls the GPIO low to switch the analog switch mode, so that the SPI interface of the SOC and the SPI NAND2 are connected.

[0181] Step B8: query whether SPI NAND1 has completed the operation of writing into the cache through the status query command (0Fh); if it has been completed, continue to execute; if it has not been completed, repeat the sending until the cache is confirmed to be written.

[0182] Step B9, send a data read command (6Bh), SPI NAND2 transfers the data in the cache to the SOC through the SPI interface, repeat the above operation, and read all the data into the SOC (steps B3-B9 correspond to step S504).

[0183] Finally, the SOC connects the first bits of the data to obtain complete data (corresponding to step S505 ).

[0184] In this way, when the entire column of storage in the two SPI NANDs is moved to the cache, the SOC is not in a state of waiting, but switches to another SPI NAND to start a new read operation. This achieves acceleration in the reading process. In the above example, the time required to read 10MB of data using the dual SPI NAND acceleration method is: 230ms, compared to the time required to read 10MB of data using the traditional method: about 450ms, the performance is improved by about 48.9%.

[0185] The flash memory data processing method provided by the embodiment of the present disclosure divides the data reading task into the first type of data reading command and the second type of data reading command executed by each flash memory, and polls and switches the flash memory, so that different flash memories respectively complete the transmission action of the corresponding sub-files to be read, until all the sub-files to be read are transmitted to the SOC chip, and then the sub-files to be read are spliced ​​to obtain the read file. Therefore, by jointly executing the data reading task by multiple flash memories, the waiting time of data transmission between the storage array and the cache is reduced, thereby significantly improving the efficiency of data reading.

[0186] Figure 6a The following is a flow chart of a flash memory data processing method provided by an embodiment of the present disclosure. Figure 6a As shown, the flash memory data processing method provided in this embodiment includes the following steps:

[0187] Step S601, determining a data processing instruction corresponding to a data erasing task.

[0188] Specifically, the embodiments of the present disclosure are used to further illustrate the data erasing task and related data processing commands in the data processing task based on the above embodiments.

[0189] Furthermore, the data processing command includes a data erase command, the data erase command includes a target erase address, the data erase command is used to enable the flash memory to erase the data corresponding to the target erase address in the storage array, the target erase address includes a first erase address corresponding to the first data processing command and a second erase address corresponding to the second data processing command.

[0190] like Figure 6bAs shown, it is a flow chart of a method for determining a data erase command, which includes the following steps:

[0191] Step S6011, determining the storage address of the target data corresponding to the data erasing task in the flash memory.

[0192] The storage addresses include at least one group of continuous storage addresses, and the continuous storage addresses include a start storage address.

[0193] Specifically, the operation of the data erasure task is similar to the data write command, and both require support for the writing of corresponding data. However, in the data erasure task, the file to be written will not be transferred from the SOC chip to the flash memory. Instead, the flash memory deletes the data in the corresponding position through the write action, thereby completing the data erasure action.

[0194] Step S6012: Based on the storage address, determine the starting storage address of all consecutive storage addresses in each flash memory.

[0195] Specifically, as can be seen from the description in the above steps, the data erasing task needs to determine the position corresponding to the data erasing action (that is, the address corresponding to the data erasing command).

[0196] Since the flash memory will erase data of a fixed length (usually a block of data, which can be 64 bytes or other lengths) each time a data erase command is executed, the address corresponding to the data erase task is the starting storage address of the fixed-length data, rather than each individual address in the flash memory.

[0197] Furthermore, if Figure 6c As shown, it is a flow chart of a method for determining a starting storage address, which includes the following steps:

[0198] Step C1, determining all consecutive storage addresses in each flash memory.

[0199] Specifically, the starting storage address is determined based on the starting position of the continuously stored data, so firstly, all the continuous storage addresses where the data to be erased are located need to be determined.

[0200] Step C2: if the length of the continuous storage address is less than the set address length, the starting address of the continuous storage address is determined as the starting storage address corresponding to the continuous storage address.

[0201] Specifically, if the length of the continuous storage address where the data to be erased is located is less than the set address length (ie the aforementioned fixed length, such as 64 bytes), the starting position of the continuous storage address (ie the starting address) can be directly determined as the starting storage address.

[0202] Step C3, if the length of the continuous storage address is greater than the set address length, the starting address of the continuous storage address and the address whose distance from the starting address is an integer multiple of the set address length are both determined as the starting storage address corresponding to the continuous storage address.

[0203] Specifically, in another case, if the continuous storage address where the data to be erased is located is long (the length is greater than the set address length), the continuous storage address needs to be divided according to the set address length, and the addresses whose distance to the starting address is an integer multiple of the set address length are all the starting storage addresses corresponding to the data erase command.

[0204] For example, if the length of a segment of data to be erased is 160 bytes and the address length is set to 64 bytes, the starting storage addresses of the segment of data to be erased are the addresses of the 1st byte, the 65th byte, and the 129th byte respectively.

[0205] In some embodiments, if the distance between the start address of a continuous storage address and the previous start storage address is less than the set address length, the continuous storage address is regarded as a storage address continuous with the previous start storage address. The method for determining the subsequent start storage address refers to the above two steps.

[0206] Step S6013: Based on all the starting storage addresses in each flash memory, determine at least one data erasing command that needs to be executed by each flash memory.

[0207] Specifically, after determining the starting storage address corresponding to the data erase command, the data erase command corresponding to each flash memory can be determined.

[0208] Furthermore, the data erase command also includes: a write enable command, used to switch the flash memory to a state that supports write operations before sending the data erase command; a data transmission command, used to notify the flash memory to receive the data erase command; and a write enable disable command, used to switch the flash memory to a state that does not support write operations after sending all data erase commands.

[0209] Specifically, the data erase command is similar to the data write command, but does not include a specific sub-file to be written, and the write address in the data write task corresponds to the starting storage address in the data erase command.

[0210] Step S602: Based on the data processing task to be executed, a corresponding first data processing command is sent to a first flash memory connected to the SOC chip.

[0211] Step S603: Based on the analog switch, the flash memory connected to the SOC chip is switched, and a corresponding data processing command is sent to the switched flash memory.

[0212] Step S604, repeatedly switching the flash memory and sending data processing commands to the switched flash memory until all data processing commands corresponding to the data processing task are completed.

[0213] Specifically, steps S602 to S604 are the same as the corresponding steps in the aforementioned embodiment and will not be described in detail here.

[0214] The following is an example based on the above steps, wherein step S601 is omitted, and the implementation of steps S602 to S604 is specifically described here:

[0215] Step D1, the SOC first pulls up the GPIO to switch the analog switch mode, so that the SPI interface of the SOC and the SPI NAND1 is connected.

[0216] Step D2, the SOC sends a write enable command (06h) through the SPI interface to enable the write operation to the SPI NAND 1.

[0217] Step D3, SOC sends a data transmission command (D8h) through the SPI interface, and then sends a data erase command. The data erase command includes the address of file 1 (that is, the starting storage address of the first block of data to be erased corresponding to SPI NAND1), notifying SPI NAND 1 that it is about to start erasing files 1, 3, 5...127 (these files all belong to the first block of data to be erased).

[0218] Step D4: After the SOC sends the command, the SPI NAND 1 will perform an erase operation in the background (the above steps correspond to step S602).

[0219] Then, erase files 2, 4, 6…128 of SPI NAND2 (that is, the starting storage address of the first block of data to be erased corresponding to SPI NAND1) through the following operations.

[0220] Step D5, the SOC pulls the GPIO low to switch the analog switch mode, so that the SPI interface of the SOC and the SPI NAND2 are connected.

[0221] Step D6, the SOC sends a write enable command (06h) through the SPI interface to enable the write operation to the SPI NAND 2.

[0222] Step D7, SOC sends a data transmission command (D8h) through the SPI interface, and then sends a data erase command with the address of file 2 (that is, the starting storage address of the first block of data to be erased corresponding to SPI NAND2), notifying SPI NAND 2 that it is about to start erasing files 2, 4, 6...128.

[0223] Step D8: After the SOC sends the command, the SPI NAND 1 will perform an erase operation in the background (the above steps correspond to step S603).

[0224] Step D9, at this time, we pull up GPIO to a high level again. When we send commands to SPI NAND 2, SPI NAND 1 continues to execute the data erase command. At this time, we send a status query command (0Fh) to confirm that the operation has been completed. If it has not been completed, the query command (0Fh) is executed repeatedly until the operation is confirmed to be completed. At this time, files 1, 3, 5...127 have been erased.

[0225] Step D10: If necessary, we continue to erase the file. The SOC writes an enable command (06h) through the SPI interface to enable the write operation to SPI NAND 1.

[0226] Step D11, SOC sends a data transmission command (D8h) through the SPI interface, and then sends a data erase command with the address of file 129 (that is, the starting storage address of the second block of data to be erased corresponding to SPI NAND1), notifying SPINAND 1 that it is about to start erasing files 129, 131, 133...255 (these files all belong to the second block of data to be erased corresponding to SPI NAND1).

[0227] Step D12: After the SOC sends the command, the SPI NAND 1 performs an erase operation in the background.

[0228] Step D13, at this time, we pull down GPIO to a low level again. When we send commands to SPI NAND 2, SPI NAND 2 continues to execute the data erase command. At this time, we send a status query command (0Fh) to confirm that the operation has been completed. If it has not been completed, we execute the query command (0Fh) repeatedly until the operation is confirmed to be completed. At this time, files 2, 4, 6...128 have been erased. Repeat the above operation until all the data to be erased is erased (the above step corresponds to step S604).

[0229] The flash memory data processing method provided by the embodiment of the present disclosure determines the starting storage address corresponding to the data erasure task, then determines the data erasure command corresponding to each flash memory, and then sends the data erasure command to each flash memory in sequence until all the data to be erased are erased. Thus, by executing the data erasure command of multiple flash memories respectively, the data erasure action corresponding to each flash memory can be quickly completed, the data stored in the flash memory can be quickly deleted, and the data processing efficiency of the flash memory can be improved.

[0230] Figure 7 The structure diagram of a flash memory data processing device provided by an embodiment of the present disclosure is as follows. Figure 7 As shown, the flash memory data processing device 700 is applied to an embedded system, the embedded system includes a SOC chip, an analog switch and a flash memory, the flash memory includes a first flash memory and a second flash memory, the SOC chip is connected to the first flash memory and the second flash memory respectively through the analog switch; the flash memory data processing device 700 includes a first sending module 710, a switching module 720 and a processing module 730:

[0231] A first sending module 710 is used to send a corresponding first data processing command to a first flash memory that is connected to the SOC chip based on a data processing task to be executed, wherein the data processing task includes a data processing command, and the data processing command includes a first data processing command corresponding to the first flash memory and a second data processing command corresponding to the second flash memory;

[0232] A switching module 720, configured to switch the flash memory connected to the SOC chip based on the analog switch, and send a corresponding data processing command to the switched flash memory, wherein the switched flash memory is used to indicate the flash memory connected to the SOC chip after the analog switch is switched;

[0233] The processing module 730 is used to repeatedly switch the flash memory and send data processing commands to the switched flash memory until all data processing commands corresponding to the data processing task are completed.

[0234] Optionally, the switching module 720 is specifically used to, based on an analog switch, switch the flash memory that is connected to the SOC chip; determine that the switched flash memory is not in a state of executing a data processing command; and send a corresponding data processing command to the switched flash memory.

[0235] Optionally, the switching module 720 is specifically used to switch the level signal input from the SOC chip to the analog switch, wherein the analog switch is used to determine the flash memory connected to the SOC chip based on the level signal.

[0236] Optionally, the switching module 720 is specifically configured to send a status query command to the switched flash memory; and determine, based on feedback information of the switched flash memory, that the switched flash memory is in a state where the data processing command is not executed.

[0237] Optionally, the switching module 720 is also used to, based on an analog switch, after switching the flash memory connected to the SOC chip, determine that the switched flash memory is in a state of executing a data processing command; based on the analog switch, switch the flash memory connected to the SOC chip, or repeatedly send a status query command to the switched flash memory until it is determined that the switched flash memory is in a state of not executing a data processing command.

[0238] Optionally, the first sending module 710 specifically includes: the data processing task includes a data writing task, the flash memory includes a cache and a storage array; the data processing command includes a data writing command, the data writing command is used to send a sub-file of a set number of a file to be written and the storage address of the sub-file to the flash memory, the flash memory is used to receive the sub-file of the set number into the cache, and the flash memory is also used to store the sub-file of the set number in a storage address corresponding to the storage array based on the data writing command, and the set number includes a first set number corresponding to the first data processing command and a second set number corresponding to the second data processing command.

[0239] Optionally, the first sending module 710 specifically includes, and the data processing command also includes: a write enable command, used to switch the flash memory to a state that supports write operations before sending a data write command; an output transmission command, used to notify the flash memory to receive the data write command; a write enable command is turned off, used to switch the flash memory to a state that does not support write operations when the transmission of the data write command corresponding to the file to be written is completed.

[0240] Optionally, the first sending module 710 specifically includes: the data processing task includes a data reading task, the flash memory includes a cache and a storage array; the data processing command includes a page read command and a data read command, the page read command includes a set address, the data read command is used to enable the flash memory to transfer the data corresponding to the set address in the storage array to the cache of the flash memory, the data read command is used to enable the flash memory to send the data in the cache to the SOC chip, and the set address includes a first set address corresponding to the first data processing command and a second set address corresponding to the second data processing command.

[0241] Optionally, the processing module 730 is specifically used to repeatedly switch the flash memory and send data processing commands to the switched flash memory until all corresponding data processing commands are sent to the flash memory; splicing the data received in the SOC chip to obtain complete data corresponding to the data reading task.

[0242] Optionally, the first sending module 710 specifically includes: the data processing task includes a data erasure task, the flash memory includes a cache and a storage array; the data processing command includes a data erasure command, the data erasure command includes a target erase address, the data erase command is used to enable the flash memory to erase the data corresponding to the target erase address in the storage array, and the target erase address includes a first erase address corresponding to the first data processing command and a second erase address corresponding to the second data processing command.

[0243] In this embodiment, the functions and principles of the flash memory data processing device have been fully explained in the above embodiments and will not be repeated here.

[0244] Figure 8 A schematic diagram of the structure of a control device provided by an embodiment of the present disclosure, such as Figure 8 As shown, the control device 800 includes: a memory 810 and a processor 820 .

[0245] The memory 810 stores a computer program that can be executed by at least one processor 820. The computer program is executed by at least one processor 820 to enable the control device to implement the material removal method provided in any of the above embodiments or the flash memory data processing method provided in any of the above embodiments.

[0246] The memory 810 and the processor 820 may be connected via a bus 830 .

[0247] The relevant instructions can be understood by referring to the relevant descriptions and effects corresponding to the method embodiments, which will not be repeated here.

[0248] Fig. 9 A schematic diagram of the structure of a flash memory data processing system provided by an embodiment of the present disclosure is shown in FIG. Fig. 9 As shown, the flash memory data processing system 900 includes: a SOC chip 910, at least two flash memory memories 920;

[0249] The SOC chip includes a built-in processor, and the built-in processor is used to execute the flash memory data processing method according to the first aspect of the present disclosure;

[0250] Flash storage consists of interconnected controllers, caches, and storage arrays.

[0251] The relevant instructions can be understood by referring to the relevant descriptions and effects corresponding to the method embodiments, which will not be repeated here.

[0252] An embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, and the computer program is executed by a processor to implement a material retrieval method as provided in any of the above method embodiments or a flash memory data processing method as provided in any of the above embodiments.

[0253] Among them, the computer readable storage medium may be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.

[0254] An embodiment of the present disclosure provides a computer program product, which includes computer execution commands. When the computer execution commands are executed by a processor, they are used to implement the material removal method in the above method embodiment or the flash memory data processing method provided in any of the above embodiments.

[0255] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules is only a logical function division, and there may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0256] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the disclosure disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0257] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A flash memory data processing method, characterized in that: Applied to an embedded system, the embedded system includes a SOC chip, an analog switch and a flash memory, the flash memory includes a first flash memory and a second flash memory, the SOC chip is connected to the first flash memory and the second flash memory respectively through the analog switch; the flash memory includes a controller, a cache and a storage array connected to each other; The flash memory data processing method comprises: Based on the data processing task to be executed, sending a corresponding first data processing command to a first flash memory that is in a connected state with the SOC chip, wherein the data processing task includes a data processing command, and the data processing command includes a first data processing command corresponding to the first flash memory and a second data processing command corresponding to the second flash memory; Based on the analog switch, switching the flash memory connected to the SOC chip, and sending a corresponding data processing command to the switched flash memory, wherein the switched flash memory is used to indicate the flash memory connected to the SOC chip after the analog switch is switched; Repeat switching the flash memory and sending data processing commands to the switched flash memory until all data processing commands corresponding to the data processing task are completed.

2. The method according to claim 1, characterized in that The method of switching the flash memory connected to the SOC chip based on the analog switch and sending a corresponding data processing command to the switched flash memory includes: Based on the analog switch, switching the flash memory connected to the SOC chip; Determining that the switched flash memory is not in a state of executing a data processing command; Sending a corresponding data processing command to the switched flash memory.

3. The method according to claim 2, characterized in that The step of switching the flash memory connected to the SOC chip based on the analog switch includes: The level signal input from the SOC chip to the analog switch is switched, wherein the analog switch is used to determine the flash memory connected to the SOC chip based on the level signal.

4. The method according to claim 2, characterized in that: The determining that the switched flash memory is not in a state of executing a data processing command includes: Sending a status query command to the switched flash memory; Based on the feedback information of the switched flash memory, it is determined that the switched flash memory is in a state where no data processing command is executed.

5. The method according to claim 2, characterized in that: After switching the flash memory connected to the SOC chip based on the analog switch, the method further includes: Determining that the switched flash memory is in a state of executing a data processing command; Based on the analog switch, the flash memory connected to the SOC chip is switched, or a status query command is repeatedly sent to the switched flash memory until it is determined that the switched flash memory is in a state where no data processing command is executed.

6. The method according to any one of claims 1 to 5, characterized in that The data processing task includes a data writing task; The data processing command includes a data write command, the data write command is used to send a sub-file of a set number of a file to be written and the storage address of the sub-file to the flash memory, the flash memory is used to receive the sub-file of the set number into a cache, the flash memory is also used to store the sub-file of the set number in the storage address corresponding to the storage array based on the data write command, the set number includes a first set number corresponding to the first data processing command and a second set number corresponding to the second data processing command.

7. The method according to claim 6, characterized in that The data processing command also includes: A write enable command, used to switch the flash memory to a state supporting write operations before sending a data write command; Outputting a transmission command, used to notify the flash memory to receive a data write command; The write enable command is disabled, and is used to switch the flash memory to a state that does not support write operations when the transmission of the data write command corresponding to the file to be written is completed.

8. The method according to any one of claims 1 to 5, characterized in that The data processing task includes a data reading task; The data processing command includes a page read command and a data read command, the page read command includes a set address, the data read command is used to enable the flash memory to transfer data corresponding to the set address in the storage array to the cache of the flash memory, the data read command is used to enable the flash memory to send the data in the cache to the SOC chip, and the set address includes a first set address corresponding to the first data processing command and a second set address corresponding to the second data processing command.

9. The method according to claim 8, characterized in that The repeatedly switching the flash memory and sending the data processing command to the switched flash memory until all the data processing commands corresponding to the data processing task are completed include: Repeatingly switching the flash memory and sending data processing commands to the switched flash memory until all corresponding data processing commands are sent to the flash memory; The data received in the SOC chip are spliced ​​to obtain complete data corresponding to the data reading task.

10. The method according to any one of claims 1 to 5, characterized in that The data processing task includes a data erasure task; The data processing command includes a data erasure command, the data erasure command includes a target erasure address, the data erasure command is used to make the flash memory erase the data corresponding to the target erasure address in the storage array, the target erasure address includes a first erasure address corresponding to the first data processing command and a second erasure address corresponding to the second data processing command.

Images