Memory chip testing method, device, equipment, medium and program product

Abstract

The present disclosure relates to a method, apparatus, device, medium and program product for testing a memory chip, and relates to the technical field of memory chip testing. The testing method comprises: writing test data to a memory cell corresponding to a target bit line; providing a first voltage to a first pseudo bit line, and reading the test data in the memory cell corresponding to the target bit line, so as to determine a first failure number of the memory cell corresponding to the target bit line; writing the test data to the memory cell corresponding to the target bit line again; providing a second voltage to the first pseudo bit line, and reading the test data in the memory cell corresponding to the target bit line, so as to determine a second failure number of the memory cell corresponding to the target bit line, wherein the second voltage is different from the first voltage; and directly judging the validity of the actual connection potential of the pseudo bit line and whether it can work normally according to the first failure number and the second failure number.

Description

Technical Field

[0001] The present disclosure relates to the technical field of memory chip testing, and in particular to a memory chip testing method, apparatus, device, medium, and program product. Background Art

[0002] With the continuous advancement of memory technology, the market demands increasingly higher performance and reliability from memory chips. Before leaving the factory, memory chips are typically subjected to various tests to obtain performance parameters and evaluate their performance. For example, during burn-in testing of memory chips, a potential difference must be established between a dummy bit line and its adjacent bit line to determine whether there are process defects between them.

[0003] Memory chips currently do not have the function of reading and writing data to the memory cells corresponding to the pseudo bit lines. As a result, it is impossible to use the method of directly reading data from the memory cells corresponding to the pseudo bit lines to determine the validity of the actual connection potential of the pseudo bit lines and whether they can work normally, affecting the efficiency and accuracy of memory chip testing. Summary of the Invention

[0004] Based on this, it is necessary to provide a memory chip testing method, device, equipment, medium and program product that can directly determine the validity of the actual connection potential of the pseudo bit line and whether it can work normally.

[0005] To achieve the above and other objectives, a first aspect of the present disclosure provides a method for testing a memory chip. The memory chip includes a plurality of memory cells arranged in an array, a plurality of word lines, a plurality of bit lines, and a first dummy bit line. Each memory cell includes a pass transistor and a capacitor coupled to a first terminal of the pass transistor. Each word line is coupled to a control terminal of a pass transistor in a row of memory cells. Each bit line is coupled to a second terminal of a pass transistor in a column of memory cells. The first dummy bit line is located on one side of the plurality of bit lines. The method for testing the memory chip includes:

[0006] Writing test data to a memory cell corresponding to a target bit line, wherein the target bit line is a bit line adjacent to the first dummy bit line among the plurality of bit lines; providing a first voltage to the first dummy bit line, and reading the test data from the memory cell corresponding to the target bit line to determine a first failure number of the memory cell corresponding to the target bit line;

[0007] writing test data again to the memory cells corresponding to the target bit line; providing a second voltage to the first dummy bit line and reading the test data from the memory cells corresponding to the target bit line to determine a second number of failures in the memory cells corresponding to the target bit line, wherein the second voltage is different from the first voltage;

[0008] Based on the first failure number and the second failure number, it is determined whether the first dummy bit line is set to the first voltage during the process of providing the first voltage to the first dummy bit line, and whether the first dummy bit line is set to the second voltage during the process of providing the second voltage to the first dummy bit line.

[0009] In the memory chip testing method described in the above embodiment, the accuracy of data read out by the memory chip is affected by the sensing margin of the sense amplifier itself, which in turn is affected by the coupling effect between the bit lines to which it is connected and the adjacent bit lines. As the spacing between adjacent bit lines in the memory chip reaches the nanometer level, the coupling effect between different bit lines has an increasingly significant impact on the sensing margin of the sense amplifier. After writing test data to a memory cell corresponding to a target bit line, wherein the target bit line is a bit line adjacent to a first dummy bit line among a plurality of bit lines, a first voltage is supplied to the first dummy bit line, and test data in the memory cell corresponding to the target bit line is read to determine a first number of failures in the memory cell corresponding to the target bit line. Then, test data is again written to the memory cell corresponding to the target bit line, and then a second voltage is supplied to the first dummy bit line, and test data in the memory cell corresponding to the target bit line is read to determine a second number of failures in the memory cell corresponding to the target bit line, wherein the second voltage is different from the first voltage. Since, when the first dummy bit line is operating normally, the first dummy bit line connected to the first voltage and the first dummy bit line connected to the second voltage have different coupling effects on their adjacent bit lines, and the different coupling effects have different impacts on the sensing margin of the sense amplifier, the first number of failures and the second number of failures are used to determine whether the first dummy bit line is set to the first voltage during the process of supplying the first voltage to the first dummy bit line, and whether the first dummy bit line is set to the second voltage during the process of supplying the second voltage to the first dummy bit line. Whether the dummy bit line can work normally and the effectiveness of the actual connection potential can be directly judged based on the first failure number and the second failure number, thereby improving the efficiency and accuracy of the memory chip test.

[0010] In some embodiments, the test data is low logic data; and determining, based on the first failure number and the second failure number, whether the first dummy bit line is set to the first voltage during a process of supplying the first voltage to the first dummy bit line, and whether the first dummy bit line is set to the second voltage during a process of supplying the second voltage to the first dummy bit line, comprises:

[0011] determining that the first dummy bit line is set to the first voltage during supply of the first voltage to the first dummy bit line and is set to the second voltage during supply of the second voltage to the first dummy bit line, when the first voltage is higher than the second voltage and the first number of failures is greater than the second number of failures, or determining that the first dummy bit line is set to the first voltage during supply of the first voltage to the first dummy bit line and is set to the second voltage during supply of the second voltage to the first dummy bit line; or

[0012] In a case where the first voltage is higher than the second voltage and the first failure number is less than or equal to the second failure number, or in a case where the first voltage is lower than the second voltage and the first failure number is greater than or equal to the second failure number, it is determined that the first pseudo bit line is not set to the first voltage during the process of providing the first voltage to the first pseudo bit line, and that the first pseudo bit line is not set to the second voltage during the process of providing the second voltage to the first pseudo bit line.

[0013] In some embodiments, the test data is high logic data; and determining, based on the first failure number and the second failure number, whether the first dummy bit line is set to the first voltage during a process of supplying the first voltage to the first dummy bit line, and whether the first dummy bit line is set to the second voltage during a process of supplying the second voltage to the first dummy bit line, comprises:

[0014] determining that the first dummy bit line is set to the first voltage during supply of the first voltage to the first dummy bit line and is set to the second voltage during supply of the second voltage to the first dummy bit line, when the first voltage is higher than the second voltage and the first number of failures is smaller than the second number of failures, or determining that the first dummy bit line is set to the first voltage during supply of the first voltage to the first dummy bit line and is set to the second voltage during supply of the second voltage to the first dummy bit line; or

[0015] In the case where the first voltage is higher than the second voltage and the first failure number is greater than or equal to the second failure number, or in the case where the first voltage is lower than the second voltage and the first failure number is less than or equal to the second failure number, it is determined that the first pseudo bit line is not set to the first voltage during the process of providing the first voltage to the first pseudo bit line, and that the first pseudo bit line is not set to the second voltage during the process of providing the second voltage to the first pseudo bit line.

[0016] In some embodiments, one of the first voltage and the second voltage is higher than a precharge voltage of the target bit line and the other is lower than the precharge voltage.

[0017] In some embodiments, the memory chip further includes: a sensing amplifier coupled to a target bit line; in a process of reading test data in a memory cell corresponding to the target bit line, the sensing amplifier is controlled to enter a sensing amplification stage in advance compared to a normal reading operation, so as to shorten a charge sharing time between a capacitor in the memory cell corresponding to the target bit line and the target bit line.

[0018] A second aspect of the present disclosure provides a test device for a memory chip, wherein the memory chip includes a plurality of memory cells arranged in an array, a plurality of word lines, a plurality of bit lines, and a first dummy bit line, each memory cell including a transmission transistor and a capacitor coupled to a first end of the transmission transistor; each word line is coupled to a control end of a transmission transistor of a row of memory cells; each bit line is coupled to a second end of a transmission transistor of a column of memory cells; the first dummy bit line is located on one side of the plurality of bit lines; the test device for the memory chip includes a first test module, a second test module, and a judgment module, wherein the first test module is used to write test data to a memory cell corresponding to a target bit line, wherein the target bit line is a bit line adjacent to the first dummy bit line among the plurality of bit lines, and a test data is provided to the first dummy bit line. a first voltage and reading test data in the storage cell corresponding to the target bit line to determine a first failure number of the storage cell corresponding to the target bit line; a second test module is used to write test data to the storage cell corresponding to the target bit line again, provide a second voltage to the first pseudo bit line, and read the test data in the storage cell corresponding to the target bit line to determine a second failure number of the storage cell corresponding to the target bit line, wherein the second voltage is different from the first voltage; and a judgment module is used to judge whether the first pseudo bit line is set to the first voltage in the process of providing the first voltage to the first pseudo bit line, and whether the first pseudo bit line is set to the second voltage in the process of providing the second voltage to the first pseudo bit line based on the first failure number and the second failure number.

[0019] In the memory chip testing device described in the above embodiment, the accuracy of data read from the memory chip is affected by the sensing margin of the sense amplifier itself, which in turn is affected by the coupling effect between the bit lines to which it is connected and the adjacent bit lines. As the spacing between adjacent bit lines in the memory chip reaches the nanometer level, the coupling effect between different bit lines has an increasingly significant impact on the sensing margin of the sense amplifier. After the first test module writes test data to a memory cell corresponding to a target bit line, wherein the target bit line is a bit line adjacent to the first dummy bit line among the plurality of bit lines, a first voltage is applied to the first dummy bit line, and the test data in the memory cell corresponding to the target bit line is read to determine a first number of failures in the memory cell corresponding to the target bit line. Then, the second test module again writes test data to the memory cell corresponding to the target bit line, and then applies a second voltage to the first dummy bit line, and reads the test data in the memory cell corresponding to the target bit line to determine a second number of failures in the memory cell corresponding to the target bit line, wherein the second voltage is different from the first voltage. Since the first dummy bit line has different coupling effects on its adjacent bit lines when the first dummy bit line is operating normally, the determination module utilizes the different amounts of influence of the different coupling effects on the sensing margin of the sense amplifier, and determines, based on the first number of failures and the second number of failures, whether the first dummy bit line was set to the first voltage during the process of applying the first voltage to the first dummy bit line, and whether the first dummy bit line was set to the second voltage during the process of applying the second voltage to the first dummy bit line. Whether the dummy bit line can work normally and the effectiveness of the actual connection potential can be directly judged based on the first failure number and the second failure number, thereby improving the efficiency and accuracy of the memory chip test.

[0020] In some embodiments, the judgment module includes a first comparison and analysis module and / or a second comparison and analysis module. The first comparison and analysis module is used to determine that in the process of providing the first voltage to the first pseudo bit line, the first pseudo bit line is set to the first voltage, and in the process of providing the second voltage to the first pseudo bit line, the first pseudo bit line is set to the second voltage when the first voltage is higher than the second voltage and the first failure number is greater than the second failure number, or when the first voltage is lower than the second voltage and the first failure number is less than the second failure number; the second comparison and analysis module is used to determine that in the process of providing the first voltage to the first pseudo bit line, the first pseudo bit line is set to the first voltage, and in the process of providing the second voltage to the first pseudo bit line, the first pseudo bit line is set to the second voltage when the first voltage is higher than the second voltage and the first failure number is less than the second failure number, or when the first voltage is lower than the second voltage and the first failure number is greater than the second failure number.

[0021] A third aspect of the present disclosure provides an electronic device including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the memory chip testing method in any of the embodiments of the present disclosure are implemented.

[0022] A fourth aspect of the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the memory chip testing method in any of the embodiments of the present disclosure are implemented.

[0023] A fifth aspect of the present disclosure provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the memory chip testing method in any of the embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1 A schematic flow chart of a method for testing a memory chip provided in some embodiments of the present disclosure;

[0026] Figure 2 A schematic diagram of the structure of a portion of a memory array in a memory chip to be tested in some embodiments of the present disclosure;

[0027] Figure 3 Schematic diagram of the structure of a portion of a memory array in a memory chip to be tested in other embodiments of the present disclosure;

[0028] Figure 4 A schematic flow chart of a memory chip testing method provided in some other embodiments of the present disclosure;

[0029] Figure 5 A schematic diagram of the principle of part of the read / write circuit in the memory chip to be tested in some embodiments of the present disclosure;

[0030] Figure 6 A schematic diagram of the principle of failure of reading data after writing "0" to a memory chip to be tested in some embodiments of the present disclosure;

[0031] Figure 7 A schematic diagram of the principle of successfully reading data after writing "0" to a memory chip to be tested in some embodiments of the present disclosure;

[0032] Figure 8 A schematic flow chart of a memory chip testing method provided in some further embodiments of the present disclosure;

[0033] Figure 9 A schematic diagram of the principle of failure of reading data after writing "1" to a memory chip to be tested in some embodiments of the present disclosure;

[0034] Figure 10 A schematic diagram of the principle of successfully reading data after writing "1" to a memory chip to be tested in some embodiments of the present disclosure;

[0035] Figure 11 A schematic structural block diagram of a memory chip testing device provided in some embodiments of the present disclosure;

[0036] Figure 12 This is a schematic structural block diagram of a memory chip testing device provided in some other embodiments of the present disclosure.

[0037] Description of reference numerals:

[0038] 10. Test device for memory chip; 11. First test module; 12. Second test module; 13. Judgment module; 131. First comparison and analysis module; 132. Second comparison and analysis module; 200. Equalizer; 300. Storage unit; 400. Sense amplifier; 201. First signal line; 301. Second signal line. DETAILED DESCRIPTION

[0039] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0041] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.

[0043] In this disclosure, unless otherwise expressly specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements. Those skilled in the art will understand the specific meanings of the above terms in this disclosure based on specific circumstances.

[0044] In addition, the terms "first", "second", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features.

[0045] In a memory chip, data is read and written from a capacitor connected to a transistor by controlling the on and off of the transistor. The PN junction of the transistor is in thermodynamic equilibrium when there is no bias voltage, and the electrochemical potential of electrons in the N phase and the P phase are equal. The interface layer between the N phase and the P phase acts as a loss layer. When a bias voltage is present, the thermodynamic equilibrium between the PN junctions is broken, and leakage current is observed due to the uneven electrochemical potential in the PN junction system.

[0046] The data signal read from a memory cell in a memory chip is transmitted to a sense amplifier via the bit line connected to the memory cell, where it is amplified before being output. However, with the continuous advancement of memory chip manufacturing processes, the spacing between bit lines has become increasingly smaller. When a bit line is activated, its coupling effect on surrounding bit lines becomes increasingly significant. This coupling effect causes increasing variations in the sensing margin of the sense amplifier, even affecting the accuracy of the data read out by the memory chip.

[0047] like Figure 1 As shown, in some embodiments of the present disclosure, a method for testing a memory chip is provided. This embodiment uses a processor to execute the memory chip testing method as an example. It is understood that the processor can be located on a terminal or a server. The memory chip testing method is used to generate judgment result information in a preset format. The judgment result information includes whether the first dummy bit line is set to the first voltage during the process of providing the first voltage to the first dummy bit line, and whether the first dummy bit line is set to the second voltage during the process of providing the second voltage to the first dummy bit line.

[0048] Based on this, please refer to Figure 1-Figure 2 The present disclosure provides a test method for a memory chip, wherein the memory chip includes a plurality of memory cells arranged in an array, a plurality of bit lines BL, a plurality of word lines WL and a first pseudo bit line DBL0, each memory cell includes a transfer transistor and a capacitor C coupled to the first end of the transfer transistor; each word line is coupled to the control end of the transfer transistor of a row of memory cells; each bit line is coupled to the second end of the transfer transistor of a column of memory cells; the first pseudo bit line DBL0 is located on one side of the plurality of bit lines BL. It should be noted that, in the present disclosure, a number of memory cells corresponding to the transfer transistors that can be controlled by each word line are referred to as a row of memory cells, regardless of whether these memory cells are located in the same row in physical space; similarly, a number of memory cells corresponding to the transfer transistors connected to each bit line are referred to as a column of memory cells, regardless of whether these memory cells are located in the same column in physical space. The test method for a memory chip includes the following steps:

[0049] Step S110, writing test data to a memory cell corresponding to a target bit line, wherein the target bit line is a bit line adjacent to the first dummy bit line among the plurality of bit lines; providing a first voltage to the first dummy bit line, and reading the test data from the memory cell corresponding to the target bit line to determine a first failure number of the memory cell corresponding to the target bit line;

[0050] Step S120, writing test data again to the memory cells corresponding to the target bit line; providing a second voltage to the first dummy bit line, and reading the test data from the memory cells corresponding to the target bit line to determine a second number of failures in the memory cells corresponding to the target bit line, wherein the second voltage is different from the first voltage;

[0051] Step S130, judging whether the first dummy bit line is set to the first voltage during the process of providing the first voltage to the first dummy bit line, and whether the first dummy bit line is set to the second voltage during the process of providing the second voltage to the first dummy bit line, based on the first failure number and the second failure number.

[0052] As an example, please refer to Figure 1 and Figure 2The accuracy of the data read out by the memory chip is affected by the sensing margin of the sensing amplifier itself, and the sensing margin of the sensing amplifier itself is affected by the coupling effect of the adjacent bit lines to which it is connected. The spacing between adjacent bit lines in the memory chip reaches the nanometer level, resulting in the coupling effect between different bit lines having an increasingly obvious effect on the sensing margin of the sensing amplifier. After writing test data to the memory cell corresponding to the target bit line, wherein the target bit line is a bit line adjacent to the first pseudo bit line DBL0 among multiple bit lines, for example, the target bit line is bit line BL0, a first voltage such as a turn-on voltage is provided to the first pseudo bit line DBL0, and the test data in the memory cell corresponding to the target bit line is read to determine the first failure number of the memory cell corresponding to the target bit line, the first failure number being the number of failures in the read data; then, writing test data to the memory cell corresponding to the target bit line again, and then providing a second voltage such as a turn-off voltage to the first pseudo bit line, and reading the test data in the memory cell corresponding to the target bit line to determine the first failure number of the memory cell corresponding to the target bit line. The second failure number of the cell is the number of read data failures; wherein the second voltage is different from the first voltage; because when the first dummy bit line DBL0 is operating normally, the first dummy bit line DBL0 connected to the first voltage and the first dummy bit line DBL0 connected to the second voltage have different coupling effects on their adjacent bit lines, and the different coupling effects have different impacts on the sensing margin of the sense amplifier. Based on the first failure number and the second failure number, it is determined whether the first dummy bit line is set to the first voltage during the process of providing the first voltage to the first dummy bit line, and whether the first dummy bit line is set to the second voltage during the process of providing the second voltage to the first dummy bit line. This allows direct determination of whether the dummy bit line is operating normally and the effectiveness of the actual connection potential based on the first failure number and the second failure number, thereby improving the efficiency and accuracy of memory chip testing.

[0053] As an example, see Figure 3 The memory chip may include multiple pseudo bit lines, a first pseudo bit line DBL0 among the multiple pseudo bit lines is located on a first side of the multiple bit lines (BL0, BL1, ..., BLN), and a second pseudo bit line DBL1 among the multiple pseudo bit lines is located on a second side of the multiple bit lines (BL0, BL1, ..., BLN), wherein the first side and the second side are opposite sides of the multiple bit lines (BL0, BL1, ..., BLN) along a first direction ox, the multiple pseudo bit lines may be symmetrically distributed on the first side and the second side of the multiple bit lines (BL0, BL1, ..., BLN), the first direction ox may be parallel to the word line extension direction, and N is a positive integer, for example, N may be 16, 32, 64, 128, 256, 512 or 1024, etc. The multiple word lines WL in the memory chip may include WL0, WL1, ..., WLM; M is a positive integer, for example, M may be 16, 32, 64, 128, 256, 512 or 1024, etc.

[0054] Figure 2 and Figure 3 The row direction in the embodiment of the present disclosure can be parallel to the first direction ox, the column direction can be parallel to the second direction oy, the second direction oy can be parallel to the bit line extension direction, and the first direction ox can be perpendicular to the second direction oy. The row direction and column direction in the embodiment of the present disclosure can be interchanged, and the technical solutions after the interchange still fall within the scope of protection of the present disclosure.

[0055] As an example, see Figure 1 、 Figure 4 The test data in step S110 and step S120 may be low logic data; and in step S130, judging, based on the first number of failures and the second number of failures, whether the first dummy bit line is set to the first voltage during the process of supplying the first voltage to the first dummy bit line, and whether the first dummy bit line is set to the second voltage during the process of supplying the second voltage to the first dummy bit line, includes:

[0056] Step S131, determining that the first dummy bit line is set to the first voltage during the process of supplying the first voltage to the first dummy bit line, and that the first dummy bit line is set to the second voltage during the process of supplying the second voltage to the first dummy bit line, when the first voltage is higher than the second voltage and the first failure number is greater than the second failure number, or when the first voltage is lower than the second voltage and the first failure number is less than the second failure number; or

[0057] Step S132, when the first voltage is higher than the second voltage and the first failure number is less than or equal to the second failure number, or when the first voltage is lower than the second voltage and the first failure number is greater than or equal to the second failure number, determine that the first pseudo bit line is not set to the first voltage during the process of providing the first voltage to the first pseudo bit line, and that the first pseudo bit line is not set to the second voltage during the process of providing the second voltage to the first pseudo bit line.

[0058] For Dynamic Random Access Memory (DRAM), the row precharge time (tRP) is the time between the precharge command (PRE) and the activate command (ACT) of the next word line. It is used to characterize the speed at which the memory array in the DRAM recovers to the precharge state, especially the time required for the bit line in the memory array to charge from a high or low level to an intermediate potential. For example, please refer to Figure 5The sense amplifier 400 includes a transistor M1, a transistor M2, a transistor M3, and a transistor M4. The source of transistor M1 and the source of transistor M2 are both connected to a second power supply, which is used to provide the NMOS (NMOS of Sense Amplifier, NSA) common source power supply signal (NSA Common Source, NCS) of the sense amplifier to transistors M1 and M2. NCS is used to provide a low potential voltage VSS. The source of transistor M3 and the source of transistor M4 are both connected to a first power supply, which is used to provide the PMOS (PMOS of Sense Amplifier, PSA) common source power supply signal (PSA Common Source, PCS) of the sense amplifier to transistors M3 and M4. PCS is used to provide a high potential voltage VARY. The gates of the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all connected to the first signal line 201, which is used to provide the equalizer 200 with the equalization voltage V EQ , to turn on or off the equalizer 200, the source of the first transistor Q1 is connected to the bit line BL, and the drain of the first transistor Q1 is connected to the reference bit line / BL. The source of the second transistor Q2 is connected to the bit line BL, and the drain of the second transistor Q2 is connected to the source of the third transistor Q3. The drain of the third transistor Q3 is connected to the complementary bit line / BL, and the drain of the second transistor Q2 and the source of the third transistor Q3 are also connected to the second signal line 301. The second signal line 301 is used to provide a reset voltage to the bit line BL and the complementary bit line / BL. The second signal line 301 is connected to the peripheral circuit and is used to provide a bit line precharge voltage VBLP to the bit line BL and the complementary bit line / BL. The second signal line 301 precharges the sense amplifier 400 to the bit line precharge voltage VBLP (Voltage of Bit Line Precharge). Please continue to refer to Figure 2 When the first pseudo bit line DBL0 operates normally, the first pseudo bit line DBL0 connected to the first voltage and the first pseudo bit line DBL0 connected to the second voltage have different coupling effects on their adjacent bit lines, such as the bit line BL0. The different coupling effects cause the potentials on the bit lines to deviate from the bit line precharge voltage VBLP to different degrees, thereby causing different sensing margins of the sense amplifier. For example, if the coupling effect causes the sensing amplification capability of the sense amplifier to decrease, it will cause read data errors. Conversely, if the coupling effect causes the sensing amplification capability of the sense amplifier to increase, it will improve the accuracy of the data read by the sense amplifier.

[0059] As an example, please refer to Figure 4-Figure 6After low logic data, such as data “0”, is written into the memory cell 300, when the first voltage is higher than the second voltage and the first pseudo bit line DBL0 is capable of normal operation, the coupling effect of the first pseudo bit line DBL0 set to the first voltage on the target bit line is greater than the coupling effect of the first pseudo bit line DBL0 set to the second voltage on the target bit line. Therefore, if, in the process of supplying the first voltage to the first pseudo bit line, a first failure number of test data read from the memory cell corresponding to the target bit line is greater than a second failure number of test data read from the memory cell corresponding to the target bit line in the process of supplying the second voltage to the first pseudo bit line, it is determined that the first pseudo bit line is set to the first voltage in the process of supplying the first voltage to the first pseudo bit line, and that the first pseudo bit line is set to the second voltage in the process of supplying the second voltage to the first pseudo bit line.

[0060] As an example, please refer to Figure 4-Figure 5 After low logic data, such as data “0”, is written into the memory cell 300, when the first voltage is lower than the second voltage and the first pseudo bit line DBL0 is able to operate normally, the coupling effect of the first pseudo bit line DBL0 set to the first voltage on the target bit line is smaller than the coupling effect of the first pseudo bit line DBL0 set to the second voltage on the target bit line. Therefore, if, in the process of supplying the first voltage to the first pseudo bit line, a first failure number of test data read from the memory cell corresponding to the target bit line is smaller than a second failure number of test data read from the memory cell corresponding to the target bit line in the process of supplying the second voltage to the first pseudo bit line, it is determined that the first pseudo bit line is set to the first voltage in the process of supplying the first voltage to the first pseudo bit line, and that the first pseudo bit line is set to the second voltage in the process of supplying the second voltage to the first pseudo bit line.

[0061] As an example, see Figure 2 、 Figure 6-Figure 7 , one of the first voltage and the second voltage can be set to be higher than the precharge voltage of the target bit line and the other to be lower than the precharge voltage. The memory chip also includes: a sense amplifier coupled to the target bit line; during the process of reading test data from the memory cell corresponding to the target bit line, compared to a normal read operation, the sense amplifier is controlled to enter the sense amplification phase earlier (i.e., the SDT is reduced, i.e., the charge sharing time, i.e., the time interval from WL on to SA on, is shortened) to shorten the charge sharing time between the capacitor in the memory cell corresponding to the target bit line and the target bit line, making it more likely that read data errors will occur, thereby making it easier to obtain the first failure count and the second failure count. In other words, if the sensing margin of the sense amplifier is sufficiently large during a normal read operation and the coupling effect between the first dummy bit line DBL0 and the adjacent target bit line is insufficient to cause a read failure, the sensing margin can be reduced by reducing the SDT.

[0062] As an example, see Figures 8-10 In step S110 and step S120, the test data may be high logic data; in step S130, based on the first number of failures and the second number of failures, determining whether the first dummy bit line is set to the first voltage during the process of providing the first voltage to the first dummy bit line, and whether the first dummy bit line is set to the second voltage during the process of providing the second voltage to the first dummy bit line, further comprising:

[0063] Step S133, determining that the first dummy bit line is set to the first voltage during the process of supplying the first voltage to the first dummy bit line, and that the first dummy bit line is set to the second voltage during the process of supplying the second voltage to the first dummy bit line, when the first voltage is higher than the second voltage and the first failure number is smaller than the second failure number; or

[0064] Step S134, when the first voltage is higher than the second voltage and the first failure number is greater than or equal to the second failure number, or when the first voltage is lower than the second voltage and the first failure number is less than or equal to the second failure number, determines that the first pseudo bit line is not set to the first voltage during the process of providing the first voltage to the first pseudo bit line, and that the first pseudo bit line is not set to the second voltage during the process of providing the second voltage to the first pseudo bit line.

[0065] As an example, please refer to Figure 2 、 Figure 5 、 Figures 8-10 After high logic data, such as data "1," is written into the memory cell 300, if the first voltage is higher than the second voltage, the first dummy bit line is connected to the high voltage, thereby increasing the sensing margin of the sense amplifier (SA) and reducing the probability of a data read failure in the SA. If the first voltage is lower than the second voltage, the first dummy bit line is connected to the low voltage, thereby decreasing the sensing margin of the SA and increasing the probability of a data read failure in the SA. After writing data "1" to the memory cell 300, when the first voltage is higher than the second voltage and the first failure number is less than the second failure number, or when the first voltage is lower than the second voltage and the first failure number is greater than the second failure number, it is determined that in the process of providing the first voltage to the first pseudo bit line, the first pseudo bit line is set to the first voltage, and in the process of providing the second voltage to the first pseudo bit line, the first pseudo bit line is set to the second voltage; when the first voltage is higher than the second voltage and the first failure number is greater than or equal to the second failure number, or when the first voltage is lower than the second voltage and the first failure number is less than or equal to the second failure number, it is determined that in the process of providing the first voltage to the first pseudo bit line, the first pseudo bit line is not set to the first voltage, and in the process of providing the second voltage to the first pseudo bit line, the first pseudo bit line is not set to the second voltage.

[0066] As an example, see Figure 2 、 Figure 5 、 Figure 9-10 After writing test data to the memory chip under test, if data "1" is read from a memory cell, before reading the data, compared to a normal read operation, the SA is controlled to enter the sense amplification phase earlier (i.e., SDT is reduced, which in turn shortens the charge sharing time, i.e., the interval between WL on and SA on). This shortens the charge sharing time between the capacitor in the memory cell corresponding to the target bit line and the target bit line, making read data errors more likely to occur, thereby making it easier to obtain the first and second failure counts. In other words, if the sensing margin of the sense amplifier is sufficiently large during a normal read operation, and the coupling effect between the first dummy bit line DBL0 and the adjacent target bit line is insufficient to cause read failures, the sensing margin can be reduced by reducing the SDT.

[0067] It should be understood that although Figure 1 、 Figure 4 and Figure 8 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 、 Figure 4 and Figure 8 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0068] like Figure 11As shown, in some embodiments of the present disclosure, a memory chip test device 10 is provided, wherein the memory chip includes a plurality of memory cells arranged in an array, a plurality of word lines, a plurality of bit lines, and a first dummy bit line, each memory cell includes a transfer transistor and a capacitor coupled to a first end of the transfer transistor; each word line is coupled to a control end of a transfer transistor of a row of memory cells; each bit line is coupled to a second end of a transfer transistor of a column of memory cells; the first dummy bit line is located on one side of the plurality of bit lines; the memory chip test device 10 includes a first test module 11, a second test module 12, and a judgment module 13, wherein the first test module 11 is used to write test data to the memory cell corresponding to the target bit line, wherein , the target bit line is a bit line adjacent to the first pseudo bit line among the multiple bit lines, a first voltage is provided to the first pseudo bit line, and test data in the storage cell corresponding to the target bit line is read to determine a first failure number of the storage cell corresponding to the target bit line; the second test module 12 is used to write test data to the storage cell corresponding to the target bit line again, provide a second voltage to the first pseudo bit line, and read the test data in the storage cell corresponding to the target bit line to determine a second failure number of the storage cell corresponding to the target bit line, wherein the second voltage is different from the first voltage; the judgment module 13 is used to judge whether the first pseudo bit line can be set to the first voltage or the second voltage based on the first failure number and the second failure number.

[0069] As an example, please refer to Figure 11The accuracy of data read out by the memory chip is affected by the sensing margin of the sense amplifier itself, and the sensing margin of the sense amplifier itself is affected by the coupling effect of the adjacent bit lines it connects to. The spacing between adjacent bit lines in the memory chip reaches the nanometer level, resulting in the coupling effect between different bit lines having an increasingly obvious impact on the sensing margin of the sense amplifier. After the first test module 11 writes test data to the memory cells corresponding to the target bit line, where the target bit line is a bit line adjacent to the first dummy bit line among the plurality of bit lines, a first voltage is applied to the first dummy bit line, and the test data in the memory cells corresponding to the target bit line are read to determine a first number of failures in the memory cells corresponding to the target bit line. Then, the second test module 12 again writes test data to the memory cells corresponding to the target bit line, and then a second voltage is applied to the first dummy bit line, and the test data in the memory cells corresponding to the target bit line are read to determine a second number of failures in the memory cells corresponding to the target bit line, where the second voltage is different from the first voltage. Because the first dummy bit line has different coupling effects on its adjacent bit lines when the first dummy bit line is operating normally, the judgment module 13 utilizes the different amounts of influence of the different coupling effects on the sensing margin of the sense amplifier to judge, based on the first number of failures and the second number of failures, whether the first dummy bit line was set to the first voltage during the process of applying the first voltage to the first dummy bit line, and whether the first dummy bit line was set to the second voltage during the process of applying the second voltage to the first dummy bit line. Whether the dummy bit line can work normally and the effectiveness of the actual connection potential can be directly judged based on the first failure number and the second failure number, thereby improving the efficiency and accuracy of the memory chip test.

[0070] As an example, see Figure 12 The judgment module 13 includes a first comparison and analysis module 131 and a second comparison and analysis module 132. The first comparison and analysis module 131 is used to determine that when the first voltage is higher than the second voltage and the first failure number is greater than the second failure number, or when the first voltage is lower than the second voltage and the first failure number is less than the second failure number, the first pseudo bit line is set to the first voltage in the process of providing the first voltage to the first pseudo bit line, and the first pseudo bit line is set to the second voltage in the process of providing the second voltage to the first pseudo bit line; the second comparison and analysis module 132 is used to determine that when the first voltage is higher than the second voltage and the first failure number is less than the second failure number, or when the first voltage is lower than the second voltage and the first failure number is greater than the second failure number, the first comparison and analysis module 131 is used to determine that when the first voltage is higher than the second voltage and the first failure number is less than the second failure number, the first voltage is lower than the second voltage and the first failure number is greater than the second failure number, the first pseudo bit line is set to the first voltage in the process of providing the first voltage to the first pseudo bit line, and the first pseudo bit line is set to the second voltage in the process of providing the second voltage to the first pseudo bit line.

[0071] The present disclosure further provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the method described in any of the above embodiments are implemented. The electronic device may be, but is not limited to, various personal computers, laptops, smartphones, and tablet computers.

[0072] The present disclosure also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the method for testing a memory chip in any of the above embodiments are implemented.

[0073] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the steps of the memory chip testing method in any one of the above embodiments.

[0074] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. For purposes of illustration and not limitation, RAM may be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The processors involved in the various embodiments provided herein may be general-purpose processors, central processing units (CPUs), graphics processors (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), data processing logic devices based on quantum computing, and the like, without limitation thereto.

[0075] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that a person skilled in the art could make numerous variations and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application.

Claims

1. A method for testing a memory chip, characterized in that: The memory chip includes: A plurality of memory cells arranged in an array, wherein each memory cell includes a pass transistor and a capacitor coupled to a first terminal of the pass transistor; a plurality of word lines, wherein each word line is coupled to a control terminal of a pass transistor of a row of memory cells; a plurality of bit lines, wherein each bit line is coupled to the second terminal of the pass transistor of a column of memory cells; a first dummy bit line located on one side of the plurality of bit lines; The test method includes: Writing test data into a memory cell corresponding to a target bit line, wherein the target bit line is a bit line adjacent to the first dummy bit line among the plurality of bit lines; providing a first voltage to the first dummy bit line, and reading the test data in the memory cell corresponding to the target bit line to determine a first failure number of the memory cell corresponding to the target bit line; writing the test data into the memory cell corresponding to the target bit line again; providing a second voltage to the first dummy bit line and reading the test data in the memory cell corresponding to the target bit line to determine a second failure number of the memory cell corresponding to the target bit line, wherein the second voltage is different from the first voltage; Based on the first failure number and the second failure number, determine whether the first pseudo bit line is set to the first voltage during the process of providing the first voltage to the first pseudo bit line, and whether the first pseudo bit line is set to the second voltage during the process of providing the second voltage to the first pseudo bit line.

2. The testing method according to claim 1, wherein: The test data is low logic data; and judging, based on the first failure number and the second failure number, whether the first dummy bit line is set to the first voltage during a process of supplying the first voltage to the first dummy bit line, and whether the first dummy bit line is set to the second voltage during a process of supplying the second voltage to the first dummy bit line, comprises: determining that, when the first voltage is higher than the second voltage and the first number of failures is greater than the second number of failures, or when the first voltage is lower than the second voltage and the first number of failures is less than the second number of failures, the first dummy bit line is set to the first voltage during the supply of the first voltage to the first dummy bit line, and the first dummy bit line is set to the second voltage during the supply of the second voltage to the first dummy bit line; or In the case where the first voltage is higher than the second voltage and the first number of failures is less than or equal to the second number of failures, or in the case where the first voltage is lower than the second voltage and the first number of failures is greater than or equal to the second number of failures, it is determined that the first pseudo bit line is not set to the first voltage during the process of providing the first voltage to the first pseudo bit line, and that the first pseudo bit line is not set to the second voltage during the process of providing the second voltage to the first pseudo bit line.

3. The testing method according to claim 1, wherein: The test data is high logic data; and judging, based on the first failure number and the second failure number, whether the first dummy bit line is set to the first voltage during a process of supplying the first voltage to the first dummy bit line, and whether the first dummy bit line is set to the second voltage during a process of supplying the second voltage to the first dummy bit line, comprises: determining that, when the first voltage is higher than the second voltage and the first number of failures is smaller than the second number of failures, or when the first voltage is lower than the second voltage and the first number of failures is larger than the second number of failures, the first dummy bit line is set to the first voltage during the supply of the first voltage to the first dummy bit line, and the first dummy bit line is set to the second voltage during the supply of the second voltage to the first dummy bit line; or In the case where the first voltage is higher than the second voltage and the first number of failures is greater than or equal to the second number of failures, or in the case where the first voltage is lower than the second voltage and the first number of failures is less than or equal to the second number of failures, it is determined that the first pseudo bit line is not set to the first voltage during the process of providing the first voltage to the first pseudo bit line, and that the first pseudo bit line is not set to the second voltage during the process of providing the second voltage to the first pseudo bit line.

4. The testing method according to any one of claims 1 to 3, characterized in that: Of the first voltage and the second voltage, one is higher than a precharge voltage of the target bit line, and the other is lower than the precharge voltage.

5. The testing method according to any one of claims 1 to 3, characterized in that: The memory chip further includes: a sense amplifier coupled to the target bit line; During the process of reading the test data in the memory cell corresponding to the target bit line, compared with a normal read operation, the sense amplifier is controlled to enter the sense amplification phase in advance to shorten the charge sharing time between the capacitor in the memory cell corresponding to the target bit line and the target bit line.

6. A memory chip testing device, characterized in that: The memory chip includes: A plurality of memory cells arranged in an array, wherein each memory cell includes a pass transistor and a capacitor coupled to a first terminal of the pass transistor; a plurality of word lines, wherein each word line is coupled to a control terminal of a pass transistor of a row of memory cells; a plurality of bit lines, wherein each bit line is coupled to the second terminal of the pass transistor of a column of memory cells; a first dummy bit line located on one side of the plurality of bit lines; The testing device comprises: a first testing module, configured to write test data to a memory cell corresponding to a target bit line, wherein the target bit line is a bit line adjacent to the first dummy bit line among the plurality of bit lines, provide a first voltage to the first dummy bit line, and read the test data from the memory cell corresponding to the target bit line to determine a first failure number of the memory cell corresponding to the target bit line; a second testing module, configured to again write the test data into the memory cells corresponding to the target bit line, provide a second voltage to the first dummy bit line, and read the test data from the memory cells corresponding to the target bit line to determine a second number of failures of the memory cells corresponding to the target bit line, wherein the second voltage is different from the first voltage; A judgment module is used to judge whether the first pseudo bit line is set to the first voltage in the process of providing the first voltage to the first pseudo bit line, and whether the first pseudo bit line is set to the second voltage in the process of providing the second voltage to the first pseudo bit line based on the first failure number and the second failure number.

7. The testing device according to claim 6, characterized in that The judgment module includes: a first comparison and analysis module, configured to determine, when the first voltage is higher than the second voltage and the first failure number is greater than the second failure number, or when the first voltage is lower than the second voltage and the first failure number is less than the second failure number, that the first dummy bit line is set to the first voltage during the process of supplying the first voltage to the first dummy bit line, and that the first dummy bit line is set to the second voltage during the process of supplying the second voltage to the first dummy bit line; and / or A second comparison and analysis module is used to determine that, when the first voltage is higher than the second voltage and the first failure number is smaller than the second failure number, or when the first voltage is lower than the second voltage and the first failure number is larger than the second failure number, the first pseudo bit line is set to the first voltage in the process of providing the first voltage to the first pseudo bit line, and that the first pseudo bit line is set to the second voltage in the process of providing the second voltage to the first pseudo bit line.

8. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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