Power distribution control method, charging host, charging equipment and chip

Abstract

This invention relates to the field of charging system technology, specifically to a power distribution control method, a charging host, a charging device, and a chip. The power distribution control method includes: receiving a bus charging enable signal indicating the usage status of each power bus, a switch status signal indicating the closed state of each switch, and a switch control signal indicating the closure of at least one designated switch; determining whether the switch control signal conforms to a pre-configured target interlock logic based on the switch status signal and the bus charging enable signal, wherein the target interlock logic matches the topology of the power distribution matrix to prevent abnormal series connection between power buses in the power distribution matrix; if so, controlling the designated switch to close according to the switch control signal. This invention improves the reliability and safety of the entire system by performing interlock logic judgment on the switch control signal to avoid abnormal series connection between different power buses during actual use.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of charging system technology, and in particular to power distribution control methods, charging host and charging equipment. Background Technology

[0002] In electric vehicle charging systems, with the increasing power demands of electric vehicles and the continuous improvement in charging efficiency and power utilization, the power distribution section of the charging system has become particularly important. To achieve power superposition between power buses and improve charging efficiency, contactors are typically installed between the power buses in the power distribution section of the charging system. While this design can meet the power superposition requirement, it also introduces complexity to the circuit structure.

[0003] In actual power distribution, if the contactor is not properly closed when both power buses are in use, it may cause abnormal series connection between the two power buses. This will not only lead to a decrease in system efficiency, but may also cause serious safety accidents, such as overload, short circuit or even fire. Summary of the Invention

[0004] One objective of this invention is to provide a power distribution control method, a charging host, and a charging device to solve the technical problem of abnormal series connection between power buses in the power distribution section of a charging system.

[0005] In a first aspect, embodiments of the present invention provide a power distribution control method applied to a charging host, the charging host including a power distribution matrix, the power distribution matrix including a switch matrix and multiple power buses, the switch matrix including switches, and at least two of the power buses being interconnected through a corresponding switch, the method including:

[0006] The system receives a bus charging enable signal, a switch status signal, and a switch control signal. The bus charging enable signal indicates the operating status of each power bus, the switch status signal indicates the closed state of each switch, and the switch control signal indicates the closure of at least one designated switch, which is a switch in the switch matrix.

[0007] Based on the switch status signal and the bus charging enable signal, it is determined whether the switch control signal conforms to the pre-configured target interlock logic. The target interlock logic matches the topology of the power distribution matrix to prevent abnormal series connection between the power buses of the power distribution matrix.

[0008] If so, then the designated switch is closed according to the switch control signal;

[0009] If not, the operation of controlling the closing of the specified switch will not be performed.

[0010] Optionally, the power allocation matrix may have multiple topology types, and the target interlock logic is one of a pre-configured set of interlock logics. Each interlock logic matches a corresponding topology type of the power allocation matrix. Before determining whether the switch control signal conforms to the pre-configured target interlock logic based on the switch status signal and the bus charging enable signal, the following steps are included:

[0011] Receive a matrix type signal, the matrix type signal being used to represent the topology type of the power allocation matrix;

[0012] The target interlock logic is determined from the plurality of interlock logics based on the matrix type signal.

[0013] Optionally, the target interlock logic includes multiple sub-logic, and the step of determining whether the switch control signal conforms to the pre-configured target interlock logic based on the switch status signal and the bus charging enable signal includes:

[0014] Based on the switch status signal and the bus charging enable signal, determine whether the switch control signal conforms to each of the sub-logic of the target interlock logic;

[0015] If each of the sub-logics is satisfied, then the target interlock logic is satisfied.

[0016] If one of the sub-logic rules is not met, then the target interlocking logic is determined to be invalid.

[0017] Optionally, determining whether the switch control signal conforms to the pre-configured target interlock logic based on the switch status signal and the bus charging enable signal includes:

[0018] Receive device status signal, the device status signal being used to indicate the operating status of the charging host;

[0019] When the device status signal indicates that the operating status is normal, the operation of determining whether the switch control signal conforms to the target interlock logic is performed.

[0020] Optionally, after the step of determining whether the switch control signal conforms to the pre-configured target interlock logic based on the switch status signal and the bus charging enable signal, the method further includes:

[0021] When the switch control signal does not conform to the target interlock logic, feedback information is sent, which indicates that the switch control signal does not conform to the target interlock logic.

[0022] Optionally, the feedback information includes a target switch, which is the switch among the at least one designated switch whose closing operation does not conform to the target interlock logic. Before sending the feedback information, the system further includes:

[0023] When the switch control signal does not conform to the target interlock logic, the target switch is determined;

[0024] The feedback information is generated based on the target switch.

[0025] In a second aspect, embodiments of the present invention provide a chip including at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method as described above through logic circuits or executing code instructions.

[0026] In a third aspect, embodiments of the present invention provide a charging host, comprising:

[0027] A power distribution matrix, comprising a switch matrix and multiple power buses, wherein the switch matrix includes switches, and at least two of the power buses are interconnected via corresponding switches; and

[0028] A switch matrix controller is connected to a switch matrix, each switch of the switch matrix is ​​controlled by the switch matrix controller, the switch matrix controller includes a memory and a processor, the memory is connected to the processor, the processor is configured to execute one or more computer programs stored in the memory, and when the processor executes the one or more computer programs, causes the switch matrix controller to perform the method as described in any of the preceding claims.

[0029] In a fourth aspect, embodiments of the present invention provide a charging device, comprising:

[0030] Charging terminal; and

[0031] As described above, the charging host is electrically connected to the charging terminal.

[0032] In a fifth aspect, embodiments of the present invention provide a computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, the computer program including program instructions, which, when executed by a processor, cause the processor to perform the method as described in any of the preceding claims.

[0033] The embodiments of the present invention can achieve the following technical effects: By performing interlocking logic judgment on the switch control signal, the embodiments of the present invention can avoid abnormal series connection of different power buses during actual use, thereby improving the reliability and safety of the entire system. Attached Figure Description

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0035] Figure 1 This is a schematic diagram of the structure of a charging device provided in an embodiment of the present invention;

[0036] Figure 2 A schematic flowchart of a power distribution control method provided in an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of the topology of a power allocation matrix provided in an embodiment of the present invention;

[0038] Figure 4 A schematic diagram of another power allocation matrix topology provided in an embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram of the structure of a power distribution control device provided in an embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention;

[0041] Figure 7 This is a schematic diagram of the structure of a chip provided in an embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.

[0043] It should be noted that, unless otherwise specified, the various features in the embodiments of this invention can be combined with each other, all of which are within the protection scope of this invention. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this invention do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0044] This invention provides a charging device 100, which is applied in a charging system. The charging device 100 includes a charging terminal 20 and a charging host 10. The charging terminal 20 is electrically connected to the charging host 10 and receives charging power from the charging host 10.

[0045] The charging terminal 20 can be regarded as a charging pile and can be equipped with at least one charging gun for charging the target vehicle through the charging power provided by the charging host 10.

[0046] The charging host 10 is used to convert external power into charging power, and then distribute the charging power to the charging terminal 20. The charging power can be AC ​​or DC. The number of charging terminals 20 electrically connected to the charging host 10 is at least two. In other embodiments, the configuration can be made by the designer according to actual business needs, and there is no limitation here.

[0047] In some embodiments, the charging host 10 includes a device controller 12, a power distribution matrix 11, and a switch matrix controller 13. The power distribution matrix 11 includes a switch matrix and multiple power buses 111. The switch matrix includes switches 112, and at least two power buses 111 are interconnected via corresponding switches 112. The switch matrix is ​​connected to the switch matrix controller 13, and each switch 112 in the switch matrix is ​​controlled by the switch matrix controller 13. Exemplarily, in one embodiment, each switch 112 in the switch matrix is ​​a DC contactor. Two synchronized switch matrix controllers 13 are configured to control the same switch matrix. The two switch matrix controllers 13 are respectively connected to the same device controller 12. One switch matrix controller 13 controls the positive terminal of each DC contactor in the switch matrix, and the other switch matrix controller controls the negative terminal of each DC contactor in the switch matrix.

[0048] The device controller 12 is connected to the switch matrix controller 13 for communicating with the switch matrix controller 13 and sending control commands or control signals to the switch matrix controller 13 to instruct the switch matrix controller 13 to perform corresponding operations, such as instructing the switch matrix controller 13 to close a specified switch in the switch matrix to enable the power bus 111 to output power or to connect the power buses 111 to each other.

[0049] The switch matrix controller 13 is pre-configured with target interlock logic matching the topology of the power distribution matrix 11. The switch matrix controller 13 is used to prevent abnormal series connection between the power buses 111 of the power distribution matrix 11 through the target interlock logic. Abnormal series connection, as referred to in this embodiment of the invention, means that two or more circuit sections that should not be directly connected are accidentally electrically connected. For example, when two or more power buses 111 are accidentally closed through switch 112, they are connected in series in the same circuit, causing overload, short circuit, and other faults and safety accidents that affect the normal operation of the charging system.

[0050] In some embodiments, the switch matrix controller 13 includes a microcontroller unit 131 and a logic chip 132. The microcontroller unit 131 is connected to both the device controller 12 and the logic chip 132. The microcontroller unit 131 can communicate with the device controller 12 and perform corresponding operations according to the instructions or signals of the device controller 12, specifically including cooperating with the logic chip 132 to perform related steps. The logic chip 132 is pre-configured with the aforementioned target interlock logic to prevent abnormal series connection between the power buses 111 of the power distribution matrix 11.

[0051] For example, the device controller 12 instructs the switch matrix controller 13 to close a specified switch in the switch matrix. The microcontroller unit 131 generates a switch control signal and a bus charging enable signal based on the signal from the device controller 12. The switch control signal indicates the closure of at least one specified switch, and the bus charging enable signal indicates the operating status of each power bus 111. The logic chip 132 receives the switch control signal and the bus charging enable signal, and acquires a switch status signal, which indicates the closed state of each switch.

[0052] In one embodiment, the logic chip 132 is connected to each switch 112 of the switch matrix. The switch status signal can be a feedback signal returned to the logic chip 132 by each switch 112 during the closing or opening process. The logic chip 132 performs target interlock logic judgment on the switch control signal based on the bus charging enable signal and the switch status signal to determine whether the switch control signal conforms to the target interlock logic. When it is determined that the switch control signal conforms to the target interlock logic, the logic chip 132 will control the designated switch to close according to the judgment result; otherwise, when the switch control signal does not conform to the target interlock logic, the operation of controlling the designated switch to close will not be performed according to the judgment result.

[0053] Understandably, in this embodiment of the invention, the switch matrix controller 13 performs interlocking logic judgment on the switch control signal to avoid abnormal series connection of different power buses 111 during actual use, thereby improving the reliability and safety of the entire system.

[0054] In some embodiments, the microcontroller unit 131 of the switch matrix controller 13 may also adopt a specific controller, processor, etc., according to actual needs, and the logic chip 132 may adopt a specific device such as a field programmable gate array chip, etc., without limitation.

[0055] In some embodiments, the microcontroller unit of the switch matrix controller may also be a specific controller, processor, etc., depending on actual needs, and the logic chip may be a specific device such as a field-programmable gate array chip, etc., without limitation.

[0056] In some embodiments, the number of device controllers 12 is at least two, and they are connected to the switch matrix controller 13, terminal controller, and other device controllers 12 in the same charging host 10 via an Ethernet interface. Each device controller 12 is also equipped with a CAN (Controller Area Network) bus interface, which allows it to be cascaded with other device controllers 12 and to send commands or signals to the microcontroller unit via the CAN bus. The microcontroller unit 131 and the logic chip 132 are connected via an SPI (Serial Peripheral Interface) communication link, a digital communication link, etc. The logic chip 132 is configured with a digital output interface for controlling the switch matrix and a digital input interface for receiving switch status signals.

[0057] Please see Figure 2 In a second aspect, embodiments of the present invention provide a power distribution control method, applied to the charging host in any of the above embodiments, the method comprising:

[0058] S21, Receive bus charging enable signal, switch status signal and switch control signal.

[0059] In this step, the bus charging enable signal is used to indicate the usage status of each power bus, the switch status signal is used to indicate the closed status of each switch 112, and the switch control signal is used to indicate the closure of at least one designated switch, which is a switch in the switch matrix.

[0060] In some embodiments, the bus charging enable signal, switch status signal, and switch control signal are all digital signals. The logic chip is configured with multiple digital interfaces and receives these digital signals through the digital interfaces.

[0061] In some embodiments, the bus charging enable signal and the switch control signal are both sent to the logic chip by the microcontroller unit of the switch matrix controller, and the switch status signal is sent to the logic chip by the switch matrix during the closing or opening of the switch, and is acquired by the logic chip. In some embodiments, the charging host may be equipped with a corresponding acquisition module to acquire parameter information of the power bus and each switch 112, so as to generate the bus charging enable signal and the switch status signal and send them to the logic chip.

[0062] S22. Determine whether the switch control signal conforms to the pre-configured target interlock logic based on the switch status signal and the bus charging enable signal.

[0063] In this step, the target interlock logic matches the topology of the power allocation matrix to prevent abnormal series connection between the power buses of the power allocation matrix.

[0064] S23. If so, then control the designated switch to close according to the switch control signal.

[0065] S24. If not, the operation of controlling the closing of the specified switch will not be performed.

[0066] It is understood that the power distribution control method of this invention performs interlocking logic judgment on the switch control signal to avoid abnormal series connection of different power buses during actual use, thereby improving the reliability and safety of the entire system.

[0067] Please see Figure 3 In some embodiments, the power distribution matrix includes four power buses (BUS#1, BUS#2, BUS#3, BUS#4) and a switch matrix (K1_2, K1_3, K1_4, K2_3, K2_4, K3_4). It should be noted that switch "K1_2" refers to the switch connecting power buses BUS#1 and BUS#2 respectively. The topology of the power distribution matrix is ​​shown in the figure.

[0068] To ensure that the power buses in each charging circuit do not connect in series, the basic rule or condition for the target interlock logic is that the switch closure condition between the two power buses must be such that at least one power bus is in an idle state, meaning at least one power bus is not in use. Taking simultaneous charging of power buses BUS#1 and BUS#2 as an example, the target interlock logic matching the topology of this power allocation matrix based on this basic rule or condition is as follows:

[0069] K1_2 must not be closed to avoid BUS#1 and BUS#2 being directly connected in series.

[0070] K1_4 and K2_4 are not allowed to be closed at the same time to avoid BUS#1 and BUS#2 being connected in series via BUS#4;

[0071] K1_3 and K2_3 are not allowed to be closed at the same time to avoid BUS#1 and BUS#2 being connected in series via BUS#3;

[0072] K1_4, K3_4, and K2_3 are not allowed to be closed simultaneously to prevent BUS#1 and BUS#2 from being connected in series via the links of BUS#4 and BUS#3.

[0073] Please see Figure 4 In other embodiments, the power distribution matrix includes eight power buses (BUS#1, BUS#2, BUS#3, BUS#4, BUS#5, BUS#6, BUS#7, BUS#8) and a switch matrix (K1_2, K1_4, K1_5, K2_3, K2_6, K3_4, K3_7, K4_8, K5_6, K5_8, K6_7, K7_8). It should be noted that switch "K1_2" refers to the switch connecting power buses BUS#1 and BUS#2 respectively. The topology of the power distribution matrix is ​​shown in the figure.

[0074] To ensure that the power buses in each charging circuit do not connect in series, the basic rule or condition for the target interlock logic is that the switch closure condition between the two power buses must be such that at least one power bus is in an idle state, meaning at least one power bus is not in use. Taking simultaneous charging of power buses BUS#1 and BUS#2 as an example, the target interlock logic matching the topology of this power allocation matrix based on this basic rule or condition is as follows:

[0075] K1_2 must not be closed to avoid BUS#1 and BUS#2 being directly connected in series.

[0076] K1_4, K3_4, and K2_3 are not allowed to be closed simultaneously to prevent BUS#1 and BUS#2 from being connected in series via the links of BUS#4 and BUS#3;

[0077] K1_4, K3_4, K3_7, K6_7, and K2_6 are not allowed to close simultaneously to prevent BUS#1 and BUS#2 from passing through BUS#4 and BUS#3. 、 Connect the links of BUS#7 and BUS#6 in series;

[0078] K1_4, K3_4, K3_7, K7_8, K8_5, K5_6, and K2_6 are not allowed to be closed simultaneously to prevent BUS#1 and BUS#2 from being connected in series via the links BUS#4, BUS#3, BUS#7, BUS#8, BUS#5, and BUS#6.

[0079] K1_4, K4_8, K5_8, K5_6, and K2_6 are not allowed to be closed simultaneously to prevent BUS#1 and BUS#2 from being connected in series via the links of BUS#4, BUS#8, BUS#5, and BUS#6.

[0080] K1_4, K4_8, K5_8, K5_6, K6_7, K3_7, and K2_3 are not allowed to be closed simultaneously to prevent BUS#1 and BUS#2 from being connected in series via the links BUS#4, BUS#8, BUS#5, BUS#6, BUS#7, and BUS#3.

[0081] K1_4, K4_8, K7_8, K3_7, and K2_3 are not allowed to be closed simultaneously to prevent BUS#1 and BUS#2 from being connected in series via the links of BUS#4, BUS#8, BUS#7, and BUS#3.

[0082] K1_4, K4_8, K7_8, K6_7, and K2_6 are not allowed to be closed simultaneously to prevent BUS#1 and BUS#2 from being connected in series via the links of BUS#4, BUS#8, BUS#7, and BUS#6.

[0083] In some embodiments, the power allocation matrix has multiple topology types, such as the two power allocation matrix topologies provided above. The target interlock logic is one of multiple interlock logics, and each interlock logic matches a corresponding power allocation matrix topology type. Before step S22, the method further includes:

[0084] S11, Receive matrix type signals.

[0085] In this step, the matrix type signal is used to represent the topology type of the power allocation matrix.

[0086] In some embodiments, during initialization, the microcontroller loads the configuration information of the power allocation matrix. This configuration information may be stored in the memory of the switch matrix controller at the beginning of the design. The microcontroller identifies the topology type of the power allocation matrix based on the configuration information, generates the corresponding matrix type signal, and sends it to the logic chip.

[0087] S12. Determine the target interlock logic from multiple interlock logics based on the matrix type signal.

[0088] It is understood that the power distribution control method of the present invention pre-configures multiple interlocking logics, and each interlocking logic matches a corresponding power distribution matrix topology type, thereby enabling the use of the same switch matrix controller or logic chip in different charging hosts.

[0089] In some embodiments, the target interlock logic includes multiple sub-logic, and step S22 includes:

[0090] S221. Determine whether the switch control signal conforms to each sub-logic of the target interlock logic based on the switch status signal and the bus charging enable signal.

[0091] S222. If each sub-logic is satisfied, then the target interlocking logic is satisfied.

[0092] S223. If one of the sub-logic rules is not met, then it is determined that the target interlocking logic is not met.

[0093] Understandably, taking the power distribution matrix using four power buses as an example, when BUS#1 and BUS#2 are charging simultaneously, the switching closure condition between the two power buses requires at least one power bus to be in an idle state as a basic rule or a list of multiple sub-logic conditions to accommodate different switching closure situations. Only when the switch control signal conforms to all sub-logic conditions can it be determined that the switch control signal conforms to the target interlocking logic; conversely, if the switch control signal does not conform to even one of the sub-logic conditions, it is determined that the switch control signal does not conform to the target interlocking logic.

[0094] In some embodiments, step S22 includes:

[0095] S224, Receive device status signal.

[0096] In this step, the device status signal is used to indicate the operating status of the charging host, including the operating status of at least one of the device controller, switch matrix controller, etc. In some embodiments, the charging system is configured with a monitoring module that monitors the operating status of the switch matrix controller and sends the device status signal of the switch matrix controller to the logic chip based on the monitoring results. In other embodiments, the charging system is configured with another monitoring module that monitors the operating status of the device controller and sends the device status signal of the charging host to the logic chip based on the monitoring results. In other embodiments, the device controller or switch matrix controller may integrate a module with status monitoring functions, capable of generating status signals based on preset thresholds and conditions.

[0097] S225. When the equipment status signal indicates that the operating status is normal, perform the operation of judging whether the switch control signal conforms to the target interlock logic.

[0098] It is understood that, by determining the operating status of at least one of the charging host and the switch matrix controller, this embodiment of the invention avoids performing the judgment operation on whether the switch control signal conforms to the target interlock logic even when the equipment is in an abnormal state, and further avoids controlling the switch matrix to close the specified switch, thereby improving the reliability and safety of the charging system.

[0099] In some embodiments, after step S22, the method further includes:

[0100] S226. When the switch control signal does not conform to the target interlock logic, generate feedback information.

[0101] In this step, the feedback information is used to indicate that the switch control signal does not conform to the target interlock logic. In some embodiments, the feedback information is sent from the switch matrix controller to the device controller, specifically by a microcontroller unit or a logic chip.

[0102] Understandably, when the switch control signal does not conform to the target interlock logic, the switch controller generates feedback information, which can be sent to the device controller so that the device controller can re-instruct the closed switch.

[0103] In some embodiments, the feedback information includes a target switch, which is at least one of the specified switches whose closing operation does not conform to the target interlock logic. Prior to step S226, the method further includes:

[0104] S2261. When the switch control signal does not conform to the target interlock logic, determine the target switch.

[0105] In this step, the logic chip sends the judgment result of whether the switch control signal conforms to the target interlock logic to the microcontroller unit. The judgment result includes the specified switch whose closing operation does not conform to the target interlock logic.

[0106] S2262. Generate feedback information based on the target switch.

[0107] It is understood that, in this embodiment of the invention, the specified switches whose closing operation does not conform to the target interlock logic are fed back to the device controller, so that the device controller can re-instruct the closing of the specified switches according to the specified switches recorded in the feedback information.

[0108] In some embodiments, step S23 includes:

[0109] S231. Generate a switching signal based on the switch control signal.

[0110] In this step, the switching signal is a digital signal, and the switch matrix can drive the corresponding switch to close or open according to the digital signal. In one embodiment, the output interface of the logic chip is configured as a digital output interface, and the logic chip generates a switching signal according to the switch control signal when the switch control signal satisfies the target interlock logic.

[0111] In some embodiments, the number of power allocation matrices is multiple, the number of switch matrix controllers is multiple, and each power allocation matrix is ​​configured with at least one corresponding switch matrix controller. The method further includes the following steps before step S22:

[0112] S25, Receive operation control signals.

[0113] In this step, the operation control signal is used to drive the logic chip of the matching switch matrix controller to perform operation or stop operation.

[0114] In some embodiments, the charging host includes multiple device controllers cascaded together, with each device controller connected to the logic chip of a corresponding switch matrix controller. One of the multiple device controllers is configured as a master device controller and connected to the logic chips of the remaining switch matrix controllers. The master device controller sends operation control signals to the logic chips of each switch matrix controller to drive the logic chip matching the operation control signal to perform the corresponding operation.

[0115] S26. Determine whether the operation control signal matches;

[0116] In some embodiments, the operation control signal is a digitally encoded signal. For example, each logic chip of the switch matrix controller is matched with two corresponding digitally encoded signals, and the specific value of one bit in the digitally encoded signal controls whether the switch matrix controller operates. For instance, if the received operation control signal is "0011", one of the logic chips matches this operation control signal and operates according to the first bit value "1" of the operation control signal, enabling functions such as target interlock logic judgment and switch signal generation. When the received operation control signal is "0010", the logic chip stops operating according to the first bit value "0", and the logic chip does not control the corresponding switch matrix. In other embodiments, the actual configuration of the operation control signal in the charging system can be adjusted according to actual needs, and is not limited here.

[0117] S27. When determining the matching operation control signal, perform the corresponding operation according to the operation control signal.

[0118] Understandably, the main device controller sends operation control signals to each logic chip and cascades with other device controllers to coordinate the control of the switching matrices of the power distribution matrices corresponding to each logic chip. In the event of a malfunction in the charging host, the main device controller can use operation control signals to individually control the opening or closing of each switching matrix, thereby protecting the charging system.

[0119] It should be noted that in the above embodiments, there is no necessarily a certain order between the steps. Those skilled in the art can understand from the description of the embodiments of the present invention that the above steps may have different execution orders in different embodiments, that is, they may be executed in parallel or in turn, etc.

[0120] As a third aspect of the present invention, an embodiment of the present invention provides a power distribution control device. The power distribution control device can be a software module, which includes several instructions stored in a memory. A processor can access the memory, invoke the instructions, and execute them to complete the power distribution control method described in the above embodiments.

[0121] In some embodiments, the power distribution control device can also be constructed from hardware components. For example, the power distribution control device can be constructed from one or more chips, which can work in coordination to complete the power distribution control method described in the various embodiments above. As another example, the power distribution control device can also be constructed from various logic devices, such as general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), microcontrollers, ARM (Acorn RISC Machine) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components.

[0122] Please see Figure 5 The power distribution control device 500 includes a first receiving module 501, a first judging module 502, and a first execution module 503.

[0123] The first receiving module 501 is used to acquire a bus charging enable signal, a switch status signal, and a switch control signal. The bus charging enable signal indicates the operating status of each power bus, the switch status signal indicates the closed state of each switch, and the switch control signal indicates the closure of at least one designated switch, which is a switch in the switch matrix. The first judging module 502 is used to judge whether the switch control signal conforms to the target interlock logic based on the switch status signal and the bus charging enable signal. The target interlock logic matches the topology of the power distribution matrix to prevent abnormal series connection between power buses in the power distribution matrix. The first executing module 503 is used to control the designated switch to close according to the switch control signal when the switch control signal conforms to the target interlock logic, and not to execute the operation of controlling the designated switch to close when the switch control signal conforms to the target interlock logic.

[0124] Understandably, the power distribution matrix in this embodiment of the invention uses interlocking logic to judge the switch control signals in order to avoid abnormal series connection of different power buses during actual use, thereby improving the reliability and safety of the entire system.

[0125] In some embodiments, the power distribution control device 500 further includes a second receiving module and a second execution module. The second receiving module is used to receive a matrix type signal, which indicates the topology type of the power distribution matrix. The second execution module is used to determine a target interlock logic from multiple interlock logics based on the matrix type signal.

[0126] In some embodiments, the first judgment module 502 is specifically used to determine whether the switch control signal conforms to each sub-logic of the target interlock logic based on the switch status signal and the bus charging enable signal; if it conforms to each sub-logic, it is determined that it conforms to the target interlock logic; if it does not conform to one of the sub-logic, it is determined that it does not conform to the target interlock logic.

[0127] In some embodiments, the first judgment module 502 is specifically used to receive a device status signal, which indicates the operating status of the charging host; when the device status signal indicates that the operating status is normal, it performs an operation to determine whether the switch control signal conforms to the target interlock logic.

[0128] In some embodiments, the power distribution control device 500 further includes an identification module and a generation module. The identification module is used to determine the target switch when the switch control signal does not conform to the target interlock logic. The generation module is used to generate feedback information based on the target switch.

[0129] In some embodiments, the first execution module 503 is specifically used to generate feedback information based on the target switch.

[0130] In some embodiments, the power distribution control device 500 further includes a third receiving module, a second determining module, and a third executing module. The third receiving module receives an operation control signal, which drives a matched switch matrix controller to perform an operation or a stop operation. The second determining module determines whether the operation control signal matches. The third executing module, upon determining that the operation control signal matches, executes the corresponding operation based on the operation control signal.

[0131] It should be noted that the power distribution control device 500 described above can execute the power distribution control method provided in the embodiments of the present invention, and has the corresponding functional modules and beneficial effects of the method. Technical details not described in detail in the embodiments of the power distribution control device 500 can be found in the power distribution control method provided in the embodiments of the present invention.

[0132] See Figure 6 In the fourth aspect, Figure 6 This is a schematic diagram of the structure of a computer device 600 provided in an embodiment of the present invention. The computer device is a switch matrix controller for a charging host. The computer device includes one or more processors 601 and a memory 602. The memory 602 is connected to one or more processors 601, for example, via a bus.

[0133] Processor 601 is configured to support the computer device in performing the corresponding functions in the methods described in the above method embodiments. Processor 601 may be a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof. The aforementioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0134] Memory 602 is used to store program code, etc. Memory 602 may include volatile memory (VM), such as random access memory (RAM); memory may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); memory 602 may also include combinations of the above types of memory.

[0135] The memory 602 can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the power distribution control method in the embodiments of the present invention. The processor 601 executes various functional applications and data processing of the power distribution control method and power distribution control device by running the non-volatile software programs, instructions, and modules stored in the memory 602, that is, it realizes the functions of each module or unit of the power distribution control method and power distribution control device provided in the above method embodiments.

[0136] The memory 602 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function. The data storage area may store data created based on the use of the power distribution control device, etc. In some embodiments, the memory may optionally include memory remotely located relative to the processor, which can be connected to the power distribution control device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0137] One or more modules are stored in memory 602. When executed by one or more processors 601, they perform the power distribution control method in any of the above method embodiments. For example, they perform the method steps described in the above method embodiments to realize the functions of the modules described in the above device embodiments.

[0138] This invention also provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a computer, cause the computer to perform the method as described in the foregoing embodiments.

[0139] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0140] Please see Figure 7 In a fifth aspect, embodiments of the present invention also provide a chip 700 applied to a switch matrix controller of a charging host. The chip includes at least one processor 701 and a communication interface 702; the communication interface 702 is used to receive signals input to the chip 700 or signals output from the chip 700, and the processor 701 communicates with the communication interface 702 and implements the power distribution control method as described above through logic circuits or executed code instructions.

[0141] The aforementioned hardware chip can be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0142] In some embodiments, the chip uses the logic chip described above, specifically a field-programmable gate array (FPGA) chip.

[0143] The above description discloses only preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A power distribution control method, characterized in that, An application is made in a charging host, the charging host including a power distribution matrix, the power distribution matrix including a switch matrix and multiple power buses, the switch matrix including switches, and at least two of the power buses being interconnected through a corresponding switch, the method including: The system receives a bus charging enable signal, a switch status signal, and a switch control signal. The bus charging enable signal indicates the operating status of each power bus, the switch status signal indicates the closed state of each switch, and the switch control signal indicates the closure of at least one designated switch, which is a switch in the switch matrix. Based on the switch status signal and the bus charging enable signal, it is determined whether the switch control signal conforms to the pre-configured target interlock logic. The target interlock logic matches the topology of the power distribution matrix to prevent abnormal series connection between the power buses of the power distribution matrix. There are multiple types of topology of the power distribution matrix. The target interlock logic is one of the multiple pre-configured interlock logics. Each interlock logic matches a corresponding type of topology of the power distribution matrix. If so, then the designated switch is closed according to the switch control signal; If not, the operation of controlling the closing of the specified switch will not be performed.

2. The power distribution control method according to claim 1, characterized in that, Before determining whether the switch control signal conforms to the pre-configured target interlock logic based on the switch status signal and the bus charging enable signal, the process includes: Receive a matrix type signal, the matrix type signal being used to represent the topology type of the power allocation matrix; The target interlock logic is determined from the plurality of interlock logics based on the matrix type signal.

3. The power distribution control method according to claim 1, characterized in that, The target interlock logic includes multiple sub-logic, and the step of determining whether the switch control signal conforms to the pre-configured target interlock logic based on the switch status signal and the bus charging enable signal includes: Based on the switch status signal and the bus charging enable signal, determine whether the switch control signal conforms to each of the sub-logic of the target interlock logic; If each of the sub-logics is satisfied, then the target interlock logic is satisfied. If one of the sub-logic rules is not met, then the target interlocking logic is determined to be invalid.

4. The power distribution control method according to claim 1, characterized in that, The step of determining whether the switch control signal conforms to the pre-configured target interlock logic based on the switch status signal and the bus charging enable signal includes: Receive device status signal, the device status signal being used to indicate the operating status of the charging host; When the device status signal indicates that the operating status is normal, the operation of determining whether the switch control signal conforms to the target interlock logic is performed.

5. The power distribution control method according to claim 1, characterized in that, After the step of determining whether the switch control signal conforms to the pre-configured target interlock logic based on the switch status signal and the bus charging enable signal, the method further includes: When the switch control signal does not conform to the target interlock logic, feedback information is sent, which indicates that the switch control signal does not conform to the target interlock logic.

6. The power distribution control method according to claim 5, characterized in that, The feedback information includes a target switch, which is the switch among the at least one designated switch whose closing operation does not conform to the target interlock logic. Before sending the feedback information, the system further includes: When the switch control signal does not conform to the target interlock logic, the target switch is determined; The feedback information is generated based on the target switch.

7. A chip, characterized in that, It includes at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method as described in any one of claims 1 to 6 through logic circuits or executing code instructions.

8. A charging host, characterized in that, include: A power distribution matrix, the power distribution matrix including a switch matrix and multiple power buses, the switch matrix including switches, and at least two of the power buses being interconnected through a corresponding switch; as well as A switch matrix controller is connected to a switch matrix, each switch of the switch matrix is ​​controlled by the switch matrix controller, the switch matrix controller includes a memory and a processor, the memory is connected to the processor, the processor is configured to execute one or more computer programs stored in the memory, and when the processor executes the one or more computer programs, causes the switch matrix controller to perform the method as described in any one of claims 1-6.

9. A charging device, characterized in that, include: Charging terminal; as well as The charging host as described in claim 8 is electrically connected to the charging terminal.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the method as described in any one of claims 1-6.

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