An electromagnetic signal acquisition and analysis system based on real-time multi-channel high-speed acquisition.

Abstract

An electromagnetic signal acquisition and analysis system based on real-time multi-channel high-speed acquisition is disclosed for the acquisition and analysis of electromagnetic signals in complex electronic warfare environments. The system includes a core control module, a clock module, a multi-channel interleaved acquisition module, and a signal analysis module. The signal output terminal of the clock module is connected to the clock input terminals of the core control module, the multi-channel interleaved acquisition module, and the signal analysis module, respectively. The signal output terminal of the core control module is connected to the signal input terminals of the clock module, the multi-channel interleaved acquisition module, and the signal analysis module, respectively. The signal output terminal of the multi-channel interleaved acquisition module is connected to the signal input terminal of the signal analysis module. The signal output terminal of the signal analysis module is connected to the input terminal of the core control module. This application utilizes a multi-channel interleaved sampling method for real-time high-speed acquisition of electromagnetic signals, effectively improving the system's sampling rate and the effective number of bits in the sampled data, while ensuring the system's stability requirements are met.

Description

Technical Field

[0001] This application relates to the field of signal acquisition technology, specifically to an electromagnetic signal acquisition and analysis system based on real-time multi-channel high-speed acquisition. Background Technology

[0002] With the further development of electromagnetic science and technology and electronic information detection technology, real-time electromagnetic signal acquisition and analysis systems are needed for various applications, including satellite signal transmission in space, in-depth detection of electronic countermeasures information under multiple operating modes, and large-scale data acquisition by high-resolution remote sensing radar. As the overall performance of real-time acquisition systems continues to improve, overcoming the bottlenecks in real-time performance, accuracy, and storability of electromagnetic signal acquisition and analysis systems has become a crucial research topic.

[0003] Current research shows that the sampling rate of standalone analog-to-digital converter (ADC) chips has not yet reached a high level, and the effective bit depth needs to be improved. Furthermore, large-scale data sampling and analysis poses significant challenges to system stability, and the issue of data storage after processing remains unresolved. While some existing high-sampling-rate ADC chips can initially meet the practical needs of systems, this incurs substantial economic costs. Moreover, improving the performance of a single high-speed ADC in actual development is difficult, as it is hard to overcome the trade-off between sampling rate and sampling accuracy, thus hindering further significant improvements in system sampling performance. Existing multi-channel sampling solutions, due to issues such as channel mismatch and high cost, cannot currently break through the 20Gb / s sampling rate while meeting a certain number of effective bits.

[0004] In summary, real-time electromagnetic signal acquisition and analysis systems urgently need further improvement in terms of sampling rate, sampling accuracy, system stability, and the data capacity implied by high-speed sampling. Summary of the Invention

[0005] To further improve the sampling rate of current electromagnetic signal sampling systems while ensuring the effective number of bits in the sampling, embodiments of this application propose an electromagnetic signal acquisition and analysis system based on real-time multi-channel high-speed acquisition. This system utilizes a multi-channel interleaved sampling method for real-time high-speed acquisition of electromagnetic signals. Under the condition of simultaneous synchronization of multiple channels, the high-speed multi-channel parallel real-time signal acquisition fully leverages the performance advantages of the processor unit, effectively improving the system's sampling rate and the effective number of bits in the sampled data, while ensuring system stability. After sampling, the obtained data is fused and stored according to the temporal relationship of the sampling process, further alleviating the pressure on the system's storage module and better meeting the performance requirements of electronic systems in real-time sampling and data processing.

[0006] To achieve the above objectives, the technical solution adopted in this application is as follows:

[0007] An electromagnetic signal acquisition and analysis system based on real-time multi-channel high-speed acquisition is used for the acquisition and analysis of electromagnetic signals in complex electronic warfare environments. The system includes a core control module, a clock module, a multi-channel interleaved acquisition module, and a signal analysis module. The signal output terminal of the clock module is connected to the signal input terminals of the core control module, the multi-channel interleaved acquisition module, and the signal analysis module. The signal output terminal of the core control module is connected to the signal input terminals of the clock module, the multi-channel interleaved acquisition module, and the signal analysis module. The signal output terminal of the multi-channel interleaved acquisition module is connected to the signal input terminal of the signal analysis module. The signal output terminal of the signal analysis module is connected to the signal input terminal of the core control module.

[0008] The core control module is used to control the operating logic of the electromagnetic signal acquisition and analysis system. It schedules and allocates the clock resources of the clock module, the analog-to-digital converter (ADC) chip of the multi-channel interleaved acquisition module and the storage medium, configures the parameters of the multi-channel interleaved acquisition module and the signal analysis module, and interacts with the outside world during the sampling process.

[0009] The clock module provides the clock resources required for sampling by the electromagnetic signal acquisition and analysis system, and is responsible for controlling the startup of the multi-channel interleaved acquisition module and the synchronous operation of the analog-to-digital converter (ADC) chip.

[0010] The multi-channel interleaving acquisition module is used to acquire and store wideband real-time high-speed signals through the signal acquisition board in the storage medium. At the same time, it redistributes the initial signals acquired and stored in real time, and performs fusion processing on the redistributed signals according to the timing relationship between the single analog-to-digital converter chip (ADC) and the multi-channel interleaving acquisition module.

[0011] The signal analysis module is used to perform parameter-configurable filtering on the signal data output by the multi-channel interleaved acquisition module, and to perform beamforming and frequency domain analysis on the filtered signal data.

[0012] The core control module is the CPU processor.

[0013] The multi-channel interleaved acquisition module includes multiple FPGA signal acquisition boards and multiple FPGA data storage boards. The FPGA signal acquisition boards and FPGA data storage boards correspond one-to-one. Each FPGA data storage board has a PCIe interface to support information exchange with the outside world. Each FPGA signal acquisition board is connected to no less than two analog-to-digital converter (ADC) chips.

[0014] The multi-channel interleaved acquisition module obtains configuration parameters from the core control module, receives task scheduling control signals sent by the core control module, and feeds back sampling status information to the core control module. The specific configuration parameters obtained by the multi-channel interleaved acquisition module from the core control module include the acquisition path number.

[0015] Sampling bandwidth, sampling rate, and sampling mode.

[0016] The clock module consists of multiple FPGA clock timing processing boards, including three types of clock resources: reference clock resources, system sampling clock resources, and trigger clocks for sampling of each channel.

[0017] The reference clock resource is used to provide the clk signal for the normal operation of the core control module, the multi-channel interleaved acquisition module, and the signal analysis module.

[0018] The system sampling clock resource is used to provide the fclk signal required by the analog-to-digital converter (ADC) chip in the multi-channel interleaved acquisition module as a high-speed sampling clock;

[0019] The trigger clock for sampling each channel is used as the control clock signal to enable the multi-channel analog-to-digital converter (ADC).

[0020] The multi-channel analog-to-digital converter (ADC) chip utilizes time interleaving to perform high-speed acquisition of external signals in a selected mode while ensuring correct timing. The selected mode is chosen by the core control module and includes continuous acquisition mode, pulse acquisition mode, and threshold acquisition mode.

[0021] The signal analysis module includes a filtering module, a beamforming module, and a frequency domain analysis module. The filtering module receives filtering coefficients from the core control module, configures the parameters, and then performs filtering. The beamforming module receives beamforming parameters from the core control module, configures the parameters, and then performs beamforming. The frequency domain analysis module performs Fourier transform and spectral analysis on the beamformed signal to solve for the parameters.

[0022] The filtering coefficients include the filter order, filter type, and filter length; the beamforming parameters include the beamforming mode, beamforming signal region, beamforming direction, and center frequency.

[0023] An electromagnetic signal acquisition and analysis method based on real-time multi-channel high-speed acquisition, used for electromagnetic signal acquisition and analysis in complex electronic warfare environments, includes the following steps:

[0024] S1. Check the connection status of each board in the electromagnetic signal acquisition and analysis system. After confirming that everything is correct, prepare to power on.

[0025] S2, the clock module starts, each module begins initialization, the core control module issues a synchronization command to synchronize the pulse signals in the gate of the multi-channel interleaved acquisition module until completion, and then feeds back a synchronization completion signal to the core control module.

[0026] S3, the core control module presets the configuration parameters of the multi-channel interleaved acquisition module and the parameters of the signal analysis module. After receiving the feedback information of the configuration completion, it sends the storage start signal and the acquisition start signal. The clock module supplies the high-speed sampling clock and the sampling trigger pulse to start sampling. At the same time, each FPGA signal acquisition board feeds back the status information of the sampling process to the core control module, and the core control module performs detection.

[0027] S4. If there is an abnormality in the sampling process, the core control module sends a storage enable signal and a data acquisition start signal to terminate the process; otherwise, it maintains the monitoring state until the end.

[0028] S5, the signal analysis module performs digital signal processing on the acquired signal, including digital filtering, beamforming and frequency domain analysis, and feeds the processing results back to the core control module;

[0029] S6. After the signal acquisition is completed, the core control module sends a sampling termination signal, the FPGA data storage board closes the storage mode, and the sampling board stops the sampling process.

[0030] The specific configuration parameters for the multi-channel interleaved acquisition module are: acquisition path number, sampling bandwidth, sampling rate, and sampling mode parameters. The specific configuration parameters for the signal analysis module are: filter coefficients and beamforming parameters.

[0031] Compared with the prior art, the beneficial effects of this application are:

[0032] This application improves the sampling rate, sampling accuracy, and system stability of the real-time electromagnetic signal acquisition system by using a multi-channel interleaved acquisition method, while reducing economic costs, in addition to achieving basic functions such as electromagnetic signal acquisition and signal storage.

[0033] This application addresses the application needs in different scenarios by pre-setting different sampling modes for the multi-channel acquisition module, making it easier for the system to better adapt to future scenario requirements.

[0034] This application, based on practical application needs, develops signal analysis functions for the collected signals. By performing some configurable digital signal processing on the sampled electromagnetic signal data, it is easy to quickly obtain some basic parameters of the collected signals, which greatly assists in further data analysis. Attached Figure Description

[0035] Figure 1The figure shows a schematic diagram of the system architecture used in this application.

[0036] Figure 2 This is a schematic diagram of the clock module structure used in this application.

[0037] Figure 3 This is a schematic diagram of the method flow during the operation of this application. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0039] According to the appendix provided in this application Figure 1 This application provides further elaboration and explanation of its technical solutions, using specific examples. However, this description only illustrates some examples of specific implementations of this application and does not fully represent all implementation cases. Any improvements or enhancements made by ordinary workers in the industry based on this application, without departing from its design principles, should fall within the scope of patent protection.

[0040] An electromagnetic signal acquisition and analysis system based on real-time multi-channel high-speed acquisition consists of four parts, specifically including: a core control module, a clock module, a multi-channel interleaved acquisition module, and a signal analysis module.

[0041] The core control module is connected to the clock module, multi-channel interleaved acquisition module, and signal analysis module, as well as an external computer (PC). Its function is to provide core control for the entire electromagnetic signal acquisition and analysis system. Through the CPU processing unit, it schedules various computing resources to complete the system's acquisition and storage tasks, receives control commands from the external PC, obtains configuration parameters for each module, and, during system operation, feeds back the status information of each module to the external PC, completing the information exchange process.

[0042] The clock module is connected to the core control module, the multi-channel interleaved acquisition module, and the signal analysis module. First, this module provides a reference clock (clk) to the core control module, signal analysis module, and multi-channel interleaved acquisition module, ensuring the normal operation of each module. Second, this module provides a high-frequency sampling clock (fclk) to ensure the base sampling rate of each ADC in the multi-channel interleaved acquisition module. Finally, this module provides sampling trigger signals for each channel to ensure synchronization during the sampling process. By training and learning from the time errors between sampling channels, it obtains empirical time parameters, thereby overcoming hardware differences between channels under fixed hardware and time errors in the sampling trigger gates, effectively ensuring sampling synchronization and guaranteeing a high sampling rate for the entire system.

[0043] The multi-channel interleaved acquisition module is connected to the core control module, clock module, and signal analysis module, and includes a multi-channel ADC sampling board and a high-speed storage unit. In its connection with the core control module, the multi-channel interleaved acquisition module obtains configuration parameters from the main control module, specifically sampling mode parameters and sampling resource parameters, and receives task scheduling control signals from the main control module and feeds back sampling status information. In its connection with the clock module, this module receives a reference clock, a high-speed sampling clock, and a sampling trigger signal provided by the clock module, such as... Figure 2 As shown, the high-speed sampling clock ensures the basic sampling rate of each individual ADC in the sampling system. The sampling trigger signal is used to turn the sampling process on and off. This signal is a gate signal and requires empirical time parameters measured during pre-training. These parameters are used for sampling compensation to overcome time mismatch during sampling. Meanwhile, channel gain mismatch is addressed using the chip's built-in gain control function. The reference clock is provided to the high-speed storage unit. The control process of the storage unit is still completed by the core control module. By supplying enable signals and other configuration signals to the storage unit, the acquired data is stored at high speed.

[0044] The signal analysis module is connected to the core control module, clock module, and interleaved acquisition module. Its main function is to preprocess the acquired signals, providing configurable filtering, array signal beamforming, and frequency domain analysis. The filtering function involves the core control module sending filtering parameters, including filter order, filter type, and filter length. After configuration, the signal analysis module performs the required filtering on the acquired data. The array signal beamforming function involves the core control module sending beamforming parameters, including beamforming mode, beamforming signal region, and other beamforming parameters (such as beam pointing and center frequency), to the signal analysis module. The signal analysis module then performs beamforming on the acquired signals based on these parameters. The frequency domain analysis function involves performing Fourier transforms on the acquired signals, analyzing their spectrum, and solving for certain parameters.

[0045] The core control module mainly consists of a display and control motherboard. The clock module consists of two FPGA (Field-Programmable Gate Array) clock timing processing boards. The multi-channel interleaved acquisition module mainly consists of four FPGA chip data acquisition boards and four FPGA data storage boards, with each signal acquisition board having a corresponding signal storage board. Each storage board has a PCIe interface for information exchange with external systems. Each FPGA chip corresponds to two high-speed AD sampling sensors. The signal analysis module consists of three separate FPGA signal processing boards (expandable) and an external power supply unit.

[0046] The FPGA chips used are all Xilinx's VX series high-speed processing chips, XC7VX690T processors, which have multiple 512MB DDR3 caches, 3 PCIe interfaces, and 9 GTHs.

[0047] It has a total of 36 lanes with a maximum speed of 13.1Gb / s, 3600 DSP slices, and multiple interfaces such as LVDS, GPIO, UART, 1000Base-BX, I2C, and SPI.

[0048] To implement the core control module's functions, dedicated acquisition and control software is designed within the display and control host. The core control module's hardware consists of an independent CPU processor. Within this CPU processor, a visual interface is used for clock module startup control, multi-channel interleaved acquisition module task parameter configuration, and signal analysis module task selection. Specific functions include...

[0049] Before the acquisition process, select whether to select the acquisition path (serial number 1-8) and determine different sampling modes according to the actual scenario, including continuous acquisition, pulse acquisition and threshold acquisition, and preset specific mode parameters for different modes.

[0050] During the data acquisition process, buttons for start, pause, and stop acquisition are designed, and corresponding control signals are sent to the clock module. At the same time, the user selects whether to store the data and sends a storage control signal.

[0051] After the acquisition process, the sampled data can be subjected to corresponding signal analysis. The three FPGA chips can respectively perform signal filtering, array signal beamforming, and frequency domain analysis.

[0052] The display and control host can send filtering modes, filtering lengths, and filtering orders, and send the filtering coefficients to the signal analysis module (board 1, filtering processing board). It can also send beamforming position parameters, frequency parameters, beam pointing parameters, and beamforming mode parameters, and send the corresponding values ​​to the signal analysis module (board 2, beamforming board). Furthermore, it can send the conversion source for frequency domain conversion to the signal analysis module (board 3, frequency domain analysis board) for spectrum conversion and use the frequency domain parameters to solve for key parameters of the electromagnetic signal. Simultaneously, each module feeds back status information to the display and control host for information exchange with the outside world.

[0053] The clock module consists of two FPGA clock boards (clock board 1 and clock board 2). Clock board 1 generates a stable low-frequency clock signal (50MHz) and uses this signal as a reference clock signal clk. This signal is then power-divided and multiplexed to other modules in the system and clock board 2. Simultaneously, using modules such as DCM, PLL, MMCM, and BUFR, a high-frequency sampling clock of 2.56GHz is generated as the high-speed sampling clock fclk. This high-frequency clock is then power-divided and input to the four ADC sampling boards and clock board 2. Additionally, the pulse control signal received by clock board 1 is input to clock board 2. Clock board 2 is a crucial part of the entire sampling system, providing the four ADC sampling boards with a set of eight pulse acquisition signals. These eight pulse acquisition signals are key to overcoming inter-channel time mismatch and ensuring channel synchronization.

[0054] Each generated ADC start control signal has a fixed phase relationship with the ADC operating clock. This fixed value depends on the signal's propagation delay and the phase relationship between the clock that generates the signal and the ADC operating clock. The signal propagation delay is determined during PCB and system design and is a fixed value. The phase relationship between the two clocks may differ in different systems. Furthermore, when the sampling rate changes, the phase of the start control signal transmitted to the ADC and the ADC operating clock may change. When this change causes the effective edge of the ADC start control signal to align with the effective edge of the ADC operating clock, it not only causes channel synchronization deviation but also leads to inconsistent signal phases during multiple ADC resets within the channel. In this case, the delay of the ADC start control signal is adjusted to offset the two effective signal edges. The same problem exists with the trigger signal. Therefore, when the phases of the two clocks change or the sampling clock frequency changes, the delay of both the ADC start control signal and the trigger signal needs to be adjusted.

[0055] To address the channel synchronization issue during multi-channel ADC sampling, the solution addresses the synchronization differences between channels caused by varying parallel data combination orders across different acquisition boards. The parallel data combination order is determined by the phase of the frequency divider clock. The starting phase of the frequency divider clock on the signal acquisition board can be directly determined by the ADC's start time. Therefore, maintaining consistency in the reset release times of each ADC ensures consistent frequency divider clock phases across all acquisition boards. The ADC reset signal for each acquisition board is uniformly provided by the clock timing board. To ensure a fixed phase relationship between the ADC reset signal and the ADC sampling clock, a 100MHz clock of the same origin as the sampling clock is used to generate the reset signal. To avoid alignment between the effective edge of the reset signal and the effective edge of the sampling clock, the reset signal undergoes adjustable delay processing. Additionally, the sampling gate signal during data truncation is also generated by the clock timing board in the same manner and provided to each acquisition board. When the sampling clock frequency or the phase relationship between the sampling clock and the originating clock changes in the acquisition system, the relationship between the ADC enable signal and the sampling clock, and the phase relationship between the sampling gate and the frequency divider clock for each acquisition board may change. In such cases, adjusting these two delays on each acquisition board achieves channel synchronization.

[0056] The multi-channel interleaved acquisition module consists of four FPGA signal acquisition boards and four FPGA data storage boards. Each signal acquisition board is connected to two external ADC sensors. The ADC chip used is the ADC32RF55, which is a dual-channel 14-bit 3GSPS RF sampling ADC with low noise spectral density (NSD) while ensuring a signal-to-noise ratio of 65.5dB and an effective bit depth of 10.5.

[0057] By using multi-channel ADC interleaved sampling, when the sampling rate of each ADC reaches 2.5Gb / s, the entire system has a total of 8 ADCs. Under the premise of ensuring that the time mismatch of each channel is overcome, the overall sampling rate of the system can reach 2.5Gsps*8=20Gb / s.

[0058] In addition, each data storage board includes a PCIe interface, enabling flexible data transfer with external devices.

[0059] The signal analysis module has three functions: basic filtering, beamforming, and frequency domain analysis.

[0060] For the filtering function, the selectable filter parameters are sent by the display and control host. The specific filtering method is implemented using an FIR filter. The selectable parameters for the FIR filter include filter length, filter bit depth, filter end, windowing type, etc.

[0061] For the beamforming function, the beamforming parameters are still sent by the display and control host, specifically including parameters such as center frequency, beam pointing, antenna aperture, and beam pointing.

[0062] Frequency domain analysis primarily refers to performing frequency domain transformation on selected acquired signals and solving for position parameters in the frequency domain. This includes using the Doppler principle to determine target velocity information and detecting peak information from multiple targets.

[0063] An electromagnetic signal acquisition and analysis method based on real-time multi-channel high-speed acquisition, combined with Figure 3 The workflow of this application is described below:

[0064] After checking the connection status of each board and confirming that everything is correct, power on the system. The clock module starts, and each module begins initialization. The display and control host sends a synchronization command to synchronize the pulse signals within the multi-channel gates until completion, and then sends a synchronization completion signal back to the display and control host. The display and control host presets the sampling module configuration parameters, such as sampling channels and sampling modes, as well as the signal processing module parameters, such as filtering coefficients and beamforming parameters. After receiving the configuration completion feedback, it sends a storage start signal and a acquisition start signal. The clock module supplies a high-speed sampling clock and triggers the sampling pulse to begin sampling. Simultaneously, each sampling board feeds back its status information during the sampling process to the display and control host, which then performs detection. If any abnormality is detected, the system terminates the sampling; otherwise, it maintains monitoring until the process ends. The signal processing module performs digital signal processing on the acquired signals, including targeted digital filtering, beamforming, and frequency domain analysis, and feeds back the processing results to the display and control host. Once the signal acquisition is complete, the display and control host sends a sampling termination signal, the storage board disables its storage mode, the acquisition board stops the sampling process, and the high-speed signal sampling ends.

[0065] An electromagnetic signal acquisition and analysis method based on real-time multi-channel high-speed acquisition, used for electromagnetic signal acquisition and analysis in complex electronic warfare environments, includes the following steps:

[0066] S1. Check the connection status of each board in the electromagnetic signal acquisition and analysis system. After confirming that everything is correct, prepare to power on.

[0067] S2, the clock module starts, each module begins initialization, the core control module issues a synchronization command to synchronize the pulse signals in the gate of the multi-channel interleaved acquisition module until completion, and then feeds back a synchronization completion signal to the core control module.

[0068] S3, the core control module presets the configuration parameters of the multi-channel interleaved acquisition module and the parameters of the signal analysis module. After receiving the feedback information of the configuration completion, it sends the storage start signal and the acquisition start signal. The clock module supplies the high-speed sampling clock and the sampling trigger pulse to start sampling. At the same time, each FPGA signal acquisition board feeds back the status information of the sampling process to the core control module, and the core control module performs detection.

[0069] S4. If there is an abnormality in the sampling process, the core control module sends a storage enable signal and a data acquisition start signal to terminate the process; otherwise, it maintains the monitoring state until the end.

[0070] S5, the signal analysis module performs digital signal processing on the acquired signal, including digital filtering, beamforming and frequency domain analysis, and feeds the processing results back to the core control module;

[0071] S6. After the signal acquisition is completed, the core control module sends a sampling termination signal, the FPGA data storage board closes the storage mode, and the sampling board stops the sampling process.

[0072] The specific configuration parameters for the multi-channel interleaved acquisition module are: acquisition path number, sampling bandwidth, sampling rate, and sampling mode parameters. The specific configuration parameters for the signal analysis module are: filter coefficients and beamforming parameters.

[0073] In summary, this application designs an electromagnetic signal acquisition, conversion and analysis system based on real-time multi-channel high-speed acquisition. By using channel interleaving acquisition, the time mismatch problem between sampling channels is overcome, and the system performance, including sampling rate, sampling accuracy and sampling stability, of the real-time high-speed acquisition system is further improved. At the same time, the basic functions of the sampling system are expanded, providing stronger real-time processing capabilities.

[0074] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An electromagnetic signal acquisition and analysis system based on real-time multi-channel high-speed acquisition, used for electromagnetic signal acquisition and analysis in complex electronic warfare environments, characterized in that, include: The system comprises a core control module, a clock module, a multi-channel interleaved acquisition module, and a signal analysis module. The signal output of the clock module is connected to the signal inputs of the core control module, the multi-channel interleaved acquisition module, and the signal analysis module, respectively. The signal output of the core control module is connected to the signal inputs of the clock module, the multi-channel interleaved acquisition module, and the signal analysis module, respectively. The signal output of the multi-channel interleaved acquisition module is connected to the signal input of the signal analysis module. The signal output of the signal analysis module is connected to the signal input of the core control module. The core control module is used to control the operating logic of the electromagnetic signal acquisition and analysis system. It schedules and allocates the clock resources of the clock module, the analog-to-digital converter (ADC) chip of the multi-channel interleaved acquisition module and the storage medium, configures the parameters of the multi-channel interleaved acquisition module and the signal analysis module, and interacts with the outside world during the sampling process. The clock module provides the clock resources required for sampling by the electromagnetic signal acquisition and analysis system, and is responsible for controlling the startup of the multi-channel interleaved acquisition module and the synchronous operation of the analog-to-digital converter (ADC) chip. The multi-channel interleaving acquisition module is used to acquire and store wideband real-time high-speed signals through the signal acquisition board in the storage medium. At the same time, it redistributes the initial signals acquired and stored in real time, and performs fusion processing on the redistributed signals according to the timing relationship between the single analog-to-digital converter chip (ADC) and the multi-channel interleaving acquisition module. The signal analysis module is used to perform parameter-configurable filtering on the signal data output by the multi-channel interleaved acquisition module, and to perform beamforming and frequency domain analysis on the filtered signal data.

2. The electromagnetic signal acquisition and analysis system based on real-time multi-channel high-speed acquisition according to claim 1, characterized in that, The core control module is the CPU processor.

3. The electromagnetic signal acquisition and analysis system based on real-time multi-channel high-speed acquisition according to claim 1, characterized in that, The multi-channel interleaved acquisition module includes multiple FPGA signal acquisition boards and multiple FPGA data storage boards. The FPGA signal acquisition boards and FPGA data storage boards correspond one-to-one. Each FPGA data storage board has a PCIe interface to support information exchange with the outside world. Each FPGA signal acquisition board is connected to no less than two analog-to-digital converter (ADC) chips.

4. The electromagnetic signal acquisition and analysis system based on real-time multi-channel high-speed acquisition according to claim 3, characterized in that, The multi-channel interleaved acquisition module obtains configuration parameters from the core control module, receives task scheduling control signals sent by the core control module, and feeds back sampling status information to the core control module. The specific configuration parameters obtained by the multi-channel interleaved acquisition module from the core control module include acquisition path number, sampling bandwidth, sampling rate, and sampling mode.

5. The electromagnetic signal acquisition and analysis system based on real-time multi-channel high-speed acquisition according to claim 1, characterized in that, The clock module consists of multiple FPGA clock timing processing boards, including three types of clock resources: reference clock resources, system sampling clock resources, and trigger clocks for sampling of each channel. The reference clock resource is used to provide the clk signal for the normal operation of the core control module, the multi-channel interleaved acquisition module, and the signal analysis module. The system sampling clock resource is used to provide the fclk signal required by the analog-to-digital converter (ADC) chip in the multi-channel interleaved acquisition module as a high-speed sampling clock; The trigger clock for sampling of each channel is used as the control clock signal to enable the multi-channel analog-to-digital converter (ADC).

6. The electromagnetic signal acquisition and analysis system based on real-time multi-channel high-speed acquisition according to claim 4, characterized in that, The multi-channel analog-to-digital converter (ADC) chip utilizes time interleaving to acquire external signals at high speed in a selected mode while ensuring correct timing. The selected mode is chosen by the core control module and includes continuous acquisition mode, pulse acquisition mode, and threshold acquisition mode.

7. The electromagnetic signal acquisition and analysis system based on real-time multi-channel high-speed acquisition according to claim 1, characterized in that, The signal analysis module includes a filtering module, a beamforming module, and a frequency domain analysis module. The filtering module receives filtering coefficients from the core control module, configures the parameters, and then performs filtering. The beamforming module receives beamforming parameters from the core control module, configures the parameters, and then performs beamforming. The frequency domain analysis module performs Fourier transform and spectral analysis on the beamformed signal to solve for the parameters.

8. The electromagnetic signal acquisition and analysis system based on real-time multi-channel high-speed acquisition according to claim 7, characterized in that, The filtering coefficients include the filter order, filter type, and filter length; the beamforming parameters include the beamforming mode, beamforming signal region, beamforming direction, and center frequency.

9. An electromagnetic signal acquisition and analysis method based on real-time multi-channel high-speed acquisition, used for electromagnetic signal acquisition and analysis in complex electronic warfare environments, implemented based on the electromagnetic signal acquisition and analysis system as described in any one of claims 1 to 8, characterized in that, Includes the following steps: S1. Check the connection status of each board in the electromagnetic signal acquisition and analysis system. After confirming that everything is correct, prepare to power on. S2, the clock module starts, each module begins initialization, the core control module issues a synchronization command to synchronize the pulse signals in the gate of the multi-channel interleaved acquisition module until completion, and then feeds back a synchronization completion signal to the core control module. S3, the core control module presets the configuration parameters of the multi-channel interleaved acquisition module and the parameters of the signal analysis module. After receiving the feedback information of the configuration completion, it sends the storage start signal and the acquisition start signal. The clock module supplies the high-speed sampling clock and the sampling trigger pulse to start sampling. At the same time, each FPGA signal acquisition board feeds back the status information of the sampling process to the core control module, and the core control module performs detection. S4. If there is an abnormality in the sampling process, the core control module will send a storage enable signal and a data acquisition start signal to terminate the process; otherwise, it will maintain the monitoring state until the end. S5, the signal analysis module performs digital signal processing on the acquired signal, including digital filtering, beamforming and frequency domain analysis, and feeds the processing results back to the core control module; S6. After the signal acquisition is completed, the core control module sends a sampling termination signal, the FPGA data storage board closes the storage mode, and the sampling board stops the sampling process.

10. The electromagnetic signal acquisition and analysis method based on real-time multi-channel high-speed acquisition according to claim 9, characterized in that, The specific configuration parameters for the multi-channel interleaved acquisition module are: acquisition path number, sampling bandwidth, sampling rate, and sampling mode parameters. The specific configuration parameters for the signal analysis module are: filter coefficients and beamforming parameters.

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