Data storage method, device, equipment and medium

Abstract

The present invention discloses a data storage method, device, equipment and medium, and relates to the field of digital integrated circuit technology. The solution utilizes the characteristic that the transparent transmission forward operation input and output unit of the pin of the target controller can maintain the state of the input / output signal. When the target controller operates normally, the target data of the data register of the target controller is transmitted to the transparent transmission forward operation input and output unit, thereby realizing the preservation of the target data; at the same time, the transparent transmission forward operation input and output unit corresponds to the unassigned pins of the target controller and will not affect the normal use of other assigned pins. After the target controller completes the firmware upgrade loading, the target data in the transparent transmission forward operation input and output unit can be directly retransmitted to the data register, and the target controller can be restored to the state before the upgrade, avoiding the loss of target data. It does not require the participation of the baseboard management controller and has the advantages of high speed and low resource occupation.

Description

Technical Field

[0001] The present invention relates to the technical field of digital integrated circuits, and in particular to a data storage method, device, equipment and medium. Background Art

[0002] In servers, complex programmable logic devices (CPLDs) are often used to control timing, device presence detection, and key signal latching and logging for boards like the motherboard, hard drive backplane, and fan board. When CPLD functions need to be modified or vulnerabilities addressed, their firmware must be updated online through the baseboard management controller (BMC).

[0003] However, after the upgrade, the CPLD's internal registers reset, potentially causing critical data loss and impacting server operation. Two main approaches are currently used to address this issue: First, reading and writing back registers through the BMC, but this involves significant latency. Because the BMC uses a polling method to access the CPLD, there's typically a one- to two-second delay from the time the CPLD firmware takes effect to the time key register data is written back, resulting in poor real-time performance. Second, the CPLD actively saves and reads back memory data, but this requires adding complex memory read and write functionality to the CPLD code, consuming significant internal resources, imposing time-sequential requirements, and making debugging difficult.

[0004] In view of the above, how to solve the current method of saving CPLD register data has poor real-time performance, occupies a large amount of internal resources, increases code complexity and debugging difficulty, which is an urgent problem to be solved by technicians in this field. Summary of the Invention

[0005] The purpose of the present invention is to provide a data storage method, device, equipment and medium to solve the problems that the current method of saving CPLD register data has poor real-time performance, occupies a large amount of internal resources, increases code complexity and debugging difficulty.

[0006] To solve the above technical problems, the present invention provides a data storage method, comprising:

[0007] When the target controller operates normally, the target data of the data register of the target controller is transmitted to the transparent transmission forward operation input and output unit to store the target data; wherein the transparent transmission forward operation input and output unit corresponds to the unassigned pin of the target controller;

[0008] Initiate a firmware upgrade of the target controller, and reload the firmware of the target controller after the upgrade is complete;

[0009] When the firmware of the target controller is loaded completely, the target data in the transparent transmission forward operation input and output unit is retransmitted to the data register, and the initial operation state of the target controller is restored.

[0010] On the one hand, the step of transmitting the target data of the data register of the target controller to the transparent transmission forward operation input and output unit includes:

[0011] Control the timer to transmit a high-level chip select signal to the data selector;

[0012] Based on the high-level chip select signal, the target data of the data register is transmitted to the output unit of the transparent transmission forward operation input and output unit through the data selector;

[0013] Transmitting the target data to the corresponding unassigned pin by transparently forwarding the output unit of the input and output unit;

[0014] The input unit of the forward running input and output unit acquires and stores the target data in the corresponding unassigned pin through transparent transmission.

[0015] On the other hand, starting the firmware upgrade of the target controller and reloading the firmware of the target controller after the upgrade is completed includes:

[0016] Initiate a firmware upgrade of the target controller based on an initial time, and control a timer and a data register to enter a reset state through a low-level global reset signal;

[0017] Completing firmware loading of the target controller based on the first moment, and controlling a timer and a data register to maintain a reset state through a low-level global reset signal;

[0018] The first moment lags behind the initial moment by one clock cycle.

[0019] On the other hand, retransmitting the target data in the transparent transmission forward operation input and output unit to the data register includes:

[0020] Based on the first moment after the firmware of the target controller is loaded, controlling the timer to transmit a low-level chip select signal to the data selector;

[0021] Based on the low-level chip select signal, the target data stored in the input unit of the transparent transmission forward operation input and output unit is transmitted to the output unit of the transparent transmission forward operation input and output unit through the data selector;

[0022] Transmitting the target data to the corresponding unassigned pin by transparently forwarding the output unit of the input and output unit;

[0023] The input unit of the forward running input and output unit acquires and stores the target data in the corresponding unassigned pin through transparent transmission;

[0024] Based on a second moment after the firmware of the target controller is loaded, controlling the timer and the data register to exit the reset state through a high-level global reset signal, and controlling the timer to transmit a low-level chip select signal to the data selector;

[0025] Controlling the data register to read the target data stored in the input unit of the transparent transmission forward operation input and output unit;

[0026] The second moment lags behind the first moment by one clock cycle.

[0027] On the other hand, it also includes:

[0028] Based on a third moment after the firmware of the target controller is loaded, controlling the timer to transmit a low-level loading signal to the data register to resume reading and writing of the data register by other functional modules;

[0029] The third moment lags behind the second moment by one clock cycle.

[0030] On the other hand, restoring the target controller to an initial operating state includes:

[0031] Based on a fourth moment after the firmware of the target controller is loaded, controlling the timer to transmit a high-level chip select signal to the data selector;

[0032] Based on the high-level chip select signal, the target data of the data register is transmitted to the output unit of the transparent transmission forward operation input and output unit through the data selector;

[0033] Transmitting the target data to the corresponding unassigned pin by transparently forwarding the output unit of the input and output unit;

[0034] Obtaining and storing the target data in the corresponding unassigned pins by transparently transmitting the input unit of the forward running input and output unit to restore the initial operating state of the target controller;

[0035] The fourth moment lags behind the third moment by one clock cycle.

[0036] On the other hand, after restoring the initial operating state of the target controller, the method further includes:

[0037] Monitor the reading and writing process of data registers by each functional module;

[0038] Determine whether there is an error in the reading and writing process of the data registers of each functional module;

[0039] If so, all read and write processes of the data register are terminated and an alarm message is output.

[0040] In order to solve the above technical problems, the present invention further provides a data storage device, comprising:

[0041] a first transmission module, configured to transmit target data of a data register of the target controller to a transparent transmission forward operation input / output unit to store the target data when the target controller operates normally; wherein the transparent transmission forward operation input / output unit corresponds to an unassigned pin of the target controller;

[0042] An upgrade loading module, configured to start a firmware upgrade of the target controller and reload the firmware of the target controller after the upgrade is completed;

[0043] The second transmission module is used to retransmit the target data in the transparent transmission forward operation input and output unit to the data register when the firmware loading of the target controller is completed, and restore the initial operation state of the target controller.

[0044] In order to solve the above technical problems, the present invention further provides a data storage device, comprising:

[0045] memory for storing computer programs;

[0046] A processor is used to implement the steps of the above-mentioned data storage method when executing the computer program.

[0047] In order to solve the above technical problems, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above data storage method are implemented.

[0048] The present invention provides a data storage method, which, when a target controller operates normally, transmits target data of a data register of the target controller to a transparent transmission forward operation input and output unit to store the target data; wherein the transparent transmission forward operation input and output unit corresponds to an unassigned pin of the target controller; starts upgrading the firmware of the target controller, and reloads the firmware of the target controller after the upgrade is completed; when the firmware loading of the target controller is completed, retransmits the target data in the transparent transmission forward operation input and output unit to the data register, and restores the initial operating state of the target controller.

[0049] The beneficial effect of the present invention is that the transparent transmission forward operation input and output unit of the target controller pin is capable of maintaining the state of the input / output signal. When the target controller is operating normally, the target data of the target controller's data register is transmitted to the transparent transmission forward operation input and output unit, thereby realizing the preservation of the target data; at the same time, the transparent transmission forward operation input and output unit corresponds to the unassigned pins of the target controller and does not affect the normal use of other assigned pins. After the target controller completes the firmware upgrade loading, the target data in the transparent transmission forward operation input and output unit can be directly retransmitted to the data register, and the target controller can be restored to its state before the upgrade, avoiding the loss of target data. Without the involvement of the baseboard management controller, it has the advantages of high speed and low resource consumption.

[0050] On the other hand, the present invention specifically controls the timer to transmit a high-level chip select signal to the data selector; based on the high-level chip select signal, the target data of the data register is transmitted to the output unit of the transparent transmission forward operation input and output unit through the data selector; the target data is transmitted to the corresponding unassigned pin through the output unit of the transparent transmission forward operation input and output unit; the target data in the corresponding unassigned pin is acquired and stored through the input unit of the transparent transmission forward operation input and output unit, thereby realizing data storage in the data register and preventing data loss during firmware upgrade. Based on the first moment after the firmware of the target controller is loaded, the timer is controlled to transmit a low-level chip select signal to the data selector; based on the low-level chip select signal, the target data stored in the input unit of the transparent transmission forward operation input and output unit is transmitted to the output unit of the transparent transmission forward operation input and output unit through the data selector; the target data is transmitted to the corresponding unassigned pin through the output unit of the transparent transmission forward operation input and output unit; the target data in the corresponding unassigned pin is acquired and stored through the input unit of the transparent transmission forward operation input and output unit; based on the second moment after the firmware of the target controller is loaded, the timer and data register are controlled to exit the reset state through a high-level global reset signal, and the timer is controlled to transmit a low-level chip select signal to the data selector; the data register is controlled to read the target data stored in the input unit of the transparent transmission forward operation input and output unit, thereby realizing the re-acquisition of the data register after the firmware is loaded, and preventing data loss from affecting the normal operation of the controller.

[0051] In addition, the present invention also provides a data storage device, equipment and medium, which have the same effects as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0053] Figure 1 A flowchart of a data storage method provided by an embodiment of the present invention;

[0054] Figure 2 A block diagram of the data storage principle provided by an embodiment of the present invention;

[0055] Figure 3 A timing diagram of target data storage provided by an embodiment of the present invention;

[0056] Figure 4 A schematic diagram of a data storage device provided by an embodiment of the present invention;

[0057] Figure 5 A schematic diagram of a data storage device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0058] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0059] The core of the present invention is to provide a data storage method, device, equipment and medium to solve the problems that the current method of saving CPLD register data has poor real-time performance, occupies a large amount of internal resources, increases code complexity and debugging difficulty.

[0060] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0061] Currently, there are two main ways to save key register information before and after a CPLD firmware upgrade: one is to read and write back information through an upgrade controller (such as a BMC), but there is a significant delay of 1 to 2 seconds because the BMC uses a polling method to access the CPLD. After the upgrade is complete, the registers are written back, and the CPLD firmware has already begun executing, resulting in poor real-time performance. The other is for the CPLD to actively save and read back memory data, but this requires adding complex memory read and write functions to the CPLD code, which consumes a large amount of internal resources, has time sequence requirements, and is difficult to debug. To address the above problems, the present invention provides a data storage method. It should be noted that the method provided by the present invention is applied to a target controller. The present invention does not limit the specific type of target controller. For example, it can be a CPLD, or other electronic device that requires register data to be saved during a firmware update, depending on the specific implementation.

[0062] Figure 1 Flowchart of a data storage method provided by an embodiment of the present invention. Figure 1 As shown, the method includes:

[0063] S10: When the target controller operates normally, the target data of the data register of the target controller is transmitted to the transparent transmission forward operation input and output unit to store the target data.

[0064] The transparent transmission forward operation input and output unit corresponds to the unassigned pins of the target controller.

[0065] Specifically, when the target controller operates normally, it is first necessary to transfer the target data of the data register of the target controller to the transparent transmission forward operation input and output unit (Transparent Field Reconfiguration Input / Output Cell), namely TransFR_IO_CELL, so as to store the target data.

[0066] TransFR technology allows the logic inside the CPLD to be updated on-site without interrupting system operation. This means that the configuration of the CPLD can be updated while the system is running without stopping or restarting the system. TransFR_IO_CELL is one of the key components for implementing the TransFR function. It is responsible for controlling the state of the input / output signals during CPLD reconfiguration. By using TransFR_IO_CELL, the known state of the input / output signals can be maintained during reconfiguration, thereby ensuring the stability and reliability of the system. In this embodiment, TransFR_IO_CELL is mainly used to store target data. It should be noted that the TransFR_IO_CELL used to store target data corresponds to the unassigned pins of the target controller, so it will not affect the normal use of other assigned pins.

[0067] In this embodiment, there is no limitation on the specific method of transmitting the target data of the data register of the target controller to the transparent transmission forward operation input and output unit, which depends on the specific implementation situation.

[0068] S11: Start the firmware upgrade of the target controller and reload the firmware of the target controller after the upgrade is complete.

[0069] After the target data in the data register is stored, the firmware upgrade of the target controller is started. After the upgrade is completed, the firmware of the target controller is reloaded. During the upgrade and loading process, the control logic of the entire target controller fails, so the target data in the data register will be lost.

[0070] S12: When the firmware loading of the target controller is completed, the target data in the transparent transmission forward operation input and output unit is retransmitted to the data register, and the initial operation state of the target controller is restored.

[0071] When the firmware loading of the target controller is completed, the target data in the transparent transmission forward operation input and output unit TransFR_IO_CELL will be retransmitted to the data register, and the initial operation state of the target controller will be restored to ensure that the target data in the data register will not be lost before and after the firmware upgrade loading.

[0072] It should be noted that, in this embodiment, the specific process of retransmitting the target data in the transparent transmission forward operation input and output unit to the data register and restoring the initial operation state of the target controller is not limited and depends on the specific implementation situation.

[0073] In this embodiment, the transparent transmission forward operation input / output unit of the target controller's pins is used to maintain the state of input / output signals. When the target controller is operating normally, the target data in the target controller's data register is transmitted to the transparent transmission forward operation input / output unit, thereby preserving the target data. Furthermore, the transparent transmission forward operation input / output unit corresponds to the target controller's unassigned pins and does not affect the normal use of other assigned pins. After the target controller completes the firmware upgrade, the target data in the transparent transmission forward operation input / output unit can be directly retransmitted to the data register, restoring the target controller to its pre-upgrade state. This avoids the loss of target data and does not require the involvement of the baseboard management controller, offering the advantages of high speed and low resource usage.

[0074] Figure 2 The data storage principle block diagram provided by the embodiment of the present invention. Based on the above embodiment, in some embodiments, such as Figure 2 As shown, the target data of the data register of the target controller is transmitted to the transparent transmission forward operation input and output unit, including:

[0075] S101: Control the timer to transmit a high-level chip select signal to the data selector;

[0076] S102: Based on the high-level chip select signal, the target data of the data register is transmitted to the output unit of the transparent transmission forward operation input and output unit through the data selector;

[0077] S103: forwarding the target data to the corresponding unassigned pins through the output unit of the input and output unit via transparent transmission;

[0078] S104: The input unit of the forward input and output unit is run through transparent transmission to obtain and store the target data in the corresponding unassigned pin.

[0079] Figure 3 This is a target data storage sequence diagram provided by an embodiment of the present invention. Figure 3 As shown, before the initial time T0, the target controller is in normal operation. At this time, the global reset signal GLB_RST_N is high, the control logic of the target controller is operating normally, and the value of the data register DAT_REG is set to 1 (target data). It should be noted that the global reset signal GLB_RST_N is active low, that is, when the global reset signal GLB_RST_N is low, the control logic of the target controller is in a reset state.

[0080] Furthermore, in the control logic of the target controller, a timer (Timer) is used to control the output of the chip select signal CS to the data selector MUX before and after firmware loading, and also to control the output of the load signal LOAD to the data register. To store the target data, the timer (Timer) needs to be controlled to transmit a high-level chip select signal to the data selector MUX. At this time, based on the high-level chip select signal CS, the target data in the data register DAT_REG is transmitted to the output unit of the transparent transmission forward operation input and output unit TransFR_IO_CELL through the data selector MUX.

[0081] It should be noted that the transparent transmission forward operation input and output unit TransFR_IO_CELL includes the output unit o_cell and the input unit i_cell; the internal logic of the target controller controls the level of the corresponding pin by controlling the output unit o_cell, and obtains the actual level of the corresponding pin by reading the value of the input unit i_cell.

[0082] Therefore, in this embodiment, the target data can be transmitted to the corresponding unassigned pin through the output unit o_cell of the transparent transmission forward running input and output unit TransFR_IO_CELL, and the target data in the corresponding unassigned pin can be further obtained and stored through the input unit i_cell of the transparent transmission forward running input and output unit TransFR_IO_CELL.

[0083] In this embodiment, a high-level chip select signal is transmitted to a data selector by controlling a timer; based on the high-level chip select signal, the target data of the data register is transmitted to the output unit of the transparent transmission forward operation input and output unit through the data selector; the target data is transmitted to the corresponding unassigned pin through the output unit of the transparent transmission forward operation input and output unit; the target data in the corresponding unassigned pin is obtained and stored through the input unit of the transparent transmission forward operation input and output unit, thereby realizing data storage in the data register and preventing data loss during firmware upgrade.

[0084] Based on the above embodiment, in some embodiments, starting a firmware upgrade of a target controller and reloading the firmware of the target controller after the upgrade is completed includes:

[0085] S111: starting a firmware upgrade for the target controller based on the initial moment, and controlling the timer and data register to enter a reset state through a low-level global reset signal;

[0086] S112: completing the firmware loading of the target controller based on the first moment, and controlling the timer and data register to maintain a reset state through a low-level global reset signal;

[0087] The first moment lags behind the initial moment by one clock cycle.

[0088] like Figure 3 As shown, the firmware upgrade of the target controller is started based on the initial time T0, and the firmware of the target controller is refreshed and reloaded. During this period, the global reset signal GLB_RST_N is pulled low, and the timer Timer and data register DAT_REG are controlled by the low-level global reset signal GLB_RST_N to enter the reset state, and the internal control logic of the target controller is disabled.

[0089] Furthermore, in the process of starting the firmware upgrade at the initial moment T0 to completing the firmware loading at the first moment T1, the transparent transmission forward operation input and output unit TransFR_IO_CELL corresponding to the unassigned pin of the target controller is not controlled by the control logic, and the output unit o_cell maintains the previous output state, that is, maintains the value of the data register DAT_REG before the upgrade, and the output value is 1; the output of the input unit i_cell is also 1.

[0090] Finally, at first moment T1, the firmware loading to the target controller is complete, and the target controller's control logic takes effect. The output unit o_cell exits the hold state, and the global reset signal GLB_RST_N remains low. Therefore, the target controller's control logic is reset. Specifically, the timer Timer and data register DAT_REG remain reset, and the data in the registers becomes 0. It will be appreciated that first moment T1 lags behind initial moment T0 by one clock cycle T. In this embodiment, the length of the clock cycle is not limited and depends on the specific implementation.

[0091] In this way, the firmware upgrade and loading of the target controller is achieved.

[0092] Based on the above embodiment, in some embodiments, retransmitting the target data in the transparent transmission forward operation input and output unit to the data register includes:

[0093] S121: Based on the first moment after the firmware of the target controller is loaded, controlling the timer to transmit a low-level chip select signal to the data selector;

[0094] S122: Based on the low-level chip select signal, the target data stored in the input unit of the transparent transmission forward operation input and output unit is transmitted to the output unit of the transparent transmission forward operation input and output unit through the data selector;

[0095] S123: forwarding the target data to the corresponding unassigned pin by running the output unit of the input and output unit through transparent transmission;

[0096] S124: The input unit of the forward input / output unit is operated through transparent transmission to obtain and store the target data in the corresponding unassigned pin;

[0097] S125: Based on the second moment after the firmware of the target controller is loaded, controlling the timer and the data register to exit the reset state through a high-level global reset signal, and controlling the timer to transmit a low-level chip select signal to the data selector;

[0098] S126: Control the data register to read the target data stored in the input unit of the transparent transmission forward operation input and output unit;

[0099] The second moment lags behind the first moment by one clock cycle.

[0100] In order to make the data register DAT_REG regain the target data after completing the firmware upgrade loading, such as Figure 3 As shown, at the first moment T1, the internal timer module Timer of the target controller is in a reset state, the load signal LOAD is at a high level, and the chip select signal CS is at a low level. Based on the low-level chip select signal CS, the data selector MUX transfers the target data stored in the input cell i_cell of the transparent transmission forward operation input and output unit TransFR_IO_CELL to the output cell o_cell of the transparent transmission forward operation input and output unit TransFR_IO_CELL. Although the output cell o_cell exits the hold state, the unassigned pins are still maintained in their previous state through the activated data selector MUX. In effect, the target data is again transferred to the corresponding unassigned pins via the output cell o_cell of the transparent transmission forward operation input and output unit TransFR_IO_CELL, and the target data in the corresponding unassigned pins is again retrieved and stored via the input cell i_cell of the transparent transmission forward operation input and output unit TransFR_IO_CELL.

[0101] Furthermore, based on the second moment T2 after the firmware of the target controller is loaded, the timer Timer and the data register DAT_REG are controlled to exit the reset state through the high-level global reset signal GLB_RST_N, and the timer Timer is controlled to transmit the low-level chip select signal CS to the data selector MUX. It should be noted that from the second moment T2 to the third moment T3, the chip select signal CS remains at a low level and the load signal LOAD remains at a high level. Therefore, the data register DAT_REG loads the value of the input unit i_cell and becomes 1. That is, starting from the second moment T2, the data register DAT_REG after the firmware of the target controller is refreshed is restored to the value before the refresh. It can be understood that the second moment T2 lags behind the first moment T1 by one clock cycle T, and the third moment T3 lags behind the second moment T2 by one clock cycle T.

[0102] In this way, the data registers can be retrieved after the firmware is loaded, preventing data loss from affecting the normal operation of the controller.

[0103] Based on the above embodiments, in some embodiments, the method further includes:

[0104] S13: Based on the third moment after the firmware of the target controller is loaded, controlling the timer to transmit a low-level loading signal to the data register to resume reading and writing of the data register by other functional modules;

[0105] The third moment lags behind the second moment by one clock cycle.

[0106] like Figure 3 As shown, at the third moment T3 after the firmware of the target controller is loaded, the control timer Timer transmits a low-level load signal LOAD to the data register. The data register DAT_REG is partially controlled by other functional modules in the control logic of the target controller, thereby restoring the reading and writing of the data register DAT_REG by the other functional modules, ensuring the normal operation of the other functional modules. In this embodiment, the specific types of the other functional modules are not limited and depend on the specific implementation.

[0107] Based on the above embodiment, in some embodiments, restoring the initial operating state of the target controller includes:

[0108] S127: Based on a fourth moment after the firmware of the target controller is loaded, controlling the timer to transmit a high-level chip select signal to the data selector;

[0109] S128: Based on the high-level chip select signal, the target data of the data register is transmitted to the output unit of the transparent transmission forward operation input and output unit through the data selector;

[0110] S129: forwarding the target data to the corresponding unassigned pin by running the output unit of the input and output unit through transparent transmission;

[0111] S130: Obtaining and storing the target data in the corresponding unassigned pin by transparently transmitting the input unit of the forward running input and output unit to restore the initial operating state of the target controller;

[0112] The fourth moment lags behind the third moment by one clock cycle.

[0113] In order to restore the target controller to its initial operating state, such as Figure 3 As shown, at the fourth moment T4 after the firmware loading of the target controller is completed, the control timer Timer transmits the high-level chip select signal CS to the data selector MUX, thereby transmitting the target data of the data register DAT_REG to the output unit o_cell of the transparent transmission forward operation input and output unit TransFR_IO_CELL through the data selector MUX based on the high-level chip select signal CS, and transmitting the target data to the corresponding unassigned pin through the output unit o_cell of the transparent transmission forward operation input and output unit TransFR_IO_CELL; finally, the target data in the corresponding unassigned pin is obtained and stored through the input unit i_cell of the transparent transmission forward operation input and output unit TransFR_IO_CELL to restore the initial operation state of the target controller.

[0114] Based on the above embodiment, in some embodiments, after restoring the initial operating state of the target controller, the method further includes:

[0115] S14: Monitor the reading and writing process of each functional module on the data register;

[0116] S15: Determine whether an error occurs in the reading and writing process of the data register by each functional module; if so, proceed to step S16;

[0117] S16: Terminate all read and write processes of the data register and output an alarm message.

[0118] In this embodiment, to ensure that the target controller firmware is correctly updated, after restoring the target controller's initial operating state, the read and write processes of each functional module to the data register can be monitored. A determination is made as to whether errors occur in the read and write processes of each functional module to the data register. If not, monitoring continues. If errors are confirmed in the read and write processes to the data register, all read and write processes to the data register are terminated, and an alarm message is output to prompt the user to perform inspection and maintenance.

[0119] Furthermore, after the firmware upgrade is complete, verify that other functional modules are functioning as expected. Specifically, compare the updated register values ​​with the pre-upgrade backup. If discrepancies are found, possible causes include errors in the functional module's code, resulting in incorrect read and write operations to the registers; or other system factors, such as power fluctuations or external interference, affecting the register status. Both of these situations require separate troubleshooting: updating the functional module's code to eliminate the fault, and replacing the power supply to eliminate external interference to ensure normal operation of the target controller.

[0120] In the above embodiments, the data storage method is described in detail. The present invention also provides corresponding embodiments of the data storage device.

[0121] Figure 4 Schematic diagram of a data storage device provided by an embodiment of the present invention. Figure 4 As shown, the device includes:

[0122] The first transmission module 10 is used to transmit the target data of the data register of the target controller to the transparent transmission forward operation input and output unit to store the target data when the target controller operates normally; wherein the transparent transmission forward operation input and output unit corresponds to the unassigned pin of the target controller.

[0123] The upgrade loading module 11 is used to start the firmware upgrade of the target controller and reload the firmware of the target controller after the upgrade is completed.

[0124] The second transmission module 12 is used to retransmit the target data in the transparent transmission forward operation input and output unit to the data register when the firmware loading of the target controller is completed, and restore the initial operation state of the target controller.

[0125] In some embodiments, the first transmission module 10 includes:

[0126] A first control submodule, used for controlling the timer to transmit a high-level chip select signal to the data selector;

[0127] A first transmission submodule is configured to transmit target data of the data register to an output unit of the transparent transmission forward operation input and output unit through a data selector based on a high-level chip select signal;

[0128] a second transmission submodule, configured to transmit target data to a corresponding unassigned pin by transparently forwarding the output unit of the input and output unit;

[0129] The first acquisition submodule is configured to forwardly execute the input unit of the input-output unit through transparent transmission to acquire and store target data in the corresponding unassigned pin.

[0130] In some embodiments, the upgrade loading module 11 includes:

[0131] A second control submodule is used to start the firmware upgrade of the target controller based on the initial time, and control the timer and data register to enter the reset state through a low-level global reset signal;

[0132] A third control submodule, configured to complete loading of the firmware on the target controller based on the first moment, and control the timer and the data register to maintain a reset state through a low-level global reset signal;

[0133] The first moment lags behind the initial moment by one clock cycle.

[0134] In some embodiments, the second transmission module 12 includes:

[0135] A fourth control submodule, configured to control the timer to transmit a low-level chip select signal to the data selector based on a first moment after the firmware of the target controller is loaded;

[0136] a third transmission submodule, configured to transmit the target data stored in the input unit of the transparent transmission forward operation input and output unit to the output unit of the transparent transmission forward operation input and output unit through the data selector based on the low-level chip select signal;

[0137] a fourth transmission submodule, configured to transmit the target data to the corresponding unassigned pin by transparently forwarding the output unit of the input and output unit;

[0138] A second acquisition submodule is used to acquire and store target data in the corresponding unassigned pin by transparently transmitting the input unit of the forward input and output unit;

[0139] a fifth control submodule, configured to control the timer and the data register to exit the reset state through a high-level global reset signal at a second moment after the firmware of the target controller is loaded, and to control the timer to transmit a low-level chip select signal to the data selector;

[0140] A sixth control submodule, configured to control the data register to read target data stored in the input unit of the transparent transmission forward operation input and output unit;

[0141] The second moment lags behind the first moment by one clock cycle.

[0142] In some embodiments, it further includes:

[0143] a seventh control submodule, configured to control the timer to transmit a low-level load signal to the data register based on a third moment after the firmware of the target controller is loaded, so as to resume reading and writing of the data register by other functional modules;

[0144] The third moment lags behind the second moment by one clock cycle.

[0145] In some embodiments, restoring the target controller to an initial operating state includes:

[0146] an eighth control submodule, configured to control the timer to transmit a high-level chip select signal to the data selector based on a fourth moment after the firmware of the target controller is loaded;

[0147] A fifth transmission submodule, configured to transmit target data of the data register to an output unit of the transparent transmission forward operation input and output unit through a data selector based on a high-level chip select signal;

[0148] a sixth transmission submodule, configured to transmit the target data to the corresponding unassigned pin by transparently forwarding the output unit of the input and output unit;

[0149] A third acquisition submodule is used to acquire and store the target data in the corresponding unassigned pin by transparently transmitting the input unit of the forward running input and output unit to restore the initial operation state of the target controller;

[0150] The fourth moment lags behind the third moment by one clock cycle.

[0151] In some embodiments, after restoring the initial operating state of the target controller, the method further includes:

[0152] The monitoring submodule is used to monitor the reading and writing process of each functional module on the data register;

[0153] The judgment submodule is used to judge whether there is an error in the reading and writing process of the data register of each functional module; if so, the alarm submodule is triggered;

[0154] The alarm submodule is used to terminate all read and write processes of the data register and output alarm information.

[0155] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, and they will not be repeated here.

[0156] In addition, the present invention also provides a computer program product, comprising a computer program / instruction, which implements the steps of the above data storage method when executed by a processor.

[0157] Figure 5 Schematic diagram of a data storage device provided by an embodiment of the present invention. Figure 5 As shown, the data storage device includes:

[0158] Memory 20, for storing computer programs;

[0159] The processor 21 is configured to implement the steps of the data storage method mentioned in the above embodiment when executing a computer program.

[0160] The data storage device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer, or a desktop computer.

[0161] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented in at least one hardware form: a digital signal processor (DSP), a field-programmable gate array (FPGA), or a programmable logic array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, the processor 21 may also include an artificial intelligence (AI) processor, which is responsible for processing computing operations related to machine learning.

[0162] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used to store the following computer program 201, wherein, after the computer program is loaded and executed by the processor 21, it can implement the relevant steps of the data storage method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include but is not limited to data involved in the data storage method.

[0163] In some embodiments, the data storage device may further include a display screen 22 , an input / output interface 23 , a communication interface 24 , a power supply 25 , and a communication bus 26 .

[0164] Those skilled in the art will understand that Figure 5 The structure shown in the figure does not constitute a limitation of the data storage device, and may include more or fewer components than shown in the figure.

[0165] Finally, the present invention also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps described in the above method embodiment.

[0166] It is understood that if the methods in the above embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage media include various media that can store program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0167] The above is a detailed introduction to a data storage method, device, equipment and medium provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the present invention.

[0168] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A data storage method, characterized in that: include: When the target controller operates normally, the target data of the data register of the target controller is transmitted to the transparent transmission forward operation input and output unit to store the target data; wherein the transparent transmission forward operation input and output unit corresponds to the unassigned pin of the target controller; Initiate a firmware upgrade of the target controller, and reload the firmware of the target controller after the upgrade is complete; When the firmware of the target controller is loaded, the target data in the transparent transmission forward operation input and output unit is retransmitted to the data register, and the initial operation state of the target controller is restored; The step of transmitting the target data of the data register of the target controller to the transparent transmission forward operation input and output unit comprises: Control the timer to transmit a high-level chip select signal to the data selector; Based on the high-level chip select signal, the target data of the data register is transmitted to the output unit of the transparent transmission forward operation input and output unit through the data selector; Transmitting the target data to the corresponding unassigned pin by transparently forwarding the output unit of the input and output unit; The input unit of the forward running input and output unit acquires and stores the target data in the corresponding unassigned pin through transparent transmission; The step of retransmitting the target data in the transparent transmission forward operation input and output unit to the data register includes: Based on the first moment after the firmware of the target controller is loaded, controlling the timer to transmit a low-level chip select signal to the data selector; Based on the low-level chip select signal, the target data stored in the input unit of the transparent transmission forward operation input and output unit is transmitted to the output unit of the transparent transmission forward operation input and output unit through the data selector; Transmitting the target data to the corresponding unassigned pin by transparently forwarding the output unit of the input and output unit; The input unit of the forward running input and output unit acquires and stores the target data in the corresponding unassigned pin through transparent transmission; Based on a second moment after the firmware of the target controller is loaded, controlling the timer and the data register to exit the reset state through a high-level global reset signal, and controlling the timer to transmit a low-level chip select signal to the data selector; Controlling the data register to read the target data stored in the input unit of the transparent transmission forward operation input and output unit; The second moment lags behind the first moment by one clock cycle.

2. The data storage method according to claim 1, wherein: The initiating the firmware upgrade of the target controller and reloading the firmware of the target controller after the upgrade is completed includes: Initiate a firmware upgrade of the target controller based on an initial time, and control a timer and a data register to enter a reset state through a low-level global reset signal; Completing firmware loading of the target controller based on the first moment, and controlling a timer and a data register to maintain a reset state through a low-level global reset signal; The first moment lags behind the initial moment by one clock cycle.

3. The data storage method according to claim 1, wherein: Also includes: Based on a third moment after the firmware of the target controller is loaded, controlling the timer to transmit a low-level loading signal to the data register to resume reading and writing of the data register by other functional modules; The third moment lags behind the second moment by one clock cycle.

4. The data storage method according to claim 1, wherein: Restoring the target controller to an initial operating state includes: Based on a fourth moment after the firmware of the target controller is loaded, controlling the timer to transmit a high-level chip select signal to the data selector; Based on the high-level chip select signal, the target data of the data register is transmitted to the output unit of the transparent transmission forward operation input and output unit through the data selector; Transmitting the target data to the corresponding unassigned pin by transparently forwarding the output unit of the input and output unit; Obtaining and storing the target data in the corresponding unassigned pins by transparently transmitting the input unit of the forward running input and output unit to restore the initial operating state of the target controller; The fourth moment lags behind the third moment by one clock cycle.

5. The data storage method according to any one of claims 1 to 4, characterized in that: After restoring the initial operating state of the target controller, the method further includes: Monitor the reading and writing process of data registers by each functional module; Determine whether there is an error in the reading and writing process of the data registers of each functional module; If so, all read and write processes of the data register are terminated and an alarm message is output.

6. A data storage device, characterized in that include: a first transmission module, configured to transmit target data of a data register of the target controller to a transparent transmission forward operation input / output unit to store the target data when the target controller operates normally; wherein the transparent transmission forward operation input / output unit corresponds to an unassigned pin of the target controller; An upgrade loading module, configured to start a firmware upgrade of the target controller and reload the firmware of the target controller after the upgrade is completed; a second transmission module, configured to retransmit the target data in the transparent transmission forward operation input and output unit to the data register when the firmware loading of the target controller is completed, and restore the initial operation state of the target controller; The first transmission module includes: A first control submodule, used for controlling the timer to transmit a high-level chip select signal to the data selector; A first transmission submodule is configured to transmit the target data in the data register to the output unit of the transparent transmission forward operation input and output unit through the data selector based on a high-level chip select signal; a second transmission submodule, configured to transmit the target data to the corresponding unassigned pin by transparently transmitting the output unit of the forward input and output unit; A first acquisition submodule is configured to acquire and store the target data in the corresponding unassigned pin by transparently transmitting the input unit of the forward input-output unit; The second transmission module includes: A fourth control submodule, configured to control the timer to transmit a low-level chip select signal to the data selector based on a first moment after the firmware of the target controller is loaded; a third transmission submodule, configured to transmit the target data stored in the input unit of the transparent transmission forward operation input and output unit to the output unit of the transparent transmission forward operation input and output unit through a data selector based on a low-level chip select signal; A fourth transmission submodule, configured to transmit the target data to the corresponding unassigned pin by transparently forwarding the output unit of the input and output unit; A second acquisition submodule is configured to acquire and store the target data in the corresponding unassigned pin by transparently transmitting the input unit of the forward input-output unit; a fifth control submodule, configured to control the timer and the data register to exit the reset state through a high-level global reset signal based on a second moment after the firmware of the target controller is loaded, and to control the timer to transmit a low-level chip select signal to the data selector; A sixth control submodule, configured to control the data register to read the target data stored in the input unit of the transparent transmission forward operation input and output unit; The second moment lags behind the first moment by one clock cycle.

7. A data storage device, characterized in that include: memory for storing computer programs; A processor, configured to implement the steps of the data storage method according to any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the data storage method according to any one of claims 1 to 5.

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