Register renaming method, device, system, equipment and medium

Abstract

The present invention provides a register renaming method, device, system, equipment and medium, belonging to the field of processor technology, the method comprising: obtaining multiple instructions after decoding, and recording the order relationship of target instructions in multiple instructions, obtaining a renaming ordering queue, the target instruction is an instruction with a destination register; assigning each instruction to a dispatch queue corresponding to each instruction for execution; based on the renaming ordering queue, submitting the executed target instruction for register renaming. The present invention solves the problem in the related art that instructions without destination registers are submitted in a reordering buffer to submit and restore register renaming information, resulting in waste of resources, thereby affecting the speed of register renaming recovery and the processing efficiency of the processor. By submitting register renaming through a renaming ordering queue, waste caused by some instructions without destination registers is avoided, saving processor resources.

Description

Technical Field

[0001] The present invention relates to the field of processor technology, and in particular to a register renaming method, device, system, equipment and medium. Background Art

[0002] In an out-of-order processor, the decoded instructions are first registered and renamed, and then assigned to different dispatch queues according to the operation type. Since superscalar processors basically use prediction to execute instructions, such as branch prediction, storage instruction and fetch instruction related prediction, when a certain instruction in the pipeline has a prediction error, or an instruction has an exception, then all instructions entering the pipeline after this instruction are not allowed to be submitted. These instructions need to be erased from the pipeline, and the processor state is restored to the state when the instruction is started. However, in the related art, when an instruction is submitted from the reorder buffer (ROB), it is necessary to determine the renaming relationship of the destination register of the instruction, and confirm the result of the destination physical register of the submitted instruction to the logical register. Therefore, when a prediction error occurs in the instruction stream of the processor, it is necessary to restore the register renaming information from the reorder buffer. Among them, a certain proportion of instructions without a destination register do not need to submit and restore the register. For these instructions, submitting and restoring register renaming information by submitting them in the reorder buffer will cause a waste of resources, thereby affecting the speed of register renaming recovery and the processing efficiency of the processor. Summary of the invention

[0003] The present invention provides a register renaming method, apparatus, system, device and medium, which are used to solve the problem in the related art that instructions without destination registers are submitted in a reorder buffer to submit and restore register renaming information, which will cause waste of resources, thereby affecting the speed of register renaming recovery and affecting the processing efficiency of the processor.

[0004] The present invention provides a register renaming method, comprising the following steps:

[0005] Obtain multiple decoded instructions, and record the order relationship of the target instruction in the multiple instructions to obtain a rename order queue, where the target instruction is an instruction stored in a destination register;

[0006] Assign each instruction to the dispatch queue corresponding to each instruction for execution;

[0007] Based on the renaming order queue, the target instructions that have been executed are submitted for register renaming.

[0008] According to a register renaming method provided by the present invention, each instruction is assigned to a dispatch queue corresponding to each instruction for execution, including:

[0009] Determine the first type of physical register corresponding to the source register of each instruction according to the renaming mapping table;

[0010] Map the second type of physical register for each target instruction's destination register, and write the mapping relationship into a renaming mapping table;

[0011] The first type physical register number and the second type physical register number corresponding to each instruction are sent to the dispatch queue to obtain the execution result of the instruction.

[0012] According to a register renaming method provided by the present invention, a second type of physical register is mapped to a destination register of each target instruction, and a mapping relationship is written into a renaming mapping table, including:

[0013] Determine the free physical registers according to the physical register table and the free physical register number table;

[0014] Mapping an idle physical register to a destination register of each target instruction, and determining the mapped idle physical register as a second type of physical register;

[0015] The mapping relationship is written into the renaming mapping table, and the status of the second type of physical registers is corrected in the physical register table and the free physical register number table.

[0016] According to a register renaming method provided by the present invention, based on a renaming order queue, the executed target instruction is submitted for register renaming, comprising:

[0017] Determine a submission order of register renaming of the target instructions that have been executed according to the renaming order queue;

[0018] Based on the submission order, the execution result corresponding to each executed target instruction is sequentially written into the second type physical register corresponding to the target instruction.

[0019] According to a register renaming method provided by the present invention, the method further includes:

[0020] When a misprediction or exception occurs, register renaming recovery is performed based on the renaming order queue.

[0021] According to a register renaming method provided by the present invention, when a prediction error or an exception occurs, register renaming recovery is performed based on a renaming order queue, comprising:

[0022] When a prediction error or an exception occurs, determining the order relationship of the target instructions based on the rename order queue;

[0023] According to the sequence relationship, starting from the current target instruction, the execution of the target instructions is restored one by one, and the renaming mapping table is restored accordingly.

[0024] The present invention also provides a register renaming device, comprising the following units:

[0025] An acquisition unit is used to acquire multiple instructions after decoding, and record the order relationship of the target instruction among the multiple instructions to obtain a rename order queue, wherein the target instruction is an instruction stored in a destination register;

[0026] An execution unit is used to assign each instruction to a dispatch queue corresponding to each instruction for execution;

[0027] The commit unit is used to commit the executed target instruction for register renaming based on the renaming order queue.

[0028] According to a register renaming device provided by the present invention, the execution unit is specifically used for:

[0029] Determine the first type of physical register corresponding to the source register of each instruction according to the renaming mapping table;

[0030] Map the second type of physical register for each target instruction's destination register, and write the mapping relationship into a renaming mapping table;

[0031] The first type physical register number and the second type physical register number corresponding to each instruction are sent to the dispatch queue to obtain the execution result of the instruction.

[0032] According to a register renaming device provided by the present invention, the execution unit is specifically used for:

[0033] Determine the free physical registers according to the physical register table and the free physical register number table;

[0034] Mapping an idle physical register to a destination register of each target instruction, and determining the mapped idle physical register as a second type of physical register;

[0035] The mapping relationship is written into the renaming mapping table, and the status of the second type of physical registers is corrected in the physical register table and the free physical register number table.

[0036] According to a register renaming device provided by the present invention, the submitting unit is specifically used for:

[0037] Determine a submission order of register renaming of the target instructions that have been executed according to the renaming order queue;

[0038] Based on the submission order, the execution result corresponding to each executed target instruction is sequentially written into the second type physical register corresponding to the target instruction.

[0039] According to a register renaming device provided by the present invention, the execution unit is further used for:

[0040] When a misprediction or exception occurs, register renaming recovery is performed based on the renaming order queue.

[0041] According to a register renaming device provided by the present invention, when a prediction error or an exception occurs, register renaming recovery is performed based on a renaming order queue, and the execution unit is specifically further used for:

[0042] When a prediction error or an exception occurs, determining the order relationship of the target instructions based on the rename order queue;

[0043] According to the sequence relationship, starting from the current target instruction, the execution of the target instructions is restored one by one, and the renaming mapping table is restored accordingly.

[0044] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-mentioned register renaming methods when executing the program.

[0045] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, any of the register renaming methods described above is implemented.

[0046] The register renaming method provided by the present invention first obtains multiple instructions after decoding, and records the order relationship of the target instructions in the multiple instructions to obtain a renaming sequencing queue, wherein the target instruction is an instruction with a destination register, and then each instruction is assigned to a dispatch queue corresponding to each instruction for execution, and finally, based on the renaming sequencing queue, the executed target instruction is submitted for register renaming. Submitting register renaming through the renaming sequencing queue avoids the waste caused by some instructions not having a destination register, and saves processor resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 It is a schematic diagram of instruction types provided by the present invention.

[0049] Figure 2 It is a flow chart of a register renaming method provided by the present invention.

[0050] Figure 3 The present invention is a flowchart of a register renaming and restoring method.

[0051] Figure 4 The present invention is a schematic diagram of the principle of a register renaming method provided by the present invention.

[0052] Figure 5 It is a structural schematic diagram of the register renaming device provided by the present invention.

[0053] Figure 6 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] In an out-of-order processor, the decoded instructions are first registered and renamed (Register Renaming), and then dispatched to different dispatch queues according to the instruction operation type. Register renaming is a key technology for out-of-order execution in the dynamic pipeline of an out-of-order processor. The out-of-order processor eliminates dependencies between instructions by renaming logical registers. Register renaming technology eliminates register read-after-write dependencies (WAR) and write-after-write dependencies (WAW) between instructions, increases the number of instructions that can be scheduled in parallel by the out-of-order processor, completes out-of-order scheduling, and ensures accuracy on the spot when a prediction error or exception occurs during instruction execution and the subsequent instructions are canceled.

[0056] However, modern superscalar processors use many prediction methods to execute instructions, and not all instructions in the pipeline can be committed. For example, when a branch instruction in the pipeline is mispredicted or an instruction is abnormal, all instructions that enter the pipeline after this instruction are not allowed to be committed. They need to be erased and the processor state restored, and then the instructions are fetched again for execution.

[0057] In the prior art, when an instruction is submitted from a reorder buffer (ROB), it is necessary to first determine the renaming relationship of the destination register of the instruction, and then confirm the result of the destination physical register of the submitted instruction into the logical register. If a prediction error occurs in the instruction stream of the processor, it is necessary to restore the register renaming information from the reorder buffer (ROB). However, many instructions do not have a destination register. For example, store instructions, branch instructions, etc. In general typical programs, these instructions without destination registers account for a large proportion of the instructions executed by the processor.

[0058] For example, RISC-V (Reduced Instruction Set Computer-V, the fifth generation of reduced instruction set) defines six instruction types, such as Figure 1 As shown in the figure, funct7 represents the 7-bit function code; rs1 represents the source register 1; rs2 represents the source register 2; funct3 represents the 3-bit function code; rd represents the destination register; opcode represents the operation code; and imm represents the immediate value. The source register rs1, the source register rs2, and the destination register rd are used to specify the registers that the instruction needs to operate. rs1 is the first source register number of the instruction; rs2 is the second source register number of the instruction; and rd is the destination register number where the instruction receives the result value. The six instruction types defined in RISC-V in the figure include: R-type instructions (R-type), instructions for arithmetic operations between registers; I-type instructions (I-type): instructions for arithmetic operations between registers and immediate numbers and read memory operations; S-type instructions (S-type): used for write memory operations; B-type instructions (B-type): instructions for branch transfers, which are a small variant of S-type instructions and were previously called SB-type instructions; U-type instructions (U-type): instructions for high 20-bit immediate number operations; J-type instructions (J-type): instructions for direct jumps, which are a small variant of U-type instructions and were previously called UJ-type instructions. Among them, both S-type instructions and B-type instructions have no destination register (rd). Instructions without destination registers do not need to submit and restore registers. Submitting and restoring register renaming information based on the submission of instructions in the reorder buffer ROB will cause a waste of resources and affect the speed of register renaming recovery. In an out-of-order processor, register renaming and recovery generally takes dozens of clock cycles to complete, which has a significant impact on the processor's processing efficiency.

[0059] Therefore, a register renaming method is urgently needed to solve the above problem.

[0060] Combine the following Figure 2-Figure 6The present invention describes a register renaming method, apparatus, system, device and medium.

[0061] Figure 2 is one of the flow charts of the register renaming method provided by the present invention, such as Figure 2 As shown, the method includes the following:

[0062] Step 201, obtain multiple decoded instructions, and record the order relationship of the target instruction in the multiple instructions to obtain a rename order queue, where the target instruction is the instruction stored in the destination register.

[0063] In specific implementation, the decoded instruction first performs register renaming. In the present invention, an independent renaming ordering queue is used to maintain the order of register submission and restoration. The renaming ordering queue only maintains the order relationship of instructions with destination registers.

[0064] Step 202: Allocate each instruction to a dispatch queue corresponding to each instruction for execution.

[0065] In specific implementation, after renaming, the instructions are allocated to different dispatch queues according to their operation types, including a fixed-point dispatch queue, a floating-point dispatch queue, and a memory access dispatch queue.

[0066] The renaming of logical registers to physical registers is to find the corresponding physical register numbers for the source register and the destination register according to the dependency relationship, map the destination register to at least one free physical register, and write the renamed register number into the dispatch queue. When mapping the free physical register to the destination register, update the status of the physical register. Specifically, according to the renaming mapping table, determine the first-class physical register assigned to the source register of each instruction, that is, the physical register corresponding to the read source operand, and also map the second-class physical register to the destination register of each target instruction, and write the mapping relationship into the renaming mapping table, and then send the first-class physical register number and the second-class physical register number corresponding to each instruction into the dispatch queue to obtain the execution result of the instruction. After execution, write the execution result back to the second-class physical register according to the number of the second-class physical register.

[0067] Step 203: Based on the renaming order queue, submit the executed target instruction for register renaming.

[0068] During specific implementation, according to the renaming order queue, a renaming mapping table is submitted to confirm the renaming relationship of the second type of physical registers, and at the same time, the previous renaming relationship of the second type of physical registers is released.

[0069] Specifically, during renaming, three renaming-related tables or pointers are maintained. The first is a mapping table from logical registers to physical registers, also known as a renaming mapping table, which is used to record the most recently allocated physical register number corresponding to each logical register. The second is a physical register table that records the status of the physical register, whether it is allocated, and whether the data is written back. The third is an idle physical register number table that records the numbers of idle physical registers in the committed state, and maintains pointers for the allocation and release of idle physical registers in the committed state.

[0070] In this embodiment, when register renaming is submitted, it is also necessary to modify the logical register and physical register mapping table in the submitted state and the pointer allocated to the free physical register. By using the method provided in the embodiment of the present invention, the register submission of register renaming can be performed without passing through the reorder buffer, thereby saving processor resources and improving the processing speed of register renaming.

[0071] Figure 3 is a flow chart of the register renaming recovery method provided by the present invention, such as Figure 3 As shown, the method includes the following:

[0072] Step 301 : When a prediction error or an exception occurs, determine the order relationship of target instructions based on the rename order queue.

[0073] In specific implementation, prediction errors may include prediction errors of processor speculative execution such as branch prediction errors, prediction errors related to store and load instructions, and cache coherence prediction errors of multi-core processors. When a prediction error or an exception occurs, register renaming recovery is required. Specifically, according to the renaming ordering queue, the mapping table from logical registers to physical registers is modified, and it is confirmed that the mapping table recording the committed status is the latest mapping of the corresponding logical register to the physical register, and the empty table pointer of the unallocated physical register is rolled back to the empty table pointer of the committed status.

[0074] Step 302: According to the sequence relationship, starting from the current target instruction, the execution of the target instructions is restored one by one, and the renaming mapping table is restored accordingly.

[0075] In specific implementation, when a branch instruction prediction error is found in the pipeline, all instructions that enter the pipeline after it become incorrect, but these instructions may have completed the process of instruction fetching, register renaming, and even execution. Therefore, when a branch prediction error is found, these erroneous instructions should be erased from the pipeline, and the state of the processor needs to be restored to the state when the branch instruction was started. At the same time, the renaming mapping table needs to be restored to correct the modifications made to the renaming mapping table (RAT) by those erroneous instructions, and the physical registers occupied by the erroneous instructions also need to be released. When branch prediction fails, most of the recovery tasks are performed on the components related to register renaming, because most of the instructions on the wrong path have gone through this step, and the renaming mapping table (RAT) and related components have been modified. In order to ensure that subsequent instructions can continue to correctly rename registers, these erroneous states need to be restored. Specifically for each instruction, the recovery of register renaming is equivalent to gradually "rewinding" the state of the renaming mapping table RAT, so that the instructions on the wrong path, such as instructions on the branch prediction failure (mis-prediction) or exception (exception) path, can recover the modification of RAT. In one example, when a branch instruction prediction failure is found, the number of this branch instruction is used to erase all related instructions in the pipeline, and the pipeline is paused at the same time. Starting from the most recent instruction in the renaming mapping table, the corresponding mapping relationship of each instruction before is written to the RAT one by one. In this way, all instructions that change the RAT can be restored in the reverse order. Using an independent renaming sequencing queue for register renaming recovery only needs to consider the number of write ports supported by the RAT, and the register renaming mapping of several instructions can be restored per cycle without any waste, avoiding the method of recovering from the reordering buffer.

[0076] By using the method disclosed in this embodiment, the register recovery of register renaming is not performed through the reorder buffer, thereby saving processor resources. At the same time, the write port of the RAT can be used to the maximum extent for fast recovery. It only takes the clock cycles equal to the ratio of the number of instructions to be restored to the number of write ports of the RAT to restore to the required state, which greatly improves the recovery speed of register renaming.

[0077] The overall process of register renaming provided by the present invention is as follows: Figure 4As shown, the received instructions are first decoded, and the decoded instructions are then registered renamed, and then assigned to different dispatch queues according to the operation type of the instructions, including fixed-point dispatch queues, floating-point dispatch queues, and memory access dispatch queues. Subsequent submissions or recovery when prediction errors or exceptions occur can all be directly determined by using the renaming sequencing queue to perform submission or recovery. Of course, for instructions that do not have a destination register, the submission of the instructions can be submitted directly through the reordering buffer. This process is consistent with the prior art and will not be repeated here. The submission of register renaming is performed through the renaming sequencing queue.

[0078] The register renaming device provided by the present invention is described below. The register renaming device described below and the register renaming method described above can be referred to each other.

[0079] like Figure 5 As shown, the register renaming device 500 provided by the present invention includes the following units:

[0080] The acquisition unit 501 is used to acquire multiple decoded instructions and record the order relationship of the target instruction in the multiple instructions to obtain a rename order queue, where the target instruction is the instruction stored in the destination register;

[0081] An execution unit 502, used to assign each instruction to a dispatch queue corresponding to each instruction for execution;

[0082] The submit unit 503 is used to submit the executed target instruction for register renaming based on the renaming order queue.

[0083] According to a register renaming device provided by the present invention, the execution unit 502 is specifically used for:

[0084] Determine the first type of physical register corresponding to the source register of each instruction according to the renaming mapping table;

[0085] Map the second type of physical register for each target instruction's destination register, and write the mapping relationship into a renaming mapping table;

[0086] The first type physical register number and the second type physical register number corresponding to each instruction are sent to the dispatch queue to obtain the execution result of the instruction.

[0087] According to a register renaming device provided by the present invention, the execution unit 502 is specifically used for:

[0088] Determine the free physical registers according to the physical register table and the free physical register number table;

[0089] Mapping an idle physical register to a destination register of each target instruction, and determining the mapped idle physical register as a second type of physical register;

[0090] The mapping relationship is written into the renaming mapping table, and the status of the second type of physical registers is corrected in the physical register table and the free physical register number table.

[0091] According to a register renaming device provided by the present invention, the submitting unit 503 is specifically used for:

[0092] Determine a submission order of register renaming of the target instructions that have been executed according to the renaming order queue;

[0093] Based on the submission order, the execution result corresponding to each executed target instruction is sequentially written into the second type physical register corresponding to the target instruction.

[0094] According to a register renaming device provided by the present invention, the execution unit 502 is further configured to:

[0095] When a misprediction or exception occurs, register renaming recovery is performed based on the renaming order queue.

[0096] According to a register renaming device provided by the present invention, when a prediction error or an exception occurs, register renaming recovery is performed based on a renaming order queue, and the execution unit 502 is specifically further used for:

[0097] When a prediction error or an exception occurs, determining the order relationship of the target instructions based on the rename order queue;

[0098] According to the sequence relationship, starting from the current target instruction, the execution of the target instructions is restored one by one, and the renaming mapping table is restored accordingly.

[0099] Figure 6 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 6 As shown, the electronic device may include: a processor 610, a communication interface 620, a memory 630 and a communication bus 640, wherein the processor 610, the communication interface 620 and the memory 630 communicate with each other through the communication bus 640. The processor 610 may call the logic instructions in the memory 630 to execute the register renaming method, which includes:

[0100] Obtain multiple decoded instructions, and record the order relationship of the target instruction in the multiple instructions to obtain a rename order queue, where the target instruction is an instruction stored in a destination register;

[0101] Assign each instruction to the dispatch queue corresponding to each instruction for execution;

[0102] Based on the renaming order queue, the target instructions that have been executed are submitted for register renaming.

[0103] In addition, the logic instructions in the above-mentioned memory 630 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0104] On the other hand, the present invention further provides a computer program product, the computer program product comprising a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the register renaming method provided by the above methods, the method comprising:

[0105] Obtain multiple decoded instructions, and record the order relationship of the target instruction in the multiple instructions to obtain a rename order queue, where the target instruction is an instruction stored in a destination register;

[0106] Assign each instruction to the dispatch queue corresponding to each instruction for execution;

[0107] Based on the renaming order queue, the target instructions that have been executed are submitted for register renaming.

[0108] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the register renaming method provided by the above methods is implemented, and the method includes:

[0109] Obtain multiple decoded instructions, and record the order relationship of the target instruction in the multiple instructions to obtain a rename order queue, where the target instruction is an instruction stored in a destination register;

[0110] Assign each instruction to the dispatch queue corresponding to each instruction for execution;

[0111] Based on the renaming order queue, the target instructions that have been executed are submitted for register renaming.

[0112] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, i.e., they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.

[0113] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A register renaming method, characterized in that: The method comprises: Acquire multiple decoded instructions, and record the order relationship of target instructions among the multiple instructions to obtain a rename order queue, wherein the target instruction is an instruction stored in a destination register; Allocate each of the instructions to a dispatch queue corresponding to each of the instructions for execution; Based on the renaming order queue, submitting the target instruction that has been executed for register renaming; Allocating each of the instructions to a dispatch queue corresponding to each of the instructions for execution includes: Determine, according to the renaming mapping table, the first type of physical register corresponding to the source register of each of the instructions; Map the second type of physical register for each destination register of the target instruction, and write the mapping relationship into the renaming mapping table; Sending the first type physical register number and the second type physical register number corresponding to each instruction into the dispatch queue to obtain the execution result of the instruction; The mapping of the second type of physical register to the destination register of each target instruction and writing the mapping relationship into the renaming mapping table includes: Determine the free physical registers according to the physical register table and the free physical register number table; Mapping an idle physical register to a destination register of each target instruction, and determining the mapped idle physical register as the second type of physical register; The mapping relationship is written into the renaming mapping table, and the state of the second type of physical registers is corrected in the physical register table and the free physical register number table.

2. The register renaming method according to claim 1, characterized in that: The submitting of register renaming of the executed target instruction based on the renaming order queue includes: Determine, according to the rename order queue, a submission order of register renaming of the target instruction that has been executed; Based on the submission order, the execution result corresponding to each executed target instruction is sequentially written into the second type physical register corresponding to the target instruction.

3. The register renaming method according to claim 1 or 2, characterized in that: The method further comprises: When a prediction error or an exception occurs, register renaming recovery is performed based on the renaming order queue.

4. The register renaming method according to claim 3, characterized in that: When a prediction error or an exception occurs, register renaming recovery is performed based on the renaming order queue, including: When a prediction error or an exception occurs, determining a sequence relationship of the target instructions based on the rename order queue; According to the sequence relationship, starting from the current target instruction, the execution of the target instructions is restored one by one, and the renaming mapping table is restored accordingly.

5. A register renaming device, characterized in that: include: An acquisition unit, used for acquiring a plurality of decoded instructions, and recording a sequence relationship of a target instruction among the plurality of instructions to obtain a renaming sequence queue, wherein the target instruction is an instruction stored in a destination register; An execution unit, used for allocating each of the instructions to a dispatch queue corresponding to each of the instructions for execution; A commit unit, configured to commit the executed target instruction for register renaming based on the renaming order queue; The execution unit is specifically used for: Determine, according to the renaming mapping table, the first type of physical register corresponding to the source register of each of the instructions; Map the second type of physical register for each destination register of the target instruction, and write the mapping relationship into the renaming mapping table; Sending the first type physical register number and the second type physical register number corresponding to each instruction into the dispatch queue to obtain the execution result of the instruction; The mapping of the second type of physical register to the destination register of each target instruction and writing the mapping relationship into the renaming mapping table includes: Determine the free physical registers according to the physical register table and the free physical register number table; Mapping an idle physical register to a destination register of each target instruction, and determining the mapped idle physical register as the second type of physical register; The mapping relationship is written into the renaming mapping table, and the state of the second type of physical registers is corrected in the physical register table and the free physical register number table.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the register renaming method according to any one of claims 1 to 4 is implemented.

7. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the register renaming method according to any one of claims 1 to 4 is implemented.

8. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the register renaming method according to any one of claims 1 to 4 is implemented.

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