Data writing method and processing system

Abstract

The present application discloses a data writing method for improving the error detection ability and error correction ability of a processing system. The method is applied to a processing system, and the processing system includes a first memory; obtaining first data, where the first data is data to be written into the first memory; determining a first arrangement manner of the memory spaces occupied by data symbols according to the first error distribution region information of at least one memory space among the multiple memory spaces included in the first memory; determining the first data as M data symbols according to the first arrangement manner of the memory spaces occupied by the data symbols, where each of the M data symbols includes multiple data bits, and M is an integer greater than or equal to 1; performing first error correction code encoding on the M data symbols to obtain N first redundant symbols, where each of the N first redundant symbols includes at least one redundant bit, and N is an integer greater than or equal to 1; and writing the M data symbols and the N first redundant symbols into the first memory.

Description

[0001] This application is a divisional application. The application number of the original application is 202210411764.4, and the filing date of the original application is April 19, 2022. The entire content of the original application is incorporated herein by reference. Technical Field

[0002] This application relates to the field of computer technology, and in particular, to a data writing method and a processing system. Background Art

[0003] In the field of computers, the reliability of memory data is crucial to the performance of the entire system. Especially for system core data or important application program data, the reliability of the data directly affects the operation of the entire system. For this reason, data error correction technology has emerged. By using error correction technology, it is determined whether the current data is correct data through a predetermined error correction algorithm, and the reliability of the currently read data is determined.

[0004] Currently, error correction code (ECC) technology is generally used to implement data error correction. With the increase in the specifications of double data rate synchronous dynamic random-access memory 3 (DDR3) particles, DDR4 particles, and DDR5 particles, and the reduction of advanced processes, the voltage of DDR is reduced, and the amount of charge stored in the capacitor of each storage unit decreases, making it prone to transient errors or soft errors. One trend is that the probability of a single transient error causing multiple-bit errors increases. Therefore, how to perform ECC encoding on data to improve the data error correction ability when data errors occur is an urgent problem to be solved currently. Summary of the Invention

[0005] This application provides a data writing method and a processing system, which are used to improve the error detection ability and error correction ability of the processing system and enhance the reliability of the system.

[0006] In a first aspect of this application, a data writing method is provided. The method is applied to a processing system, and the processing system includes a first memory, and the first memory includes multiple memory spaces. The method includes:

[0007] Obtain first data, where the first data is data to be written into a first memory; determine a first arrangement manner of the memory spaces occupied by data symbols according to first error distribution region information of at least one of a plurality of memory spaces; determine the first data as M data symbols according to the first arrangement manner of the memory spaces occupied by the data symbols, where each of the M data symbols includes a plurality of data bits, and M is an integer greater than or equal to 1; perform first ECC encoding on the M data symbols to obtain N first redundant symbols, where each of the N first redundant symbols includes at least one redundant bit, and N is an integer greater than or equal to 1; write the M data symbols into a data memory space in the first memory, and write the N first redundant symbols into a first ECC memory space in the first memory.

[0008] In the above technical solution, the processing system determines the first arrangement manner of the memory spaces occupied by the data symbols according to the first error distribution region information of at least one of the plurality of memory spaces. That is, the processing system designs the arrangement manner of the memory spaces occupied by the data symbols in combination with the region distribution where errors occur in at least one memory space. Then, the processing system determines the first data as M data symbols in combination with the first arrangement manner of the memory spaces occupied by the data symbols, and each of the M data symbols includes data bits. Since the destination addresses of the data bits in the first data are all known, the processing system divides the data bits that can form the shape of the first arrangement manner in the first data into the same data symbol. This is beneficial for the subsequent processing system to perform maximum error detection and maximum error correction on the data during the data reading process. It improves the error detection ability and error correction ability of the processing system and enhances the reliability of the system. Thus, the maximum error detection ability and maximum error correction ability of the first ECC memory space in the first memory are fully utilized, the data error region is maximally covered, and the reliability of the system is enhanced.

[0009] In a possible implementation manner, the first error distribution region information of at least one memory space is used to indicate the specific regions of at least one memory space where the error data bits are located when data errors occur in at least one memory space.

[0010] In this implementation, the first error distribution region information is used to indicate the range of the region where the data bits that are usually in error fall when a data error occurs in at least one memory space. Generally, this range of the region is smaller than the size of the at least one memory space. This is conducive to the processing system determining the arrangement mode of the memory space occupied by the data symbols in combination with this range of the region. Then, the processing system divides the data bits in the first data that can form the shape of the first arrangement mode into the same data symbol in combination with the first arrangement mode. This is conducive to maximizing error detection and maximizing error correction of the data during the subsequent data reading process by the processing system. It improves the error detection ability and error correction ability of the processing system and enhances the reliability of the system. Thus, the maximum error detection ability and maximum error correction ability of the first ECC memory space in the first memory are fully utilized, the data error region is maximally covered, and the reliability of the system is enhanced.

[0011] In another possible implementation, each data symbol occupies 8 bits of memory space, and the first arrangement mode of the memory space occupied by the data symbol includes any one of the following: a four-row two-column arrangement, a two-row four-column arrangement, an eight-row one-column arrangement, a one-row eight-column arrangement; or,

[0012] each data symbol occupies 16 bits of memory space, and the first arrangement mode of the memory space occupied by the data symbol includes any one of the following: a four-row four-column arrangement, an eight-row two-column arrangement, a two-row eight-column arrangement, a sixteen-row one-column arrangement; or,

[0013] each data symbol occupies 32 bits of memory space, and the first arrangement mode of the memory space occupied by the data symbol includes any one of the following: a one-row thirty-two-column arrangement, a thirty-two-row one-column arrangement, a two-row sixteen-column arrangement, a sixteen-row two-column arrangement, a four-row eight-column arrangement, an eight-row four-column arrangement.

[0014] In this implementation, some possible implementations of the number of data bits included in the data symbol are provided, and various possible arrangement modes of the memory space occupied by the data symbol in each implementation are also shown, providing a certain basis for the implementation of the solution. It is conducive to the processing system selecting a suitable arrangement mode in combination with these arrangement modes and the first error distribution region information. It is convenient for maximizing error detection and maximizing error correction of the data during the subsequent data reading process by the processing system. It improves the error detection ability and error correction ability of the processing system and enhances the reliability of the system.

[0015] In another possible implementation, the method further includes:

[0016] obtaining the first error distribution region information of at least one memory space among multiple memory spaces.

[0017] In this implementation, the processing system can obtain the information of the first error distribution area, so as to facilitate the processing system to determine the first arrangement mode of the memory space occupied by the data symbols. For example, the processing system can obtain the information of the first error distribution area through an external interface. Or, the processing system obtains the information of the first error distribution area through pre-configured information.

[0018] In another possible implementation, the method further includes:

[0019] Read all data from the first memory, where all data includes data bits and redundant bits; determine the second arrangement mode of the memory space occupied by the data symbols according to the second error distribution area information of at least one memory space among multiple memory spaces; determine the data bits in all data as P data symbols according to the second arrangement mode of the memory space occupied by the data symbols, where each of the P data symbols includes multiple data bits, and P is an integer greater than or equal to 1; perform first ECC encoding on the P data symbols to obtain Q first redundant symbols, where each of the Q first redundant symbols includes at least one redundant bit, and Q is an integer greater than or equal to 1; write the P data symbols to the data memory space in the first memory, and write the Q first redundant symbols to the first ECC memory space in the first memory.

[0020] In this implementation, if the error distribution area information of the at least one memory space changes to the second error distribution area information, the processing system can read all data from the first memory, and then determine the second arrangement mode of the memory space occupied by the data symbols in combination with the second error distribution area information. Then, the processing system encodes according to the second arrangement mode and the data bits in all data. Thus, the arrangement mode of the memory space occupied by the data symbols is changed. It is convenient for the processing system to perform maximum error detection and maximum error correction on the data during subsequent data reading. The error detection ability and error correction ability of the processing system are improved.

[0021] In another possible implementation, the method further includes:

[0022] Obtain the second error distribution area information of at least one memory space among multiple memory spaces.

[0023] In this implementation, the processing system obtains the second error distribution area information, so as to facilitate the processing system to re-encode and write the data, thereby changing the arrangement mode of the content space occupied by the data symbols. It is convenient for the processing system to perform maximum error detection and maximum error correction on the data during subsequent data reading.

[0024] In another possible implementation, obtaining the second error distribution region information of at least one memory space among multiple memory spaces includes: determining the second error distribution region information of at least one memory space among multiple memory spaces according to the historical data error situation.

[0025] In this implementation, the processing system can determine the second error distribution region information in combination with the historical data error situation. That is, the processing system can dynamically change the error distribution region of at least one memory space according to the actual situation. This makes the solution more applicable to the actual application scenario and improves the practicality of the solution.

[0026] In another possible implementation, the data symbols and the first redundant symbols are Reed-Solomon (RS) code symbols; or; the data symbols and the first redundant symbols are Bose Ray-Chaudhuri Hocquenghem (BCH) code symbols.

[0027] In this implementation, some possible forms of the data symbols and the first redundant symbols are provided, which are specifically determined by the coding algorithm adopted by the processing system, facilitating the implementation of the solution.

[0028] In another possible implementation, performing a first ECC encoding on M data symbols to obtain N first redundant symbols includes: performing a first ECC encoding on M data symbols using a finite field encoding algorithm to obtain N first redundant symbols, and the finite field encoding algorithm includes algorithms such as the RS algorithm or the BCH algorithm.

[0029] In this implementation, the processing system can perform ECC encoding on M data symbols through a finite field encoding algorithm to implement ECC protection for the data. This facilitates subsequent processing systems to perform maximum error correction and maximum error detection on the data. It improves the error detection ability and error correction ability of the processing system.

[0030] In another possible implementation, the first memory is a memory that supports second ECC encoding; the first memory further includes a second ECC memory space; the method includes:

[0031] Performing a second ECC encoding on M data symbols and N first redundant symbols as data to obtain R second redundant symbols, where each of the R second redundant symbols includes at least one redundant bit, and R is an integer greater than or equal to 1;

[0032] Writing the M data symbols to the data memory space, writing the N first redundant symbols to the first ECC memory space, and writing the R second redundant symbols to the second ECC memory space.

[0033] In this implementation, the first memory further includes a second ECC memory space, and the processing system can also perform second ECC encoding on M data symbols and N first redundant symbols, thereby achieving further second-level ECC protection for the M data symbols and N first redundant symbols.

[0034] In another possible implementation, the first memory is an on-die ECC memory.

[0035] In this implementation, the first memory can be an on-die ECC memory. In the subsequent data reading process, the data bits read by the processing system can be obtained through error detection and correction processing of the on-die ECC memory. That is to say, the technical solution of this application can realize the joint error detection and correction of data by the first ECC memory space and the on-die ECC memory space in the first memory, improve the error detection ability and error correction ability of the processing system, and improve the reliability of the system.

[0036] The second aspect of this application provides a processing system, which includes a first memory, and the first memory includes multiple memory spaces; the processing system includes:

[0037] An acquisition unit for acquiring first data, where the first data is data to be written into the first memory;

[0038] A determination unit for determining a first arrangement mode of the memory space occupied by the data symbols according to the first error distribution area information of at least one memory space among the multiple memory spaces; and determining the first data as M data symbols according to the first arrangement mode of the memory space occupied by the data symbols, where each data symbol in the M data symbols includes multiple data bits, and M is an integer greater than or equal to 1;

[0039] An encoding unit for performing first ECC encoding on the M data symbols to obtain N first redundant symbols, where each first redundant symbol in the N first redundant symbols includes at least one redundant bit, and N is an integer greater than or equal to 1;

[0040] A writing unit for writing the M data symbols and the N first redundant symbols into the first memory.

[0041] In a possible implementation, the first error distribution area information of at least one memory space is used to indicate the specific area of the at least one memory space where the error data bits fall when data errors occur in the at least one memory space.

[0042] In another possible implementation, each data symbol occupies 8-bit memory space, and the first arrangement mode of the memory space occupied by the data symbols includes any one of the following: four rows and two columns arrangement, two rows and four columns arrangement, eight rows and one column arrangement, one row and eight columns arrangement; or,

[0043] Each data symbol occupies 16-bit memory space, and the first arrangement mode of the memory space occupied by the data symbol includes any one of the following: four rows and four columns arrangement, eight rows and two columns arrangement, two rows and eight columns arrangement, sixteen rows and one column arrangement; or,

[0044] Each data symbol occupies 32-bit memory space, and the first arrangement mode of the memory space occupied by the data symbol includes any one of the following: one row and thirty-two columns arrangement, thirty-two rows and one column arrangement, two rows and sixteen columns arrangement, sixteen rows and two columns arrangement, four rows and eight columns arrangement, eight rows and four columns arrangement.

[0045] In another possible implementation manner, the obtaining unit is further configured to:

[0046] Obtain the first error distribution area information of at least one memory space among multiple memory spaces.

[0047] In another possible implementation manner, the processing system further includes a reading unit;

[0048] The reading unit is configured to read all data from the first memory, and all data includes data bits and redundant bits;

[0049] The determining unit is further configured to:

[0050] Determine the second arrangement mode of the memory space occupied by the data symbol according to the second error distribution area information of at least one memory space among multiple memory spaces; determine the data bits in all data as P data symbols according to the second arrangement mode of the memory space occupied by the data symbol, each data symbol in the P data symbols includes multiple data bits, and P is an integer greater than or equal to 1;

[0051] The encoding unit is further configured to:

[0052] Perform first ECC encoding on the P data symbols to obtain Q first redundant symbols, each first redundant symbol in the Q first redundant symbols includes at least one redundant bit, and Q is an integer greater than or equal to 1;

[0053] The writing unit is further configured to:

[0054] Write the P data symbols and the Q first redundant symbols into the first memory.

[0055] In another possible implementation manner, the obtaining unit is further configured to:

[0056] Obtain the second error distribution area information of at least one memory space among multiple memory spaces.

[0057] In another possible implementation manner, the obtaining unit is specifically configured to:

[0058] Determine the second error distribution area information of at least one memory space among multiple memory spaces according to the historical data error situation.

[0059] In another possible implementation, the data symbols and the first redundant symbols are RS code symbols; or; the data symbols and the first redundant symbols are BCH code symbols.

[0060] In another possible implementation, the encoding unit is specifically configured to:

[0061] Perform first ECC encoding on M data symbols by using a finite field encoding algorithm to obtain N first redundant symbols, and the finite field encoding algorithm includes algorithms such as RS algorithm or BCH algorithm.

[0062] In another possible implementation, the first memory is a memory that supports second ECC encoding, and the first memory further includes a second ECC memory space; the encoding unit is further configured to:

[0063] Perform second ECC encoding on the M data symbols and the N first redundant symbols as data to obtain R second redundant symbols, and each of the R second redundant symbols includes at least one redundant bit, and R is an integer greater than or equal to 1;

[0064] The writing unit is specifically configured to:

[0065] Write the M data symbols to the data memory space, write the N first redundant symbols to the first ECC memory space, and write the R second redundant symbols to the second ECC memory space.

[0066] In another possible implementation, the first memory is an on die ECC memory.

[0067] A third aspect of the present application provides a processing system, which includes a first memory and a first memory controller, and the first memory includes multiple memory spaces; the first memory controller is configured to execute the following solution:

[0068] Obtain the first data, where the first data is the data to be written into the first memory; determine the first arrangement mode of the memory spaces occupied by the data symbols according to the first error distribution region information of at least one memory space among multiple memory spaces; determine the first data as M data symbols according to the first arrangement mode of the memory spaces occupied by the data symbols, where each of the M data symbols includes multiple data bits, and M is an integer greater than or equal to 1; perform first ECC encoding on the M data symbols to obtain N first redundant symbols, where each of the N first redundant symbols includes at least one redundant bit, and N is an integer greater than or equal to 1; write the M data symbols into the data memory space in the first memory, and write the N first redundant symbols into the first ECC memory space in the first memory.

[0069] In a possible implementation manner, the first error distribution region information of at least one memory space is used to indicate the specific region of the at least one memory space where the erroneous data bits fall when a data error occurs in the at least one memory space.

[0070] In another possible implementation manner, each data symbol occupies 8-bit memory space, and the first arrangement mode of the memory spaces occupied by the data symbols includes any one of the following: four rows and two columns arrangement, two rows and four columns arrangement, eight rows and one column arrangement, one row and eight columns arrangement; or,

[0071] each data symbol occupies 16-bit memory space, and the first arrangement mode of the memory spaces occupied by the data symbols includes any one of the following: four rows and four columns arrangement, eight rows and two columns arrangement, two rows and eight columns arrangement, sixteen rows and one column arrangement; or,

[0072] each data symbol occupies 32-bit memory space, and the first arrangement mode of the memory spaces occupied by the data symbols includes any one of the following: one row and thirty-two columns arrangement, thirty-two rows and one column arrangement, two rows and sixteen columns arrangement, sixteen rows and two columns arrangement, four rows and eight columns arrangement, eight rows and four columns arrangement.

[0073] In another possible implementation manner, the first memory controller is used to:

[0074] Obtain the first error distribution region information of at least one memory space among multiple memory spaces.

[0075] In another possible implementation manner, the first memory controller is further used to:

[0076] Read all the data from the first memory, where all the data includes data bits and redundant bits;

[0077] Determine the second arrangement mode of the memory space occupied by the data symbols according to the second error distribution area information of at least one memory space among multiple memory spaces; determine the data bits in all data as P data symbols according to the second arrangement mode of the memory space occupied by the data symbols, where each data symbol in the P data symbols includes multiple data bits, and P is an integer greater than or equal to 1;

[0078] Perform first ECC encoding on the P data symbols to obtain Q first redundant symbols, where each first redundant symbol in the Q first redundant symbols includes at least one redundant bit, and Q is an integer greater than or equal to 1;

[0079] Write the P data symbols to the data memory space in the first memory, and write the Q first redundant symbols to the first ECC memory space in the first memory.

[0080] In another possible implementation, the first memory controller is further configured to:

[0081] Obtain the second error distribution area information of at least one memory space among multiple memory spaces.

[0082] In another possible implementation, the first memory controller is specifically configured to:

[0083] Determine the second error distribution area information of at least one memory space among multiple memory spaces according to the historical data error situation.

[0084] In another possible implementation, the data symbols and the first redundant symbols are RS code symbols; or; the data symbols and the first redundant symbols are BCH code symbols.

[0085] In another possible implementation, the first memory controller is specifically configured to:

[0086] Perform first ECC encoding on M data symbols using a finite field encoding algorithm to obtain N first redundant symbols, where the finite field encoding algorithm includes RS algorithm or BCH algorithm, etc.

[0087] In another possible implementation, the first memory is a memory supporting second ECC encoding, and the first memory further includes a second ECC memory space;

[0088] The first memory controller is specifically configured to:

[0089] Perform second ECC encoding on the M data symbols and the N first redundant symbols as data to obtain R second redundant symbols, where each second redundant symbol in the R second redundant symbols includes at least one redundant bit, and R is an integer greater than or equal to 1;

[0090] Write M data symbols to the data memory space, write N first redundant symbols to the first ECC memory space, and write R second redundant symbols to the second ECC memory space.

[0091] In another possible implementation, the first memory is a memory that supports second ECC encoding, and the first memory further includes a second ECC memory space; the processing system further includes a second memory controller;

[0092] The second memory controller is configured to perform second ECC encoding on M data symbols and N first redundant symbols as data to obtain R second redundant symbols, where each of the R second redundant symbols includes at least one redundant bit, and R is an integer greater than or equal to 1; write the M data symbols to the data memory space, write the N first redundant symbols to the first ECC memory space, and write the R second redundant symbols to the second ECC memory space.

[0093] In another possible implementation, the first memory is an on die ECC memory.

[0094] A fourth aspect of the present application provides a processing system, which includes a processor, a memory, and an input / output interface, and the processor, the memory, and the input / output interface are connected; the memory is configured to store program codes; the processor calls the program codes in the memory to execute the method as shown in the first aspect.

[0095] A fifth aspect of the embodiments of the present application provides a storage medium, including computer instructions, which are used to execute the program designed by the processing system in the first aspect when running on a computer.

[0096] A sixth aspect of the embodiments of the present application provides a computer program product including instructions, which causes a computer to execute the method described in any optional implementation manner of the first aspect of the present application when running on the computer.

[0097] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0098] As can be seen from the above technical solutions, the present application provides a data writing method, which is applied to a processing system. The processing system includes a first memory, and the first memory includes multiple memory spaces; obtain first data, where the first data is data to be written into the first memory; determine a first arrangement mode of the memory spaces occupied by data symbols according to the first error distribution area information of at least one of the multiple memory spaces; determine the first data as M data symbols according to the first arrangement mode of the memory spaces occupied by data symbols, where each of the M data symbols includes multiple data bits, and M is an integer greater than or equal to 1; then, perform a first ECC encoding on the M data symbols to obtain N first redundant symbols, where each of the N first redundant symbols includes at least one redundant bit, and N is an integer greater than or equal to 1; write the M data symbols into the data memory space in the first memory, and write the N first redundant symbols into the first ECC memory space in the first memory. Thus, it can be seen that the processing system determines the first arrangement mode of the memory spaces occupied by data symbols according to the first error distribution area information of at least one of the multiple memory spaces. That is, the processing system designs the arrangement mode of the memory spaces occupied by data symbols in combination with the area distribution where errors occur in at least one memory space. Then, the processing system combines the first arrangement mode of the memory spaces occupied by data symbols to determine the first data as M data symbols, and each of the M data symbols includes data bits. Since the destination addresses of the data bits in the first data are all known, the processing system combines the first arrangement mode to divide the data bits that can form the shape of the first arrangement mode in the first data into the same data symbol. This is conducive to maximizing error detection and maximizing error correction of data during the subsequent data reading process by the processing system. It improves the reliability of the system. Thus, it can fully utilize the maximum error detection ability and the maximum error correction ability of the ECC memory space in the first memory, maximize the coverage of the data error area, and improve the reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0099] Figure 1 It is a schematic diagram of a memory provided by an embodiment of the present application;

[0100] Figure 2a It is a schematic diagram of a processing system according to an embodiment of the present application;

[0101] Figure 2b It is another schematic diagram of a processing system according to an embodiment of the present application;

[0102] Figure 3 It is a schematic diagram of an embodiment of a data writing method according to an embodiment of the present application;

[0103] Figure 4 It is a schematic diagram of a first memory according to an embodiment of the present application;

[0104] Figure 5a It is a schematic diagram of the area where data errors occur in the memory particles of the embodiment of the present application;

[0105] Figure 5b It is another schematic diagram of the area where data errors occur in the memory particles of the embodiment of the present application;

[0106] Figure 6a It is a schematic diagram of the arrangement of the memory space occupied by the data symbols in the embodiment of the present application;

[0107] Figure 6b It is another schematic diagram of the arrangement of the memory space occupied by the data symbols in the embodiment of the present application;

[0108] Figure 6c It is another schematic diagram of the arrangement of the memory space occupied by the data symbols in the embodiment of the present application;

[0109] Figure 6d It is another schematic diagram of the arrangement of the memory space occupied by the data symbols in the embodiment of the present application;

[0110] Figure 7a It is a schematic diagram of the arrangement of the memory space occupied by the first redundant symbols in the embodiment of the present application;

[0111] Figure 7b It is another schematic diagram of the arrangement of the memory space occupied by the first redundant symbols in the embodiment of the present application;

[0112] Figure 7c It is another schematic diagram of the arrangement of the memory space occupied by the first redundant symbols in the embodiment of the present application;

[0113] Figure 7d It is another schematic diagram of the arrangement of the memory space occupied by the first redundant symbols in the embodiment of the present application;

[0114] Figure 8 It is a schematic diagram of the data symbols with errors in the first memory of the embodiment of the present application;

[0115] Figure 9 It is a schematic diagram of N data symbols and M first redundant symbols in the first memory of the embodiment of the present application;

[0116] Figure 10 It is another schematic diagram of N data symbols and M first redundant symbols in the first memory of the embodiment of the present application;

[0117] Figure 11 It is a schematic diagram of P data symbols and Q first redundant symbols in the first memory of the embodiment of the present application;

[0118] Figure 12 It is a structural schematic diagram of the processing system according to an embodiment of the present application;

[0119] Figure 13 It is another structural schematic diagram of the processing system according to an embodiment of the present application. Detailed implementation manners

[0120] The embodiments of the present application provide a data writing method and a processing system, which are used to improve the error detection ability and error correction ability of the processing system and enhance the reliability of the system.

[0121] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present application.

[0122] The reference to "an embodiment" or "some embodiments" etc. described in the present application means that specific features, structures or characteristics described in connection with the embodiment are included in one or more embodiments of the present application. Thus, the phrases "in an embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. appearing in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "include", "comprise", "have" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0123] In the description of the present application, unless otherwise specified, " / " means "or", for example, A / B may mean A or B. The "and / or" herein is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B may mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, "at least one" means one or more, and "a plurality" means two or more. "At least one (item)" or similar expressions thereof refer to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a, b, or c may mean: a, b, c; a and b; a and c; b and c; or a and b and c. Wherein a, b, c can be single or multiple.

[0124] Next, some technical terms related to the present application will be introduced.

[0125] A cache line refers to the size of a block of data cached by the cache unit in a processor. The size of a cache line varies depending on the processor. In current mainstream computers and servers, the size of a cache line is 64 bytes (Byte). Generally, the internal transfer of cacheable data within the processor also uses the same size of 64 Byte.

[0126] Memory devices are the core components of memory modules and the storage media of memory, which can directly affect the performance of memory. Please refer to Figure 1 , Figure 1 which is a schematic diagram of a memory provided by an embodiment of the present application. As can be seen from Figure 1 Figure, a memory 100 is composed of one or more memory devices. According to the different contents stored in the memory devices, the memory devices are further divided into data devices 102 and ECC devices 101. The specifications of memory devices usually include X4 device, X8 device, and X16 device. X4, X8, and X16 respectively represent that the external data lines of each memory device are 4DQ, 8DQ, and 16DQ. One DQ corresponds to a pin on a physical dual-inline-memory-module (DIMM). DQ can be translated as data strobe signals.

[0127] On-die ECC memory: Supports on-die error correction code, that is, the data bits in the on-die ECC memory can be encoded through the ECC algorithm to obtain on-die ECC bits. The on-die ECC bits are invisible to the central processing unit. Usually, the ECC algorithm used in on-die ECC memory is generally relatively simple.

[0128] The technical solution provided by the present application can be applied to a processing system, which includes a first memory that includes multiple memory spaces. The processing system is a collection composed of multiple hardware and software components. The processing system can be a storage system and can be integrated into a node device or a server. Specifically, the present application does not make any limitations.

[0129] Next, in combination with Figure 2a and Figure 2b two possible schematic diagrams of the processing system provided by the present application will be introduced.

[0130] Figure 2a is a schematic diagram of the processing system according to an embodiment of the present application. Please refer to Figure 2a, the processing system includes a first memory controller 201 and a first memory 202. The first memory controller 201 is connected to the first memory 202. The first memory controller 201 has the function of first ECC encoding. For the relevant description of first ECC decoding, please refer to the detailed introduction in the following embodiments.

[0131] Optionally, the first memory controller 201 also has the function of second ECC encoding, which is used to perform second ECC encoding on the redundant bits obtained by first ECC encoding and the data bits to be written into the first memory 202. For the relevant description of second ECC decoding, please refer to the detailed introduction in the following embodiments. That is, in Figure 2a the architecture shown, the first memory controller has both the first ECC encoding function and the second ECC encoding function. Thus, multi-level ECC protection for data can be achieved.

[0132] Optionally, the first memory controller 201 can be integrated in a central processing unit (CPU). The data writing method provided in this application can be executed by the first memory controller 201.

[0133] Figure 2b This is another schematic diagram of the processing system according to the embodiments of this application. Please refer to Figure 2b , the processing system includes a first memory controller 203, a second memory controller 204, and a first memory 205. The first memory controller 203 is connected to one side of the second memory controller 204, and the other side of the second memory controller 204 is connected to the first memory 205.

[0134] The first memory controller 203 has the function of first ECC encoding. For the relevant description of first ECC decoding, please refer to the detailed introduction in the following embodiments. The second memory controller 204 has the function of second ECC encoding, which is used to perform second ECC encoding on the redundant bits obtained by first ECC encoding and the data bits to be written into the first memory 205. For the relevant description of second ECC decoding, please refer to the detailed introduction in the following embodiments. The data writing method of this application can be executed by the first memory controller 203 and the second memory controller 204.

[0135] The following introduces some possible deployment methods of the first memory controller 203 and the second memory controller 204.

[0136] 1. The first memory controller 203 can be integrated in the central processor, and the second memory controller 204 can be integrated in the first memory 205.

[0137] 2. Both the first memory controller 203 and the second memory controller 204 are integrated in the central processor.

[0138] 3. Both the first memory controller 203 and the second memory controller 204 are integrated in the first memory 205.

[0139] The above Figure 2a and Figure 2b The processing system shown above is only for introducing the system architecture to which the embodiments of the present application are applied, and does not limit the system architecture to which the embodiments of the present application are applied. For example, the data writing method provided by the present application is equally applicable to a chip system, and the data writing process is carried out in the chip system.

[0140] It should be noted that the above Figure 2a and Figure 2b The processing system shown above is only an example. In actual applications, the processing system may also include more memory controllers and more memories, and the present application does not make specific limitations in this regard.

[0141] Currently, in computer systems, the demand for high reliability is becoming increasingly obvious. One technical trend is that media manufacturers support on-die ECC (error-correcting code) technology. However, on-die ECC memory has a significant problem. Due to cost and resource limitations, the ECC algorithms used in on-die ECC memory are generally relatively simple. For example, on-die ECC memory usually uses Hamming code to perform ECC encoding on 128 bits, and can correct one incorrect bit and detect two incorrect bits.

[0142] As the specifications of DDR3, DDR4, DDR5, and DDR6 memory chips increase, the advanced manufacturing process decreases. The voltage of DDR decreases, and the amount of charge that each storage unit can hold decreases, making it prone to transient errors or soft errors. One trend is that the probability of a single transient error causing multiple-bit errors increases. Therefore, how the memory controller performs ECC encoding on data to improve the data error correction ability when data errors occur is an urgent problem to be solved currently.

[0143] It should be noted that the above uses on-die ECC memory as an example to introduce the problems to be solved by the present application. In actual applications, the technical solutions of the present application can also be applied to the data writing process of other types of memory, and the present application does not make specific limitations in this regard. For example, the technical solutions of the present application can also be applied to ordinary memory (i.e., memory that supports first-level ECC encoding, and the data is protected by first-level ECC) or memory that supports multi-level ECC encoding (for example, memory that supports first-level ECC encoding and second-level ECC encoding, and the data is protected by first-level ECC and second-level ECC). For the relevant introduction of the first-level ECC encoding and the second-level ECC encoding, please refer to the relevant content later.

[0144] For ease of understanding, the technical solution of the present application will be introduced below in conjunction with specific embodiments.

[0145] Figure 3 The figure is a schematic diagram of an embodiment of the data writing method according to an embodiment of the present application. Please refer to Figure 3 , the method includes:

[0146] 301. Obtain first data, where the first data is the data to be written into the first memory.

[0147] The data writing method provided by the present application is applied to a processing system, and the processing system includes a first memory, and the first memory includes multiple memory spaces.

[0148] Optionally, among the multiple memory spaces of the first memory, the size of each memory space is the size of one memory die, or a memory space of other sizes. Specifically, the present application does not make a limitation.

[0149] Optionally, the sizes of different memory spaces in the first memory may be the same or different. Hereinafter, the technical solution of the present application will be introduced by taking the size of each memory space in the first memory as the size of one memory die as an example.

[0150] Optionally, each memory space in the first memory may be used as a data memory space and / or an ECC memory space. Specifically, the present application does not make a limitation.

[0151] For example, as Figure 4 shown, the first memory includes data die 1 to data die 4 and ECC die. That is, it can be understood that the first memory includes five memory spaces, and the size of each memory space is the size of one memory die.

[0152] For example, the processing system caches the first data, and the size of the first data is 64 bytes (Byte), that is, 512 bits.

[0153] It should be noted that, optionally, the type of the first memory is DDR3, DDR4, DDR5, DDR6, high bandwidth memory (HBM), low power double data rate synchronous dynamic random access memory (LPDDR), or a memory that does not conform to the joint electron device engineering council (JEDEC) standard, etc. Specifically, the present application does not make a limitation.

[0154] It should be noted that the first memory can be a common memory (i.e., a memory that supports first-level ECC encoding), or a memory that supports multi-level ECC encoding (for example, the first memory is a memory that supports first ECC encoding and second ECC encoding), or other types of memory, and the specific type is not limited in this application. For the first ECC encoding and the second ECC encoding, please refer to the relevant introduction later.

[0155] For example, the first memory is an on-die ECC memory. For example, as Figure 4 shown, each memory die in the first memory is an on-die ECC memory. The ECC die in the first memory is used to perform first-level ECC protection on data, while the on-die ECC bits in each memory die can implement second-level ECC protection on data.

[0156] 302. Determine the first arrangement mode of the memory spaces occupied by data symbols according to the first error distribution area information of at least one memory space among multiple memory spaces.

[0157] Among them, the first error distribution area information of at least one memory space among the multiple memory spaces is used to indicate the specific area in the at least one memory space where the error data bits fall when a data error occurs in the at least one memory space. The area size indicated by the first error distribution area information is smaller than the size of the at least one memory space.

[0158] It should be noted that optionally, the first memory includes multiple memory spaces, and the areas where data errors occur in different memory spaces among the multiple memory spaces can be the same or different, and the specific situation is not limited in this application.

[0159] For example, if the areas where data errors occur in each memory space among the multiple memory spaces are the same, then the processing system can obtain the first error distribution area information of any one of the multiple memory spaces. Then, the processing system can determine the first arrangement mode of the memory spaces occupied by data symbols in combination with the first error distribution area information of any one of the memory spaces.

[0160] For example, the multiple memory spaces include a data memory space and a first ECC memory space. The area where a data error occurs in the data memory space is different from the area where a data error occurs in the first ECC memory space. The areas where data errors occur in different data memory spaces are the same. Then the processing system obtains the first error distribution area information of any one data memory in the first memory. Then, the processing system can determine the first arrangement mode of the memory spaces occupied by data symbols in combination with the first error distribution area information of any one of the data memories.

[0161] For example, the multiple memory spaces include a data memory space and a first ECC memory space. The regions where data errors occur in different data memory spaces are different. Then, the processing system obtains the first error distribution region information corresponding to one or more data memory spaces included in the multiple memory spaces. Then, the processing system can determine the first arrangement mode of the memory spaces occupied by data symbols in combination with the first error distribution region information corresponding to one or more data memory spaces included in the multiple memory spaces.

[0162] The following uses the example where the regions where data errors occur in each of the multiple memory spaces are the same to introduce the technical solution of this application.

[0163] For example, as Figure 4 shown, the first memory includes data grains 1 to 4 and ECC grains. That is, it can be understood that the first memory includes five memory spaces, and each memory space is the size of one memory grain. For example, when a data error occurs in a memory grain, the specific region in the memory space where the erroneous data bit falls is as Figure 5a or as Figure 5b shown as the region where the data error occurs. That is, the 1 / 2 memory space starting from the left of the memory grain or the 1 / 2 memory space starting from the top of the memory grain.

[0164] It should be noted that Figure 5a and Figure 5b are only examples. In actual applications, when a data error occurs in a memory grain, the specific region in the memory grain where the erroneous data bit falls includes: the 1 / 4 or 1 / 8 memory space starting from the left of the memory grain; or, when a data error occurs in a memory grain, the specific region in the memory grain where the erroneous data bit falls includes: the 1 / 4 memory space starting from the top of the memory grain. The specific application of this application is not limited.

[0165] Specifically, the processing system determines the first arrangement mode of the memory spaces occupied by data symbols according to the first error distribution region information of at least one memory space in the multiple memory spaces.

[0166] The first arrangement mode of the memory spaces occupied by data symbols matches the arrangement mode of the regions indicated by the first error distribution region information. Or rather, the first arrangement mode of the memory spaces occupied by data symbols is strongly associated with the arrangement mode of the regions indicated by the first error distribution region information.

[0167] Optionally, the symbol can be an RS code symbol or a BCH code symbol. Specifically, it should be determined in combination with the encoding algorithm adopted by the processing system in the subsequent step 304. For example, if the processing system uses the RS algorithm to perform the first ECC encoding on the first data, the symbol in this article is an RS code symbol. For example, if the processing system uses the BCH algorithm to perform the first ECC encoding on the first data, the symbol in this article is a BCH code symbol. BCH is an abbreviation taken from Bose, Ray-Chaudhuri, and Hocquenghem.

[0168] Optionally, each data symbol occupies 8 bits of memory space, and the first arrangement method of the memory space occupied by the data symbol includes any one of the following: four rows and two columns arrangement, two rows and four columns arrangement, eight rows and one column arrangement, one row and eight columns arrangement.

[0169] Optionally, each data symbol occupies 16 bits of memory space, and the first arrangement method of the memory space occupied by the data symbol includes any one of the following: four rows and four columns arrangement, eight rows and two columns arrangement, two rows and eight columns arrangement, sixteen rows and one column arrangement.

[0170] Optionally, each data symbol occupies 32 bits of memory space, and the first arrangement method of the memory space occupied by the data symbol includes any one of the following: one row and thirty-two columns arrangement, thirty-two rows and one column arrangement, two rows and sixteen columns arrangement, sixteen rows and two columns arrangement, four rows and eight columns arrangement, eight rows and four columns arrangement.

[0171] The following takes the case where each data symbol occupies 16 bits of memory space as an example to introduce some possible arrangement methods.

[0172] For example, as Figure 6a shown, each data symbol occupies 16 bits of memory space, and the specific arrangement method is four rows and four columns arrangement.

[0173] For example, as Figure 6b shown, each data symbol occupies 16 bits of memory space, and the specific arrangement method is eight rows and two columns arrangement.

[0174] For example, as Figure 6c shown, each data symbol occupies 16 bits of memory space, and the specific arrangement method is two rows and eight columns arrangement.

[0175] For example, as Figure 6d shown, each data symbol occupies 16 bits of memory space, and the specific arrangement method is sixteen rows and one column arrangement.

[0176] The following introduces some examples of the processing system determining the first arrangement method of the memory space occupied by the data symbol in combination with the first error distribution area information of at least one of the multiple memory spaces.

[0177] For example, each data symbol occupies 16 bits of memory space. In the case of the arrangement of the area where data errors occur as shown Figure 5a below, the processing system can set the first arrangement of the memory space occupied by the data symbol to be as shown Figure 6a or Figure 6d below.

[0178] Preferably, the processing system can separately determine that the arrangement shown Figure 6a below is a four-row and four-column arrangement. These four rows are four consecutive rows. If multiple data bit errors occur and are distributed in different memory grains, it will cause the processing system to be unable to correct the data bits to the maximum extent. For specific examples, please refer to the relevant introduction later. Therefore, preferably, based on the scenario shown Figure 5a below, the processing system can determine that the first arrangement is the arrangement shown Figure 6d below.

[0179] For example, each data symbol occupies 16 bits of memory space. In the case of the arrangement of the area where data errors occur as shown Figure 5b below, the processing system can set the first arrangement of the memory space occupied by the data symbol to be as shown Figure 6b or Figure 6c below.

[0180] Optionally, Figure 3 the embodiment shown below further includes step 302a. Step 302a can be executed before step 302.

[0181] 302a. Obtain the first error distribution area information of at least one memory space among multiple memory spaces.

[0182] Specifically, the processing system can obtain the first error distribution area information of at least one memory space among multiple memory spaces.

[0183] Optionally, the processing system can receive the first error distribution area information of at least one memory space among the multiple memory spaces provided by the manufacturer through an external interface. Or, the processing system can determine the first error distribution area information of at least one memory space among the multiple memory spaces from the user manual. Specifically, this application does not make any limitations.

[0184] In a possible implementation manner, the first memory is a general memory, and the first error distribution area information may include the specific area of the at least one memory space where the error data bits fall when data errors occur in the at least one memory space.

[0185] In another possible implementation, the first memory is a memory that supports second ECC (such as on die ECC), and the first memory further includes a second ECC memory space. The first error distribution area information includes an error area detected in the second ECC memory space or an additional mis-correction area generated by error correction in the second ECC memory space.

[0186] In this implementation, optionally, the first error distribution area information may be determined by the manufacturer in combination with the encoding algorithm and decoding algorithm adopted for the second ECC memory space (such as the on die ECC memory space).

[0187] For example, as Figure 4 shown, the first memory is an on die ECC memory. The first memory includes data grains 1 to 4 and ECC grains. Each memory grain is an on die ECC memory. Each on die ECC memory encodes the data to be stored in the on die ECC memory using the Hamming code algorithm to obtain the ECC bits in the on die ECC memory. Generally, the error distribution area in a memory grain may be: the memory space starting from the left half of the memory grain, or the memory space starting from the right half, or the memory space starting from the left quarter of the memory grain, or the memory space starting from the right quarter, or the memory space starting from the upper half, or the memory space starting from the lower half, or the memory space of odd columns, or the memory space of even columns.

[0188] 303. Determine the first data as M data symbols according to the first arrangement mode of the memory space occupied by the data symbols.

[0189] Among them, each of the M data symbols includes multiple data bits, and M is an integer greater than or equal to 1.

[0190] For example, if the first data includes 512 bits and a data symbol includes 16 bits, then the processing system can determine the 512 bits as 32 data symbols according to the first arrangement mode of the memory space occupied by the data symbols.

[0191] For example, the first arrangement mode of the memory space occupied by the data symbols is the arrangement mode as Figure 6d shown, that is, arranged in 16 rows and 1 column. The processing system can determine the 512 bits as 32 data symbols in combination with the destination memory address of the data bits in the first data and the first arrangement mode. For example, as Figure 9As shown, the processing system divides the data bits of the first data to be stored in the memory space of the first column of data granule 1 into the data bits included in data symbol 1. The processing system divides the data bits of the first data to be stored in the memory space of the second column of data granule 1 into the data bits included in data symbol 2. And so on, the processing system divides the data bits of the first data to be stored in the memory space of the last column of data granule 4 into the data bits included in data symbol 32. It can be seen that the arrangement of each data symbol is the first arrangement method.

[0192] For example, the first arrangement method of the memory space occupied by the data symbol is the arrangement method as Figure 6a shown, that is, arranged in four rows and four columns. The processing system can determine the 512 bits as 32 data symbols in combination with the destination memory address of the data bits in the first data and the first arrangement method. For example, as Figure 10 shown, the processing system divides the 512 bits into data symbols 1 to data symbol 32 as Figure 10 shown according to the memory space where the 512-bit data is to be stored. It can be seen that the arrangement of each data symbol is the first arrangement method.

[0193] 304. Perform the first ECC encoding on M data symbols to obtain N first redundant symbols.

[0194] Among them, each of the N first redundant symbols includes at least one redundant bit.

[0195] The above step 304 specifically includes: The processing system can use a finite field encoding algorithm to perform ECC encoding on M data symbols to obtain N first redundant symbols. For example, the finite field includes a Galois field (GF(p)). That is to say, the first ECC encoding can include the processing system using a finite field encoding algorithm to perform ECC encoding on M data symbols.

[0196] For example, the finite field encoding algorithm includes the RS algorithm, or the BCH algorithm, etc., and can also be other finite field encoding algorithms. Specifically, the present application does not make a limitation.

[0197] Among the N first redundant symbols, there are error correction symbols. One error correction symbol can be used to correct one data symbol. Optionally, the first redundant symbol includes an error detection symbol.

[0198] For example, the first data includes 512 bits. The processing system forms a cacheline with 16 bursts of data. Each memory cell of the first memory is an X4 memory cell. Therefore, it can be known that the processing system can determine that the length of each codeword is 4 Bits * 16 Bursts * 10 cells = 640 bits. From this, it can be known that the N first redundant symbols include 4 Bits * 16 Bursts * 2 cells = 128 redundant bits. Optionally, the arrangement of the memory space occupied by the first redundant symbols may or may not be the same as the arrangement of the memory space occupied by the data symbols. Specifically, this application does not make any limitations.

[0199] It should be noted that, optionally, the first ECC encoding may also be referred to as the first-level ECC encoding.

[0200] Optionally, the processing system determines the arrangement of the memory space occupied by the first redundant symbols according to the first error distribution region information of the first ECC memory space in the first memory. The specific determination process is similar to the aforementioned process by which the processing system determines the first arrangement.

[0201] Optionally, the arrangement of the memory space occupied by the first redundant symbols may or may not be the same as the arrangement of the memory space occupied by the data symbols. Specifically, this application does not make any limitations. For example, if the error distribution region of the first ECC memory space in the first memory is the same as the error distribution region of the data memory space in the first memory, the arrangement of the memory space occupied by the first redundant symbols may be the aforementioned first arrangement. Hereinafter, the technical solution of this application will be introduced by taking the arrangement of the memory space occupied by the first redundant symbols being the same as the arrangement of the memory space occupied by the data symbols as an example.

[0202] Next, in combination with Figures 7a to 7d the arrangement of these N first redundant symbols will be introduced. It should be noted that the following Figures 7a to 7d is introduced by taking the size ratio of the error detection space to the error correction space in the first ECC memory space of the first memory as 1:1 as an example. That is, the ratio of the error correction symbols to the error detection symbols is 1:1. The arrangement of the memory space occupied by the error detection symbols may be the aforementioned first arrangement. The error detection symbols will not be introduced in detail hereinafter.

[0203] For example, as Figure 7a shown, the N first redundant symbols include four error correction symbols, which are respectively represented as: the first redundant symbol 1, the first redundant symbol 2, the first redundant symbol 3, and the first redundant symbol 4. The arrangement of the memory space occupied by each of these error correction symbols is the arrangement as Figure 6a shown, that is, arranged in four rows and four columns.

[0204] For example, as Figure 7bAs shown, the N first redundant symbols include four error correction symbols, respectively represented as: the first redundant symbol 1, the first redundant symbol 2, the first redundant symbol 3, and the first redundant symbol 4. The arrangement of the memory space occupied by each of these error correction symbols is as Figure 6b shown, that is, an eight-row and two-column arrangement.

[0205] For example, as Figure 7c shown, the N first redundant symbols include four error correction symbols, respectively represented as: the first redundant symbol 1, the first redundant symbol 2, the first redundant symbol 3, and the first redundant symbol 4. The arrangement of the memory space occupied by each of these error correction symbols is as Figure 6c shown, that is, a two-row and eight-column arrangement.

[0206] For example, as Figure 7d shown, the N first redundant symbols include four error correction symbols, respectively represented as: the first redundant symbol 1, the first redundant symbol 2, the first redundant symbol 3, and the first redundant symbol 4. The arrangement of the memory space occupied by each of these error correction symbols is as Figure 6d shown, that is, a sixteen-row and one-column arrangement.

[0207] It should be noted that the codeword lengths adopted by the processing system in the above examples are all 640 bits. In practical applications, the codeword length can also be other lengths. For example, when the codeword length is 320 bits, the processing system can use multiple codewords for encoding, and the specific details of this application are not limited.

[0208] From the perspective of codeword design, the more rows there are, the more burst numbers of the first memory read are required, and the longer the delay is. For the subsequent decoding and error correction time windows, they are larger. Therefore, the processing system can also use smaller codewords for ECC encoding to reduce the decoding and error correction delays.

[0209] It should be noted that the first memory includes multiple memory chips, and each memory chip can be regarded as a memory storage medium with built-in support for second ECC encoding (such as on die ECC). The above technical solution of this application is introduced by taking an example where the length of a coding codeword in the second ECC memory space of each memory chip includes 128 data bits and 8 redundant bits (which can also be called second ECC bits). In practical applications, the length of the coding codeword in the second ECC memory space of each memory chip can be larger or smaller. For example, the coding codeword length in the second ECC memory space of each memory chip can include 256 data bits and 16 redundant bits. Or, the coding codeword length in the second ECC memory space of each memory chip can include 512 data bits and 32 redundant bits. Specifically, this application does not make any limitations. Optionally, the second ECC encoding can also be called the second-level ECC encoding.

[0210] 305. Write M data symbols to the data memory space of the first memory, and write N first redundant symbols to the first ECC memory space of the first memory.

[0211] Specifically, the processing system writes M data symbols to the data memory space of the first memory, and writes N first redundant symbols to the first ECC memory space of the first memory.

[0212] For example, as Figure 2a shown, the first memory controller 201 writes M data symbols to the data memory space of the first memory, and writes N first redundant symbols to the first ECC memory space of the first memory.

[0213] For example, as Figure 9 shown, the processing system writes the data bits included in M data symbols to the data memory space of the first memory, and writes the redundant bits included in N first redundant symbols to the first ECC memory space of the first memory. The arrangement of the memory space occupied by specific data symbols or first redundant symbols is as Figure 9 shown, that is, the arrangement of the memory space occupied by data symbols or first redundant symbols is arranged in 16 rows and 1 column.

[0214] Optionally, if the first memory is a memory that supports second ECC encoding (such as on die ECC), the above Figure 3 shown embodiment further includes step 305a. Step 305a can be executed before step 305.

[0215] 305a. Perform second ECC encoding on M data symbols and N first redundant symbols as data to obtain R second redundant symbols.

[0216] Each of the R second redundant symbols includes at least one redundant bit, where R is an integer greater than or equal to 1.

[0217] Optionally, step 305a specifically includes: The processing system performs second ECC encoding on the M data symbols and the N first redundant symbols as data to obtain R second redundant symbols.

[0218] Optionally, the second ECC encoding may include the processing system performing Hamming code encoding on the M data symbols and the N first redundant symbols as data to obtain R second redundant symbols.

[0219] For example, as Figure 2a shown, the first memory controller 201 performs first ECC encoding on the M data symbols to obtain N first redundant symbols. Then, the first memory controller 201 performs second ECC encoding on the M data symbols and the N first redundant symbols as data to obtain R second redundant symbols.

[0220] For example, as Figure 2b shown, the first memory controller 203 performs first ECC encoding on the M data symbols to obtain N first redundant symbols. Then, the first memory controller 203 transmits the M data symbols and the N first redundant symbols to the second memory controller 204 through the memory interface. The second memory controller 204 performs second ECC encoding on the M data symbols and the N first redundant symbols as data to obtain R second redundant symbols.

[0221] Based on the above step 305a, optionally, step 305 specifically includes:

[0222] Writing the M data symbols to the data memory space of the first memory, writing the N first redundant symbols to the first ECC memory space of the first memory, and writing the R second redundant symbols to the second ECC memory space of the first memory.

[0223] For example, in combination with Figure 2b and Figure 9 shown, the second memory controller 204 performs second ECC encoding on data symbols 1 to data symbol 8 to be stored in data particle 1 to obtain the second redundant symbols of data particle 1. Then, the second memory controller 204 writes data symbols 1 to data symbol 8 and the second redundant symbols of data particle 1 to the corresponding spatial positions of data particle 1 respectively. The second memory controller 204 performs second ECC encoding on data symbols 9 to data symbol 16 to be stored in data particle 2 to obtain the second redundant symbols of data particle 2. Then, the second memory controller 204 writes data symbols 9 to data symbol 16 and the second redundant symbols of data particle 2 to data particle 2.

[0224] The second memory controller 204 performs second ECC encoding on data symbols 17 to 24 to be stored in data granule 3, obtaining second redundant symbols of data granule 3. Then, the second memory controller 204 writes data symbols 17 to 24 and the second redundant symbols of data granule 3 into data granule 3. The second memory controller 204 performs second ECC encoding on data symbols 25 to 32 to be stored in data granule 4, obtaining second redundant symbols of data granule 4. Then, the second memory controller 204 writes data symbols 25 to 32 and the second redundant symbols of data granule 4 into data granule 4. The second memory controller 204 performs second ECC encoding on N first redundant symbols (including redundant symbols for error detection space and redundant symbols 1 to 4) to be stored in the ECC granule, obtaining second redundant symbols of the ECC granule. Then, the second memory controller 204 writes the N first redundant symbols and the second redundant symbols of the ECC granule into the ECC granule.

[0225] It should be noted that the above Figure 2b is implemented by one second memory controller 204 to write data into each memory granule as shown Figure 9 In practical applications, each memory granule can be connected to a second memory controller, and different memory granules are connected to different second memory controllers. The second memory controller connected to each memory granule performs second ECC encoding on the data symbols or first redundant symbols to be written into the memory granule, obtaining second redundant symbols of the memory granule. Then, the second memory controller writes the data symbols or first redundant symbols to be written into the memory granule and the second redundant symbols of the memory granule to the corresponding spatial positions of the memory granule. The specific details of this application are not limited.

[0226] Next, some scenarios applicable to the technical solution of this application will be introduced using the processing system shown above Figure 2b Scenario 1: During the process of the processing system reading M data symbols and N first redundant symbols from the first memory, if the second memory controller 204 performs read error detection and no error is detected, the second memory controller 204 discards the second redundant symbols. Then, the second memory controller 204 transmits the M data symbols and N first redundant symbols back to the first memory controller 203 through the first memory channel.

[0227]

[0228] ​Scenario 2: During the process of the processing system reading M data symbols and N first redundant symbols from the first memory, if the second memory controller 204 performs read error detection and detects an error, and the range of the faulty data is within the error correction capability of the second memory controller 204, the second memory controller 204 corrects the error using the second redundant symbols. Then, the second memory controller 204 transmits the corrected M data symbols and N first redundant symbols back to the buffer of the first memory controller 203 through the first memory channel.

[0229] Scenario 3: During the process of the processing system reading M data symbols and N first redundant symbols from the first memory, if the second memory controller 204 performs read error detection and detects an error, and the range of the faulty data exceeds the error correction capability of the second memory controller 204, the second memory controller 204 discards the second redundant symbols (i.e., does not perform second ECC error correction). The second memory controller 204 directly transmits the M data symbols and N first redundant symbols back to the first memory controller 203 through the first memory channel. The second memory controller 204 sends an error notification to the first memory controller 203 to indicate that the second memory controller 204 detected errors in the M data symbols but failed to correct them.

[0230] Scenario 4: During the process of the processing system reading M data symbols and N first redundant symbols from the first memory, if the second memory controller 204 performs read error detection and detects an error, and the range of the faulty data exceeds the error detection capability of the second memory controller 204, the second memory controller 204 may mistakenly think that it can correct the error and attempt to correct it, which may result in the correction of the data, that is, the faulty area is further enlarged. However, the second memory controller itself is unaware of this. Then, the second memory controller 204 transmits the M data symbols and N first redundant symbols after second ECC correction back to the first memory controller 203 through the first memory channel. This scenario is the second ECC (such as on die ECC) mis-correction scenario.

[0231] The technical solution of the present application can be applied to the above-mentioned scenarios 1 to 4, especially the error correction scenario of scenario 4. In scenarios 2 and 4, when the second memory controller 204 corrects M data symbols and N first redundant symbols by using R second redundant symbols, a specially designed generation matrix of the second ECC code is adopted, and as a result, the range of data changes in the second ECC error correction process is limited to a relatively small range. For example, it is the leftmost 1 / 4 memory space of the memory space occupied by "M data symbols and N first redundant symbols". Therefore, based on the above information of the first error distribution area indicating the error area detected by the second ECC memory space or the additional error correction area generated by error correction in the second ECC memory space, etc., the processing system can set an appropriate arrangement mode of the memory space occupied by symbols during the data writing process, which is convenient for the subsequent processing system to maximize error detection and error correction of data in the error correction scenario of scenario 4.

[0232] During the data application process, the processing system can read M data symbols and N first redundant symbols from the first memory. If the first memory is a memory that supports the second ECC encoding (such as on die ECC), both M data symbols and N first redundant symbols can be obtained through error detection and error correction processing in the second ECC memory space. Specifically, as Figure 9 shown, M data symbols include data symbol 1 to data symbol 32. N first redundant symbols include first redundant symbol 1 to second redundant symbol (which can also be called error correction symbol 1 to error correction symbol 4) and error detection symbols in the error detection space. The error detection space includes four error detection symbols. Therefore, the processing system can detect at most four incorrect data symbols. Specifically, the processing system detects the data symbols in the third data through the error detection symbols in the error detection space to determine that there are data bit errors in data symbol 1, data symbol 2, data symbol 21, and data symbol 23. Specifically, the processing system can determine how many data bit errors may exist in data symbol 1, data symbol 2, data symbol 21, and data symbol 23. Since one error correction symbol can correct one data symbol, the processing system can use first redundant symbol 1 to correct data symbol 1, first redundant symbol 2 to correct data symbol 2, first redundant symbol 3 to correct data symbol 21, and first redundant symbol 4 to correct data symbol 23. It should be noted that any error correction symbol can correct any data symbol. For example, here the processing system can also use first redundant symbol 2 to correct data symbol 1. Specifically, the present application does not make any limitations.

[0233] It should be noted that, optionally, after the second ECC memory space performs error detection and correction on the data, it can notify the first memory controller of the error detection result and error correction situation of the second ECC memory space through the Alert_N Pin. Thus, the first memory controller can determine the error detection result and error correction situation of the second ECC memory space. This is beneficial to further enhancing the error detection ability and error correction ability of the first memory controller.

[0234] It can be seen from this that during the data writing process, the processing system determines the first arrangement mode of the memory space occupied by the data symbols in combination with the first error distribution area information of at least one memory space among the multiple memory spaces. The first arrangement mode matches or is strongly associated with the arrangement mode of the specific area indicated by the first error distribution area information. Thus, the error detection ability of the error detection space in the first ECC memory space in the first memory and the repair ability of the error correction space in the first ECC memory space are fully utilized, maximizing the coverage of the error area, thereby obtaining the maximum error detection ability and the maximum error correction ability, and improving the reliability. In addition, the first memory can be a memory storage medium that supports second-level ECC, and the M data bits can be obtained through error detection and correction by the second ECC memory space. That is to say, the technical solution of the present application can implement the joint error detection and correction of data by the first-level ECC memory and the second-level ECC, thereby improving the reliability of the system.

[0235] It should be noted that the first memory can be a memory that supports second ECC encoding (such as on die ECC), and the M data bits can be obtained through error detection and correction processing by the second ECC memory space. That is to say, in the technical solution of the present application, the first-level ECC memory and the second-level ECC jointly perform error detection and correction on the data. The first-level ECC protection and the second-level ECC protection of the data are realized. The combined error detection ability, error correction ability, and fault tolerance ability are more powerful. Of course, the technical solution of the present application is introduced here by taking two-layer ECC protection as an example. In practical applications, the processing system can also perform more-layer ECC protection on the data. For example, the processing system can also implement third-layer ECC protection on the data through other ECC memories, and the specific details of the present application are not limited.

[0236] For example, if the processing system determines the first arrangement mode of the memory space occupied by the data symbols as Figure 10The four-row and four-column arrangement shown. Since the error detection space includes four error detection symbols, the processing system can only detect that four data symbols are in error through the error detection symbols in the error detection space. For example, the processing system detects that data symbols 1 to 4 are in error, but cannot detect that data symbols 21 to 24 are also in error. That is, actually eight data symbols are in error, but the processing system can only detect that four data symbols are in error. The specific processing system can determine how many data bit errors exist in each of the data symbols from data symbol 1 to data symbol 4. Since one error correction symbol can correct one data symbol, the processing system can use the first redundant symbol 1 to correct data symbol 1, the first redundant symbol 2 to correct data symbol 2, the first redundant symbol 3 to correct data symbol 3, and the first redundant symbol 4 to correct data symbol 4. It can be seen therefrom that the actual error correction internal space of the processing system is only 32 bits, that is, the data bits in the first and second columns of data granule 1. And the data bits in the fifth and seventh columns of data granule 3 cannot be corrected. Therefore, the processing system uses Figure 10 The arrangement of the memory space occupied by the symbols shown cannot achieve maximum error detection and maximum error correction. In the technical solution of the present application, the processing system determines the first arrangement mode of the memory space occupied by the data symbol in combination with the first error distribution area information of at least one of the multiple memory spaces. The first arrangement mode matches or is strongly associated with the arrangement mode of the specific area indicated by the first error distribution area information. For example, as Figure 8 The data error scenario shown. That is Figure 10 For a similar data error scenario, the processing system sets the first arrangement mode of the memory space occupied by the data symbol to be the sixteen-row and one-column arrangement shown in Figure 9 . The processing system can detect that data symbol 1, data symbol 2, data symbol 21, and data symbol 23 are in error. Moreover, the processing system can use four first redundant symbols to correct data symbol 1, data symbol 2, data symbol 21, and data symbol 23 respectively. That is to say, through the technical solution of the present application, the processing system can achieve maximum error detection and maximum error correction of the data. Thus, the maximum error detection ability and maximum error correction ability of the first ECC memory space in the first memory are fully exerted, the data error area is maximally covered, and the reliability is improved.

[0237] It should be noted that the second ECC is not limited to on-die ECC. For any two-level or multi-level cascaded error detection and correction algorithms, the encoded data range and arrangement mode should achieve a complementary and non-overflowing effect. Thereby, it is beneficial to maximally improve the error detection and error correction capabilities of the first memory or multi-level memories.

[0238] Optionally, the embodiment shown in FIG. 6 further includes steps 306 to 310. Steps 306 to 310 can be executed after step 305.

[0239] 306. Read all the data from the first memory.

[0240] The all data includes data bits and redundant bits.

[0241] For example, if the first error distribution area information of the at least one memory space changes, the processing system can read all the data from the first memory. Thereby facilitating the processing system to re-encode the data bits in the all data to change the arrangement of the memory spaces occupied by the data symbols. It is beneficial for the subsequent processing system to maximize error detection and error correction of the data.

[0242] 307. Determine the second arrangement of the memory spaces occupied by the data symbols according to the second error distribution area information of at least one of the multiple memory spaces.

[0243] Specifically, the error distribution area of the at least one memory space changes dynamically. Here, the second error distribution area information of the at least one memory space represents the error distribution area of the at least one memory space after the dynamic change. That is, the second error distribution area information of the at least one memory space is used to indicate the specific area of the at least one memory space where the error data bits fall when a data error occurs in the at least one memory space after the dynamic change.

[0244] For example, the first error distribution area information is used to indicate that when a data error occurs in a memory die, the specific area where the error data bits fall in the memory die is the area where the data error occurs as shown in Figure 5a The second error distribution area information is used to indicate that when a data error occurs in a memory die, the specific area where the error data bits fall in the memory die is the area where the data error occurs as shown in Figure 5b shown.

[0245] Specifically, the processing system determines the second arrangement of the memory spaces occupied by the data symbols according to the second error distribution area information of at least one of the multiple memory spaces.

[0246] The second arrangement of the memory spaces occupied by the data symbols matches the arrangement of the area indicated by the second error distribution area information. Or rather, the second arrangement of the memory spaces occupied by the data symbols is strongly correlated with the arrangement of the area indicated by the second error distribution area information.

[0247] For example, each data symbol occupies 16-bit memory space. In the case of the arrangement of the area where the data error occurs as shown in Figure 5b the processing system can set the second arrangement of the memory spaces occupied by the data symbols to the arrangement as shown in Figure 6c shown.

[0248] Optionally, Figure 3 The illustrated embodiment further includes step 307a. Step 307a may be performed before step 307.

[0249] 307a. Obtain second error distribution region information of at least one memory space among a plurality of memory spaces.

[0250] Specifically, the processing system obtains second error distribution region information of at least one memory space among the plurality of memory spaces.

[0251] Optionally, the processing system may determine the second error distribution region information of at least one memory space among the plurality of memory spaces according to historical data error conditions.

[0252] Specifically, the processing system may combine the data error conditions in the historical data reading results to determine the distribution region of the data that often goes wrong in the at least one memory space. Then, the processing system updates the error distribution region of the at least one memory space according to the distribution region of the data that often goes wrong in the at least one memory space, and obtains the second error distribution region information of the at least one memory space.

[0253] It should be noted that, optionally, the error distribution region of the at least one memory space changes dynamically. The reason for the dynamic change of the error distribution region in the memory space is related to the operating environment, business model, etc. of the processing system. For example, the operating environment includes the operating temperature of the processing system, the altitude of the place where the device is located, etc. The business model includes that data is frequently stored in certain positions during business processing. The processing system may update the error distribution region of the at least one memory space in combination with historical data error conditions within a period of time, so as to maximize the error correction ability of the first ECC memory space of the first memory.

[0254] 308. Determine the data bits in all the data as P data symbols according to the second arrangement mode of the memory spaces occupied by the data symbols.

[0255] Wherein, each of the P data symbols includes a plurality of data bits, and P is an integer greater than or equal to 1.

[0256] Step 308 is similar to the foregoing step 303, and specific reference may be made to the foregoing related introduction.

[0257] For example, the second arrangement mode of the memory spaces occupied by the data symbols is the arrangement mode as Figure 6c shown, that is, two rows and eight rows of arrangement. The data bits in all the data include 512 bits. The processing system may combine the destination memory address of the data bits in all the data and the second arrangement mode to determine the 512 bits as 32 data symbols. For example, asFigure 11 As shown, the processing system divides the data bits of the first data to be stored in the memory space of the 15th to 16th rows in data granule 1 into the data bits included in data symbol 1. The processing system divides the data bits of the first data to be stored in the memory space of the 13th to 14th rows in data granule 1 into the data bits included in data symbol 2. And so on, the processing system divides the data bits of the first data to be stored in the memory space of the 1st to 2nd rows in data granule 4 into the data bits included in data symbol 32. It can be seen that the arrangement of each data symbol is the second arrangement method.

[0258] 309. Perform ECC encoding on P data symbols to obtain Q first redundant symbols.

[0259] Among them, each of the Q first redundant symbols includes at least one redundant bit, and Q is an integer greater than or equal to 1.

[0260] Step 309 is similar to the foregoing step 304, and the relevant introduction of the foregoing step 304 can be specifically referred to.

[0261] 310. Write the P data symbols and the Q first redundant symbols into the first memory.

[0262] Step 310 is similar to the foregoing step 305, and the relevant introduction of the foregoing step 305 can be specifically referred to.

[0263] For example, as Figure 11 shown, the processing system writes the data bits included in the P data symbols and the redundant bits included in the Q first redundant symbols into the first memory. The arrangement method of the memory space occupied by each symbol specifically is as Figure 11 shown, the arrangement method of the memory space occupied by each symbol is arranged in two rows and eight columns.

[0264] Optionally, Figure 3 the embodiment shown further includes step 310a, and step 310a can be executed before step 310.

[0265] 310a. Perform second ECC encoding on the P data symbols and the Q first redundant symbols as data to obtain Y second redundant symbols.

[0266] Each of the P second redundant symbols includes at least one redundant bit, and P is an integer greater than or equal to 1.

[0267] Step 310a can be similar to the foregoing step 305a, and the relevant introduction of the foregoing step 310a can be specifically referred to.

[0268] Based on the above step 310a, optionally, step 301 specifically includes:

[0269] Write P data symbols to the data memory space of the first memory, write Q first redundant symbols to the first ECC memory space of the first memory, and write Y second redundant symbols to the second ECC memory space of the first memory.

[0270] It can be seen from this that if the error distribution area of at least one memory space of the first memory changes, the processing system can re-encode the data bits in all the data to change the arrangement of the memory spaces occupied by the data symbols. This is beneficial for the subsequent processing system to perform maximum error detection and maximum error correction on the data during the data reading process, improving the reliability of the system.

[0271] This application provides a data writing method, which is applied to a processing system. The processing system includes a first memory, and the first memory includes multiple memory spaces; obtain first data, which is the data to be written into the first memory; determine the first arrangement of the memory spaces occupied by the data symbols according to the first error distribution area information of at least one memory space among the multiple memory spaces; determine the first data as M data symbols according to the first arrangement of the memory spaces occupied by the data symbols, where each data symbol in the M data symbols includes multiple data bits, and M is an integer greater than or equal to 1; then, perform ECC encoding on the M data symbols to obtain N first redundant symbols, where each first redundant symbol in the N first redundant symbols includes at least one redundant bit, and N is an integer greater than or equal to 1; write the M data symbols to the data memory space in the first memory, and write the N first redundant symbols to the first ECC memory space in the first memory. It can be seen from this that the processing system determines the first arrangement of the memory spaces occupied by the data symbols according to the first error distribution area information of at least one memory space among the multiple memory spaces. That is, the processing system designs the arrangement of the memory spaces occupied by the data symbols in combination with the area distribution of the errors occurring in at least one memory space. Then, the processing system combines the first arrangement of the memory spaces occupied by the data symbols to determine the first data as M data symbols, and each data symbol in the M data symbols includes data bits. Since the destination addresses of the data bits in the first data are all known, the processing system divides the data bits that can form the shape of the first arrangement in the first data into the same data symbol. This is beneficial for the subsequent processing system to perform maximum error detection and maximum error correction on the data during the data reading process, improving the reliability of the system. Thus, the maximum error detection and maximum error correction capabilities of the first ECC memory space in the first memory are fully utilized, the data error area is maximally covered, and the reliability of the system is improved.

[0272] The data writing method in the embodiment of this application is described above. Next, the processing system in the embodiment of this application will be described.

[0273] Please refer to Figure 12 Figure 1, a schematic structural diagram of a processing system according to an embodiment of the present application. The processing system includes a first memory, and the first memory includes multiple memory spaces; the processing system includes: an acquisition unit 1201, a determination unit 1202, an encoding unit 1203, and a writing unit 1204. The processing system further includes a reading unit 1205.

[0274] The acquisition unit 1201 is configured to acquire first data, where the first data is data to be written into the first memory;

[0275] The determination unit 1202 is configured to determine a first arrangement mode of the memory space occupied by the data symbol according to the first error distribution area information of at least one memory space among the multiple memory spaces; determine the first data as M data symbols according to the first arrangement mode of the memory space occupied by the data symbol, where each of the M data symbols includes multiple data bits, and M is an integer greater than or equal to 1;

[0276] The encoding unit 1203 is configured to perform first error correction code (ECC) encoding on the M data symbols to obtain N first redundant symbols, where each of the N first redundant symbols includes at least one redundant bit, and N is an integer greater than or equal to 1;

[0277] The writing unit 1204 is configured to write the M data symbols into the data memory space in the first memory, and write the N first redundant symbols into the first ECC memory space in the first memory.

[0278] In a possible implementation manner, the first error distribution area information of at least one memory space is used to indicate the specific area of the at least one memory space where the erroneous data bits are located when data errors occur in the at least one memory space.

[0279] In another possible implementation manner, each data symbol occupies 8-bit memory space, and the first arrangement mode of the memory space occupied by the data symbol includes any one of the following: four rows and two columns arrangement, two rows and four columns arrangement, eight rows and one column arrangement, one row and eight columns arrangement; or,

[0280] each data symbol occupies 16-bit memory space, and the first arrangement mode of the memory space occupied by the data symbol includes any one of the following: four rows and four columns arrangement, eight rows and two columns arrangement, two rows and eight columns arrangement, sixteen rows and one column arrangement; or,

[0281] each data symbol occupies 32-bit memory space, and the first arrangement mode of the memory space occupied by the data symbol includes any one of the following: one row and thirty-two columns arrangement, thirty-two rows and one column arrangement, two rows and sixteen columns arrangement, sixteen rows and two columns arrangement, four rows and eight columns arrangement, eight rows and four columns arrangement.

[0282] In another possible implementation, the obtaining unit 1201 is further configured to:

[0283] Obtain first error distribution region information of at least one memory space among multiple memory spaces.

[0284] In another possible implementation, the reading unit 1205 is configured to read all data from the first memory, and all data includes data bits and redundant bits;

[0285] The determining unit 1202 is further configured to:

[0286] Determine a second arrangement mode of the memory space occupied by the data symbols according to the second error distribution region information of at least one memory space among multiple memory spaces; determine the data bits in all data as P data symbols according to the second arrangement mode of the memory space occupied by the data symbols, each of the P data symbols includes multiple data bits, and P is an integer greater than or equal to 1;

[0287] The encoding unit 1203 is further configured to:

[0288] Perform first ECC encoding on the P data symbols to obtain Q first redundant symbols, each of the Q first redundant symbols includes at least one redundant bit, and Q is an integer greater than or equal to 1;

[0289] The writing unit 1204 is further configured to:

[0290] Write the P data symbols to the data memory space in the first memory, and write the Q first redundant symbols to the first ECC memory space in the first memory.

[0291] In another possible implementation, the obtaining unit 1201 is further configured to:

[0292] Obtain second error distribution region information of at least one memory space among multiple memory spaces.

[0293] In another possible implementation, the obtaining unit 1201 is specifically configured to:

[0294] Determine the second error distribution region information of at least one memory space among multiple memory spaces according to the historical data error situation.

[0295] In another possible implementation, the data symbols and the first redundant symbols are RS code symbols; or; the data symbols and the first redundant symbols are BCH code symbols.

[0296] In another possible implementation, the first memory is an on die ECC memory.

[0297] In another possible implementation, the encoding unit 1203 is specifically configured to:

[0298] Perform a first ECC encoding on M data symbols using a finite field encoding algorithm to obtain N first redundant symbols. The finite field encoding algorithm includes algorithms such as the RS algorithm or the BCH algorithm.

[0299] In another possible implementation, the first memory is a memory that supports a second ECC encoding (such as on die ECC), and the first memory also has a second ECC memory space; the encoding unit 1203 is further configured to:

[0300] Perform a second ECC encoding on the M data symbols and the N first redundant symbols as data to obtain R second redundant symbols. Each of the R second redundant symbols includes at least one redundant bit, and R is an integer greater than or equal to 1;

[0301] The writing unit 1204 is specifically configured to:

[0302] Write the M data symbols to the data memory space, write the N first redundant symbols to the first ECC memory space, and write the R second redundant symbols to the second ECC memory space.

[0303] Please refer to Figure 13 , the processing system 1300 may vary greatly due to configuration or performance differences, and may include one or more central processing units (CPUs) 1322 (for example, one or more processors) and a memory 1332, and one or more storage media 1330 (for example, one or more mass storage devices) that store application programs 1342 or data 1344.

[0304] Among them, the memory 1332 and the storage medium 1330 may be transient storage or persistent storage. The program stored in the storage medium 1330 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations on the processing system. Further, the central processor 1322 may be configured to communicate with the storage medium 1330 and execute a series of instruction operations in the storage medium 1330 on the processing system 1300.

[0305] The processing system 1300 may further include one or more power supplies 1326, one or more wired or wireless network interfaces 1350, one or more input / output interfaces 1358, and / or one or more operating systems 1341, for example, the Microsoft operating system, the Apple operating system, etc.

[0306] The above embodiments Figure 3The specific steps executed by the processing system may be based on the Figure 13 processing system structure shown. The central processing unit 1322 is used to execute the following scheme:

[0307] Obtain first data, where the first data is the data to be written into the first memory;

[0308] Determine a first arrangement manner of the memory space occupied by the data symbol according to the first error distribution region information of at least one memory space among multiple memory spaces;

[0309] Determine the first data as M data symbols according to the first arrangement manner of the memory space occupied by the data symbol, where each of the M data symbols includes multiple data bits, and M is an integer greater than or equal to 1;

[0310] Perform error correction code ECC encoding on the M data symbols to obtain N first redundant symbols, where each of the N first redundant symbols includes at least one redundant bit, and N is an integer greater than or equal to 1;

[0311] Write the M data symbols into the data memory space in the first memory, and write the N first redundant symbols into the first ECC memory space in the first memory.

[0312] In a possible implementation manner, the first error distribution region information of at least one memory space is used to indicate the specific region of the at least one memory space where the erroneous data bits fall when data errors occur in the at least one memory space.

[0313] In another possible implementation manner, each data symbol occupies 8-bit memory space, and the first arrangement manner of the memory space occupied by the data symbol includes any one of the following: four rows and two columns arrangement, two rows and four columns arrangement, eight rows and one column arrangement, one row and eight columns arrangement; or,

[0314] Each data symbol occupies 16-bit memory space, and the first arrangement manner of the memory space occupied by the data symbol includes any one of the following: four rows and four columns arrangement, eight rows and two columns arrangement, two rows and eight columns arrangement, sixteen rows and one column arrangement; or,

[0315] Each data symbol occupies 32-bit memory space, and the first arrangement manner of the memory space occupied by the data symbol includes any one of the following: one row and thirty-two columns arrangement, thirty-two rows and one column arrangement, two rows and sixteen columns arrangement, sixteen rows and two columns arrangement, four rows and eight columns arrangement, eight rows and four columns arrangement.

[0316] In another possible implementation manner, the central processing unit 1322 is further used to:

[0317] Obtain the first error distribution region information of at least one memory space among multiple memory spaces.

[0318] In another possible implementation, the central processing unit 1322 is further configured to:

[0319] Read all data from the first memory, where all data includes data bits and redundant bits;

[0320] Determine a second arrangement mode of the memory space occupied by the data symbols according to the second error distribution region information of at least one memory space among multiple memory spaces; determine the data bits in all data as P data symbols according to the second arrangement mode of the memory space occupied by the data symbols, where each of the P data symbols includes multiple data bits, and P is an integer greater than or equal to 1;

[0321] Perform ECC encoding on the P data symbols to obtain Q first redundant symbols, where each of the Q first redundant symbols includes at least one redundant bit, and Q is an integer greater than or equal to 1;

[0322] Write the P data symbols to the data memory space in the first memory, and write the Q first redundant symbols to the first ECC memory space in the first memory.

[0323] In another possible implementation, the central processing unit 1322 is further configured to:

[0324] Obtain the second error distribution region information of at least one memory space among multiple memory spaces.

[0325] In another possible implementation, the central processing unit 1322 is specifically configured to:

[0326] Determine the second error distribution region information of at least one memory space among multiple memory spaces according to the historical data error situation.

[0327] In another possible implementation, the data symbols and the first redundant symbols are RS code symbols; or; the data symbols and the first redundant symbols are BCH code symbols.

[0328] In another possible implementation, the first memory is an on die ECC memory.

[0329] In another possible implementation, the central processing unit 1322 is specifically configured to:

[0330] Perform first ECC encoding on M data symbols using a finite field encoding algorithm to obtain N first redundant symbols, where the finite field encoding algorithm includes algorithms such as RS algorithm or BCH algorithm.

[0331] In another possible implementation, the first memory is a memory that supports second ECC encoding, and the first memory further includes a second ECC memory space; the central processing unit 1322 is further configured to:

[0332] Perform second ECC encoding on the M data symbols and the N first redundant symbols as data to obtain R second redundant symbols, where each of the R second redundant symbols includes at least one redundant bit, and R is an integer greater than or equal to 1;

[0333] Specifically, the central processing unit 1322 is configured to:

[0334] Write the M data symbols to the data memory space, write the N first redundant symbols to the first ECC memory space, and write the R second redundant symbols to the second ECC memory space.

[0335] An embodiment of the present application further provides a computer program product including instructions, which, when running on a computer, cause the computer to execute the data writing method of the embodiment as described above Figure 3 as shown.

[0336] An embodiment of the present application further provides a computer-readable storage medium including computer instructions, which, when running on a computer, cause the computer to execute the data writing method of the embodiment as described above Figure 3 as shown.

[0337] In another possible design, when the processing system is a chip in a terminal, the chip includes: a processing unit and a communication unit. The processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, a pin, or a circuit, etc. The processing unit can execute the computer execution instructions stored in the storage unit to cause the chip in the terminal to execute the data writing method of the embodiment as described above Figure 3 as shown. Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, etc., and the storage unit may also be a storage unit outside the chip in the terminal, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc.

[0338] Wherein, the processor mentioned anywhere above may be a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit (ASIC), or an integrated circuit for controlling the execution of the program of the data writing method of the embodiment as described above Figure 3 as shown.

[0339] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0340] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, and the indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0341] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0342] In addition, in each embodiment of the present application, the functional units can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0343] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, ROM, RAM, magnetic disks, or optical discs that can store program codes.

[0344] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A data writing method, characterized in that, The method includes: Obtaining first data to be written into a first memory of a processing system, where the first memory includes multiple memory spaces; Determining a first arrangement manner of the memory spaces occupied by data symbols according to first error distribution region information of at least one memory space among the multiple memory spaces; wherein, the first error distribution region information of at least one memory space among the multiple memory spaces is used to indicate the region of the at least one memory space where error data bits fall when data errors occur in the at least one memory space; Determining the first data as M data symbols according to the first arrangement manner, where each of the M data symbols includes multiple data bits, and M is an integer greater than or equal to 1; Performing first error correction code (ECC) encoding on the M data symbols to obtain N first redundant symbols, where each first redundant symbol includes at least one redundant bit, and N is an integer greater than or equal to 1; Writing the M data symbols and the N first redundant symbols into a data memory space in the first memory and a first ECC memory space of the first memory respectively.

2. The method according to claim 1, wherein Each data symbol occupies 8-bit memory space, and the first arrangement manner of the memory spaces occupied by the data symbols includes any one of the following: arranged in four rows and two columns, arranged in two rows and four columns, arranged in eight rows and one column, arranged in one row and eight columns; Or, Each data symbol occupies 16-bit memory space, and the first arrangement manner of the memory spaces occupied by the data symbols includes any one of the following: arranged in four rows and four columns, arranged in eight rows and two columns, arranged in two rows and eight columns, arranged in sixteen rows and one column; Or, Each data symbol occupies 32-bit memory space, and the first arrangement manner of the memory spaces occupied by the data symbols includes any one of the following: arranged in one row and thirty-two columns, arranged in thirty-two rows and one column, arranged in two rows and sixteen columns, arranged in sixteen rows and two columns, arranged in four rows and eight columns, arranged in eight rows and four columns.

3. The method according to any one of claims 1 to 2, characterized in that, The method further includes: Obtaining the first error distribution region information of at least one memory space among the multiple memory spaces.

4. The method according to any one of claims 1 to 2, characterized in that The method further includes: Reading all data from the first memory, where the all data includes data bits and redundant bits; Determining a second arrangement manner of the memory spaces occupied by data symbols according to second error distribution region information of at least one memory space among the multiple memory spaces; Determining the data bits in the all data as P data symbols according to the second arrangement manner of the memory spaces occupied by the data symbols, where each of the P data symbols includes multiple data bits, and P is an integer greater than or equal to 1; Performing first ECC encoding on the P data symbols to obtain Q first redundant symbols, where each of the Q first redundant symbols includes at least one redundant bit, and Q is an integer greater than or equal to 1; Writing the P data symbols into the data memory space in the first memory and writing the Q first redundant symbols into the first ECC memory space of the first memory.

5. The method according to claim 4, wherein The method further includes: Obtain second error distribution region information of at least one memory space among the multiple memory spaces.

6. The method according to claim 5, wherein The obtaining of the second error distribution region information of at least one memory space among the multiple memory spaces includes: Determine the second error distribution region information of at least one memory space among the multiple memory spaces according to the historical data error situation.

7. The method according to any one of claims 1 to 2, characterized in that, The data symbol and the first redundant symbol are Reed-Solomon (RS) code symbols; or The data symbol and the first redundant symbol are Bose-Chaudhuri-Hocquenghem (BCH) code symbols.

8. The method according to any one of claims 1 to 2, characterized in that The first memory is a memory that supports second ECC encoding; the first memory further includes a second ECC memory space; the method further includes: Perform second ECC encoding on the M data symbols and the N first redundant symbols as data to obtain R second redundant symbols, each of the R second redundant symbols includes at least one redundant bit, and R is an integer greater than or equal to 1; Write the M data symbols to the data memory space, write the N first redundant symbols to the first ECC memory space, and write the R second redundant symbols to the second ECC memory space.

9. The method according to claim 8, wherein The first memory is an on-die ECC memory.

10. A processing system, characterized in that, The processing system includes a first memory controller and a first memory, the first memory includes multiple memory spaces; the first memory controller is configured to execute the method according to any one of claims 1 to 7.

11. The processing system according to claim 10, characterized in that, The first memory controller is further configured to execute the method according to claim 8 or 9; or The processing system includes a second memory controller, one side of the second memory controller is connected to the first memory controller, and the other side of the second memory controller is connected to the first memory, and the second memory controller is configured to execute the method according to claim 8 or 9.

12. A processing system, characterized in that, Includes: A memory for storing a program; A processor for executing the program stored in the memory, and when the program is executed, the processor is configured to execute the method according to any one of claims 1 to 9.

13. A computer-readable storage medium, including computer instructions, when the computer instructions run on a computer, causing the computer to execute the method according to any one of claims 1 to 9.

Images