A performance testing method and device for a data acquisition system

Abstract

The present application provides a performance testing method and device for a data acquisition system. The performance testing method comprises: an ADC module of an acquisition board collects a sine wave signal input by an analog front end, outputs digitized discrete sine wave data and transmits it to a storage module; the FPGA module generates accumulated data and transmits it to the storage module; checks whether the discrete sine wave data is continuous, and determines whether the transmission process from the analog front end to the second DDR module and the storage module is abnormal; checks whether the accumulated data is continuous, and determines whether the transmission process from the FPGA module to the second DDR module and the storage module is abnormal, thereby determining the performance test result of the data acquisition system and locating the abnormal point, thereby performing a long-term integrity and correctness check on the data transmitted in the data acquisition system itself, and determining whether the performance test result of the data acquisition system is reliable during the long-term and massive data transmission process based on the check result.

Description

Technical Field

[0001] The present application relates to the field of data acquisition, and in particular to a performance testing method and device for a data acquisition system. Background Art

[0002] When the data acquisition system collects and streams data to disk for a long time on the acquisition board (referred to as the board), it will store tens or hundreds of GBytes or even TBytes of data in the board memory. In order to ensure the correctness and continuity of data transmission from the board DDR through communication modules and interfaces such as PCIe, Ethernet, USB, etc. to the computer memory, it is often necessary to verify the data, detect whether there are abnormal points in the data transmission process and locate the abnormal point positions, so as to determine whether there are acquisition errors or losses in the transmission process of the acquisition system. Conventional methods for detecting abnormal points include wavelet transform, statistical distribution, cluster analysis, etc. However, for acquisition systems with high real-time requirements, the verification speed is required to reach at least 1GB / s. The complexity of the data verification algorithm is too high, which will make it difficult for the verification speed to reach the rate requirement of more than 1GB / s. Moreover, the verification of high-speed and large-volume data is generally to intercept a continuous time segment of the transmitted data, such as the beginning, middle, end or fixed feature position, for analysis, rather than to verify the integrity and correctness of the data itself for a long time and give a conclusion on whether the data acquisition system is reliable. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide a performance testing method and device for a data acquisition system, which can perform long-term integrity and correctness verification on the data transmitted in the data acquisition system itself, and determine whether the data acquisition system has reliable performance test results during long-term and massive data transmission based on the verification results.

[0004] A performance test method of a data acquisition system provided in an embodiment of the present application is applied to a data acquisition system, wherein the data acquisition system comprises: an acquisition board, a host computer, and an input device; the acquisition board comprises an ADC module, an FPGA module, and a first DDR module; the host computer comprises a CPU module, a second DDR module, and a storage module; the input device is connected to the host computer; the performance test method comprises:

[0005] The ADC module of the acquisition board collects the sine wave signal input by the analog front end and outputs digital discrete sine wave data, and the discrete sine wave data is transmitted to the storage module through the FPGA module, the first DDR module, the CPU module, and the second DDR module;

[0006] The FPGA module generates accumulated data, and the accumulated data is transmitted to the storage module through the first DDR module, the CPU module, and the second DDR module;

[0007] Based on the discrete sine wave data and the configured first data verification rule, determine whether the discrete sine wave data received by the second DDR module and the storage module is continuous, and determine a first verification result; wherein the first verification result indicates whether the transmission process from the analog front end to the second DDR module and the storage module is abnormal;

[0008] Based on the accumulated data and the configured first data verification rule, determine whether the accumulated data received by the second DDR module and the storage module are continuous, and determine a second verification result; wherein the second verification result indicates whether the transmission process from the FPGA module to the second DDR module and the storage module is abnormal;

[0009] Determining a performance test result of the data acquisition system based on the first verification result and the second verification result;

[0010] When the performance test result is abnormal, the abnormal point of the data acquisition system is located based on the first verification result and the second verification result.

[0011] In some embodiments, in the performance test method of the data acquisition system, determining the performance test result of the data acquisition system based on the first verification result and the second verification result includes:

[0012] When both the first verification result and the second verification result are normal, determining that the performance test result of the data acquisition system is normal;

[0013] When the first verification result or the second verification result is abnormal, it is determined that the performance test result of the data acquisition system is abnormal.

[0014] In some embodiments, in the performance testing method of the data acquisition system, locating abnormal points of the data acquisition system based on the first verification result and the second verification result includes:

[0015] When it is determined based on the second verification result that the transmission process of data from the FPGA module to the second DDR module is abnormal, determining that the abnormal point is located between the FPGA module and the second DDR module;

[0016] When it is determined based on the second verification result that the transmission process of data from the FPGA module to the second DDR module is normal and the transmission process from the FPGA module to the storage module is abnormal, it is determined that the abnormal point is located between the second DDR module and the storage module;

[0017] When the second verification result is normal and the first verification result is abnormal, it is determined that the abnormal point is located between the analog front end and the FPGA module.

[0018] In some embodiments, the performance testing method of the data acquisition system further includes:

[0019] First, the FPGA module generates accumulated data to determine a second verification result;

[0020] When the second verification result is normal, the sine wave signal input by the analog front end is collected by the ADC module of the acquisition board, and digitized discrete sine wave data is output to determine the first verification result.

[0021] In some embodiments, in the performance test method of the data acquisition system, the ADC module of the acquisition board acquires the sine wave signal input by the analog front end and outputs digitized discrete sine wave data, and the discrete sine wave data is transmitted to the storage module through the FPGA module, the first DDR module, the CPU module, and the second DDR module, including:

[0022] The ADC module of the acquisition board acquires the sine wave signal input by the analog front end, and outputs digitized discrete sine wave data to the FPGA module. The FPGA module receives the discrete sine wave data and stores it in the first DDR module mounted on the FPGA module.

[0023] The CPU module of the host computer reads the discrete sine wave data in the first DDR module mounted on the FPGA, and caches the discrete sine wave data in the second DDR module mounted on the CPU module;

[0024] The second DDR module of the host computer interacts with the storage module to store the discrete sine wave data into the storage module.

[0025] In some embodiments, in the performance test method of the data acquisition system, the FPGA module generates accumulated data, and the accumulated data is transmitted to the storage module through the first DDR module, the CPU module, and the second DDR module, including:

[0026] The FPGA module replaces the discrete digital signal data with accumulated data having an accumulation rule, and stores the accumulated data into a first DDR module mounted on the FPGA module;

[0027] The CPU module of the host computer reads the accumulated data in the first DDR module mounted on the FPGA, and caches the accumulated data in the second DDR module mounted on the CPU module;

[0028] The second DDR module of the host computer interacts with the storage module to store the accumulated data into the storage module.

[0029] In some embodiments, in the performance test method of the data acquisition system, judging whether the discrete sine wave data received by the second DDR module and the storage module is continuous based on the discrete sine wave data and the configured first data verification rule includes:

[0030] Based on the properties of the acquisition board, configure the board sampling rate and signal frequency;

[0031] Based on the sampling rate and signal frequency of the board, a check threshold corresponding to the difference between adjacent data in the discrete sine wave data output by the ADC module of the acquisition board is determined;

[0032] When the absolute value of the difference between adjacent data in the discrete sine wave data does not exceed the verification threshold, it is determined that the adjacent data are continuous.

[0033] In some embodiments, in the performance test method of the data acquisition system, based on the sampling rate and signal frequency of the board, determining the verification threshold corresponding to the difference between adjacent data in the discrete sine wave data output by the ADC module of the acquisition board includes:

[0034] Calculate the number of points N of each cycle of the discrete sine wave data based on the board sampling rate and the signal frequency;

[0035] Determine the maximum and minimum values ​​of the signal amplitude of discrete sine wave data within a complete sine wave cycle;

[0036] The verification threshold is calculated based on the distance between the two most distant adjacent points in the sine wave discrete into N points, the maximum and minimum values ​​of the signal amplitude of the discrete sine wave data, and the reference tolerance.

[0037] In some embodiments, in the performance test method of the data acquisition system, judging whether the accumulated data received by the second DDR module and the storage module are continuous based on the accumulated data and the configured second data verification rule includes:

[0038] Based on the bit width of the accumulated data generated by the FPGA, configure the data bit width in the first data verification rule;

[0039] For accumulated data with a bit width of 8 bits or 16 bits, the accumulated data is processed into corresponding integers, and it is determined whether the difference between the integers corresponding to adjacent data in the accumulated data is 1, so as to determine whether the adjacent data are continuous;

[0040] For 32-bit and 64-bit accumulated data, based on the preset adjacent data comparison rule, the byte arrays of adjacent data are compared to determine whether the adjacent data are continuous; wherein the preset adjacent data comparison rule is determined based on the characteristics of the byte array corresponding to the 32-bit or 64-bit data with a difference of 1.

[0041] In some embodiments, a performance test device for a data acquisition system is also provided, which is applied to the data acquisition system. The data acquisition system includes: an acquisition board, a host computer, and an input device; the acquisition board includes an ADC module, an FPGA module, and a first DDR module; the host computer includes a CPU module, a second DDR module, and a storage module; the input device is connected to the host computer; the performance test device includes:

[0042] An acquisition module, used to enable the ADC module of the acquisition board to acquire the sine wave signal input by the analog front end and output digital discrete sine wave data, and the discrete sine wave data is transmitted to the storage module through the FPGA module, the first DDR module, the CPU module, and the second DDR module;

[0043] A generating module, used to enable the FPGA module to generate accumulated data, and the accumulated data is transmitted to the storage module through the first DDR module, the CPU module, and the second DDR module;

[0044] A first judgment module is used to judge whether the discrete sine wave data received by the second DDR module and the storage module is continuous based on the discrete sine wave data and the configured first data verification rule when a preset test condition is met, and determine a first verification result; wherein the first verification result indicates whether the transmission process from the analog front end to the second DDR module and the storage module is abnormal;

[0045] A second judgment module is used to judge whether the accumulated data received by the second DDR module and the storage module are continuous based on the accumulated data and the configured first data verification rule, and determine a second verification result; wherein the second verification result indicates whether the transmission process from the FPGA module to the second DDR module and the storage module is abnormal;

[0046] A determination module, which determines a performance test result of the data acquisition system based on the first verification result and the second verification result;

[0047] A positioning module is used to locate an abnormal point of the data acquisition system based on the first verification result and the second verification result when the performance test result is abnormal.

[0048] Based on this, in an embodiment of the present application, a performance test method and device for a data acquisition system are provided, wherein the performance test method comprises: an ADC module of an acquisition board collects a sine wave signal input by an analog front end, outputs digitized discrete sine wave data and transmits it to a storage module; the FPGA module generates accumulated data and transmits it to the storage module; the discrete sine wave data is checked to see if it is continuous, and whether the transmission process from the analog front end to the second DDR module and the storage module is abnormal; the accumulated data is checked to see if it is continuous, and whether the transmission process from the FPGA module to the second DDR module and the storage module is abnormal, thereby determining the performance test result of the data acquisition system and locating the abnormal point; during the test, the integrity and continuity of the massive accumulated data and the discrete sine wave data themselves are firstly checked, thereby determining the stability of the data acquisition system when collecting and transmitting massive data through the check result; secondly, a simple algorithm is used to check the accumulated number signal and the sine wave signal, and these two The waveform data of the first signal is simple, which greatly reduces the complexity of the verification algorithm. At the same time, FPGA can easily process accumulated data and sine wave data, which is convenient for system acquisition and verification at the same time. The last two types of data can respectively verify the continuity and integrity of different communication data transmission processes. The accumulated data verifies the continuity and integrity of the data transmitted from the FPGA module through the PCIe, Ethernet, USB and other communication modules and interfaces to the host computer process. The sine wave signal data verifies the continuity and integrity of the data transmitted from the board analog front end to the host computer process, thereby comprehensively verifying the data acquisition system and locating abnormalities. It should be noted that the user can flexibly select the signals that need to be paid attention to for acquisition and verification according to the test scenarios of different specific applications of the data acquisition system and the different types of signals that need to be paid attention to in the test scenarios, so as to more specifically test the performance of the data acquisition system in different test scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 A flow chart showing a performance testing method of a data acquisition system according to an embodiment of the present application is shown;

[0051] Figure 2 A schematic diagram of the structure of the data acquisition system according to an embodiment of the present application is shown;

[0052] Figure 3A flow chart of a method for determining whether discrete sinusoidal wave data received by the second DDR module and the storage module is continuous according to an embodiment of the present application is shown;

[0053] Figure 4 The scatter plot after the sine wave signal is converted according to the embodiment of the present application is shown;

[0054] Figure 5 A flow chart of a method for determining whether the accumulated data received by the second DDR module and the storage module are continuous according to an embodiment of the present application is shown;

[0055] Figure 6 A schematic diagram of the structure of a performance testing device for a data acquisition system according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0056] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0057] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0058] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0059] When the data acquisition system performs long-term data collection and streaming on the acquisition board (referred to as the board), it will store tens or hundreds of GBytes or even TBytes of data in the board memory. In order to ensure the correctness and continuity of data transmission from the board DDR through communication modules and interfaces such as PCIe, Ethernet, USB to the computer memory (or vice versa), it is often necessary to verify the data, detect whether there are abnormal points in the data transmission process and locate the abnormal point position, so as to determine whether there are acquisition errors or losses in the transmission process of the acquisition system. Conventional abnormal point detection methods include wavelet transform, statistical distribution, cluster analysis, etc. However, for acquisition systems with high real-time requirements, the verification speed is required to reach at least 1GB / s. The complexity of the data verification algorithm is too high, which will make it difficult for the verification speed to reach the rate requirement of more than 1GB / s. Moreover, the verification of high-speed and large-volume data is generally to intercept a continuous time segment of the transmitted data, such as the beginning, middle, end or fixed feature position, for analysis, rather than to verify the integrity and correctness of the data itself for a long time and give a conclusion on whether the data acquisition system is reliable.

[0060] Here, the data acquisition system can also be called a data acquisition and playback system.

[0061] Based on this, in an embodiment of the present application, a performance test method and device for a data acquisition system are provided, the performance test method is applied to a data acquisition system, the data acquisition system comprises: an acquisition board, a host computer, and an input device; the acquisition board comprises an ADC module, an FPGA module, and a first DDR module; the host computer comprises a CPU module, a second DDR module, and a storage module; the input device is connected to the host computer; the performance test method comprises: the ADC module of the acquisition board acquires a sine wave signal input by an analog front end, and outputs digitized discrete sine wave data, the discrete sine wave data is transmitted through the FPGA module, the first DDR module, and the CPU module , the second DDR module is transmitted to the storage module; the FPGA module generates accumulated data, and the accumulated data is transmitted to the storage module through the first DDR module, the CPU module, and the second DDR module; based on the discrete sine wave data and the configured first data verification rule, it is judged whether the discrete sine wave data received by the second DDR module and the storage module are continuous, and a first verification result is determined; wherein the first verification result indicates whether the transmission process from the analog front end to the second DDR module and the storage module is abnormal; based on the accumulated data and the configured first data verification rule, it is judged whether the accumulated data received by the second DDR module and the storage module are continuous, and a first verification result is determined. The second verification result is determined; wherein the second verification result indicates whether the transmission process from the FPGA module to the second DDR module and the storage module is abnormal; based on the first verification result and the second verification result, the performance test result of the data acquisition system is determined; when the performance test result is abnormal, the abnormal point of the data acquisition system is located based on the first verification result and the second verification result; during the test process, the integrity and continuity of the massive accumulated data and the discrete sine wave data are first verified, so as to determine the stability of the data acquisition system in collecting and transmitting massive data through the verification results; secondly, a simple algorithm is used to verify the accumulated number signal and the sine wave signal, and these two The waveform data of this signal is simple, which greatly reduces the complexity of the verification algorithm. At the same time, FPGA can easily process accumulated data and sine wave data, which is convenient for system acquisition and verification to be carried out simultaneously. The last two types of data can respectively verify the continuity and integrity of different communication data transmission processes. The accumulated data verifies the continuity and integrity of the data transmission from the FPGA module through the PCIe, Ethernet, USB and other communication modules and interfaces to the host computer. The sine wave signal data verifies the continuity and integrity of the data transmission from the data collected from the board analog front end to the computer, thereby comprehensively verifying the data acquisition system and locating abnormalities.

[0062] It should be noted that the user can flexibly select the signals that need to be paid attention to for collection and verification according to the test scenarios of different specific applications of the data acquisition system and the different types of signals that need to be paid attention to in the test scenarios, so as to more specifically test the performance of the data acquisition system in different test scenarios.

[0063] Please refer to Figure 1 , Figure 1 A flow chart showing a performance test method of a data acquisition system according to an embodiment of the present application is shown; please refer to Figure 2 , Figure 2 The structure diagram of the data acquisition system described in the embodiment of the present application is shown; the performance test method of the data acquisition system is applied to the data acquisition system, such as Figure 2 As shown, the data acquisition system includes: an acquisition board 201, a host computer 202, and an input device 203; the acquisition board 201 includes an ADC module, an FPGA module, and a first DDR module; the host computer 202 includes a CPU module, a second DDR module, and a storage module; the input device 203 is connected to the host computer 202.

[0064] like Figure 1 As shown, the performance test method of the data acquisition system includes the following steps S101-S106:

[0065] S101, the ADC module of the acquisition board acquires the sine wave signal input by the analog front end, and outputs digital discrete sine wave data, and the discrete sine wave data is transmitted to the storage module through the FPGA module, the first DDR module, the CPU module, and the second DDR module;

[0066] S102, the FPGA module generates accumulated data, and the accumulated data is transmitted to the storage module through the first DDR module, the CPU module, and the second DDR module;

[0067] S103, based on the discrete sine wave data and the configured first data verification rule, determine whether the discrete sine wave data received by the second DDR module and the storage module is continuous, and determine a first verification result; wherein the first verification result indicates whether the transmission process from the analog front end to the second DDR module and the storage module is abnormal;

[0068] S104, based on the accumulated data and the configured first data verification rule, determine whether the accumulated data received by the second DDR module and the storage module are continuous, and determine a second verification result; wherein the second verification result indicates whether the transmission process from the FPGA module to the second DDR module and the storage module is abnormal;

[0069] S105, determining a performance test result of the data acquisition system based on the first verification result and the second verification result;

[0070] S106: When the performance test result is abnormal, locate the abnormal point of the data acquisition system based on the first verification result and the second verification result.

[0071] The external devices include a mouse, a keyboard, etc.

[0072] The host computer may be a computer, and the computer memory of the computer is the second DDR module described in the embodiment of the present application.

[0073] The DDR chip, namely the DDR module, Double Data Rate Synchronous Dynamic Random Access Memory, is a high-performance memory technology used to store massive amounts of data.

[0074] The storage module may be a hard disk or a storage array SSD.

[0075] Please refer to Figure 2 The data acquisition system consists of three parts. The user controls the computer through external devices to issue control instructions, and the computer completes data processing and data display. The acquisition board receives computer instructions to complete corresponding signal acquisition and signal playback.

[0076] The specific working process of the data acquisition system is as follows: after the external analog signal (electrical signal) is digitized by the analog-to-digital conversion chip ADC, the data is sent to the FPGA carrier board for signal processing through the JESD204 interface, LVDS, SPI and other interfaces. After the FPGA completes the signal processing, it stores the data in the DDR chip mounted on the FPGA. The CPU (computer) reads the data in the DDR chip mounted on the FPGA through the interface connected to the FPGA (PCIe, Ethernet, USB and other interfaces), and caches the data in the DDR chip mounted on the CPU. The upper computer software draws and displays the data in the memory (DDR chip) on the computer monitor. According to the usage scenario, the user chooses whether to store the data in the hard disk.

[0077] In step S101, the ADC module of the acquisition board acquires the sine wave signal input by the analog front end and outputs digitized discrete sine wave data, which is transmitted to the storage module through the FPGA module, the first DDR module, the CPU module, and the second DDR module.

[0078] Specifically, the ADC module of the acquisition board acquires the sine wave signal input by the analog front end and outputs digital discrete sine wave data, and the discrete sine wave data is transmitted to the storage module through the FPGA module, the first DDR module, the CPU module, and the second DDR module, including:

[0079] The ADC module of the acquisition board acquires the sine wave signal input by the analog front end, and outputs digitized discrete sine wave data to the FPGA module. The FPGA module receives the discrete sine wave data and stores it in the first DDR module mounted on the FPGA module.

[0080] The CPU module of the host computer reads the discrete sine wave data in the first DDR module mounted on the FPGA, and caches the discrete sine wave data in the second DDR module mounted on the CPU module;

[0081] The second DDR module of the host computer interacts with the storage module to store the discrete sine wave data into the storage module.

[0082] In the step S102, the FPGA module generates accumulated data, and the accumulated data is transmitted to the storage module through the first DDR module, the CPU module, and the second DDR module.

[0083] The FPGA module generates accumulated data, and the accumulated data is transmitted to the storage module through the first DDR module, the CPU module, and the second DDR module, including:

[0084] The FPGA module replaces the discrete digital signal data with accumulated data having an accumulation rule, and stores the accumulated data into a first DDR module mounted on the FPGA module;

[0085] The CPU module of the host computer reads the accumulated data in the first DDR module mounted on the FPGA, and caches the accumulated data in the second DDR module mounted on the CPU module;

[0086] The second DDR module of the host computer interacts with the storage module to store the accumulated data into the storage module.

[0087] Based on this, the present invention verifies two signals, a sine wave signal and an accumulated signal, which are commonly used in an acquisition system.

[0088] The characteristics of the accumulated data are: the difference between the two adjacent data is 1; the latter number is larger than the former number; the numbers are accumulated to the maximum value and then return to zero, and then continue to accumulate. The accumulated data constructed in this way has obvious rules and is convenient for data verification.

[0089] The characteristics of the discrete sine wave data are: the amplitude changes sinusoidally with time; the overall amplitude changes periodically, and the number of points in each period depends on the multiple between the board sampling rate and the signal frequency.

[0090] Specifically, the discrete sine wave data is acquired by analog front-end accessing the sine wave signal. After passing through the ADC module, the digitized discrete sine wave signal is sent to the FPGA module through the transmission bus (JESD204 / LVDS / SPI and other interfaces); the FPGA stores the received discrete sine wave data in the DDR mounted on the FPGA. The host computer software controls the board and the computer to transmit the discrete sine wave data through communication modules and interfaces such as PCIe, Ethernet, and USB. At the same time, the CPU verifies the acquired discrete sine wave data, or stores it in the hard disk / storage array SSD for offline verification; the discrete sine wave data verifies the integrity and accuracy of the data transmission during the entire process from the analog front-end input, through the FPGA to the computer memory.

[0091] The method for acquiring the accumulated data is that after the ADC sends the FPGA data, the FPGA replaces the discrete digital signal data with accumulated data with an accumulation rule, and stores it in the DDR mounted on the FPGA; the upper computer software controls the board and the computer to transmit the accumulated number through communication modules and interfaces such as PCIe, Ethernet, USB, etc., and the CPU verifies the acquired accumulated number, or stores it in the hard disk / storage array SSD for offline verification; the accumulated data verifies the integrity and accuracy of the data transmission during the flow of data from the FPGA to the computer memory.

[0092] In the step S103, based on the discrete sine wave data and the configured first data verification rule, it is determined whether the discrete sine wave data received by the second DDR module and the storage module are continuous, and a first verification result is determined; wherein, the first verification result represents whether the transmission process from the analog front end to the second DDR module and the storage module is abnormal.

[0093] In step S104, based on the accumulated data and the configured first data verification rule, it is determined whether the accumulated data received by the second DDR module and the storage module are continuous, and a second verification result is determined; wherein, the second verification result indicates whether the transmission process from the FPGA module to the second DDR module and the storage module is abnormal.

[0094] In step S103 and step S104, the accumulated data and the discrete sine wave data are specifically verified. The data verification can be performed when the CPU and FPGA DDR interact, or when the hard disk / storage array SSD interacts with the computer memory.

[0095] When performing data verification, massive data is obtained from computer memory or storage devices such as NVME, and the verification algorithm input data type is configured to be sinusoidal wave data and / or accumulated data, and the data format is configured based on the encoding method and bit width of the data output by the FPGA.

[0096] Exemplarily, the data format configured is but not limited to integer types (such as int8, uint8, int16, uint16, int32, uint32, etc.), each type represents a signed or unsigned integer in a different range, where int represents a signed integer, uint represents an unsigned integer, and the number that follows indicates the bit width of that type of data.

[0097] In specific implementation, only the sine wave data or only the accumulated data can be verified according to user needs, so it is necessary to configure the verification algorithm input data type to be sine wave data and / or accumulated data.

[0098] The data formats output by FPGAs of different functions and models may be different, so the data format needs to be configured.

[0099] In the embodiment of the present application, the collection time of the accumulated data or the discrete sine wave data is greater than the preset collection time, for example, greater than 1 hour, 8 hours, etc.

[0100] Alternatively, the amount of the verified accumulated data or the discrete sine wave data is greater than a preset data amount, for example, greater than 3.5 TB or greater than 10 TB.

[0101] Specifically, the preset collection duration and the preset data volume can be configured according to business needs.

[0102] For the verification of sine wave data, the verification algorithm also requires the user to configure the board sampling rate and signal frequency Two parameters are used to calculate the number of points N in each cycle of discrete sine wave data.

[0103] For details, please refer to Figure 3 In the performance test method of the data acquisition system described in the embodiment of the present application, judging whether the discrete sine wave data received by the second DDR module and the storage module is continuous based on the discrete sine wave data and the configured first data verification rule includes the following steps S301-S303:

[0104] S301, based on the properties of the acquisition board, configure the board sampling rate and signal frequency;

[0105] S302, based on the sampling rate and signal frequency of the board, determining a verification threshold corresponding to the difference between adjacent data in the discrete sine wave data output by the ADC module of the acquisition board;

[0106] S303: When the absolute value of the difference between adjacent data in the discrete sine wave data does not exceed the verification threshold, it is determined that the adjacent data are continuous.

[0107] Based on the sampling rate and signal frequency of the board, determining the verification threshold corresponding to the difference between adjacent data in the discrete sine wave data output by the ADC module of the acquisition board, including:

[0108] Calculate the number of points N of each cycle of the discrete sine wave data based on the board sampling rate and the signal frequency;

[0109] Determine the maximum and minimum values ​​of the signal amplitude of discrete sine wave data within a complete sine wave cycle;

[0110] The verification threshold is calculated based on the distance between the two most distant adjacent points in the sine wave discrete into N points, the maximum and minimum values ​​of the signal amplitude of the discrete sine wave data, and the reference tolerance.

[0111] Based on the sampling rate of the board and the signal frequency, the number of points N of each cycle of the discrete sine wave data is calculated; specifically, the number of points N is calculated based on the following formula (1):

[0112] , (1);

[0113] Wherein, N represents the number of points in each cycle of discrete sine wave data; Characterize the sampling rate of the board; Characterizes the signal frequency.

[0114] Take the first N points of the data, find the maximum value (max) and minimum value (min) of the signal amplitude of the discrete sine wave data within a complete cycle, and calculate the initial threshold according to the following formula (2): .

[0115] , (2);

[0116] Among them, the represents the calculated initial threshold, N represents the number of points in each cycle of the discrete sine wave data, Characterizes the maximum value of the signal amplitude of discrete sine wave data within a complete sine wave cycle. Characterizes the minimum value of the signal amplitude of discrete sine wave data within a complete sine wave cycle.

[0117] Based on the reference tolerance of 10% to 30%, the initial threshold Increase by 10% to 30% as the verification threshold, which is the basis for judging the continuity of discrete sine wave data.

[0118] When performing data verification specifically, when the absolute value of the difference between the data in the discrete sine wave data and the next data does not exceed the verification threshold, the adjacent data is considered to be continuous at the current position, and the absolute value of the difference between the next adjacent data is compared; when the absolute value of the difference between the adjacent data exceeds the verification threshold, the current data is considered to be discontinuous, and the position index of the current data is recorded in the log for subsequent viewing, and then the absolute value of the difference between the next adjacent data is compared until all data verification is completed to obtain the first verification result.

[0119] The first verification result includes the number of abnormal data verified and the location index of the abnormal data.

[0120] When the number of abnormal data verified in the first verification result is greater than a first number threshold, the first verification result is determined to be abnormal; otherwise, the first verification result is determined to be normal.

[0121] The first quantity threshold may be determined based on a user's business needs.

[0122] The following analysis determines the reasons for the above verification threshold.

[0123] If it is sine wave data, the signal frequency of the sine wave It is a parameter configured by the user in the host computer software. First, obtain the amount of data in one cycle. Generally, the data bit width of the sine wave signal is processed as no more than 16 bits, so there is no need to consider data with a larger bit width, such as 20 bits / 24 bits.

[0124] According to the sine wave formula, substitute the general sine wave formula (3):

[0125] , (3);

[0126] in, represents a sine wave, is the signal amplitude, is the initial phase of the signal, is the signal bias, Characterizes the signal frequency.

[0127] Please refer to Figure 4 , Figure 4 The scatter plot after the sine wave signal is normalized is shown in the embodiment of the present application; after the sine wave signal is normalized, the scatter plot is as follows Figure 4 As shown, the difference between the dotted lines is the difference between two adjacent data.

[0128] like Figure 4 As shown, it is determined that the absolute value of the difference between adjacent data near the y=0 axis is the largest, that is Figure 4The difference between the two thick dashed lines is the largest. The calculation formula is as follows (4):

[0129] , (4)

[0130] Then, based on the following formula (5), this normalized difference is converted into the maximum difference between adjacent data of the actual signal: for:

[0131] , (5);

[0132] Wherein, N represents the number of points in each cycle of discrete sine wave data, is the signal amplitude, that is, ; is the maximum difference between adjacent data of the actual sine wave signal, that is, the initial threshold calculated in formula (2).

[0133] Afterwards, this The value is appropriately enlarged by 10%~30% as the verification threshold for sine wave data comparison, which can be used as the basis for subsequent data comparison.

[0134] Please refer to Figure 5 , based on the accumulated data and the configured second data verification rule, determining whether the accumulated data received by the second DDR module and the storage module are continuous, including the following steps S501-S503:

[0135] S501, configuring the data bit width in the first data verification rule based on the bit width of the accumulated data generated by the FPGA;

[0136] S502, for accumulated data with a bit width of 8 bits or 16 bits, processing the accumulated data into corresponding integers, judging whether the difference between the integers corresponding to adjacent data in the accumulated data is 1, and determining whether the adjacent data are continuous;

[0137] S503. For 32-bit and 64-bit accumulated data, based on a preset adjacent data comparison rule, compare the byte arrays of adjacent data to determine whether the adjacent data are continuous; wherein the preset adjacent data comparison rule is determined based on the characteristics of the byte array corresponding to the 32-bit or 64-bit data with a difference of 1.

[0138] When verifying the accumulated data, take out the first two values ​​of the data and determine whether the difference between the latter data and the former data is 1. If the difference is 1, continue to compare the second and third numbers; otherwise, record the index of the current position in the log for subsequent viewing, and then continue to compare the subsequent data until all data verification is completed.

[0139] Similarly, the second verification result includes the number of abnormal data verified and the location index of the abnormal data.

[0140] When the number of abnormal data verified in the second verification result is greater than a second number threshold, the second verification result is determined to be abnormal; otherwise, the second verification result is determined to be normal.

[0141] The second quantity threshold may be determined based on a user's business needs.

[0142] If it is an accumulated signal, determine whether the difference between adjacent signals is 1. The data is judged according to the four data bit widths of 8 / 16 / 32 / 64 bits. The data bit width is obtained by the host computer software through user configuration. For 8-bit or 16-bit data, the byte splicing speed is fast, and the accumulated data is processed into corresponding integers to obtain the true value; for 32-bit or 64-bit data, the byte splicing is relatively slow, and comparing after splicing will delay the overall verification speed. Therefore, for 32-bit and 64-bit accumulated data, the byte arrays are directly compared.

[0143] Compare the byte arrays of adjacent data to determine whether the adjacent data are continuous; wherein the preset adjacent data comparison rule is determined based on the characteristics of the byte array corresponding to the 32-bit or 64-bit data with a difference of 1. Specifically, analyze the characteristics of the byte array corresponding to the data with a difference of 1. Except for the last byte with a difference of 1, the other bytes are the same. When 0xFF is encountered, the number of digits of the difference value increases by one.

[0144] The following example uses int32-bit wide accumulated data.

[0145] For uint32-bit-wide accumulated data, take two adjacent byte arrays char1[4] and char2[4], each containing 4 bytes. These 4 bytes form a uint32 accumulated data. Compare these two byte arrays according to the following steps A1-A4 to get the result.

[0146] A1. Determine whether the first byte of char1 is 0xFF. If so, proceed to step A2. Otherwise, determine whether the difference between the first bytes of char1 and char2 is 1, and the other bytes are all the same. If so, the two adjacent uint32 accumulated numbers are continuous and there is no abnormality. Otherwise, an abnormality occurs here and the comparison ends.

[0147] A2. Continue to determine whether the second byte of char1 is 0xFF. If so, proceed to step A3. Otherwise, determine whether the difference between the first and second bytes of char1 and char2 is 1, and the other bytes are all the same. If so, the two adjacent uint32 accumulated numbers are continuous and there is no abnormality. Otherwise, an abnormality occurs here and the comparison ends.

[0148] A3. Continue to determine whether the third byte of char1 is 0xFF. If so, proceed to step A4. Otherwise, determine whether the difference between the first three bytes of char1 and char2 is 1, and the other bytes are all the same. If so, the two adjacent uint32 accumulated numbers are continuous and there is no abnormality. Otherwise, an abnormality occurs here and the comparison ends.

[0149] A4. Continue to determine whether the fourth byte of char1 is 0xFF. If so, determine whether the differences corresponding to the four bytes of char1 and char2 are all 1. If so, the two adjacent uint32 accumulated numbers are continuous and there is no abnormality. Otherwise, an abnormality occurs here and the comparison ends.

[0150] In the step S105, a performance test result of the data acquisition system is determined based on the first verification result and the second verification result.

[0151] Specifically, when both the first verification result and the second verification result are normal, determining that the performance test result of the data acquisition system is normal;

[0152] When the first verification result or the second verification result is abnormal, it is determined that the performance test result of the data acquisition system is abnormal.

[0153] In the step S106, when the performance test result is abnormal, the abnormal point of the data acquisition system is located based on the first verification result and the second verification result.

[0154] Locating abnormal points of the data acquisition system based on the first verification result and the second verification result includes:

[0155] When it is determined based on the second verification result that the transmission process of data from the FPGA module to the second DDR module is abnormal, determining that the abnormal point is located between the FPGA module and the second DDR module;

[0156] When it is determined based on the second verification result that the transmission process of data from the FPGA module to the second DDR module is normal and the transmission process from the FPGA module to the storage module is abnormal, it is determined that the abnormal point is located between the second DDR module and the storage module;

[0157] When the second verification result is normal and the first verification result is abnormal, it is determined that the abnormal point is located between the analog front end and the FPGA module.

[0158] When it is determined that the abnormal point is located between the FPGA module and the second DDR module, it may be that the FPGA module is abnormal, the first DDR module is abnormal, the interface between the CPU module and the FPGA module is abnormal, or the second DDR module is abnormal.

[0159] When it is determined that the abnormal point is located between the second DDR module and the storage module, it may be that the second DDR module is abnormal or a storage module such as a hard disk / storage array SSD is abnormal.

[0160] It is determined that the abnormal point is located between the analog front end and the FPGA module. It may be an abnormality in the ADC module, the FPGA module, the ADC module, the interface between the FPGA modules, the bus, etc.

[0161] Based on this, the performance testing method of the data acquisition system described in the embodiment of the present application performs a long-term integrity and correctness check on the data itself being transmitted, rather than intercepting a continuous time segment of the transmitted data (such as the beginning, middle, end or fixed feature position) for analysis, thereby determining whether the performance test results of the data acquisition system are reliable during the transmission of long-term and massive data based on the verification results.

[0162] In a data acquisition system, using the performance testing method of the data acquisition system described in the embodiment of the present application, data anomalies can be detected at a speed of at least 1GB / s, supporting real-time verification, verifying the continuity and integrity of the data, and verifying the reliability of the communication interface between the computer and the data acquisition and playback board: PCIe / Ethernet / USB interface communication.

[0163] Based on the same inventive concept, an embodiment of the present application also provides a performance testing method device for a data acquisition system corresponding to the performance testing method for a data acquisition system. Since the principle of solving the problem by the device in the embodiment of the present application is similar to the performance testing method for the data acquisition system in the embodiment of the present application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0164] Please refer to Figure 6 , Figure 6 The structural schematic diagram of the performance test device of the data acquisition system described in the embodiment of the present application is shown; the performance test device of the data acquisition system is applied to the data acquisition system, and the data acquisition system includes: an acquisition board, a host computer, and an input device; the acquisition board includes an ADC module, an FPGA module, and a first DDR module; the host computer includes a CPU module, a second DDR module, and a storage module; the input device is connected to the host computer; the performance test device includes:

[0165] The acquisition module 601 is used to enable the ADC module of the acquisition board to acquire the sine wave signal input by the analog front end and output digital discrete sine wave data, and the discrete sine wave data is transmitted to the storage module through the FPGA module, the first DDR module, the CPU module, and the second DDR module;

[0166] A generating module 602 is used to enable the FPGA module to generate accumulated data, and the accumulated data is transmitted to the storage module through the first DDR module, the CPU module, and the second DDR module;

[0167] The first judgment module 603 is used to judge whether the discrete sine wave data received by the second DDR module and the storage module is continuous based on the discrete sine wave data and the configured first data verification rule when the preset test condition is met, and determine a first verification result; wherein the first verification result indicates whether the transmission process from the analog front end to the second DDR module and the storage module is abnormal;

[0168] A second judgment module 604 is used to judge whether the accumulated data received by the second DDR module and the storage module are continuous based on the accumulated data and the configured first data verification rule, and determine a second verification result; wherein the second verification result indicates whether the transmission process from the FPGA module to the second DDR module and the storage module is abnormal;

[0169] A determination module 605 determines a performance test result of the data acquisition system based on the first verification result and the second verification result;

[0170] The positioning module 606 is used to locate the abnormal point of the data acquisition system based on the first verification result and the second verification result when the performance test result is abnormal.

[0171] In some embodiments, in the performance test device for the data acquisition system, the determination module, when determining the performance test result of the data acquisition system based on the first verification result and the second verification result, is specifically used to:

[0172] When both the first verification result and the second verification result are normal, determining that the performance test result of the data acquisition system is normal;

[0173] When the first verification result or the second verification result is abnormal, it is determined that the performance test result of the data acquisition system is abnormal.

[0174] In some embodiments, in the performance testing device for the data acquisition system, the determination module, when locating an abnormal point of the data acquisition system based on the first verification result and the second verification result, is specifically used to:

[0175] When it is determined based on the second verification result that the transmission process of data from the FPGA module to the second DDR module is abnormal, determining that the abnormal point is located between the FPGA module and the second DDR module;

[0176] When it is determined based on the second verification result that the transmission process of data from the FPGA module to the second DDR module is normal and the transmission process from the FPGA module to the storage module is abnormal, it is determined that the abnormal point is located between the second DDR module and the storage module;

[0177] When the second verification result is normal and the first verification result is abnormal, it is determined that the abnormal point is located between the analog front end and the FPGA module.

[0178] In some embodiments, the performance testing device of the data acquisition system first generates accumulated data through the FPGA module to determine a second verification result;

[0179] When the second verification result is normal, the sine wave signal input by the analog front end is collected by the ADC module of the acquisition board, and digitized discrete sine wave data is output to determine the first verification result.

[0180] In some embodiments, in the performance test device of the data acquisition system, the acquisition module, when enabling the ADC module of the acquisition board to acquire the sine wave signal input by the analog front end and outputting digitized discrete sine wave data, and the discrete sine wave data is transmitted to the storage module through the FPGA module, the first DDR module, the CPU module, and the second DDR module, is specifically used to:

[0181] The ADC module of the acquisition board acquires the sine wave signal input by the analog front end, and outputs digitized discrete sine wave data to the FPGA module. The FPGA module receives the discrete sine wave data and stores it in the first DDR module mounted on the FPGA module.

[0182] The CPU module of the host computer reads the discrete sine wave data in the first DDR module mounted on the FPGA, and caches the discrete sine wave data in the second DDR module mounted on the CPU module;

[0183] The second DDR module of the host computer interacts with the storage module to store the discrete sine wave data into the storage module.

[0184] In some embodiments, in the performance test device of the data acquisition system, the generation module enables the FPGA module to generate accumulated data, and the accumulated data is transmitted to the storage module through the first DDR module, the CPU module, and the second DDR module, specifically for:

[0185] The FPGA module replaces the discrete digital signal data with accumulated data having an accumulation rule, and stores the accumulated data into a first DDR module mounted on the FPGA module;

[0186] The CPU module of the host computer reads the accumulated data in the first DDR module mounted on the FPGA, and caches the accumulated data in the second DDR module mounted on the CPU module;

[0187] The second DDR module of the host computer interacts with the storage module to store the accumulated data into the storage module.

[0188] In some embodiments, in the performance test device of the data acquisition system, the first judgment module, when judging whether the discrete sine wave data received by the second DDR module and the storage module is continuous based on the discrete sine wave data and the configured first data verification rule, is specifically used to:

[0189] Based on the properties of the acquisition board, configure the board sampling rate and signal frequency;

[0190] Based on the sampling rate and signal frequency of the board, a check threshold corresponding to the difference between adjacent data in the discrete sine wave data output by the ADC module of the acquisition board is determined;

[0191] When the absolute value of the difference between adjacent data in the discrete sine wave data does not exceed the verification threshold, it is determined that the adjacent data are continuous.

[0192] In some embodiments, in the performance test device of the data acquisition system, the first judgment module, when determining the verification threshold corresponding to the difference between adjacent data in the discrete sine wave data output by the ADC module of the acquisition board based on the board sampling rate and the signal frequency, is specifically used to:

[0193] Calculate the number of points N of each cycle of the discrete sine wave data based on the board sampling rate and the signal frequency;

[0194] Determine the maximum and minimum values ​​of the signal amplitude of discrete sine wave data within a complete sine wave cycle;

[0195] The verification threshold is calculated based on the distance between the two most distant adjacent points in the sine wave discrete into N points, the maximum and minimum values ​​of the signal amplitude of the discrete sine wave data, and the reference tolerance.

[0196] In some embodiments, in the performance test device of the data acquisition system, the second judgment module, when judging whether the accumulated data received by the second DDR module and the storage module are continuous based on the accumulated data and the configured second data verification rule, is specifically used to:

[0197] Based on the bit width of the accumulated data generated by the FPGA, configure the data bit width in the first data verification rule;

[0198] For accumulated data with a bit width of 8 bits or 16 bits, the accumulated data is processed into corresponding integers, and it is determined whether the difference between the integers corresponding to adjacent data in the accumulated data is 1, so as to determine whether the adjacent data are continuous;

[0199] For 32-bit and 64-bit accumulated data, based on the preset adjacent data comparison rule, the byte arrays of adjacent data are compared to determine whether the adjacent data are continuous; wherein the preset adjacent data comparison rule is determined based on the characteristics of the byte array corresponding to the 32-bit or 64-bit data with a difference of 1.

[0200] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0201] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0202] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0203] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a platform server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0204] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A performance testing method for a data acquisition system, characterized in that: Applied to a data acquisition system, the data acquisition system comprises: an acquisition board, a host computer, and an input device; the acquisition board comprises an ADC module, an FPGA module, and a first DDR module; the host computer comprises a CPU module, a second DDR module, and a storage module; the input device is connected to the host computer; the performance test method comprises: The ADC module of the acquisition board collects the sine wave signal input by the analog front end and outputs digital discrete sine wave data, and the discrete sine wave data is transmitted to the storage module through the FPGA module, the first DDR module, the CPU module, and the second DDR module; The FPGA module generates accumulated data, and the accumulated data is transmitted to the storage module through the first DDR module, the CPU module, and the second DDR module; Based on the discrete sine wave data and the configured first data verification rule, determine whether the discrete sine wave data received by the second DDR module and the storage module is continuous, and determine a first verification result; wherein the first verification result indicates whether the transmission process from the analog front end to the second DDR module and the storage module is abnormal; Based on the accumulated data and the configured second data verification rule, determine whether the accumulated data received by the second DDR module and the storage module are continuous, and determine a second verification result; wherein the second verification result indicates whether the transmission process from the FPGA module to the second DDR module and the storage module is abnormal; Determining a performance test result of the data acquisition system based on the first verification result and the second verification result; When the performance test result is abnormal, locating the abnormal point of the data acquisition system based on the first verification result and the second verification result; Locating abnormal points of the data acquisition system based on the first verification result and the second verification result includes: When it is determined based on the second verification result that the transmission process of data from the FPGA module to the second DDR module is abnormal, determining that the abnormal point is located between the FPGA module and the second DDR module; When it is determined based on the second verification result that the transmission process of data from the FPGA module to the second DDR module is normal and the transmission process from the FPGA module to the storage module is abnormal, it is determined that the abnormal point is located between the second DDR module and the storage module; When the second verification result is normal and the first verification result is abnormal, it is determined that the abnormal point is located between the analog front end and the FPGA module.

2. The performance testing method of the data acquisition system according to claim 1, characterized in that: Determining a performance test result of the data acquisition system based on the first verification result and the second verification result includes: When both the first verification result and the second verification result are normal, determining that the performance test result of the data acquisition system is normal; When the first verification result or the second verification result is abnormal, it is determined that the performance test result of the data acquisition system is abnormal.

3. The performance testing method of the data acquisition system according to claim 1, characterized in that: The performance testing method also includes: First, the FPGA module generates accumulated data to determine a second verification result; When the second verification result is normal, the sine wave signal input by the analog front end is collected by the ADC module of the acquisition board, and digitized discrete sine wave data is output to determine the first verification result.

4. The performance testing method of the data acquisition system according to claim 1, characterized in that: The ADC module of the acquisition board collects the sine wave signal input by the analog front end and outputs digital discrete sine wave data, and the discrete sine wave data is transmitted to the storage module through the FPGA module, the first DDR module, the CPU module, and the second DDR module, including: The ADC module of the acquisition board acquires the sine wave signal input by the analog front end, and outputs digitized discrete sine wave data to the FPGA module. The FPGA module receives the discrete sine wave data and stores it in the first DDR module mounted on the FPGA module. The CPU module of the host computer reads the discrete sine wave data in the first DDR module mounted on the FPGA, and caches the discrete sine wave data in the second DDR module mounted on the CPU module; The second DDR module of the host computer interacts with the storage module to store the discrete sine wave data into the storage module.

5. The performance testing method of the data acquisition system according to claim 1, characterized in that: The FPGA module generates accumulated data, and the accumulated data is transmitted to the storage module through the first DDR module, the CPU module, and the second DDR module, including: The FPGA module replaces the discrete digital signal data with accumulated data having an accumulation rule, and stores the accumulated data into a first DDR module mounted on the FPGA module; The CPU module of the host computer reads the accumulated data in the first DDR module mounted on the FPGA, and caches the accumulated data in the second DDR module mounted on the CPU module; The second DDR module of the host computer interacts with the storage module to store the accumulated data into the storage module.

6. The performance testing method of the data acquisition system according to claim 1, characterized in that: Based on the discrete sine wave data and the configured first data verification rule, determining whether the discrete sine wave data received by the second DDR module and the storage module is continuous includes: Based on the properties of the acquisition board, configure the board sampling rate and signal frequency; Based on the sampling rate and signal frequency of the board, a check threshold corresponding to the difference between adjacent data in the discrete sine wave data output by the ADC module of the acquisition board is determined; When the absolute value of the difference between adjacent data in the discrete sine wave data does not exceed the verification threshold, it is determined that the adjacent data are continuous.

7. The performance testing method of the data acquisition system according to claim 6, characterized in that: Based on the sampling rate and signal frequency of the board, determining the verification threshold corresponding to the difference between adjacent data in the discrete sine wave data output by the ADC module of the acquisition board, including: Calculate the number of points N of each cycle of the discrete sine wave data based on the board sampling rate and the signal frequency; Determine the maximum and minimum values ​​of the signal amplitude of discrete sine wave data within a complete sine wave cycle; The verification threshold is calculated based on the distance between the two most distant adjacent points in the sine wave discrete into N points, the maximum and minimum values ​​of the signal amplitude of the discrete sine wave data, and the reference tolerance.

8. The performance testing method of the data acquisition system according to claim 1, characterized in that: Based on the accumulated data and the configured second data verification rule, determining whether the accumulated data received by the second DDR module and the storage module are continuous includes: Based on the bit width of the accumulated data generated by the FPGA, configure the data bit width in the second data verification rule; For accumulated data with a bit width of 8 bits or 16 bits, the accumulated data is processed into corresponding integers, and it is determined whether the difference between the integers corresponding to adjacent data in the accumulated data is 1, so as to determine whether the adjacent data are continuous; For 32-bit and 64-bit accumulated data, based on the preset adjacent data comparison rule, the byte arrays of adjacent data are compared to determine whether the adjacent data are continuous; wherein the preset adjacent data comparison rule is determined based on the characteristics of the byte array corresponding to the 32-bit or 64-bit data with a difference of 1.

9. A performance test device for a data acquisition system, characterized in that: Applied to a data acquisition system, the data acquisition system comprises: an acquisition board, a host computer, and an input device; the acquisition board comprises an ADC module, an FPGA module, and a first DDR module; the host computer comprises a CPU module, a second DDR module, and a storage module; the input device is connected to the host computer; the performance test device comprises: An acquisition module, used to enable the ADC module of the acquisition board to acquire the sine wave signal input by the analog front end and output digital discrete sine wave data, and the discrete sine wave data is transmitted to the storage module through the FPGA module, the first DDR module, the CPU module, and the second DDR module; A generating module, used to enable the FPGA module to generate accumulated data, and the accumulated data is transmitted to the storage module through the first DDR module, the CPU module, and the second DDR module; A first judgment module is used to judge whether the discrete sine wave data received by the second DDR module and the storage module is continuous based on the discrete sine wave data and the configured first data verification rule when a preset test condition is met, and determine a first verification result; wherein the first verification result indicates whether the transmission process from the analog front end to the second DDR module and the storage module is abnormal; A second judgment module is used to judge whether the accumulated data received by the second DDR module and the storage module are continuous based on the accumulated data and the configured second data verification rule, and determine a second verification result; wherein the second verification result indicates whether the transmission process from the FPGA module to the second DDR module and the storage module is abnormal; A determination module, which determines a performance test result of the data acquisition system based on the first verification result and the second verification result; A positioning module, configured to locate an abnormal point of the data acquisition system based on the first verification result and the second verification result when the performance test result is abnormal; The determination module, when locating the abnormal point of the data acquisition system based on the first verification result and the second verification result, is specifically used to: When it is determined based on the second verification result that the transmission process of data from the FPGA module to the second DDR module is abnormal, determining that the abnormal point is located between the FPGA module and the second DDR module; When it is determined based on the second verification result that the transmission process of data from the FPGA module to the second DDR module is normal and the transmission process from the FPGA module to the storage module is abnormal, it is determined that the abnormal point is located between the second DDR module and the storage module; When the second verification result is normal and the first verification result is abnormal, it is determined that the abnormal point is located between the analog front end and the FPGA module.

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