A reconfigurable encryption circuit and image encryption method based on reconfigurable unit

Abstract

The present invention discloses an encryption circuit and an image encryption method based on a reconfigurable memristor, belonging to the field of integrated circuit design. The encryption circuit comprises a reconfigurable unit and a true random number generation circuit. The reconfigurable unit comprises a first reconfigurable memristor, a second reconfigurable memristor, and an N-type transistor. The first reconfigurable memristor and the second reconfigurable memristor are connected in reverse parallel and then in series with the N-type transistor. Exclusive OR logic operations can be implemented. The true random number generation circuit uses the reconfigurable unit as a random source and comprises a comparator and a 1-bit counter connected in series. The present invention simplifies the design of the encryption circuit, reduces occupied space, and improves system utilization.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and in particular relates to an encryption circuit and an image encryption method based on a reconfigurable memristor. Background Art

[0002] Hardware encryption, which encrypts data using a dedicated hardware module, is a more secure means of information protection. Compared to software encryption, hardware encryption offers significant advantages. First, hardware encryption effectively resists physical and logical attacks, such as tampering, reverse engineering, and side-channel attacks, thereby ensuring the security of the encryption process. Second, hardware encryption utilizes dedicated hardware resources, enabling faster encryption processing and improving encryption and decryption efficiency. Furthermore, hardware encryption addresses the inherent security risks and efficiency issues of software encryption, providing a more reliable solution to critical encryption issues. Therefore, hardware encryption plays a vital role in protecting important data and ensuring information security.

[0003] Memristors, with their low power consumption, high durability, fast switching performance, simple structure, and compatibility with CMOS processes, have become the preferred alternative to traditional CMOS technology for implementing hardware encryption circuits. This significantly improves the energy efficiency and robustness of hardware encryption circuits and expands their applicability in various application scenarios, particularly for mobile devices and IoT devices that require high security and high performance. Furthermore, these advantages of memristors inject greater flexibility and scalability into circuit design, ensuring that hardware encryption solutions can more flexibly respond to evolving security challenges and performance standards.

[0004] In hardware encryption, traditional encryption algorithms such as AES (Advanced Encryption Standard) and RSA are widely used, but they typically require complex hardware design and significant computing resources. In contrast, the exclusive OR (XOR) operation, as a simple logical operation, has found widespread application in the encryption field due to its high performance and ease of implementation. The XOR operation can be used to quickly encrypt and decrypt data while maintaining good security. However, the XOR operation alone does not provide sufficient security, as an attacker who can obtain the encryption key can easily decrypt the data. To enhance security, a high-quality random number generator (TRNG) is required to generate encryption keys. A true random number generator (TRNG) generates unpredictable random numbers based on physical phenomena, providing higher security and attack resistance. Therefore, hardware encryption circuits combining the XOR operation and TRNG have become an ideal solution. However, since XOR logic circuits often utilize the non-volatile storage properties of memristors, while TRNG circuits often exploit the random properties associated with volatile storage, no memristor has yet been discovered or developed that can simultaneously meet the different performance requirements of these two circuits. This means that in practical applications, two different memristor modules need to be designed, one for the XOR operation and the other for the TRNG function. This not only increases the complexity and cost of the circuit, but also limits the potential of memristors in multifunctional integrated systems. Summary of the Invention

[0005] In view of the deficiencies in the prior art, the purpose of the present invention is to provide an encryption circuit and an image encryption method based on a reconfigurable memristor, which solve the problems in the prior art.

[0006] The purpose of the present invention can be achieved through the following technical solutions:

[0007] A reconfigurable memristor-based encryption circuit includes a reconfigurable unit and a true random number generation circuit; the reconfigurable unit includes a first reconfigurable memristor, a second reconfigurable memristor, and an N-type transistor; the first reconfigurable memristor and the second memristor are reconfigurably connected in reverse parallel and then in series with the N-type transistor; the negative terminal of the first reconfigurable memristor is connected to the drain of the N-type transistor, the positive terminal of the first reconfigurable memristor is connected to an input voltage, the positive terminal of the second reconfigurable memristor is connected to the drain of the N-type transistor, the negative terminal of the second reconfigurable memristor is connected to the input voltage, and the gate of the N-type transistor is connected to a control voltage;

[0008] The true random number generation circuit uses a reconfigurable unit as a random source, including: a comparator and a 1-bit counter connected in series; the source of the N-type transistor is connected to the positive end of the comparator and then to the CLK end of the 1-bit counter, and the negative end of the comparator is connected to a reference voltage.

[0009] Furthermore, when the reconfigurable memristor is in a volatile storage state, the positive end of the first reconfigurable memristor and the negative end of the second reconfigurable memristor in the reconfigurable unit are used as input ends, and the source of the N-type transistor is used as an output end;

[0010] When the source voltage of the N-type transistor exceeds the reference voltage, the comparator outputs a logic high level, selects the pulse width and amplitude of the CLR signal, and sends the value output by the comparator to a 1-bit counter. At the end of each input pulse, the output of the 1-bit counter represents the key used for image encryption.

[0011] The generated key is input into the positive end of the first reconfigurable memristor and the negative end of the second reconfigurable memristor in the reconfigurable unit, the image to be encrypted is input into the source of the N-type transistor, and the total resistance of the first reconfigurable memristor and the second reconfigurable memristor in parallel is taken as the output value after image encryption.

[0012] An image encryption method, using the above-mentioned reconfigurable encryption circuit based on a reconfigurable unit, comprises the following steps:

[0013] S1, convert the image into a binary image;

[0014] S2, uses a true random number generation circuit to generate a key to encrypt the image;

[0015] S3, input the converted binary image into the positive end of the first reconfigurable memristor and the negative end of the second reconfigurable memristor in the reconfigurable unit, input the generated key into the source of the N-type transistor, and take the total resistance of the first reconfigurable memristor and the second reconfigurable memristor in parallel as the output value after image encryption.

[0016] The above-mentioned reconfigurable encryption circuit based on reconfigurable units is applied in image, number and letter encryption.

[0017] The above-mentioned reconfigurable encryption circuit based on reconfigurable units is applied in image, number and letter decryption.

[0018] An image encryption system includes the above-mentioned reconfigurable encryption circuit based on a reconfigurable unit.

[0019] A reconfigurable unit includes: a first reconfigurable memristor, a second reconfigurable memristor, and an N-type transistor; the first reconfigurable memristor and the second memristor are reconfigurable and connected in reverse parallel and then in series with the N-type transistor; the negative end of the first reconfigurable memristor is connected to the drain of the N-type transistor, the positive end of the first reconfigurable memristor is connected to the input voltage, the positive end of the second reconfigurable memristor is connected to the drain of the N-type transistor, the negative end of the second reconfigurable memristor is connected to the input voltage, and the gate of the N-type transistor is connected to a control voltage.

[0020] Beneficial effects of the present invention:

[0021] 1. The reconfigurable memristor used in the present invention can realize not only volatile storage but also non-volatile storage by applying a large current or a small current to the memristor.

[0022] 2. The reconfigurable unit proposed in this invention can implement XOR logic operations through the non-volatile memory of the reconfigurable memristor. It can also use the random characteristics of the volatile memory of the reconfigurable memristor as a random source for the TRNG circuit. This increases the potential for the application of memristors in multifunctional integrated systems.

[0023] 3. The encryption circuit of the present invention integrates the two different memristor modules required by the XOR circuit and the TRNG circuit into a multifunctional memristor module (reconfigurable unit), which simplifies the circuit design, reduces costs, reduces occupied space, and improves system utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1 is a schematic structural diagram of the reconfigurable unit of the present invention;

[0026] Figure 2 It is a schematic diagram of the structure of the reconfigurable unit XOR logic circuit of the present invention;

[0027] Figure 3 It is the reconfigurable unit XOR logic analysis table of the present invention;

[0028] Figure 4 It is a schematic diagram of the overall structure of the encryption circuit of the present invention;

[0029] Figure 5 It is a schematic diagram of the image encryption and decryption process of the encryption circuit of the present invention. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0031] Example 1

[0032] like Figure 1 As shown, the reconfigurable unit includes a first reconfigurable memristor, a second reconfigurable memristor and an N-type transistor. The first reconfigurable memristor and the second reconfigurable memristor are connected in reverse parallel and then in series with the N-type transistor. The negative end of the first reconfigurable memristor is connected to the drain of the N-type transistor, the positive end of the first memristor is connected to the input voltage V1, the positive end of the second reconfigurable memristor is connected to the drain of the N-type transistor, the negative end of the second reconfigurable memristor is connected to the input voltage V2, and the gate of the N-type transistor is connected to the control voltage V c , the source is connected to the input voltage V3;

[0033] like Figure 1 As shown in ac, since the reconfigurable memristor is in volatile working mode at low current state and in non-volatile working mode at high current state, it can be switched by applying gate control voltage V c =V ch (high voltage) or V c =V cl (low voltage) to precisely control the working state of the reconfigurable memristor, such as Figure 1 As shown in d.

[0034] The reconfigurable unit performs exclusive OR (XOR) logic, such as Figure 2 As shown, the XOR operation process is as follows:

[0035] First, apply V to the gate voltage of the transistor ch The current is controlled to be large, so that the reconfigurable memristor is in a non-volatile programmable state. The RRAM is reset and the RRAM device is adjusted to a high-resistance state. The total resistance of the first reconfigurable memristor and the second reconfigurable memristor in parallel is read as the output logic value. The high-resistance state is logic '0' and the low-resistance state is logic '1'. Due to the different applied voltages V1 = V2 and V3, the total resistance of the two reconfigurable memristors in parallel changes. The specific XOR logic is as follows: Figure 3 As shown, the operation is as follows:

[0036] When V1=V2=0V, V3=0V, which corresponds to the situation of '0', '0', since the voltage drop between the first and second reconfigurable memristors is 0, the total resistance of the two reconfigurable memristors in parallel remains in a high impedance state, corresponding to the output "0".

[0037] When V1=V2=1V, V3=0V, this corresponds to the case of '1' and '0'. Since the voltage drop of the first reconfigurable memristor is -1V and the voltage drop of the second reconfigurable memristor is 1V, the first reconfigurable memristor is in a low-resistance state and the second reconfigurable memristor is in a high-resistance state. The total resistance of the two reconfigurable memristors in parallel is low-resistance, corresponding to the output "1".

[0038] When V1=V2=0V and V3=1V, which corresponds to the cases of '0' and '1', since the voltage drop of the first reconfigurable memristor is 1V and the voltage drop of the second reconfigurable memristor is -1V, the first reconfigurable memristor is in a high-resistance state and the second reconfigurable memristor is in a low-resistance state. The total resistance of the two reconfigurable memristors in parallel is a low-resistance state, corresponding to the output "1".

[0039] When V1=V2=1V, V3=1V, which corresponds to the case of '1', '1', since the voltage drop between the first and second reconfigurable memristors is 0, the total resistance of the two reconfigurable memristors in parallel remains in a high-impedance state, corresponding to the output of '0'.

[0040] like Figure 4 As shown, an encryption circuit based on a reconfigurable memristor includes a reconfigurable unit and a true random number generator (TRNG) circuit; wherein the TRNG circuit includes a comparator and a 1-bit counter connected in series, and the reconfigurable unit is used as a random source for the TRNG. The source of the NMOS transistor in the reconfigurable unit is connected to the positive terminal of the comparator, and the negative terminal of the comparator is input with a comparison voltage V ref The output of the comparator is connected to the clock terminal CLK of the 1-bit counter, the re-made signal is input from the CLR terminal, and the QA terminal is taken as the output signal.

[0041] The operation process of the true random number generator (TRNG) is as follows:

[0042] First, a voltage V is applied to the gate of the N-type transistor. cl When the current is controlled to be small (V cl ) makes the memristor work in a random state where the volatile conductive filament forms a broken state, and uses the positive terminal (V1) of the first reconfigurable memristor and the negative terminal (V2) of the second reconfigurable memristor in the reconfigurable unit as inputs, and the source (V3) of the N-type transistor as output; due to the volatility of the reconfigurable memristor, when voltage is applied to the memristor, the resistance value of the memristor will change, but this change is not immediate, but there is a delay time. This delay time is uncertain due to the complex physical and chemical processes inside the memristor and can be regarded as a random source. Connect the source voltage of the N-type transistor in the reconfigurable unit (i.e., V3 voltage) to the positive terminal of the comparator in the TRNG and then to the CLK terminal of the 1-bit counter, and input the reference voltage V to the negative terminal of the comparator. ref If the source voltage of the N-type transistor in the reconfigurable unit (i.e., V3 voltage) exceeds V ref The comparator will output a logic high level, select the appropriate pulse width and amplitude of the CLR signal, and finally send the random value output by the comparator to a 1-bit counter. At the end of each input pulse, the output of the counter is the key for image encryption.

[0043] The operation process of the encryption circuit is as follows:

[0044] First, apply voltage V to the gate of the N-type transistor. cl When the current is kept low, the memristor operates in a state where the volatile conductive filaments form a random break. In the reconfigurable unit, a signal is input to the positive terminal (V1) of the first reconfigurable memristor and the negative terminal (V2) of the second reconfigurable memristor. The output of a 1-bit counter is used as the key for image encryption.

[0045] Then apply voltage V to the gate of the N-type transistor cl When the current is controlled to be large, the reconfigurable memristor is in a non-volatile programmable state. The image and key are respectively input to the positive terminal (V1=V2) of the first reconfigurable memristor and the source terminal (N3) of the N-type transistor, and the total resistance (R parallel ) as the output value after image encryption (i.e. the encrypted image). Using the same key, perform an XOR operation on the above process again to obtain the original image information (i.e. the decrypted image).

[0046] Example 2

[0047] In this embodiment, the process of encrypting and decrypting an image using the reconfigurable encryption circuit disclosed in Example 1 is described;

[0048] The steps of image encryption include:

[0049] S1, first use software to convert the image into a binary image, which corresponds to a binary matrix (m×n array);

[0050] S3, input the converted binary image into the positive terminal (V1) of the first memristor and the negative terminal (V2) of the second memristor in the reconfigurable unit (V1=V2), input the generated key into the source (V3) of the N-type transistor, and take the total resistance (R parallel ) as the output value after image encryption.

[0051] S2 uses TRNG to generate a key (m×n array) to encrypt the image.

[0052] In addition, the decryption process of the image only requires performing an XOR operation on the matrix generated after encryption and the matrix used during encryption, which is similar to the encryption process, to obtain the decrypted image.

[0053] The reconfigurable encryption circuit can also encrypt and decrypt letters; Figure 5As shown, let's take the letter sequence "U" as an example. Here, dark cells represent logical "1," while white cells represent logical "0." Therefore, the logical matrix representing the original letter "U" is [1001; 1001; 1001; 1111]. Furthermore, a TRNG is used to generate the key [1010; 0101; 1100; 1010]. The encryption mechanism for the array is simply the XOR of the two matrices above, with inputs from V1 = V2 and V3, respectively. The output is simply S = [0011; 1100; 0101; 0101]. This completes the encryption process.

[0054] The decryption process of the image is similar to the encryption process, which requires only performing an XOR operation on the matrix generated after encryption and the matrix used during encryption to obtain the decrypted image.

[0055] Throughout this specification, references to terms such as "one embodiment," "example," or "specific example" indicate that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0056] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely illustrative of the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention, and such changes and modifications fall within the scope of the invention as claimed.

Claims

1. An encryption circuit based on a reconfigurable memristor, characterized in that: The invention comprises a reconfigurable unit and a true random number generation circuit; the reconfigurable unit comprises a first reconfigurable memristor, a second reconfigurable memristor and an N-type transistor; the first reconfigurable memristor and the second reconfigurable memristor are reconfigurable to be connected in reverse parallel and then in series with the N-type transistor; the negative end of the first reconfigurable memristor is connected to the drain of the N-type transistor, the positive end of the first reconfigurable memristor is connected to the input voltage, the positive end of the second reconfigurable memristor is connected to the drain of the N-type transistor, the negative end of the second reconfigurable memristor is connected to the input voltage, and the gate of the N-type transistor is connected to the control voltage; The true random number generation circuit uses a reconfigurable unit as a random source, including: a comparator and a 1-bit counter connected in series; after the source of the N-type transistor is connected to the positive terminal of the comparator, the output terminal of the comparator is connected to the CLK terminal of the 1-bit counter, and the negative terminal of the comparator is connected to a reference voltage.

2. The encryption circuit based on a reconfigurable memristor according to claim 1, characterized in that: When the reconfigurable memristor is in a volatile storage state, the positive end of the first reconfigurable memristor and the negative end of the second reconfigurable memristor in the reconfigurable unit are used as input ends, and the source of the N-type transistor is used as an output end; When the source voltage of the N-type transistor exceeds the reference voltage, the comparator outputs a logic high level, selects the pulse width and amplitude of the CLR signal, and sends the value output by the comparator to a 1-bit counter. At the end of each input pulse, the output of the 1-bit counter represents the key used for image encryption. The generated key is input into the positive end of the first reconfigurable memristor and the negative end of the second reconfigurable memristor in the reconfigurable unit, the image to be encrypted is input into the source of the N-type transistor, and the total resistance of the first reconfigurable memristor and the second reconfigurable memristor in parallel is taken as the output value after image encryption.

3. An image encryption method, using a reconfigurable encryption circuit based on a reconfigurable unit according to any one of claims 1 to 2, characterized in that: The following steps are involved: S1, convert the image into a binary image; S2, uses a true random number generation circuit to generate a key to encrypt the image; S3, input the converted binary image into the positive end of the first reconfigurable memristor and the negative end of the second reconfigurable memristor in the reconfigurable unit, input the generated key into the source of the N-type transistor, and take the total resistance of the first reconfigurable memristor and the second reconfigurable memristor in parallel as the output value after image encryption.

4. Application of a reconfigurable encryption circuit based on a reconfigurable unit as described in any one of claims 1-2 in image, number and letter encryption.

5. Application of a reconfigurable encryption circuit based on a reconfigurable unit as described in any one of claims 1-2 in image, number and letter decryption.

6. An image encryption system, characterized in that: A reconfigurable encryption circuit based on a reconfigurable unit comprising any one of claims 1-2.

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