A method for checking parasitic matching of high-frequency differential lines in layout

Abstract

The invention discloses a method for checking parasitic matching of high-frequency differential lines in a layout, and relates to the technical field of integrated circuits. The method includes extracting corresponding GDS and CDL files, confirming the consistency of GDS and CDL through LVS verification; using StarRC software to set environmental parameters, dividing the layout through grid division technology, extracting parasitic parameters using StarRC, and generating parasitic files; searching for the netname of the differential line in the parasitic file to determine whether the parasitic parameters of the differential line meet the consistency requirements of the design; modifying the layout for inconsistent parasitic parameters; re-extracting GDS and CDL after modification, extracting and checking parasitic parameters; realizing the effect of quickly finding the parasitics of the corresponding differential line, performing segmented inspection, and accurately locating, and solving the problem of difficulty in accurately extracting and locating parasitic parameters in complex layouts.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a method for checking parasitic matching of high-frequency differential lines in a layout. Background Art

[0002] In integrated circuit design, high-speed differential lines are usually used to transmit high-speed data signals. They have the characteristics of strong anti-interference and high transmission rate, and are often widely used to transmit high-speed data signals. However, the parasitic parameter matching problem of high-frequency differential signals has an important impact on signal integrity and transmission performance. In the prior art, the method of extracting parasitic parameters through software such as StarRC has limitations, especially when there are many differential lines, long lengths or complex layouts, it becomes difficult to find and locate the problem. Summary of the invention

[0003] The purpose of the present invention is to provide a method for checking the parasitic matching of high-frequency differential lines in a layout, so as to quickly find the parasitics of the corresponding differential lines, perform segmented inspection, and accurately locate the problem.

[0004] The purpose of the present invention can be achieved through the following technical solutions:

[0005] The present application provides a method for checking parasitic matching of high-frequency differential lines in a layout, comprising the following steps:

[0006] Extract the corresponding GDS and CDL files, and verify the consistency of GDS and CDL through LVS verification;

[0007] Use StarRC software to set environmental parameters, including temperature range and process corners, divide the layout through meshing technology, extract parasitic parameters using StarRC, and generate parasitic files;

[0008] Search for the netname of the differential line in the parasitic file to determine whether the parasitic parameters of the differential line meet the consistency of the design requirements;

[0009] When it is determined that the parasitic parameters of the differential line do not meet the consistency of the design requirements, add two pins to the differential line on the layout and schematic, and add ideal resistors to the long traces to perform segmented search;

[0010] Modify the layout for inconsistent parasitic parameters, including layout adjustment, routing optimization, and adding fillers;

[0011] After modification, GDS and CDL are re-extracted to extract and check parasitic parameters.

[0012] Furthermore, extract the corresponding GDS and CDL files to verify the consistency between GDS and CDL, including:

[0013] Obtain and prepare GDS and CDL documents;

[0014] Load GDS and CDL files in the LVS tool, and configure technology files and rule files;

[0015] Use the LVS tool to extract the physical netlist of GDS and compare it with the logical netlist of CDL;

[0016] Generate LVS report based on comparison results, analyze differences in LVS report and make corrections, and confirm the consistency of GDS and CDL files.

[0017] Furthermore, the differences in the LVS report are analyzed and corrected. The LVS report is generated based on the comparison results, the type and location of each difference is identified, and corrections are made based on the type of difference, including:

[0018] Device correction: when there are missing devices in the physical netlist, add the corresponding devices in the layout according to the description in the logical netlist; when there are redundant devices in the physical netlist, delete or modify the devices in the layout according to the report; adjust the device parameters in the physical netlist by checking the device properties and the logical netlist;

[0019] Connection correction: when a connection is missing in the physical netlist, find the specific connection point of the connection in the logical netlist, modify the layout to add the connection point; when a connection is incorrectly connected in the physical netlist, find the correct connection point and modify it;

[0020] Attribute correction: by checking the attribute mismatch items listed in the LVS report, find the specific location of the corresponding device in the physical netlist, and adjust the attributes to match the logical netlist.

[0021] Furthermore, StarRC is used to extract parasitic parameters and generate parasitic files. Grids of different scales are used to capture global and local parasitic effects, including:

[0022] Perform a preliminary meshing of the entire layout in StarRC, using the mesh to capture the overall parasitic effects;

[0023] Apply StarRC’s global parameter extraction algorithm to the preliminary grid to calculate the parasitic parameters of the entire layout;

[0024] Generate and save the extracted parasitic resistance, capacitance, mutual capacitance, and coupling capacitance results as parasitic files.

[0025] Furthermore, the parasitic parameters of the entire layout are calculated, including extracting the resistance of the wires in each grid, extracting the capacitance between adjacent wires, and extracting the mutual capacitance and coupling capacitance for differential lines or interconnects;

[0026] Among them, the resistance of the wire in each grid is extracted, and the resistance is calculated using StarRC, which is expressed as: ;in, is the resistivity, is the wire length, is the cross-sectional area of ​​the conductor;

[0027] To calculate the capacitance between adjacent conductors, the formula is: ;in, is the dielectric constant, is the vacuum dielectric constant, B is the electrode area, and d is the electrode spacing;

[0028] Calculate the mutual capacitance and coupling capacitance of differential lines or interconnects. The mutual capacitance formula is: ; where k is the coupling coefficient that depends on the conductor geometry and arrangement, L is the conductor length, and g is the interconnect distance;

[0029] The coupling capacitance formula is: ;in, is the area of ​​the coupling region, is the coupling distance.

[0030] Furthermore, the netname of the differential line is searched in the parasitic file to determine whether the parasitic parameters of the differential line meet the consistency of the design requirements, including:

[0031] Open the generated parasitic file;

[0032] Search for the differential line netname in the parasitic file;

[0033] Check the values ​​of parasitic parameters corresponding to the searched differential lines;

[0034] For each record found, record all parasitic parameter values ​​related to netname, including resistance, capacitance, mutual capacitance, and coupling capacitance;

[0035] Compare the parasitic parameter values ​​with the expected parameter values ​​to determine whether the parasitic parameters of the differential line meet the consistency of the design requirements.

[0036] Furthermore, when the judgment results are inconsistent, segmented search is performed on the layout, including:

[0037] Use layout design tools to determine appropriate segmentation points on the differential lines based on the length of the differential lines and the expected parasitic parameter distribution;

[0038] Add test pins at selected locations of differential lines on the layout to analyze parasitic parameters of each segment independently, and add test pins at corresponding locations on the schematic;

[0039] On long traces, ideal resistors are added at specific locations according to the design to simulate and analyze the resistance distribution on the traces;

[0040] Use the parasitic parameter extraction tool to re-extract the modified layout, generate segmented parasitic files, analyze the parasitic parameters of each segment independently, and compare the differences between the parasitic parameters and the expected values;

[0041] According to the difference values ​​of the parasitic parameters of each segment, the location where the problem exists is determined.

[0042] Furthermore, the difference value of the parasitic parameters of each segment is calculated and compared with the expected value, specifically including:

[0043] ;

[0044] in, is the difference value, is the actual parameter value of the i-th segment, is the expected parameter value,

[0045] Set the deviation threshold when If the deviation threshold is exceeded, it is indicated as a significant deviation. >Threshold, indicating that there is a problem with the current segmentation;

[0046] For the identified problem segment, the parasitic parameter data of the problem segment is loaded into the analysis tool, and the turning points of all routings and device interfaces in the problem segment are checked to obtain the precise location of the problem.

[0047] Furthermore, the layout is modified for the inconsistencies of parasitic parameters, including:

[0048] Arrange the layout and adjust the layout of the problem area, including moving components and rerouting the routing;

[0049] Moving a device includes: moving the device from a location Move to , then the new device coordinates are expressed as ,in, Indicates the new device coordinate position;

[0050] Rearranging the routing includes adjusting the routing and obtaining the new routing path through the Euclidean distance, which is expressed as: ,in, Indicates that a new routing path is obtained after adjusting the routing;

[0051] Routing optimization: adjust the routing width and spacing of problem segments, and optimize the resistance and capacitance values;

[0052] Adjust the width of the trace according to the resistance formula for the problem segment , expressed as:

[0053] in is the resistor, is the trace length, t is the conductor thickness;

[0054] The capacitance value is optimized by adjusting the trace spacing s, which is specifically expressed as: ; Where C is the capacitance and A is the overlap area;

[0055] Add fillers, add fillers to the blank areas or high-frequency areas of the layout, the fillers include ground wires or guard rings;

[0056] Add filler to determine and calculate the optimal position and size of the filler. The distance from the center of the filler to the trace is expressed as ;in, is the loop area of ​​the trace, is the perimeter of the trace;

[0057] Then calculate the size of the filler, the width W is calculated according to the following formula:

[0058] ; Where L2 represents the filler length, is the resistivity of the ground wire, is the target resistance value.

[0059] Furthermore, after modifying the layout of the inconsistent parasitic parameters, the process also includes: re-extracting the GDS and CDL to extract and check the parasitic parameters, including:

[0060] Use statistical analysis to identify inconsistencies in parasitic parameters by calculating the average value of the parasitic parameters for each segment. and standard deviation , using the mean plus or minus 2 times the standard deviation as the normal range, determine the confidence interval of the expected parameter value;

[0061] Then use control charts to monitor and identify deviations in parasitic parameters. By constructing a sigma control chart, plot each segmented parasitic parameter value and monitor whether the parasitic parameter is within the confidence interval.

[0062] When the monitored parasitic parameter is within the confidence interval, the segmented parasitic parameters are consistent. When the monitored parasitic parameter is not within the confidence interval, the segmented parasitic parameter is still inconsistent, and the layout of the segment is modified again.

[0063] The beneficial effects of the present invention are:

[0064] StarRC software is used to extract global and local parasitic parameters of the entire layout in combination with grid division technology of different scales. The parasitic parameters of specific differential lines can be quickly located by searching for the netname of the differential line in the parasitic file. The application of multi-scale grids can more accurately capture global and local parasitic effects, providing reliable data support for subsequent problem diagnosis and correction, solving the problem of the difficulty in accurately extracting and locating parasitic parameters in complex layouts in the existing technology.

[0065] When the StarRC software is used to analyze and identify areas with inconsistent parasitic parameters, the layout design tool is used to add test pins and ideal resistors at specific segment points on the differential lines. This segmentation method allows independent parasitic parameter analysis for each segment, thereby improving the accuracy of problem diagnosis. The difference between the parasitic parameters of each segment and the expected value is then calculated, and a deviation threshold is set. Segments that deviate significantly from the expected value can be quickly identified. The use of automated analysis tools can accurately locate the problem area, which not only speeds up the problem diagnosis, but also improves the targetedness of layout correction. Through this segmented search and the addition of test structures, the problem area can be quickly locked and targeted layout adjustments can be made. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0067] Figure 1 A schematic flow chart of a method for checking parasitic matching of high-frequency differential lines in a layout provided in Example 1 of the present application;

[0068] Figure 2 A schematic diagram of a flow chart of a method for checking parasitic matching of high-frequency differential lines within a layout to verify the consistency of GDS and CDL provided in Example 1 of the present application;

[0069] Figure 3 A schematic flow chart of a method for checking parasitic matching of high-frequency differential lines in a layout provided in Example 1 of the present application, using grids of different scales to capture global and local parasitic effects;

[0070] Figure 4 A schematic diagram of a consistency flow of a method for checking parasitic matching of high-frequency differential lines in a layout provided in Embodiment 1 of the present application to determine whether the parasitic parameters of the differential lines meet the design requirements;

[0071] Figure 5 A schematic diagram of the segmented search process on a layout for a method for checking parasitic matching of high-frequency differential lines within a layout provided in Example 1 of the present application. DETAILED DESCRIPTION

[0072] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0073] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0074] The specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0075] Example 1

[0076] See also Figure 1-Figure 5 This embodiment provides a method for checking the parasitic matching of high-frequency differential lines in a layout, which can quickly find the parasitics of the corresponding differential lines, perform segmented inspection, and accurately locate the problem.

[0077] The present invention provides a method for checking parasitic matching of high-frequency differential lines in a layout, comprising the following steps:

[0078] S1. Extract the corresponding GDS and CDL files and verify the consistency of GDS and CDL through LVS;

[0079] It needs to be explained that the GDS (Graphic Data System) file contains the layout information of the integrated circuit, while the CDL (Circuit Description Language) file describes the connections and components of the circuit. LVS (Layout Versus Schematic) verification is a key step to ensure that the layout design accurately reflects the schematic design and avoid errors in the design.

[0080] S2. Use StarRC software to set environmental parameters, including temperature range (-40℃ to 125℃) and process corners (SS / SF / TT / FS / FF), divide the layout by grid division technology, extract parasitic parameters (R / C / RC / CC / RCC) using StarRC, and generate parasitic files;

[0081] Among them, StarRC is a software for parasitic parameter extraction. Setting the correct environmental parameters is crucial to ensure the accuracy of the extracted parasitic parameters. Process corners are used to describe different process parameter combinations that appear in the integrated circuit manufacturing process, including SS / SF / TT / FS / FF, where SS (Slow NMOS, Slow PMOS) is a combination of slow N-channel MOSFET and slow P-channel MOSFET, which refers to the situation where the threshold voltage of the transistor is higher, resulting in a slower switching speed of the transistor at a given voltage; SF (Slow NMOS, Fast PMOS) is a combination of slow N-channel MOSFET and fast P-channel MOSFET; TT (Typical NMOS, Typical PMOS) is a combination of typical N-channel MOSFET and typical P-channel MOSFET; FS (Fast NMOS, Slow PMOS) is a combination of fast N-channel MOSFET and slow P-channel MOSFET; FF (Fast NMOS, Fast PMOS) is a combination of fast N-channel MOSFET and fast P-channel MOSFET.

[0082] Among them, R represents resistance, C represents capacitance, RC represents resistance-capacitance, CC represents mutual capacitance, and RCC represents resistance-mutual capacitance, which have a significant impact on the transmission characteristics of high-speed signals. These parameters are extracted through StarRC.

[0083] S3. Search the netname of the differential line in the parasitic file to determine whether the parasitic parameters of the differential line meet the consistency of the design requirements;

[0084] S4. When it is determined that the parasitic parameters of the differential line do not meet the consistency of the design requirements, add two pins (such as A and A+) to the differential line on the layout and schematic, and add ideal resistors on the long traces to achieve segmented search;

[0085] Among them, Layout refers to the layout, which is the physical layout of the integrated circuit, that is, the geometric representation of the circuit actually manufactured on the silicon wafer, including the precise position and size information of all physical structures such as transistors, interconnects, contact holes, and fillers. In the layout, the various components and connections of the circuit are converted into graphic patterns that can be used in the semiconductor manufacturing process; Schematic is the circuit schematic diagram of the circuit, which shows the various components of the circuit and the connection relationship between them. The ideal resistor will not produce any parasitic parameters such as inductance, capacitance or coupling effects.

[0086] S5. Modify the layout for inconsistent parasitic parameters, including layout adjustment, routing optimization, and adding fillers;

[0087] S6. After modification, re-extract GDS and CDL, and extract and check parasitic parameters again.

[0088] Furthermore, the consistency between GDS and CDL is verified, including:

[0089] S11. Obtain and prepare GDS and CDL documents;

[0090] S12. Load GDS and CDL files in the LVS tool, and configure technical files and rule files;

[0091] S13, use LVS tool to extract the physical netlist of GDS and compare it with the logical netlist of CDL;

[0092] Specifically, the physical netlist of GDS is a set obtained by mapping the geometric images and features in the GDS file; the logical netlist of CDL is a set obtained by mapping the circuit elements and attributes in the CDL file.

[0093] S14. Generate an LVS report based on the comparison results, analyze the differences in the LVS report and make corrections, and confirm the consistency of the GDS and CDL files.

[0094] Furthermore, the differences in the LVS report were analyzed and corrected, including:

[0095] Generate an LVS report based on the comparison results, identify the type and location of each difference, and make corrections based on the type of difference, including:

[0096] Device correction: when a device is missing in the physical netlist, add the corresponding device in the layout according to the description in the logical netlist; when there are redundant devices in the physical netlist, delete or modify the device in the layout according to the report; adjust the device parameters in the physical netlist by checking the device properties and the logical netlist.

[0097] Connection correction: when a connection is missing in the physical netlist, find the specific connection point of the connection in the logical netlist, modify the layout to add the connection point; when a connection is incorrectly connected in the physical netlist, find the correct connection point and modify it.

[0098] Attribute correction: by checking the attribute mismatches listed in the LVS report, find the specific location of the corresponding device in the physical netlist, and adjust the attributes to match the logical netlist.

[0099] Furthermore, StarRC is used to extract parasitic parameters and generate parasitic files, including the application of grids of different scales to capture global and local parasitic effects.

[0100] S21. Perform a preliminary grid division on the entire layout in StarRC, and use the grid to capture the overall parasitic effects;

[0101] S22, apply StarRC's global parameter extraction algorithm to the preliminary grid to calculate the parasitic parameters of the entire layout;

[0102] These include extracting the resistance of the wires in each grid, extracting the capacitance between adjacent wires, and extracting the mutual capacitance and coupling capacitance for differential lines or interconnects;

[0103] Perform resistance extraction on the wires in each grid and use StarRC to calculate the resistance, which is expressed as: ;in, is the wire length, is the cross-sectional area of ​​the conductor;

[0104] To calculate the capacitance between adjacent conductors, the formula is: ;in, is the dielectric constant, is the vacuum dielectric constant, B is the electrode area, and d is the electrode spacing;

[0105] Calculate the mutual capacitance and coupling capacitance of differential lines or interconnects. The mutual capacitance formula is: ; where k is the coupling coefficient that depends on the conductor geometry and arrangement, L is the conductor length, and g is the interconnect distance;

[0106] The coupling capacitance formula is: ;in, is the area of ​​the coupling region, is the coupling distance.

[0107] S23, generating and saving the extracted parasitic resistance, capacitance, mutual capacitance and coupling capacitance results as a parasitic file.

[0108] Furthermore, the netname of the differential line is searched in the parasitic file to determine whether the parasitic parameters of the differential line meet the consistency of the design requirements, including:

[0109] S31, open the generated parasitic file;

[0110] S32, search for the differential line netname in the parasitic file;

[0111] S33, checking the values ​​of parasitic parameters corresponding to the searched differential lines;

[0112] Specifically, for each found record, all parasitic parameter values ​​associated with netname are recorded, including resistance, capacitance, mutual capacitance, and coupling capacitance.

[0113] S34. Compare the parasitic parameter values ​​with the expected parameter values ​​to determine whether the parasitic parameters of the differential line meet the consistency requirements of the design.

[0114] The expected reference values ​​are simulated using a circuit simulation tool to predict parasitic parameters under ideal conditions.

[0115] Furthermore, when the judgment results are inconsistent, segmented search is performed on the layout, including:

[0116] S41. According to the length of the differential line and the expected parasitic parameter distribution, use the layout design tool to determine the appropriate segmentation points on the differential line. The segmentation points are used to add test pins and ideal resistors later.

[0117] S42. Add test pins at selected locations of differential lines on the layout. The pins will be used for subsequent measurement and parameter extraction to independently analyze the parasitic parameters of each segment. Add these test pins at corresponding locations on the schematic to ensure consistency between the schematic and the layout.

[0118] S43. On long traces, add ideal resistors at specific locations according to the design. The ideal resistors are part of the test structure to help simulate and analyze the resistance distribution on the traces.

[0119] S44. Use the parasitic parameter extraction tool to re-extract the modified layout, generate segmented parasitic files, analyze the parasitic parameters of each segment independently, and compare the differences between parameters such as resistance and capacitance and expected values.

[0120] S45. Determine the location where the problem exists according to the difference values ​​of the parasitic parameters of each segment.

[0121] According to the difference in the parasitic parameters of each segment, the specific location of the problem is determined, helping engineers to accurately locate and solve the parasitic effect problems in circuit design. Through accurate problem location, the layout can be adjusted, the routing can be optimized, and necessary fillers or ideal resistors can be added to improve circuit performance and meet design requirements.

[0122] Furthermore, the difference value of the parasitic parameters of each segment is calculated and compared with the expected value, specifically including:

[0123] ;

[0124] in, is the difference value, is the actual parameter value of the i-th segment, is the expected parameter value,

[0125] Set the deviation threshold when If the deviation threshold is exceeded, it is indicated as a significant deviation. >Threshold, indicating that there is a problem with the current segment;

[0126] For the identified problem segment, the parasitic parameter data of the problem segment is loaded into the analysis tool, and the turning points of all routings and device interfaces in the problem segment are checked to obtain the precise location of the problem.

[0127] Furthermore, the layout is modified for the inconsistencies of parasitic parameters, including:

[0128] Arrange the layout and adjust the layout of the problem area, including moving components and re-routing the routing to reduce the impact of parasitic parameters;

[0129] Specifically adjust the device and calculate the new device coordinates as follows: Move to , then the new device coordinates are expressed as ,in, Indicates the new device coordinate position;

[0130] Rearranging the routing includes adjusting the routing and obtaining the new routing path through the Euclidean distance, which is expressed as: ,in, Indicates that a new routing path is obtained after adjusting the routing;

[0131] Routing optimization: adjust the routing width and spacing of problem segments, and optimize the resistance and capacitance values;

[0132] Adjust the width of the trace according to the resistance formula for the problem segment , expressed as:

[0133] in is the resistor, is the trace length, t is the conductor thickness;

[0134] The capacitance value is optimized by adjusting the trace spacing s, which is specifically expressed as: ; Where C is the capacitance and A is the overlap area;

[0135] Add fillers, add fillers to the blank areas or high-frequency areas of the layout, the fillers include ground wires or guard rings;

[0136] Add filler to determine and calculate the optimal position and size of the filler. The distance from the center of the filler to the trace is expressed as ;in, is the loop area of ​​the trace, is the perimeter of the trace;

[0137] Then calculate the size of the filler, the width W is calculated according to the following formula:

[0138] ; Where L2 represents the filler length, is the resistivity of the ground wire, is the target resistance value.

[0139] Furthermore, after modifying the layout of the inconsistent parasitic parameters, the process also includes: re-extracting the GDS and CDL to extract and check the parasitic parameters, including:

[0140] Use statistical analysis to identify inconsistencies in parasitic parameters by calculating the average value of the parasitic parameters for each segment. and standard deviation , using the mean plus or minus 2 times the standard deviation as the normal range, determine the confidence interval of the expected parameter value;

[0141] Then use control charts to monitor and identify deviations in parasitic parameters. Specifically, a sigma control chart is constructed to plot the parasitic parameter values ​​for each segment and monitor whether the parasitic parameters are within the confidence interval.

[0142] When the monitored parasitic parameter is within the confidence interval, the segmented parasitic parameters are consistent. When the monitored parasitic parameter is not within the confidence interval, the segmented parasitic parameter is still inconsistent and the layout of the segment needs to be modified again.

[0143] This embodiment ensures that the parasitic parameters of the differential lines in the layout design meet the consistency of the design requirements through a series of precise and systematic steps. The GDS and CDL files are extracted from the layout design, and the LVS tool is used to perform consistency verification. This step ensures the precise correspondence between the layout and the schematic diagram. In the LVS verification process, the physical netlist and the logical netlist are carefully compared through the configuration of the technical files and rule files, and an LVS report is generated. According to the report results, necessary device corrections, connection corrections, and attribute corrections are performed, thereby ensuring the complete consistency of the GDS and CDL files.

[0144] Subsequently, StarRC software is used to set environmental parameters and use grid division technology to extract detailed parasitic parameters of the layout and generate parasitic files. In this step, StarRC software not only takes into account the temperature range and process corners, but also captures global and local parasitic effects through grids of different scales, and applies complex electromagnetic field algorithms to calculate parasitic resistance, capacitance, mutual capacitance and coupling capacitance. When inconsistencies are found in parasitic parameters, test pins are added to the corresponding positions of the differential lines on the layout and schematic, and ideal resistors are added to the traces to achieve segmented search, so that the parasitic parameters of each segment can be analyzed independently to quickly locate the problem area.

[0145] For inconsistent parasitic parameters, perform layout adjustment, routing optimization, and add fillers when necessary to improve the consistency of parasitic parameters. By searching the netname of the differential line, check and compare the actual parasitic parameter values ​​with the expected values ​​to ensure their consistency. For the identified problem segments, use statistical analysis and control charts to monitor parameter deviations, calculate difference values, and use deviation thresholds to identify segments that deviate significantly from expectations.

[0146] After the layout is modified, the GDS and CDL files are re-extracted, and the parasitic parameters are extracted and checked again to verify the effectiveness of the correction measures. Finally, the layout is modified in a targeted manner, including rearranging devices, adjusting routing paths and widths, and adding fillers to optimize resistance and capacitance values. These modifications not only solve the problem of difficulty in quickly locating and correcting parasitic parameter inconsistencies in long differential lines or complex layouts, but also improve the performance and reliability of the circuit.

[0147] Example 2

[0148] Another embodiment of the present application provides a method for checking parasitic matching of high-frequency differential lines within a layout, which is applied to a chip design team that is performing layout checking of high-frequency differential lines and finds that parasitic parameters of some differential lines do not meet design requirements. It is decided to use a method for checking parasitic matching of high-frequency differential lines within a layout for checking and correction. Through the implementation of this method, the problem of inconsistent parasitic parameters can be quickly located and corrected to ensure the stability and performance of the high-frequency circuit.

[0149] Specific process:

[0150] Extract GDS and CDL files and verify consistency. The design team extracted GDS and CDL files from the design database, loaded GDS and CDL files using the LVS tool, configured relevant technical files and rule files, extracted the physical netlist of GDS, and compared it with the logical netlist of CDL. An LVS report was generated, and it was found that there were inconsistencies in the connections and properties of several devices. The missing connections were added by correcting the device properties in the physical netlist.

[0151] Use StarRC software to extract parasitic parameters. Set environmental parameters in StarRC, including temperature range (-40°C to 125°C) and process corners (TT, FF, SS). Perform preliminary grid division on the layout. Use grid to capture the overall parasitic effects. Use StarRC to extract resistance, capacitance, mutual capacitance and coupling capacitance parameters and generate parasitic files.

[0152] Check the consistency of parasitic parameters, open the generated parasitic file, search for the netname of the differential line, check whether the parasitic parameters meet the design requirements, perform segmentation check when they are inconsistent, and find that the parasitic parameters of some differential lines do not meet the design requirements. Add test pins at both ends of the differential lines on the layout and schematic, add ideal resistors to long traces, use the parasitic parameter extraction tool to re-extract the modified layout, and perform segmentation analysis.

[0153] Modify the layout where parasitic parameters are inconsistent. For problem areas, rearrange components and traces, move some components, adjust their positions to reduce parasitic effects, or adjust trace width and spacing, reduce resistance and capacitance values, or add ground wires or guard rings in high-frequency areas to optimize parasitic parameters.

[0154] Re-extract GDS and CDL to extract and check parasitic parameters, re-extract parasitic parameters, independently analyze the parasitic parameters of each segment, calculate the mean and standard deviation of each segment, determine the confidence interval, and use the sigma control chart to monitor the deviation of parasitic parameters to ensure that they are within the confidence interval. If problems are still found in some segments, continue to modify the layout of these segments until there are no more problems in the checked segments.

[0155] After the above systematic inspection and correction, the design team successfully adjusted the parasitic parameters of all high-frequency differential lines to meet the design requirements, ensuring the consistency and reliability of the chip design.

[0156] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for checking parasitic matching of high-frequency differential lines in a layout, characterized in that: The steps include: Extract the corresponding GDS and CDL files and confirm the consistency of GDS and CDL through LVS verification; specifically including: obtaining and preparing GDS and CDL files; Load GDS and CDL files in the LVS tool, and configure technology files and rule files; Use the LVS tool to extract the physical netlist of GDS and compare it with the logical netlist of CDL; Generate LVS report based on comparison results, analyze differences in LVS report and make corrections, and confirm the consistency of GDS and CDL files; Use StarRC software to set environmental parameters, including temperature range and process corners, divide the layout through meshing technology, extract parasitic parameters using StarRC, and generate parasitic files; The use of StarRC to extract parasitic parameters and generate parasitic files includes: Perform a preliminary meshing of the entire layout in StarRC, using the mesh to capture the overall parasitic effects; Apply StarRC’s global parameter extraction algorithm to the preliminary grid to calculate the parasitic parameters of the entire layout; The calculation of the parasitic parameters of the entire layout includes extracting the resistance of the wires in each grid, extracting the capacitance between adjacent wires, and extracting the mutual capacitance and coupling capacitance of differential lines or interconnects; using StarRC to calculate the resistance, expressed as: ;in, is the resistivity, is the wire length, is the cross-sectional area of ​​the conductor; To calculate the capacitance between adjacent conductors, the formula is: ;in, is the dielectric constant, is the vacuum dielectric constant, B is the electrode area, and d is the electrode spacing; Calculate the mutual capacitance and coupling capacitance of differential lines or interconnects. The mutual capacitance formula is: ; where k is the coupling coefficient that depends on the conductor geometry and arrangement, L is the conductor length, and g is the interconnection distance; The coupling capacitance formula is: ;in, is the area of ​​the coupling region, is the coupling distance; Generate and save the extracted parasitic resistance, capacitance, mutual capacitance and coupling capacitance results as parasitic files; Search for the netname of the differential line in the parasitic file to determine whether the parasitic parameters of the differential line meet the consistency of the design requirements; The process of searching the netname of the differential line in the parasitic file and determining whether the parasitic parameters of the differential line meet the consistency of the design requirements includes: Open the generated parasitic file; Search for the differential line netname in the parasitic file; Check the values ​​of parasitic parameters corresponding to the searched differential lines; Compare the parasitic parameter values ​​with the expected parameter values ​​to make judgments; When it is determined that the parasitic parameters of the differential line do not meet the consistency required by the design, add two pins to the differential line on the layout and schematic, and add ideal resistors to the long traces for segmented search; The segmented search comprises: Use layout design tools to determine appropriate segmentation points on the differential lines based on the length of the differential lines and the expected parasitic parameter distribution; Add test pins at selected locations of differential lines on the layout to analyze parasitic parameters of each segment independently, and add test pins at corresponding locations on the schematic; On long traces, ideal resistors are added at specific locations according to the design to simulate and analyze the resistance distribution on the traces; Use the parasitic parameter extraction tool to re-extract the modified layout, generate segmented parasitic files, analyze the parasitic parameters of each segment independently, compare the differences between the parasitic parameters and the expected values, and generate difference values; Determine the location of the problem based on the difference values ​​of the parasitic parameters of each segment; Modify the layout where the parasitic parameters are inconsistent, including layout adjustment, routing optimization, and adding fillers; The layout adjustment is used to adjust the layout of the problem area, including moving devices and rearranging routing; Moving a device includes: moving the device from a location Move to , then the new device coordinates are expressed as ,in, Indicates the new device coordinate position; Rearranging the routing includes adjusting the routing and obtaining the new routing path through the Euclidean distance, which is expressed as: ,in, Indicates that a new routing path is obtained after adjusting the routing; The routing optimization adjusts the routing width and spacing of the problem segments and optimizes the resistance and capacitance values; Adjust the width of the trace according to the resistance formula for the problem segment , expressed as: ,in is the resistor, is the trace length, t is the conductor thickness; The capacitance value is optimized by adjusting the trace spacing s, which is specifically expressed as: ; Where C is the capacitance and A is the overlap area; The adding of fillers is used to determine and calculate the optimal position and size of the fillers. The distance from the center of the filler to the trace is expressed as is the loop area of ​​the trace, is the perimeter of the trace; Then calculate the size of the filler, the width W is calculated according to the following formula: ; Where L2 represents the filler length, is the resistivity of the ground wire, is the target resistance value.

2. The method for checking parasitic matching of high-frequency differential lines in a layout according to claim 1, characterized in that: Generating an LVS report according to the comparison results, analyzing the differences in the LVS report and making corrections include: Device correction: when there are missing devices in the physical netlist, add the corresponding devices in the layout according to the description in the logical netlist; when there are redundant devices in the physical netlist, delete or modify the devices in the layout according to the report; adjust the device parameters in the physical netlist by checking the device properties and the logical netlist; Connection correction: when a connection is missing in the physical netlist, find the specific connection point of the connection in the logical netlist, modify the layout to add the connection point; when a connection is incorrectly connected in the physical netlist, find the correct connection point and modify it; Attribute correction: by checking the attribute mismatch items listed in the LVS report, find the specific location of the corresponding device in the physical netlist, and adjust the attributes to match the logical netlist.

3. The method for checking parasitic matching of high-frequency differential lines in a layout according to claim 1, characterized in that: The independent analysis of the parasitic parameters of each segment, comparing the difference between the parasitic parameters and the expected values, and generating the difference values ​​specifically include: ； in, is the difference value, is the actual parameter value of the i-th segment, is the expected parameter value, Set the deviation threshold when If the deviation threshold is exceeded, it is indicated as a significant deviation. >Threshold, indicating that there is a problem with the current segment; For the identified problem segments, load the parasitic parameter data of the problem segments into the analysis tool to check the inflection points of all routings and device interfaces in the problem segments.

4. The method for checking parasitic matching of high-frequency differential lines in a layout according to claim 1, characterized in that: After modifying the layout of the inconsistent parasitic parameters, it also includes: re-extracting GDS and CDL, extracting and checking parasitic parameters, specifically: Use statistical analysis to identify inconsistencies in parasitic parameters and calculate the average value of parasitic parameters for each segment and standard deviation , using the mean plus or minus 2 times the standard deviation as the normal range, determine the confidence interval of the expected parameter value; Use control charts to monitor and identify deviations in parasitic parameters, build sigma control charts, plot each segmented parasitic parameter value, and monitor whether the parasitic parameters are within the confidence interval; When the monitored parasitic parameter is within the confidence interval, the segmented parasitic parameters are consistent; when the monitored parasitic parameter is not within the confidence interval, the segmented parasitic parameters are inconsistent, and the layout of the segment is modified.

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