Timing control circuit and control method thereof, and display device

Abstract

Embodiments of the present application provide a timing control circuit and a control method thereof, and a display device, and relate to the technical field of display. The timing control circuit is configured to receive and store a control signal, and in the case of interruption of the control signal, control a display panel to display according to the stored control signal. The timing control circuit detects the interruption of the control signal to adjust the working timing thereof, and controls the display panel to display according to the stored control signal, so as to avoid abnormal display output caused by the interruption of the control signal, thereby improving the ESD resistance of the product and realizing the test of Class A standard.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a timing control circuit and a control method thereof, and a display device. BACKGROUND

[0002] Electro Static Discharge (ESD) refers to a phenomenon of sudden discharge caused by accumulation or movement of electric charges. For ESD test of a display device, test results are divided into four levels of A, B, C and D, and Class A corresponds to no any abnormality in the test.

[0003] In some display application scenarios, it is required that the ESD test result of the display device reaches Class A so as to avoid affecting use due to display abnormality. Based on this, how to improve the anti-ESD capability of the product and realize the test of Class A standard has become a problem to be solved in the field. SUMMARY

[0004] The present application provides a timing control circuit and a control method thereof, and a display device, aiming to improve the anti-ESD capability of the product and realize the test of Class A standard.

[0005] To achieve the above-mentioned purpose, the embodiments of the present application provide the following technical solutions:

[0006] In one aspect, a timing control circuit is provided, which is configured to receive and store a control signal, and in the case of interruption of the control signal, control a display panel to display according to the stored control signal.

[0007] The timing control circuit provided by the embodiments of the present application does not need to modify the structure of the display panel, and can detect interruption of the control signal by the timing control circuit in the case that optimization of the structure and signal wiring still cannot achieve the anti-ESD test level, adjust the working timing, and control the display panel to display according to the stored control signal, so as to avoid abnormal display output caused by interruption of the control signal, and further improve the anti-ESD capability of the product and realize the test of Class A standard.

[0008] In some embodiments, the timing control circuit is further configured to output a clock signal, and in the case of interruption of both the control signal and the clock signal, output a frame start signal of at least one frame period, the frame start signal being used to control a gate driving circuit of the display panel to stop outputting a gate scanning signal.

[0009] In some embodiments, the clock signal is a pulse signal that switches between a first level and a second level, where the first level is greater than the second level. The timing control circuit is configured to output multiple clock signals, and when the control signal is interrupted and all multiple clock signals switch from the first level to the second level, output a frame start signal for at least one frame period.

[0010] In some embodiments, the timing control circuit is configured to output a received signal based on a stored control signal when the control signal is interrupted. The received signal is used to control the source drive circuit of the display panel to output a data signal.

[0011] In some embodiments, the timing control circuit is configured to store control signals for n frames, and, in the event that a control signal interruption is detected in the i-th frame period, output the same received signal in the i+n-1-th and i+n-th frame periods, where i≥1, n≥1, and i and n are both natural numbers.

[0012] On the other hand, a timing control method is provided, which includes receiving and storing control signals, and controlling a display panel to display according to the stored control signals when the control signals are interrupted.

[0013] The timing control method provided in the embodiments of this application detects the interruption of the control signal through the timing control circuit, adjusts its working timing, and controls the display panel to display according to the stored control signal, so as to avoid abnormal display output caused by the interruption of the control signal, thereby improving the product's ESD resistance and achieving Class A test compliance.

[0014] In some embodiments, when both the control signal and the clock signal are interrupted, a frame start signal of at least one frame period is output to control the gate drive circuit of the display panel to stop outputting the gate scan signal.

[0015] In some embodiments, the clock signal is a pulse signal that switches between a first level and a second level, where the first level is greater than the second level. When the control signal is interrupted and multiple clock signals switch from the first level to the second level, a frame start signal of at least one frame period is output.

[0016] In some embodiments, when the control signal is interrupted, controlling the display panel to display according to the stored control signal includes: when the control signal is interrupted, outputting a received signal according to the stored control signal to control the source drive circuit of the display panel to output a data signal.

[0017] In some embodiments, receiving and storing control signals includes: receiving control signals and storing control signals for n frames, where n ≥ 1 and n is a natural number.

[0018] In the case of interruption of the control signal, the received signal is output according to the stored control signal, comprising: in the case of interruption of the control signal detected in the i th frame period, outputting the same received signal in the i+n-1 th frame period and the i+n th frame period, i≥1, and i is a natural number.

[0019] In another aspect, a display device is provided, comprising the timing control circuit in any of the above embodiments, and a display panel electrically connected with the timing control circuit. The timing control circuit is configured to receive and store a control signal, and in the case of interruption of the control signal, control the display panel to display according to the stored control signal.

[0020] The display device has the same structure and beneficial technical effects as the timing control circuit provided in some of the above embodiments, and will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present application, the following will briefly introduce the drawings needed to be used in some embodiments of the present application. Obviously, the drawings in the following description are only some of the drawings of the present application, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present application.

[0022] Figure 1 Structure diagram of the display device provided by the embodiments of the present application;

[0023] Figure 2 Circuit architecture diagram of the shift register of the gate drive circuit provided by the embodiments of the present application;

[0024] Figure 3 A driving timing diagram of the timing control circuit provided by the embodiments of the present application;

[0025] Figure 4 Timing diagram for the case of abnormal output of the control signal received by the timing control circuit due to interference;

[0026] Figure 5 A driving timing diagram of the timing control circuit provided by the embodiments of the present application;

[0027] Figure 6 And Figure 7 Waveform measurement diagram of the timing control circuit provided by the embodiments of the present application;

[0028] Figure 8 Another driving timing diagram of the timing control circuit provided by the embodiments of the present application;

[0029] Figure 9 Another driving timing diagram of the timing control circuit provided by the embodiments of the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments provided by the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0031] Unless otherwise required by the context, the term “comprises” in the specification and claims is to be construed as an open, inclusive meaning, i.e. “including, but not limited to”.

[0032] Hereinafter, the terms “first” and “second” are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more features. In the description of the embodiments of the present application, the meaning of “a plurality of” is two or more, unless otherwise specified.

[0033] In describing some embodiments, the term “connected” and its conjugations can be used. The term “connected” should be interpreted broadly, for example, “connected” can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. For example, in describing some embodiments, the term “connected” can be used to indicate that two or more components have direct physical contact or electrical contact with each other.

[0034] In addition, the use of “based on” means open and inclusive, because the process, step, calculation or other action “based on” one or more stated conditions or values can be based on additional conditions or values beyond those stated in practice.

[0035] Electro Static Discharge (ESD) refers to the phenomenon of sudden discharge caused by the accumulation or movement of electric charge. Electrostatic discharge is easy to cause damage to integrated circuits and electronic devices, etc. The purpose of ESD test is to verify whether the components in the integrated circuit or the electronic device can work normally in the electrostatic discharge environment, and its ability to resist ESD damage. ESD test can evaluate the electrostatic protection capability and design quality of electronic devices, help designers improve the reliability and stability of electronic devices, and improve the usability of electronic devices. Therefore, it is very important to perform ESD test on electronic devices, and in the field of display technology, ESD test is also an essential test item for evaluating the anti-static capability of products.

[0036] For the ESD test of the display device, under the prescribed air and contact test energy requirements, the test results are divided into four grades. In simple terms, if the display device is damaged during the test and cannot be recovered, the test result is Class D (Class D). If abnormal display occurs during the test and cannot be recovered, it needs to be re-powered to recover, the test result is Class C (Class C). If the display device appears abnormal such as flashing screen, flashing line, etc. during the test, but can recover itself, the test result is Class B (Class B). If there is no any abnormality in the test, the test result is Class A (Class A).

[0037] For the current display industry, the higher demand for ESD test of general products is Class B, that is, abnormal display occurs due to ESD, but can recover itself. However, for special application scenarios such as high-end medical display, due to the high requirement of application environment, the ESD test result of electronic equipment needs to reach Class A to avoid affecting use due to abnormal display.

[0038] Currently, in order to meet the ESD test result of Class A, optimization is made from the structure of the display device, signal wiring and the like. However, the best state of the test result obtained through the lighting ESD test is Class B, that is, under the state of the test in which the control signal (front-end signal) is input by the front-end lighting device, the display device mostly has problems such as flicker, flashing line or flashing black, but can recover normally.

[0039] The inventor of the present application found through research that when tested in the built-in self-test (BIST) mode, that is, the signal is provided by the timer control register (TCON) itself, the display device can reach Class A, which indicates that the control signal received by the timer control circuit is greatly disturbed during the ESD test, resulting in abnormal overall output. Although the timer control circuit can perform self-reset, because the signal will be interrupted and re-linked in the reset state, the display screen will correspondingly appear display states such as flicker, flashing black, etc.

[0040] To solve the above problems, the embodiments of the present application provide a display device, which starts from the display principle, avoids abnormal display output by optimizing the circuit, and further improves the anti-ESD capability of the product to achieve Class A test standard.

[0041] Figure 1 The structure diagram of the display device provided by the embodiments of the present application is shown.

[0042] Referring to Figure 1The display device 1 can be a liquid crystal display (LCD), or an electroluminescent display or a photoluminescent display. In the case that the display device 1 is an electroluminescent display, the electroluminescent display can be an organic light-emitting diode (OLED) or a quantum dot light emitting diode (QLED). In the case that the display device 1 is a photoluminescent display, the photoluminescent display can be a quantum dot photoluminescent display.

[0043] With reference to the drawings again, Figure 1 The display device 1 comprises a display panel 2, and a timing control circuit 3 electrically connected with the display panel 2, the timing control circuit 3 is used for controlling the display panel 2 to display.

[0044] Exemplarily, the display device 1 further comprises a circuit board 4 and a flexible circuit board 5, the timing control circuit 3 is arranged on the circuit board 4 and electrically connected with the display panel 2 through the flexible circuit board 5.

[0045] The display panel 2 comprises a gate drive circuit 21 and a source drive circuit 22, the gate drive circuit 21 can be a GOA (Gate Driver on Array) circuit, the GOA circuit refers to a multi-stage cascaded shift register composed of a plurality of thin film transistors and capacitors made on an array substrate. The source drive circuit 22 can be integrated on the flexible circuit board 5, and this structure can be called Chip On Flex (COF).

[0046] The display device described above can be any device that displays images whether in motion (e.g., video) or stationary (e.g., still images) and whether textual or pictorial. More specifically, it is contemplated that the embodiments can be implemented in or in association with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and / or displays, camera view displays (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projections, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry) and the like.

[0047] Figure 2A circuit architecture diagram of a shift register of a gate drive circuit provided by an embodiment of the present application.

[0048] Referring to Figure 2 The shift register 23 includes a pull-up driving module 24, a pull-up module 25, a driving pull-down module 26, a pull-down module 27, a reset module 28, and a global reset module 29. An output port OUTPUT of the shift register 23 is electrically connected with a gate line (Gate Line, GL).

[0049] The timing control circuit 3 is electrically connected with the shift register 23 of the gate drive circuit 21, Figure 3 A driving timing diagram of a timing control circuit provided by an embodiment of the present application.

[0050] Referring to Figure 3 The timing control circuit 3 receives and stores a control signal TXDE, and outputs a timing control signal (including a frame start signal STV0 and a clock signal CLK) required by the shift register 23 after decoding the control signal TXDE. The clock signal CLK is transmitted to the pull-up module 25 of the shift register 23, and the frame start signal STV0 is transmitted to the global reset module 29, so as to drive the multi-stage shift register 23 to output a gate scanning signal (high square wave) to the multiple gate lines, and to drive multiple rows of sub-pixels to be turned on row by row.

[0051] In addition, the timing control circuit 3 also outputs a timing control signal required by the source drive circuit 22 after decoding the control signal TXDE, so as to drive the source drive circuit 22 to output a data signal to the multiple data lines (Data Line, DL). During the process of turning on the multiple rows of sub-pixels row by row, the data signal is written into the sub-pixel, so that the required picture can be displayed

[0052] As mentioned above, during the ESD test, the control signal TXDE is easy to be disturbed, Figure 4 A timing diagram of a control signal received by a timing control circuit and abnormally outputted due to disturbance.

[0053] Referring to Figure 4 In the case that the control signal TXDE received by the timing control circuit 3 is disturbed, the control signal TXDE will be interrupted, resulting in that the clock signal CLK outputted by the timing control circuit 3 is also abnormally interrupted, so that the shift register 23 of the gate drive circuit 21 stops outputting the gate scanning signal, and the sub-pixels of the current row cannot be turned on. A frame of picture is not completely printed, and the display picture will also be abnormal.

[0054] Based on this, the embodiment of the present application provides a timing control circuit and a control method thereof. The timing control circuit 3 detects the control signal TXDE. In the case of interruption of the control signal TXDE, the working timing is adjusted. The display panel 2 is controlled to display according to the stored control signal TXDE, so as to avoid abnormal display output, thereby improving the product ESD resistance and realizing the test Class A standard.

[0055] Figure 5 A driving timing diagram of the timing control circuit provided by the embodiment of the present application; Figure 6 and Figure 7 A waveform measurement diagram of the timing control circuit provided by the embodiment of the present application.

[0056] Referring to Figure 5 and Figure 6 The control program of the timing control circuit 3 is adjusted. The timing control circuit 3 is configured to output a frame start signal STV0 of at least one frame period in the case of interruption of both the control signal TXDE and the clock signal CLK. It can be understood that the frame start signal STV0 is a pulse signal with high and low level switching. In the case of detecting interruption of both the control signal TXDE and the clock signal CLK, the frame start signal STV0 is switched to high level, that is, the frame start signal STV0 is pulled up.

[0057] According to the foregoing, in combination with Figure 2 The frame start signal STV0 is transmitted to the global reset module 29 of each stage of shift register 23. In the case of pulling up of the frame start signal STV0, the frame start signal STV0 controls the global reset module 29 to be opened. The VGL signal is transmitted to the output port OUTPUT through the global reset module 29, so that the gate scanning signal output by each stage of shift register 23 is pulled down to VGL. It can be understood that each stage of shift register 23 stops outputting the gate scanning signal, so that each row of sub-pixels is turned off, and each row of sub-pixels maintains the level (stored data) of the data signal charged in the last frame, and maintains the display picture of the last frame.

[0058] Corresponding to this time, referring to Figure 6 Even if the control signal TXDE is interrupted due to ESD interference, the timing control signal (received signal RXDE) output by the timing control circuit 3 to the source driving circuit 22 is abnormal, and the data signal (source output) output by the source driving circuit 22 is abnormal. By controlling each row of sub-pixels to be turned off, the abnormal data signal cannot be written into the sub-pixel, so that the abnormal picture can be avoided, thereby improving the product ESD resistance and realizing the test Class A standard.

[0059] Exemplarily, referring to Figure 5In the case that the control signal TXDE and the clock signal CLK are interrupted, the timing control circuit 3 can output a frame start signal STV0 of one frame period, and in the frame period in which the frame start signal STV0 is pulled high, the display picture stops refreshing and holding, which does not affect the display and can avoid abnormal pictures.

[0060] For example, referring to Figure 6 In the case that the control signal TXDE and the clock signal CLK are interrupted, the timing control circuit 3 can output a frame start signal STV0 of one frame period, and in the frame period in which the frame start signal STV0 is pulled high, the display picture stops refreshing and holding, which does not affect the display and can avoid abnormal pictures.

[0061] In the above embodiments of the present application, the number of frame periods in which the frame start signal STV0 is pulled high can be determined according to the duration of the recovery of the control signal TXDE, which is not limited in the present application.

[0062] In some embodiments, referring to Figure 7 The timing control circuit 3 is configured to output a plurality of clock signals CLK, and each of the plurality of clock signals CLK is a pulse signal switching between high and low levels. The above-mentioned “interruption of the clock signal CLK” refers to that each of the plurality of clock signals CLK is switched from high level to low level, and all the clock signals CLK complete a complete high, or all the clock signals CLK have been output completely.

[0063] Based on this, in the case that the control signal TXDE is interrupted and each of the plurality of clock signals CLK is switched from high level to low level, the timing control circuit 3 outputs a frame start signal STV0 of at least one frame period, so as to avoid pulling high the frame start signal STV0 in the case that the clock signal CLK is high and display abnormality occurs.

[0064] In addition, by pulling high the frame start signal STV0, the picture can be held, and the abnormal data signal in this time is avoided, that is, when the ESD interference is detected, the picture information affected by the interference will not be displayed, and at the same time, the timing control circuit 3 does not need to be reset, and abnormal phenomena such as flashing screen and flashing line will not occur, so as to achieve ESD test Class A standard.

[0065] For example, referring to Figure 7, the timing control circuit 3 outputs a first clock signal CLK1 and a second clock signal CLK2, both of which are pulse signals switching between high and low levels, and the second clock signal CLK2 is set high after the first clock signal CLK1. It can be understood that after the control signal TXDE is interrupted and the second clock signal CLK2 is switched from high to low, the frame start signal STV0 can be pulled high. In the embodiment of the present application, the frame start signal STV0 is pulled high after the second clock signal CLK2 is set for a period of time (for example, 120 μs), so as to ensure that the frame start signal STV0 is pulled high when the clock signal CLK is low, and display abnormalities can be avoided.

[0066] Figure 8 Another driving timing diagram of the timing control circuit provided by the embodiment of the present application.

[0067] Referring to Figure 8 , after receiving the control signal TXDE, the timing control circuit 3 stores the control signal TXDE in the memory and outputs the received signal RXDE to the source driving circuit 22 with a delay, that is, the current output of the received signal RXDE is not generated according to the currently received control signal TXDE, but the received signal RXDE is generated according to the control signal TXDE stored in the memory. It can be seen that the timing control circuit 3 controls the display by delayed output.

[0068] In some examples, referring to Figure 8 , the memory of the timing control circuit 3 can store a frame of control signal TXDE (containing a frame of picture data) and output the received signal RXDE to the source driving circuit 22 with a delay of one frame, that is, the picture data contained in the received signal RXDE is generated according to the control signal TXDE of the last frame, so as to realize one-frame-delayed output of the picture.

[0069] In another example, the memory of the timing control circuit 3 can also store n frames of control signal TXDE (containing n frames of picture data) and output the received signal RXDE to the source driving circuit 22 with a delay of n frames, that is, the picture data contained in the received signal RXDE is generated according to the control signal TXDE of n frames ago, so as to realize n-frame-delayed output of the picture, wherein n > 1 and n is a natural number.

[0070] Figure 9 Another driving timing diagram of the timing control circuit provided by the embodiment of the present application.

[0071] Referring to Figure 9The memory of the timing control circuit 3 is adjusted, and the timing control circuit 3 is configured to output the normal receiving signal RXDE according to the control signal TXDE stored in the memory in the case of interruption of the control signal TXDE, to control the source driving circuit 22 to output the normal data signal, and to ensure normal display of the display panel 2.

[0072] It can be understood that when the timing control circuit 3 detects abnormal interruption of the control signal TXDE, the control signal TXDE (including picture data) of the corresponding frame is not stored, and the picture data stored in the memory is still the picture data stored before, and the timing control circuit 3 can control the display according to the stored picture data, and the output picture of the corresponding next frame does not change, so as to skip the picture data of the abnormal frame and avoid displaying the picture data of the abnormal frame, thereby improving the ESD resistance of the product and achieving the test Class A standard.

[0073] In some examples, the timing control circuit 3 is configured to store n frames of control signals TXDE, and in the case of detection of interruption of the control signal TXDE in the ith frame period, the same receiving signal RXDE is output in the ith+n-1 frame period and the ith+n frame period, where i≥1 and i is a natural number.

[0074] It can be understood that the timing control circuit 3 outputs the same normal receiving signal RXDE in the ith+n frame period and the ith+n-1 frame period according to the control signal TXDE (normal picture data) stored before the abnormal frame (the ith frame period), and the picture output in the ith+n frame period and the ith+n-1 frame period does not change, so as to skip the control signal TXDE (abnormal picture data) of the ith frame period and not to store and delay output.

[0075] For example, referring to Figure 9 , the timing control circuit 3 is configured to store one frame of control signal TXDE, and in the case of detection of interruption of the control signal TXDE in the second frame period, the same receiving signal RXDE is output in the third frame period as in the second frame period, that is, the timing control circuit 3 outputs the corresponding normal receiving signal RXDE in the second frame period according to the control signal TXDE (normal picture data) stored in the previous frame (the first frame period) of the abnormal frame (the second frame period), and also outputs the corresponding normal receiving signal RXDE in the third frame period, that is, the same receiving signal RXDE is output in the third frame period as in the second frame period, and the picture output in the third frame period and the second frame period does not change, so as to skip the control signal TXDE (abnormal picture data) of the second frame period and not to store and delay output.

[0076] In some examples, the timing control circuit 3 also has a panel self refresh (PSR) function, and the timing control circuit 3 is configured to enter the PSR mode in the case of interruption of the control signal TXDE, and the timing control circuit 3 takes over the display task from a graphics processing unit (GPU), automatically refreshes the display content from the internal memory, without the continuous participation of the GPU, ensures the normal display of the display panel 2, avoids display abnormalities, and thus improves the ESD resistance of the product and realizes the test Class A standard.

[0077] In summary, the timing control circuit and the control method thereof provided by the embodiments of the present application do not need to change the structure of the display panel, and can adjust only the control program or the memory of the timing control circuit in the case that the structure and signal wiring optimization still cannot achieve the ESD resistance test level, adjust the working timing by detecting the interruption of the control signal, control the display panel to display according to the stored control signal, avoid abnormal display output, and thus improve the ESD resistance of the product and realize the test Class A standard.

[0078] The above merely provides specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical scope disclosed by the present application, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A timing control circuit, characterized by comprising: The timing control circuit is configured to receive and store a control signal, and control the display panel to display according to the stored control signal in case of interruption of the control signal. The timing control circuit is further configured to output a clock signal, and output a frame start signal of at least one frame period in case of interruption of both the control signal and the clock signal, the frame start signal being used to control a gate driving circuit of the display panel to stop outputting a gate scanning signal.

2. The timing control circuit of claim 1, wherein, The clock signal is a pulse signal switching between a first level and a second level, the first level being greater than the second level. The timing control circuit is configured to output a plurality of clock signals, and output the frame start signal of at least one frame period in case of interruption of the control signal and switching of all the plurality of clock signals from the first level to the second level.

3. The timing control circuit of claim 1, wherein, The timing control circuit is configured to output a receiving signal according to the stored control signal in case of interruption of the control signal, the receiving signal being used to control a source driving circuit of the display panel to output a data signal.

4. The timing control circuit of claim 3, wherein, The timing control circuit is configured to store the control signal of n frames. And output the same receiving signal in the i+n-1th frame period and the i+nth frame period in case of detection of interruption of the control signal in the ith frame period, i≥1, n≥1, i and n being natural numbers.

5. A method of timing control, characterized by, Comprising: Receiving and storing a control signal; Controlling the display panel to display according to the stored control signal in case of interruption of the control signal, and outputting a frame start signal of at least one frame period in case of interruption of both the control signal and a clock signal to control a gate driving circuit of the display panel to stop outputting a gate scanning signal.

6. The timing control method according to claim 5, wherein The clock signal is a pulse signal switching between a first level and a second level, the first level being greater than the second level. Outputting the frame start signal of at least one frame period in case of interruption of the control signal and switching of all the plurality of clock signals from the first level to the second level.

7. The timing control method according to claim 5, wherein Controlling the display panel to display according to the stored control signal in case of interruption of the control signal, comprising: Outputting a receiving signal according to the stored control signal in case of interruption of the control signal to control a source driving circuit of the display panel to output a data signal.

8. The timing control method according to claim 7, wherein Receiving and storing a control signal, comprising: Receiving a control signal and storing the control signal of n frames, n≥1, and n being a natural number; Outputting a receiving signal according to the stored control signal in case of interruption of the control signal, comprising: Outputting the same receiving signal in the i+n-1th frame period and the i+nth frame period in case of detection of interruption of the control signal in the ith frame period, i≥1, and i being a natural number.

9. A display device comprising: Comprising: The timing control circuit according to any one of claims 1-4; The display panel is electrically connected with the timing control circuit. The timing control circuit is configured to receive and store a control signal, and control the display panel to display according to the stored control signal in case of interruption of the control signal.

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