Display panel and display device

Abstract

The present application discloses a display panel and a display device, relating to the technical field of displays. The disclosed display panel includes: two charging gate driving units are respectively disposed on non-display areas on both sides of the display area. Each charging gate driving unit is respectively connected to and stores a discharge start signal. The charging gate driving unit is connected to each pixel unit in the display area through a scanning line, and is used for counting the number of outputs of the output pixel clock signal, and generating a charging start signal when the counted current number of outputs is a multiple of the target signal number, and outputting the charging start signal to the pixel unit row by row through the scanning line to control the pixel unit to perform row-by-row charging; and is further used for, after detecting that the row-by-row charging of the pixel unit is completed, outputting the discharge start signal to the pixel unit row by row through the scanning line to control the pixel unit to perform row-by-row discharge, which not only ensures the charging efficiency of the liquid crystal, but also avoids the increase in the number of gate driving units.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] TZS (Thousand Zones Scanning) technology is a technology that realizes the charging and discharging of liquid crystals in a display panel within the same frame to cover the residual image of the display screen and eliminate ghosting. The current TZS technology has TZS single-sided driving to realize the charging and discharging of liquid crystals and TZS double-sided driving to realize the charging and discharging of liquid crystals.

[0003] Specifically, TZS single-sided driving is to set the gate driving unit on one side of the display panel to charge the liquid crystals, and the gate driving unit on the other side to discharge the liquid crystals. However, since only one gate driving unit is used to charge the liquid crystals on the entire panel, there is a problem of low charging efficiency of the liquid crystals.

[0004] And TZS double-sided driving is proposed based on the problems existing in TZS single-sided driving. By respectively setting a group of gate driving units on both sides of the display panel to charge and discharge the liquid crystals, that is, there is one gate driving unit on each side of the display panel to charge the liquid crystals, which avoids the situation of insufficient charging of the liquid crystals. However, correspondingly, the increase in the setting of gate driving units will cause an increase in the number of traces on the non-display area of the display panel, resulting in the defects of complex trace design and insufficient reserved space on the panel.

[0005] Application Content

[0006] The main purpose of the present application is to provide a display panel and a display device, aiming to solve the technical problem of how to ensure the charging efficiency of liquid crystals while avoiding the increase in the setting of gate driving units.

[0007] To achieve the above object, the present application proposes a display panel, which includes two charging gate driving units. The charging gate driving units are respectively arranged in the non-display areas on both sides of the display area, and each charging gate driving unit respectively accesses and stores a discharge start signal;

[0008] The charging gate driving unit is connected to each pixel unit in the display area through a scanning line;

[0009] The charging gate driving unit is used to count the number of outputs of the output pixel clock signal, and when the counted current number of outputs is a multiple of the target signal number, generate a charging start signal, and output the charging start signal to the pixel unit row by row through the scanning line to control the pixel unit to perform row-by-row charging;

[0010] The charging gate driving unit is further configured to, after detecting that the pixel units are charged row by row, output a discharge start signal row by row to the pixel units through the scan lines, and control the pixel units to discharge row by row.

[0011] In one embodiment, the charging gate driving unit includes a timing controller;

[0012] The timing controller is configured to output a frame start signal and a continuous clock pulse signal, count the number of output pixel clock signals generated and output based on the frame start signal and the continuous clock pulse signal, and when the counted current output number is a multiple of the target signal number, generate a charging start signal and transmit the charging start signal to each pixel unit to charge each pixel unit row by row;

[0013] The timing controller is further configured to, when detecting that the pixel units are charged row by row and the counted next output number is a multiple of the target signal number, transmit the stored discharge start signal to each pixel unit to discharge each pixel unit row by row.

[0014] In one embodiment, the charging gate driving unit further includes a latch clock generator connected to the timing controller;

[0015] The latch clock generator is configured to periodically output a target number of pixel clock signals according to the received frame start signal and continuous clock pulse signal.

[0016] In one embodiment, the charging start signal is output before the latch clock generator outputs the pixel clock signal of the next cycle, so as to include the rising edge of the first pixel clock signal in the next cycle within the time period corresponding to the high level of the charging start signal.

[0017] In one embodiment, the discharge start signal is output before the latch clock generator outputs the pixel clock signal of the new next cycle, so as to include the rising edge of the first pixel clock signal in the new next cycle within the time period corresponding to the high level of the discharge start signal.

[0018] In one embodiment, the number of rows of the pixel units charged row by row is a multiple of the target signal number;

[0019] The number of rows of the pixel units discharged row by row is a multiple of the target signal number.

[0020] In one embodiment, the rising edge of the pixel clock signal is included within the time period corresponding to the high level of the previous pixel clock signal in the same cycle.

[0021] In one embodiment, the structures of the pixel units on the same display area are the same. The pixel units are arranged between two adjacent scan lines. The pixel unit includes a first transistor, and a storage capacitor and a liquid crystal capacitor connected in parallel;

[0022] The control terminal of the first transistor is connected to the first scan line, and the first ends of the storage capacitor and the liquid crystal capacitor are respectively connected to the output terminal of the first transistor;

[0023] The first transistor is configured to enter a conducting state when a charging start signal is received through the first scan line, charge the liquid crystal capacitor, and store energy through the storage capacitor.

[0024] In one embodiment, the pixel unit further includes a second transistor;

[0025] The control terminal of the second transistor is connected to a second scan line adjacent to the first scan line, and the second transistor is connected in parallel with the storage capacitor;

[0026] The second transistor is configured to enter a conducting state when a discharge start signal is received through the second scan line, and discharge the electrical energy stored in the storage capacitor.

[0027] In addition, to achieve the above object, the present application further provides a display device. The display device includes the above display panel. The display panel includes two charging gate driving units, which are respectively disposed on non-display areas on both sides of the display area. Each charging gate driving unit receives and stores a discharge start signal;

[0028] The charging gate driving unit is connected to each pixel unit in the display area through a scan line;

[0029] The charging gate driving unit is configured to count the number of output pixel clock signals, generate a charging start signal when the counted current output number is a multiple of the target signal number, and output the charging start signal to the pixel unit row by row through the scan line to control the pixel unit to perform row-by-row charging;

[0030] The charging gate driving unit is further configured to, after detecting that the row-by-row charging of the pixel unit is completed, output a discharge start signal to the pixel unit row by row through the scan line to control the pixel unit to perform row-by-row discharge.

[0031] One or more technical solutions proposed by the present application have at least the following technical effects:

[0032] A display panel is proposed. The display panel includes two charging gate driving units, which are respectively arranged on the non-display areas on both sides of the display area. Each charging gate driving unit is respectively connected to and stores a discharge start signal; the charging gate driving unit is connected to each pixel unit in the display area through a scanning line; the charging gate driving unit is configured to count the number of outputs of the output pixel clock signal, and when the counted current number of outputs is a multiple of the target signal number, generate a charging start signal, and output the charging start signal to the pixel unit row by row through the scanning line to control the pixel unit to perform row-by-row charging; the charging gate driving unit is further configured to, after detecting that the pixel unit has completed row-by-row charging, output the discharge start signal to the pixel unit row by row through the scanning line to control the pixel unit to perform row-by-row discharge.

[0033] This application proposes a novel display panel with bilateral driving. By respectively arranging a charging gate driving unit on both sides of the display panel, the charging gate driving unit can generate a charging start signal to charge the pixel unit. At the same time, the charging gate driving unit is also respectively connected to and stores a discharge start signal. When it is necessary to discharge the liquid crystal, the discharge start signal is output to control the pixel unit to discharge, which not only ensures the charging efficiency of the liquid crystal but also avoids the increase in the number of gate driving units. Since the charging start signal and the discharge start signal are controlled by a single charging gate driving unit, in order to achieve accurate and orderly control of charging and discharging, this application sets the charging gate driving unit to count the number of outputs of the output pixel clock signal, generate and output a charging start signal according to the counting result, and then output the discharge start signal after detecting the completion of charging, so as to perform black frame insertion, eliminate ghosting, and avoid the signal output chaos caused by sharing a single charging gate driving unit for the charging start signal and the discharge start signal, thereby avoiding the phenomenon of abnormal display. Brief Description of the Drawings

[0034] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the accompanying drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0036] Figure 1 It is a schematic structural diagram of the display panel of this application;

[0037] Figure 2 It is a schematic structural diagram of a conventional single-sided driving display panel;

[0038] Figure 3 It is a schematic structural diagram of a conventional bilateral drive display panel;

[0039] Figure 4 It is a schematic timing diagram of the charging gate driving unit of the present application;

[0040] Figure 5 It is a schematic structural diagram of the pixel unit of the present application;

[0041] Figure 6 It is a schematic brief flowchart of the method for charging and discharging the pixel unit of the present application.

[0042] Explanation of the reference numerals in the drawings:

[0043] A, display area; B, non-display area;

[0044] 10. Charging gate driving unit; Gate line, scanning line; STV, frame start signal; CKV, continuous clock pulse signal; CK1, first pixel clock signal; CK2, second pixel clock signal; CK3, third pixel clock signal; CK4, fourth pixel clock signal; CK5, fifth pixel clock signal; CK6, sixth pixel clock signal; CK7, seventh pixel clock signal; CK8, eighth pixel clock signal; STV1, charging start signal; STV2, discharging start signal;

[0045] 20. Pixel unit; TFT1, first transistor; TFT2, second transistor; Cst, storage capacitor; Clc, liquid crystal capacitor.

[0046] The realization of the purpose, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. Specific embodiments

[0047] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0048] For a better understanding of the technical solutions of the present application, the following will be described in detail with reference to the drawings of the specification and specific embodiments.

[0049] The main solution of the embodiment of the present application is: to provide a display panel, which includes two charging gate driving units. The charging gate driving units are respectively arranged on the non-display areas on both sides of the display area. Each charging gate driving unit is respectively connected to and stores a discharge start signal; the charging gate driving unit is connected to each pixel unit in the display area through a scanning line; the charging gate driving unit is configured to count the number of outputs of the output pixel clock signal, and when the counted current number of outputs is a multiple of the target signal number, generate a charging start signal, and output the charging start signal to the pixel unit row by row through the scanning line to control the pixel unit to perform row-by-row charging; the charging gate driving unit is further configured to, after detecting that the pixel unit has completed row-by-row charging, output the discharge start signal to the pixel unit row by row through the scanning line to control the pixel unit to perform row-by-row discharge.

[0050] The current TZS technology has TZS single-sided driving for implementing the charging and discharging of liquid crystal and TZS double-sided driving for implementing the charging and discharging of liquid crystal. Specifically, TZS single-sided driving is to set the gate driving unit on one side of the display panel to charge the liquid crystal, and the gate driving unit on the other side to discharge the liquid crystal. However, since only one gate driving unit is used to charge the liquid crystal on the entire panel, there is a problem of low charging efficiency of the liquid crystal. And TZS double-sided driving is proposed based on the problems existing in TZS single-sided driving. By respectively arranging a set of gate driving units on both sides of the display panel to charge and discharge the liquid crystal, that is, there is one gate driving unit on each side of the display panel to charge the liquid crystal, which avoids the situation of insufficient charging of the liquid crystal. However, correspondingly, the increase in the setting of gate driving units will cause an increase in the number of traces on the non-display area of the display panel, resulting in complex trace design and insufficient reserved space on the panel.

[0051] The present application provides a novel double-sided driving display panel. By respectively arranging a charging gate driving unit on both sides of the display panel, the charging gate driving unit can generate a charging start signal to charge the pixel unit. At the same time, the charging gate driving unit is also respectively connected to and stores a discharge start signal. When it is necessary to discharge the liquid crystal, the discharge start signal is output to control the pixel unit to discharge, which not only ensures the charging efficiency of the liquid crystal but also avoids the increase in the number of gate driving units. And because the charging start signal and the discharge start signal are controlled by one charging gate driving unit, in order to accurately and orderly control the charging and discharging, the present application sets the charging gate driving unit to count the number of outputs of the output pixel clock signal, generate and output a charging start signal according to the counting result, and then output the discharge start signal after detecting the completion of charging, so as to perform black frame insertion, eliminate ghosting, and avoid the signal output chaos caused by sharing one charging gate driving unit for the charging start signal and the discharge start signal, thereby causing abnormal display.

[0052] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication, and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device, a display device, etc. that can implement the above functions. Hereinafter, taking the display device as an example, this embodiment and the following embodiments will be described.

[0053] Based on this, an embodiment of the present application provides a display panel. Referring to Figure 1 , Figure 1 which is a schematic structural diagram of the display panel of the present application.

[0054] The display panel includes two charging gate driving units 10, which are respectively arranged on the non-display areas B on both sides of the display area A. Each charging gate driving unit 10 is respectively connected to and stores a discharge start signal, and the charging gate driving unit 10 is connected to each pixel unit 20 in the display area A through a scan line Gate line.

[0055] According to Figure 1 the display panel shown, in this embodiment, a charging gate driving unit 10 is respectively arranged on the non-display areas B on both sides of the display panel. The charging gate driving unit 10 can generate a charging start signal by itself, and at the same time, the charging gate driving unit 10 is also connected to and stores an externally input discharge start signal, so that a charging gate driving unit 10 can output a charging start signal and a discharge start signal.

[0056] The charging gate driving units 10 arranged on both sides simultaneously charge each pixel unit 20 in the display area A through the scan line Gate line. Compared with Figure 2 the single-sided driving display panel shown, in which only the charging gate driving unit 10 on one side can charge the pixel units 20 of the whole panel, and the liquid crystal charging efficiency is insufficient due to the fact that the discharge gate driving unit on the other side controls the pixel units 20 of the whole panel to discharge, this embodiment can ensure the charging efficiency of the liquid crystal in the pixel units 20.

[0057] At the same time, because only one charging gate driving unit 10 is arranged on one side, compared with Figure 3 the double-sided driving display panel shown for improving the charging efficiency of liquid crystal, in which a charging gate driving unit 10 and a discharge gate driving unit are respectively arranged on both sides of the display panel, resulting in an increase in the number of gate driving unit traces, an increase in the complexity of the trace design of the display panel, and a shortage of reserved space on the display panel. This embodiment reduces the increase in the complexity of the trace design and avoids the shortage of reserved space on the panel. At the same time, because a latch clock generator needs to be correspondingly configured for each gate driving unit to output a pixel clock signal for the counting of the timing controller, this embodiment is relative to Figure 3In the case where 4 latch clocks need to be correspondingly configured as shown, 2 latch clocks are reduced, reducing the device cost.

[0058] The charge gate driving unit 10 is used to count the number of outputs of the output pixel clock signal, and when the counted current number of outputs is a multiple of the target signal number, generate a charge start signal, and output the charge start signal row by row to the pixel unit 20 through the scan line Gateline to control the pixel unit 20 to perform row-by-row charging; it is also used to output the discharge start signal row by row to the pixel unit 20 through the scan line Gate line after detecting that the pixel unit 20 has completed row-by-row charging, and control the pixel unit 20 to perform row-by-row discharging.

[0059] Since in this embodiment, the charge start signal and the discharge start signal are commonly used in a charge gate driving unit 10 for output, in order to avoid the display abnormality phenomenon caused by the chaotic output of the charge start signal and the discharge start signal, the output timings of the charge start signal and the discharge start signal are re-set.

[0060] Assume that the charge gate driving unit 10 outputs 8 pixel clock signals in one cycle. Specifically, it is set that the charge gate driving unit 10 calculates the output pixel clock signals, and when the counted number of the currently output pixel clock signals is a multiple of 8, generates a charge start signal, and through Figure 1 the scan line Gate line in, outputs the charge start signal row by row to the corresponding pixel unit 20 to control the pixel unit 20 to perform row-by-row charging. And after detecting that the row-by-row charging is completed, through Figure 1 the scan line Gate line in, outputs the stored discharge start signal row by row to the corresponding pixel unit 20 to control the pixel unit 20 to perform row-by-row discharging, so as to reduce the smear phenomenon existing in the displayed image.

[0061] Specifically, referring to Figure 4 as shown, the charge gate driving unit 10 includes a timing controller;

[0062] The timing controller is used to output a frame start signal STV and a continuous clock pulse signal CKV, count the number of outputs of the pixel clock signal generated and output based on the frame start signal STV and the continuous clock pulse signal CKV, and when the counted current number of outputs is a multiple of the target signal number, generate a charge start signal STV1, and transmit the charge start signal STV1 to each pixel unit 20 to perform row-by-row charging on each pixel unit 20; it is also used to transmit the stored discharge start signal STV2 to each pixel unit 20 when detecting that the pixel unit 20 has completed row-by-row charging and the counted next number of outputs is a multiple of the target signal number, and perform row-by-row discharging on each pixel unit 20.

[0063] Further, the charging gate driving unit 10 further includes a latch clock connected to the timing controller;

[0064] The latch clock is configured to periodically output a target number of pixel clock signals according to the received frame start signal STV and continuous clock pulse signal CKV.

[0065] Figure 4 For the signal timings of the signals output by the timing controller and the latch clock in the charging gate driving unit 10, and based on the signal timings of the timing controller and the latch clock, the timings of the charging start signal STV1 and the discharge start signal STV2 output.

[0066] According to Figure 4 It can be known that the timing controller outputs a frame start signal STV and a continuous clock pulse signal CKV in the time section of the frame start signal STV to the latch clock. When the latch clock detects the rising edge of any clock pulse signal in the continuous clock pulse signal CKV during the high level period of the frame start signal STV, it starts to periodically output pixel clock signals. This periodicity means that the latch clock repeats outputting a target number of pixel clock signals. For Figure 4 example, the target number of signals is 8, and the latch clock periodically outputs the first pixel clock signal CK1 to the eighth pixel clock signal CK8.

[0067] At this time, the timing controller counts the number of outputs of the pixel clock signals output by the latch clock, and when the counted number of outputs of the currently output pixel clock signal is a multiple of 8, it starts to generate a charging start signal STV1, and outputs the charging start signal STV1 to the pixel unit 20 row by row through the scan line Gate line for liquid crystal charging operation. At the same time, when it is detected through the timing controller that the row-by-row charging of the pixel unit 20 is completed and the counted number of outputs of the currently output pixel clock signal is a multiple of 8, the stored discharge start signal STV2 is transmitted to each pixel unit 20 to perform row-by-row discharge on each pixel unit 20.

[0068] For example, when the timing controller counts that the number of output pixel clock signals for the current output is 16, which is a multiple of 8, it starts to generate and output the charging start signal STV1. When it detects that the charging is completed and counts that the number of output pixel clock signals for the current output is 32, which is a multiple of 8, it starts to output the discharging start signal STV2. In this way, the output times of the charging start signal STV1 and the discharging start signal STV2 are separated to ensure the orderliness of the output and the effectiveness of the liquid crystal charging and discharging. Among them, the output charging start signal STV1 and discharging start signal STV will undergo voltage conversion through a latch clock to convert them from a low voltage to a high voltage.

[0069] The following provides supplementary explanations for the output timings of the charging start signal STV1 and the discharging start signal STV2 and the corresponding charging and discharging operations:

[0070] ① The charging start signal STV1 is output before the latch clock outputs the pixel clock signal for the next cycle, so as to include the rising edge of the first pixel clock signal in the next cycle within the time period corresponding to the high level of the charging start signal STV1. Based on Figure 4 it can be known that the high-level time period of the charging start signal STV1 includes the rising edge of the first pixel clock signal CK1 in one cycle. The purpose is to ensure the accuracy of the output timing of the charging start signal STV1 and avoid display abnormalities caused by incorrect charging.

[0071] ② The discharging start signal STV2 is output before the latch clock outputs the pixel clock signal for the new next cycle, so as to include the rising edge of the first pixel clock signal in the new next cycle within the time period corresponding to the high level of the discharging start signal STV2. Based on Figure 4 it can be known that the discharging start signal STV2, like the charging start signal STV1, has a high-level time period that includes the rising edge of the first pixel clock signal CK1 in one cycle. The purpose is to ensure the accuracy of the output timing of the discharging start signal STV2 and avoid display abnormalities caused by incorrect discharging.

[0072] ③ The number of rows of the pixel units 20 that are charged row by row is a multiple of the number of target signals; the number of rows of the pixel units 20 that are discharged row by row is a multiple of the number of target signals. It should be noted that the row-by-row charging operation of the pixel units 20 by the charging start signal STV1 is not necessarily to charge all the pixel units 20 in the whole panel, but based on the actual liquid crystal charging requirement, the number of rows of the pixel units 20 to be charged row by row is set as a multiple of the number of pixel clock signals output by the latch clock generator in one cycle; similarly, the row-by-row discharging operation of the pixel units 20 by the discharging start signal STV2 is not necessarily to discharge all the pixel units 20 in the whole panel, but based on the actual liquid crystal discharging requirement, the number of rows of the pixel units 20 to be discharged row by row is set as a multiple of the number of pixel clock signals output by the latch clock generator in one cycle, so as to fit with the periodically output pixel clock signals and avoid signal timing disorder.

[0073] ④ The rising edge of the pixel clock signal is included in the time period corresponding to the high level of the previous pixel clock signal in the same cycle. Taking Figure 4 the first pixel clock signal CK1 and the second pixel clock signal CK2 in one cycle as an example, according to Figure 4 it can be known that when the time point of the rising edge of any clock pulse signal is within the high level time section of the frame start signal STV, the time point corresponding to the rising edge of this clock pulse signal (hereinafter referred to as the first clock pulse signal) is the time point when the latch clock generator starts to output the first pixel clock signal in the first cycle, that is, the time point when the first pixel clock signal starts to generate the rising edge, and the time point when the first pixel clock signal starts to generate the falling edge is the time when the next clock pulse signal of the first clock pulse signal (hereinafter referred to as the second clock pulse signal) generates the falling edge, and the time point when the second pixel clock signal CK2 in this cycle generates the rising edge is the time point when the second clock pulse signal generates the rising edge. Therefore, the rising edge of the second pixel clock signal CK2 is included in the time period corresponding to the high level of the first pixel clock signal CK1 in the same cycle, so as to ensure the continuity between the output pixel clock signals.

[0074] Specifically, referring to Figure 5 as shown, the structures of the pixel units 20 in the same display area A are the same. The pixel units 20 are arranged between two adjacent scan lines Gate line. The pixel unit 20 includes a first transistor TFT1, and a storage capacitor Cst and a liquid crystal capacitor Clc connected in parallel;

[0075] The control terminal of the first transistor TFT1 is connected to the first scan line Gate line1. The first ends of the storage capacitor Cst and the liquid crystal capacitor Clc are respectively connected to the output terminal of the first transistor TFT1, and are used to enter the conducting state when the charging start signal STV1 is accessed through the first scan line Gate line1, charge the liquid crystal capacitor Clc, and store energy through the storage capacitor Cst.

[0076] According to Figure 5 From the structure diagram of the pixel unit 20 of the present example shown, the pixel unit 20 in this embodiment is a 2T2C structure. Among them, the control terminal of the first transistor TFT1 on the pixel unit 20 is connected to the scan line Gate line, and this scan line Gate line is the scan line Gateline for the charge gate driving unit 10 to output the charging start signal STV1. Therefore, this scan line Gate line is defined as the first scan line Gate line1. After the charging start signal STV1 is accessed through the first scan line Gateline1, the first transistor TFT1 conducts. Since the input terminal of the first transistor TFT1 is connected to the data line, the conducting first transistor TFT1 will access the data voltage on the data line. This data voltage will be applied to the first ends of the storage capacitor Cst and the liquid crystal capacitor Clc. The second end of the storage capacitor Cst is connected to the common voltage of the array substrate, and the second end of the liquid crystal capacitor Clc is connected to the common voltage of the color filter substrate, so as to form a voltage difference across the storage capacitor Cst and the liquid crystal capacitor Clc respectively, charge the liquid crystal capacitor Clc, and store energy in the storage capacitor Cst.

[0077] Furthermore, the pixel unit 20 further includes a second transistor TFT2;

[0078] The control terminal of the second transistor TFT2 is connected to the second scan line Gateline2 adjacent to the first scan line Gate line1. The second transistor TFT2 is connected in parallel with the storage capacitor Cst; and is used to enter the conducting state when the discharge start signal STV2 is accessed through the second scan line Gate line2, and discharge the electrical energy stored in the storage capacitor Cst.

[0079] Specifically, the control terminal of the second transistor TFT2 on the pixel unit 20 is connected to a scan line adjacent to the first scan line Gate line1. This adjacent scan line is the scan line used by the charge gate driving unit 10 to output the discharge start signal STV2. Therefore, this scan line is defined as the second scan line Gate line2. After the discharge start signal STV2 is accessed through the second scan line Gate line2, the second transistor TFT2 is turned on. Since the first transistor TFT1 enters the cut-off state at this time, and the second transistor TFT2 is connected in parallel across both ends of the storage capacitor Cst, the turned-on second transistor TFT2 will cause the storage capacitor Cst to start releasing the electrical energy it stores. At this time, the storage capacitor Cst can no longer supply energy to the liquid crystal capacitor Clc. The liquid crystal corresponding to this pixel unit 20 has no electric field and is in a random arrangement. The backlight cannot pass through the liquid crystal molecules, realizing black frame insertion.

[0080] Exemplarily, to facilitate understanding of the implementation process of the charging method obtained by combining this embodiment with the above embodiments, please refer to Figure 6 , Figure 6 A schematic flowchart of a brief process for charging and discharging a pixel unit is provided. Specifically:

[0081] The timing controller outputs a frame start signal and a continuous clock pulse signal in the time section of the frame start signal to the latch clock generator ( Figure 6 S1 in), and the latch clock generator starts to periodically output pixel clock signals according to the accessed frame start signal and continuous clock pulse signal ( Figure 6 S2 in). After receiving the front-end data, the timing controller stores the front-end data in the line buffer ( Figure 6 S3 in), starts to count the number of output pixel clock signals output by the latch clock generator ( Figure 6 S4 in), and determines whether the counted number of output pixel clock signals currently output is a multiple of the target signal number ( Figure 6 S5 in). If not, continue counting. If so, before the rising edge of the first pixel clock signal in the next cycle, start generating a charge start signal and output the charge start signal to the pixel unit row by row through the scan line for liquid crystal charging operation ( Figure 6 S6 in). At the same time, when it is detected by the timing controller that the pixel unit is charged row by row, and the counted number of output pixel clock signals currently output is a multiple of the target signal number, before the rising edge of the first pixel clock signal in the new next cycle, the stored discharge start signal is passed into each pixel unit, and after discharging each pixel unit row by row ( Figure 6 S7 in), at this time, it is judged whether there is newly accessed front-end data ( Figure 6In S8), if so, the timing controller counts the number of output pixel clock signals output by the latch clock again. If no new front-end data is connected, the charging and discharging operation of the pixel unit ends.

[0082] It should be noted that the above examples are only for understanding the present application and do not constitute a limitation on the method for charging and discharging the pixel unit of the present application. Based on this technical concept, more forms of simple transformations are within the protection scope of the present application.

[0083] The above is only an exemplary embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structural transformation made by using the content of the specification and drawings of the present application under the technical concept of the present application, or directly / indirectly applied to other related technical fields, is included in the patent protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel includes two charging gate driving units, which are respectively arranged on non-display areas on both sides of the display area, each of which is connected to and stores a discharge start signal, and is connected to each pixel unit on the display area through a scanning line, and each of which includes a timing controller; The timing controller is used to count the number of output pixel clock signals outputted, and when the current number of outputs counted is a multiple of the number of target signals, generate a charging start signal, and output the charging start signal to the pixel units row by row through the scanning lines, and control the pixel units to charge row by row, wherein the pixel clock signal is generated based on a frame start signal and a continuous clock pulse signal outputted by the timing controller; The timing controller is also used to output the discharge start signal to the pixel unit row by row through the scan line when it is detected that the pixel unit has completed charging row by row and the next output number obtained by counting is a multiple of the target signal number, so as to control the pixel unit to discharge row by row.

2. The display panel according to claim 1, wherein: The charging gate driving unit also includes a latch clock connected to the timing controller; The latch clock is used to periodically output the pixel clock signal of the target signal number according to the input frame start signal and the continuous clock pulse signal.

3. The display panel according to claim 2, wherein: The charging start signal is output before the latch clock outputs the pixel clock signal of the next cycle, so that the rising edge of the first pixel clock signal in the next cycle is included in the time period corresponding to the high level of the charging start signal.

4. The display panel according to claim 2, wherein: The discharge start signal is output before the latch clock outputs the pixel clock signal of the new next cycle, so that the rising edge of the first pixel clock signal in the new next cycle is included in the time period corresponding to the high level of the discharge start signal.

5. The display panel according to claim 2, wherein: The number of rows of pixel units charged row by row is a multiple of the number of target signals; The number of rows of pixel units discharged row by row is a multiple of the number of target signals.

6. The display panel according to claim 2, wherein: The rising edge of the pixel clock signal is included in the time period corresponding to the high level of the previous pixel clock signal in the same cycle.

7. The display panel according to claim 1, wherein: The pixel units on the same display area have the same structure, the pixel unit is arranged between two adjacent scanning lines, and the pixel unit includes a first transistor, and a storage capacitor and a liquid crystal capacitor connected in parallel; The control terminal of the first transistor is connected to the first scan line, and the first terminal of the storage capacitor and the first terminal of the liquid crystal capacitor are respectively connected to the output terminal of the first transistor; The first transistor is used to enter a conducting state when the charging start signal is connected through the first scanning line, charge the liquid crystal capacitor and store energy through the storage capacitor.

8. The display panel according to claim 7, wherein: The pixel unit further includes a second transistor; The control terminal of the second transistor is connected to a second scan line adjacent to the first scan line, and the second transistor is connected in parallel with the storage capacitor; The second transistor is used to enter a conducting state when the discharge start signal is connected through the second scan line, so as to discharge the electric energy stored in the storage capacitor.

9. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 8.

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