Passive equalizer for inter-corelet interconnect and inter-corelet interconnect system

Abstract

The application provides a passive equalizer for inter-core particle interconnection and an inter-core particle interconnection system, which comprises upper sawtooth metal copper wires, lower sawtooth metal copper wires, a first via and a second via; the upper sawtooth metal copper wires are provided with the second via on one side and connected to the lower sawtooth metal copper wires through the first via on the other side; and the upper sawtooth metal copper wires and the lower sawtooth metal copper wires are both provided in a sawtooth shape and staggered. The double-layer sawtooth cross metal copper wires embedded in the metal grounding layer can effectively solve the serious inter-symbol interference (ISI) problem existing in the high-speed parallel data transmission system, and the voltage transmission curve of the channel in the transmission system is flattened in the range of direct current frequency and Nyquist frequency, so that the eye diagram quality of the receiver is obviously improved.

Description

Technical Field

[0001] This invention relates to the field of high-speed data transmission technology, specifically to a passive equalizer and inter-chip interconnection system for inter-chip interconnection; and more particularly to a passive equalizer for high-speed, high-bandwidth inter-chip interconnection. Background Technology

[0002] With the ever-increasing demand for memory bandwidth in electronic devices, traditional data transmission methods can no longer meet the memory bandwidth requirements of terabyte-level devices. During high-speed data transmission, frequency-dependent attenuation of the signal in the transmission medium leads to inter-symbol interference (ISI), which in turn affects the receiver's eye diagram opening, voltage margin, and timing jitter, reducing system sensitivity and bit error rate (BER). To compensate for the frequency-dependent losses in high-speed I / O channels, equalization methods are required.

[0003] Traditional active equalizers use active devices (such as transistors and amplifiers) to modulate signals during circuit implementation, resulting in high power consumption. Furthermore, they require larger chip areas for circuit layout, making design on high-density interposers particularly challenging and difficult to apply in high I / O density systems. Therefore, passive equalizers are more advantageous in low-power, high-bandwidth, and high I / O density systems. Summary of the Invention

[0004] In view of the deficiencies in the prior art, the purpose of this invention is to provide a passive equalizer and an inter-chip interconnection system for chip interconnection.

[0005] A passive equalizer for inter-chip interconnection provided by the present invention includes: an upper serrated copper wire, a lower serrated copper wire, a first via, and a second via;

[0006] The upper serrated copper wire is provided with a second via on one side and connected to the lower serrated copper wire through a first via on the other side;

[0007] Both the upper and lower layer sawtooth-shaped copper wires are configured in a sawtooth shape and are arranged alternately.

[0008] Preferably, the upper serrated copper wire is connected to the signal path through a second via.

[0009] Preferably, the transmitting end of the signal path is connected to the first pad, and the receiving end of the signal path is connected to the second pad.

[0010] Preferably, the first via is located at one end of the upper serrated copper wire, and the second via is located at the other end of the upper serrated copper wire.

[0011] Preferably, both the upper and lower serrated copper wires are formed by connecting multiple straight metal lines end to end at a set angle.

[0012] Preferably, an inter-chip interconnect system employing the passive equalizer for inter-chip interconnection includes: a metal signal layer, a metal ground layer, a dielectric layer, and a substrate;

[0013] The substrate is disposed on one side of the dielectric layer, and the metal ground layer and the metal signal layer are disposed within the dielectric layer;

[0014] One or more passive equalizers are provided in the metal grounding layer, and one or more signal paths are provided in the metal signal layer, with the passive equalizers connected to the signal paths.

[0015] Preferably, the dielectric layer is made of silicon dioxide, and the substrate is made of silicon.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] This application employs a passive equalizer composed of double-layer sawtooth-crossing copper wires embedded in a metallic ground layer. Utilizing structural resistance and inductance, it reduces signal gain in the low-to-mid frequency range while maintaining channel gain in the high-frequency range. This is reflected in the voltage transmission curve of the transmission system channel as a flattening of the transmission spectrum within the DC and Nyquist frequency ranges. This effectively solves the severe inter-symbol interference (ISI) problem present in high-speed parallel data transmission systems, significantly improving the eye diagram quality of the receiver. Attached Figure Description

[0018] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0019] Figure 1 A top view of the overall connection between the passive equalizer and the multi-core interconnect target channel;

[0020] Figure 2 A schematic diagram of a single passive equalizer structure embedded in a metal grounding layer;

[0021] Figure 3 A schematic diagram of the overall connection profile of the passive equalizer with the first, third, and fifth interconnection channels (along...) Figure 1 (AA section);

[0022] Figure 4 A schematic diagram of the overall connection profile of the passive equalizer with the second and fourth interconnection channels (along...) Figure 1 BB location);

[0023] Figure 5 Based on Figure 1 An eye diagram simulation measurement circuit was established after extracting the channel S-parameters from the overall interconnected channel system.

[0024] Figure 6 Eye diagram of the original target channel without passive equalizer applied at a transmission rate of 8Gbps;

[0025] Figure 7 Eye diagram of the target channel to which passive equalizer is applied at a transmission rate of 8Gbps;

[0026] Figure 8 Eye diagram of the original target channel without passive equalizer applied at a transmission rate of 16Gbps;

[0027] Figure 9 Eye diagram of the target channel to which passive equalizer is applied at a transmission rate of 16Gbps;

[0028] As shown in the figure:

[0029] Detailed Implementation

[0030] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0031] Example 1

[0032] This embodiment utilizes the principle of a resistance-inductance (RL) resonant circuit. This structure can effectively solve the severe inter-symbol interference (ISI) problem in high-speed parallel data transmission systems. In the voltage transmission equation of the transmission system, it manifests as a flattening of the transmission spectrum in the DC frequency and Nyquist frequency range, thus significantly improving the eye diagram quality of the receiver.

[0033] This embodiment can be applied to a storage-processor interconnect system, which includes: a metal ground layer 601, a dielectric layer 701, and a substrate 801. The substrate 801 is disposed on one side of the dielectric layer 701. The metal ground layer 601 and a metal signal layer are disposed within the dielectric layer 701. One or more passive equalizers are disposed within the metal ground layer 601. The passive equalizers are double-layered sawtooth-shaped cross-shaped copper wires embedded within the metal ground layer 601. The metal signal layer provides one or more signal paths, and the passive equalizers are connected to the signal paths. The dielectric layer 701 is made of silicon dioxide, and the substrate 801 is made of silicon.

[0034] The passive equalizer in this embodiment includes: an upper sawtooth-shaped copper wire, a lower sawtooth-shaped copper wire, a first via, and a second via; one side of the upper sawtooth-shaped copper wire is connected to a signal path through the second via, and the other side is connected to the lower sawtooth-shaped copper wire through the first via; the first via is located at one end of the upper sawtooth-shaped copper wire. Figure 2 The second via is located at the other end of the upper layer of serrated copper wire (top right corner). Figure 2 (The left middle part of the image). The transmitting end of the signal path is connected to the first pad, and the receiving end of the signal path is connected to the second pad. In actual interconnection, the transmitting chip is connected to the first pad through microbumps, and the receiving chip is connected to the second pad through microbumps, thereby realizing chip-to-chip interconnection.

[0035] Both the upper and lower serrated copper wires are serrated and staggered. The upper and lower serrated copper wires are formed by connecting multiple straight metal lines end to end at a set angle.

[0036] Specifically, such as Figure 1-4 As shown, a first passive equalizer 104, a second passive equalizer 204, a third passive equalizer 304, a fourth passive equalizer 404, and a fifth passive equalizer 504 are embedded in the metal grounding layer 601; a first signal path 103, a second signal path 203, a third signal path 303, a fourth signal path 403, and a fifth signal path 503 are provided in the metal signal layer; the first passive equalizer 104 is connected to the first signal path 103, the second passive equalizer 204 is connected to the second signal path 203, the third passive equalizer 304 is connected to the third signal path 303, the fourth passive equalizer 404 is connected to the fourth signal path 403, and the fifth passive equalizer 504 is connected to the fifth signal path 503. The transmitting end of the first signal path 103 is connected to the first pad 101 of the first signal path, and the receiving end is connected to the second pad 102 of the first signal path. The transmitting end of the second signal path 203 is connected to the first pad 201 of the second signal path, and the receiving end is connected to the second pad 202 of the second signal path. The transmitting end of the third signal path 303 is connected to the first pad 301 of the third signal path, and the receiving end is connected to the second pad 302 of the third signal path. The transmitting end of the fourth signal path 403 is connected to the first pad 401 of the fourth signal path, and the receiving end is connected to the second pad 402 of the fourth signal path. The transmitting end of the fifth signal path 503 is connected to the first pad 501 of the fifth signal path, and the receiving end is connected to the second pad 502 of the fifth signal path.

[0037] The first passive equalizer 104 includes: a first upper-layer sawtooth-shaped copper wire 1041, a first lower-layer sawtooth-shaped copper wire 1042, a first passive equalizer via 1043, and a first passive equalizer via 105; one end of the first upper-layer sawtooth-shaped copper wire 1041 is connected to the first signal path 103 through the first passive equalizer via 105, and the other end of the first upper-layer sawtooth-shaped copper wire 1041 is connected to the first lower-layer sawtooth-shaped copper wire 1042 through the first passive equalizer via 1043; the second passive equalizer 204 includes: a second upper-layer sawtooth-shaped copper wire 2041 and a second lower-layer sawtooth-shaped copper wire 2042. The second passive equalizer has a first via 2043 and a second via 205; one end of the second upper sawtooth copper wire 2041 is connected to the second signal path 203 through the second passive equalizer second via 205, and the other end of the second upper sawtooth copper wire 2041 is connected to the second lower sawtooth copper wire 2042 through the second passive equalizer first via 2043; the third passive equalizer 304 includes: a third upper sawtooth copper wire 3041, a third lower sawtooth copper wire 3042, a third passive equalizer first via 3043, and a third passive equalizer second via 305; the third upper sawtooth copper wire 304... One end of the third upper sawtooth copper wire 3041 is connected to the third signal path 303 through the second via 305 of the third passive equalizer. The other end of the third upper sawtooth copper wire 3041 is connected to the third lower sawtooth copper wire 3042 through the first via 3043 of the third passive equalizer. The fourth passive equalizer 404 includes: a fourth upper sawtooth copper wire 4041, a fourth lower sawtooth copper wire 4042, a fourth passive equalizer first via 4043, and a fourth passive equalizer second via 405. One end of the fourth upper sawtooth copper wire 4041 is connected to the fourth signal path 403 through the second via 405 of the fourth passive equalizer. The other end of the other side of 4041 is connected to the fourth lower layer sawtooth copper wire 4042 through the first via 4043 of the fourth passive equalizer; the fifth passive equalizer 504 includes: a fifth upper layer sawtooth copper wire 5041, a fifth lower layer sawtooth copper wire 5042, a fifth passive equalizer first via 5043, and a fifth passive equalizer second via 505; one end of the fifth upper layer sawtooth copper wire 5041 is connected to the fifth signal path 503 through the fifth passive equalizer second via 505, and the other end of the fifth upper layer sawtooth copper wire 5041 is connected to the fifth lower layer sawtooth copper wire 5042 through the fifth passive equalizer first via 5043.

[0038] Example 2

[0039] Example 2 is a preferred example of Example 1.

[0040] like Figure 1-4 As shown, this embodiment includes five sets of passive equalizers with identical structures. The metal wires of the first passive equalizer 104, the second passive equalizer 204, the third passive equalizer 304, the fourth passive equalizer 404, and the fifth passive equalizer 504 all have a double-layered serrated cross-line shape. Their vertical distribution in the metal grounding layer 601, from top to bottom, is an upper layer of serrated copper wire, an intermediate layer, and a lower layer of serrated copper wire, all of which are embedded in the metal grounding layer 601. The serrated cross-line is formed by splicing together multiple straight metal lines.

[0041] When the five sets of passive equalizers are connected to the parallel signal path structure, the metal wires of the first passive equalizer 104, the second passive equalizer 204, the third passive equalizer 304, the fourth passive equalizer 404, and the fifth passive equalizer 504 are all buried in the metal grounding layer 601 (GND layer), and the signal paths of the first passive equalizer 104, the second passive equalizer 204, the third passive equalizer 304, the fourth passive equalizer 404, and the fifth passive equalizer 504 are all located in the metal signal layer.

[0042] like Figure 1 As shown, all signal paths are located in the metal signal layer, and the passive equalizer is embedded in the metal ground layer 601. All metals involved in the entire system are copper. The overall parallel path structure includes: a first signal path 103 and a first passive equalizer 104 connected thereto; the transmitter of the first signal path 103 is connected to the first pad 101 of the first signal path, and the receiver is connected to the second pad 102 of the first signal path; a second signal path 203 and a second passive equalizer 204 connected thereto; the transmitter of the second signal path 203 is connected to the first pad 201 of the second signal path, and the receiver is connected to the second pad 202 of the second signal path; a third signal path 303 and a third passive equalizer 304 connected thereto. The transmitter of path 303 is connected to the first pad 301 of the third signal path, and the receiver is connected to the second pad 302 of the third signal path; the fourth signal path 403 and the fourth passive equalizer 404 connected thereto, the transmitter of the fourth signal path 403 is connected to the first pad 401 of the fourth signal path, and the receiver is connected to the second pad 402 of the fourth signal path; the fifth signal path 503 and the fifth passive equalizer 504 connected thereto, the transmitter of the fifth signal path 503 is connected to the first pad 501 of the fifth signal path, and the receiver is connected to the second pad 502 of the fifth signal path.

[0043] like Figure 2-3As shown, the specific structure of the double-layer sawtooth-shaped cross-metal copper wires, taking the third channel as an example, is as follows: The third passive equalizer 304 applied in the third channel consists of a third upper-layer sawtooth-shaped metal copper wire 3041, a third passive equalizer first via 3043 connecting the upper and lower layers of sawtooth-shaped metal copper wires, and a third lower-layer sawtooth-shaped metal copper wire 3042. The connection relationship of the third passive equalizer 304 is as follows: the upper side of the third upper-layer sawtooth-shaped metal copper wire 3041 is connected to the third signal path 303 through the third passive equalizer second via 305, and the lower side of the third lower-layer sawtooth-shaped metal copper wire 3042 is connected to the metal ground layer 601. Its substrate 801 is silicon, and the dielectric layer 701 is silicon dioxide.

[0044] The simulation and verification process of the miniature passive equalizer in this embodiment is as follows:

[0045] like Figure 5 As shown, in this embodiment: the power supply VTX at the transmitting end of the signal path is 1.2V, and the resistor at the transmitting end is selected as 50 ohms to reduce channel power consumption and reduce crosstalk between adjacent I / O channels; the transmitting end capacitor CTX is set to 2.5pF according to JEDEC Standard No. 238, and the receiving end load capacitor C... load The value was determined to be 2.5pF. The S-parameter file was obtained by modeling the overall interconnection model using HFSS and performing finite element simulation. The S-parameters describe the frequency domain characteristics of the transmission channel, including S12 as the reverse transmission coefficient, S21 as the forward transmission coefficient, S11 as the input reflection coefficient, and S22 as the output reflection coefficient, which are used to reflect the frequency domain response of the signal during transmission.

[0046] like Figure 6 and Figure 7 As shown, comparing the receiver eye diagrams at 8Gbps with and without a passive equalizer, it can be found that the quality of the receiver eye diagram is significantly improved. The eye diagram height increases from the closed state to 189mV, an increase of 15.8% of the transmitter power supply VTX; the eye diagram width increases from the closed state to 111.2ps, an increase of 89.0% UI.

[0047] like Figure 8 and Figure 9 As shown, comparing the receiver eye diagrams at 16Gbps with and without a passive equalizer, it can be found that the receiver eye diagram quality is significantly improved. The eye diagram height increases from the closed state to 112mV, an increase of 9.3% of the transmitter power supply VTX; the eye diagram width increases from the closed state to 52.5ps, an increase of 84.0% UI.

[0048] This embodiment is applied to a high-speed, high-bandwidth memory (HBM) interconnect system, but is not limited to HBM interconnect systems; the interconnect substrate used in this embodiment is a silicon-based substrate, but is not limited to silicon substrates.

[0049] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0050] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A passive equalizer for inter-chip interconnection, characterized in that, include: Upper layer sawtooth copper wire, lower layer sawtooth copper wire, first via and second via; The upper serrated copper wire is provided with a second via on one side and connected to the lower serrated copper wire through a first via on the other side; Both the upper and lower layer sawtooth-shaped copper wires are configured in a sawtooth shape and are arranged alternately.

2. The passive equalizer for inter-chip interconnection according to claim 1, characterized in that: The upper-layer sawtooth-shaped copper wire is connected to the signal path through a second via.

3. The passive equalizer for inter-chip interconnection according to claim 2, characterized in that: The transmitting end of the signal path is connected to the first pad, and the receiving end of the signal path is connected to the second pad.

4. The passive equalizer for inter-chip interconnection according to claim 1, characterized in that: The first via is located at one end of the upper serrated copper wire, and the second via is located at the other end of the upper serrated copper wire.

5. The passive equalizer for inter-chip interconnection according to claim 1, characterized in that: Both the upper and lower serrated copper wires are formed by connecting multiple straight metal lines end to end at a set angle.

6. A core-to-core interconnection system employing the passive equalizer for core-to-core interconnection as described in any one of claims 1-5, characterized in that, include: Metal signal layer, metal ground layer (601), dielectric layer (701) and substrate (801); The substrate (801) is disposed on one side of the dielectric layer (701), and the metal ground layer (601) and the metal signal layer are disposed within the dielectric layer (701); One or more passive equalizers are provided in the metal grounding layer (601), and one or more signal paths are provided in the metal signal layer, with the passive equalizers connected to the signal paths.

7. The chip interconnect system according to claim 6, characterized in that: The dielectric layer (701) is made of silicon dioxide, and the substrate (801) is made of silicon.

8. The chip interconnect system according to claim 6, characterized in that: The first passive equalizer (104), the second passive equalizer (204), the third passive equalizer (304), the fourth passive equalizer (404) and the fifth passive equalizer (504) are embedded in the metal grounding layer (601). The metal signal layer is provided with a first signal path (103), a second signal path (203), a third signal path (303), a fourth signal path (403), and a fifth signal path (503). The first passive equalizer (104) is connected to the first signal path (103), the second passive equalizer (204) is connected to the second signal path (203), the third passive equalizer (304) is connected to the third signal path (303), the fourth passive equalizer (404) is connected to the fourth signal path (403), and the fifth passive equalizer (504) is connected to the fifth signal path (503).

9. The chip interconnect system according to claim 8, characterized in that: The first passive equalizer (104) includes: a first upper sawtooth copper wire (1041), a first lower sawtooth copper wire (1042), a first passive equalizer via (1043), and a first passive equalizer via (105). One end of the first upper sawtooth copper wire (1041) is connected to the first signal path (103) through the second via (105) of the first passive equalizer, and the other end of the first upper sawtooth copper wire (1041) is connected to the first lower sawtooth copper wire (1042) through the first via (1043) of the first passive equalizer. The second passive equalizer (204) includes: a second upper layer sawtooth metal copper wire (2041), a second lower layer sawtooth metal copper wire (2042), a second passive equalizer first via (2043), and a second passive equalizer second via (205). One end of the second upper layer sawtooth copper wire (2041) is connected to the second signal path (203) through the second passive equalizer second via (205), and the other end of the second upper layer sawtooth copper wire (2041) is connected to the second lower layer sawtooth copper wire (2042) through the second passive equalizer first via (2043). The third passive equalizer (304) includes: a third upper layer sawtooth copper wire (3041), a third lower layer sawtooth copper wire (3042), a third passive equalizer first via (3043), and a third passive equalizer second via (305). One end of the third upper layer sawtooth copper wire (3041) is connected to the third signal path (303) through the second via (305) of the third passive equalizer, and the other end of the third upper layer sawtooth copper wire (3041) is connected to the third lower layer sawtooth copper wire (3042) through the first via (3043) of the third passive equalizer. The fourth passive equalizer (404) includes: a fourth upper layer sawtooth copper wire (4041), a fourth lower layer sawtooth copper wire (4042), a first via of the fourth passive equalizer (4043), and a second via of the fourth passive equalizer (405). One end of the fourth upper-layer sawtooth copper wire (4041) is connected to the fourth signal path (403) through the second via (405) of the fourth passive equalizer, and the other end of the fourth upper-layer sawtooth copper wire (4041) is connected to the fourth lower-layer sawtooth copper wire (4042) through the first via (4043) of the fourth passive equalizer. The fifth passive equalizer (504) includes: a fifth upper layer sawtooth copper wire (5041), a fifth lower layer sawtooth copper wire (5042), a fifth passive equalizer first via (5043), and a fifth passive equalizer second via (505). One end of the fifth upper-layer sawtooth copper wire (5041) is connected to the fifth signal path (503) through the second via (505) of the fifth passive equalizer, and the other end of the fifth upper-layer sawtooth copper wire (5041) is connected to the fifth lower-layer sawtooth copper wire (5042) through the first via (5043) of the fifth passive equalizer.

10. The chip interconnect system according to claim 8, characterized in that: The transmitting end of the first signal path (103) is connected to the first pad (101) of the first signal path, and the receiving end is connected to the second pad (102) of the first signal path. The transmitting end of the second signal path (203) is connected to the first pad (201) of the second signal path, and the receiving end is connected to the second pad (202) of the second signal path. The transmitting end of the third signal path (303) is connected to the first pad (301) of the third signal path, and the receiving end is connected to the second pad (302) of the third signal path. The transmitting end of the fourth signal path (403) is connected to the first pad (401) of the fourth signal path, and the receiving end is connected to the second pad (402) of the fourth signal path. The transmitting end of the fifth signal path (503) is connected to the first pad (501) of the fifth signal path, and the receiving end is connected to the second pad (502) of the fifth signal path.

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