Anti-fuse array structure, programming method, reading method and memory

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a structure of anti-fuse array, a programming method, a reading method and a memory. The structure of anti-fuse array comprises: a plurality of anti-fuse integrated units on a substrate; the anti-fuse integrated unit comprises: a first anti-fuse unit and a second anti-fuse unit; the first anti-fuse unit comprises a first selection transistor and a first anti-fuse device; the second anti-fuse unit comprises a second selection transistor and a second anti-fuse device; the first selection transistor and the second selection transistor share a third doped region; a word line extends along a first direction, each word line is connected with the gate of the first selection transistor and / or the gate of the second selection transistor in at least one row of anti-fuse integrated units; a bit line extends along a second direction, each bit line is electrically connected with the third doped region in the same column of anti-fuse integrated units; the first direction intersects with the second direction. The embodiment of the present disclosure can at least improve the performance and integration of the structure of anti-fuse array.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductors, and specifically relates to an antifuse array structure, a programming method, a reading method, and a memory. Background Technology

[0002] An antifuse array structure includes an antifuse device, which is a one-time programmable device (OTP) widely used in memories such as Dynamic Random Access Memory (DRAM). An antifuse device is a semiconductor device consisting of two conductive layers and a dielectric layer between them. When unprogrammed, the two conductive layers are separated by the dielectric layer, and the antifuse is open. During programming, an applied high voltage causes the dielectric layer to break down, creating an electrical connection between the two conductive layers; this short circuit, or fuse, is called a short circuit. This fuse-breaking process is physically one-time, permanent, and irreversible. The two states of the antifuse—unfused and fused—can represent the logic value "0" or "1," respectively.

[0003] The antifuse array structure includes multiple antifuse units. Each antifuse unit includes a select transistor and an antifuse device connected in series. The gate of the select transistor is connected to the word line. The select transistor and the antifuse share a doped region. Another doped region of the select transistor is connected to the bit line.

[0004] However, the performance and integration of the antifuse array structure still need to be improved. Summary of the Invention

[0005] This disclosure provides an antifuse array structure, a programming method, a reading method, and a memory, which at least help improve the performance of the antifuse array structure.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides an antifuse array structure, wherein the antifuse array structure includes: a substrate, and a plurality of antifuse integrated units arranged in an array on the substrate; the antifuse integrated unit includes: a first antifuse unit and a second antifuse unit; the first antifuse unit includes a first selection transistor and a first antifuse device, which share a first doped region; the second antifuse unit includes a second selection transistor and a second antifuse device, which share a second doped region; the first selection transistor and the second selection transistor share a third doped region; the programming electrode of the first antifuse device, the gate of the first selection transistor, and the second selection transistor are also included. The gate of the transistor and the programming electrode of the second antifuse device are arranged along a first direction; multiple word lines extend along the first direction, each word line being connected to the gate of the first selection transistor and / or the gate of the second selection transistor in at least one row of the antifuse integrated units; multiple bit lines extend along a second direction, each bit line being electrically connected to a third doped region in the same column of the antifuse integrated units; multiple programming wires extend along the second direction, each programming wire being electrically connected to the programming electrode of the first antifuse device in the same column of the antifuse integrated units, or electrically connected to the programming electrode of the second antifuse device in the same column of the antifuse integrated units; the first direction and the second direction intersect.

[0007] According to some embodiments of this disclosure, another aspect of this disclosure provides a programming method applied to the aforementioned antifuse array structure. The programming method includes obtaining a target antifuse cell to be programmed in the antifuse array structure, as well as a word line, programming wire, and bit line corresponding to the target antifuse cell; applying an enable voltage to the word line corresponding to the target antifuse cell to turn on the select transistor of the target antifuse cell; applying a programming voltage to the programming wire corresponding to the target antifuse cell; and applying a zero voltage to the bit line corresponding to the target antifuse cell to break down the antifuse device in the target antifuse cell.

[0008] According to some embodiments of this disclosure, another aspect of this disclosure provides a reading method applied to the aforementioned antifuse array structure, which acquires the target antifuse unit to be read in the antifuse array structure, as well as the word line, programming wire, and bit line corresponding to the target antifuse unit; applies an enable voltage to the word line corresponding to the target antifuse unit to turn on the select transistor in the target antifuse unit; applies a read voltage to the programming wire corresponding to the target antifuse unit; applies zero voltage to the bit line corresponding to the target antifuse unit; and sets the programming wire corresponding to another antifuse unit electrically connected to the same bit line and the same word line as the target antifuse unit to a floating state; reads the current flowing through the target antifuse device; and determines the stored data of the target antifuse device based on the magnitude of the current.

[0009] According to some embodiments of this disclosure, in another aspect, this disclosure also provides a memory including the aforementioned antifuse array structure.

[0010] The technical solution provided in this disclosure has at least the following advantages: the extension direction of the bit lines is different from the arrangement direction of the programming electrode, the gate of the first select transistor, and the gate of the second select transistor of the first antifuse device, and also different from the arrangement direction of the first doped region, the third doped region, and the second doped region. This effectively reduces the area of ​​the bit lines facing these structures, thereby reducing parasitic capacitance. Furthermore, each word line is connected to the gate of the first select transistor and / or the gate of the second select transistor in at least one row of antifuse integrated units; multiple bit lines extend along a second direction, and each bit line is electrically connected to the second doped region in the same column of antifuse integrated units. This helps to reduce the total number of word lines and bit lines, thereby improving the integration density of the antifuse array structure. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0012] Figure 1 A partial top view of an antifuse array structure is shown.

[0013] Figure 2 A partial cross-sectional view of an antifuse array structure is shown.

[0014] Figure 3 An equivalent circuit diagram of an antifuse array structure is shown.

[0015] Figure 4 A partial cross-sectional view of an antifuse array structure provided in an embodiment of this disclosure is shown.

[0016] Figure 5 A top view of an antifuse integrated unit provided in an embodiment of this disclosure is shown.

[0017] Figure 6 , Figure 7 , Figure 9 Partial top views of different antifuse array structures are shown.

[0018] Figure 8 for Figure 6 and Figure 7 The equivalent circuit diagram of the antifuse array structure is shown.

[0019] Figure 10 for Figure 9 The equivalent circuit diagram of the antifuse array structure is shown. Detailed Implementation

[0020] As the background technology shows, the performance and integration of antifuse array structures still need improvement. This will be analyzed and explained below. Figure 1 A partial top view of an antifuse array structure is shown. Figure 2 A partial cross-sectional view of an antifuse array structure is shown. Figure 3 An equivalent circuit diagram of an antifuse array structure is shown. (Reference) Figures 1-3 In the antifuse array structure, multiple word lines WL0 extend along the second direction Y, multiple programming electrodes AF0 extend along the second direction Y, and multiple bit lines BL0 extend along the first direction X. The gates of the two selection transistors of the antifuse integrated unit 200 are respectively connected to the two word lines WL0. The first doped region SD1, the third doped region SD3, and the second doped region SD2 of the antifuse integrated unit 200 are arranged in the first direction X, wherein the third doped region SD3 is connected to the bit line WL0. As shown in the figure, the orthogonal projections of the first doped region SD1, the third doped region SD3, and the second doped region SD2 on the substrate 100, i.e., the orthogonal projections of the active region AA0 on the substrate 100, have a large overlap with the orthogonal projections of the bit line WL0 on the substrate 100, which will generate a large parasitic capacitance and affect the operating speed of the antifuse array structure. In addition, the antifuse array structure has a lot of wiring, that is, a large number of word lines WL0 and bit lines BL0. One word line WL0 and one bit line BL0 are connected to one antifuse unit, so the integration of the antifuse array structure is low.

[0021] This disclosure provides an antifuse array structure in which multiple word lines extend along a first direction, each word line being connected to the gate of a first selection transistor and / or the gate of a second selection transistor in at least one row of antifuse integrated units; multiple bit lines extend along a second direction, each bit line being electrically connected to a second doped region in the same column of antifuse integrated units; that is, the extension direction of the bit lines is different from the arrangement direction of the programming electrode of the first antifuse device, the gate of the first selection transistor, and the gate of the second selection transistor, and is also different from the arrangement direction of the first doped region, the third doped region, and the second doped region, thereby effectively reducing the area of ​​the bit lines facing these structures, thereby reducing parasitic capacitance and ensuring the operating speed of the semiconductor structure. Furthermore, the antifuse array structure of this disclosure can also reduce the total number of wirings, i.e., reduce the total number of word lines and bit lines, thereby improving the integration density of the antifuse array structure, which will be described in detail later.

[0022] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0023] like Figures 4-10 As shown in the figure, one embodiment of this disclosure provides an antifuse array structure, which will be described in detail below with reference to the accompanying drawings.

[0024] The substrate 1 has multiple antifuse integrated units 2 arranged in an array. It should be noted that... Figure 4 In the following description, an example is given where multiple antifuse integrated units 2 are arranged in an array along the first direction X and the second direction Y, and the angle between the first direction X and the second direction Y is 90°. However, this does not constitute a limitation on this embodiment. In other embodiments, the angle between the first direction X and the second direction Y can also be 20°, 40°, 60°, or 80°, as long as the first direction X intersects the second direction Y.

[0025] Figure 4 An antifuse array structure provided in an embodiment of this disclosure is shown. Figure 5 A top view of an antifuse integrated unit provided in an embodiment of this disclosure is shown. (Reference) Figures 4-5The antifuse integrated unit 2 includes a first antifuse unit 21 and a second antifuse unit 22, which can be arranged sequentially in the first direction X. The first antifuse unit 21 includes a first selection transistor T1 and a first antifuse device C1, which share a first doped region SD1. This allows the first antifuse device C1 to be electrically connected to the bit line BL after the first selection transistor T1 is turned on, enabling the first antifuse device C1 to be programmed or read.

[0026] The first antifuse device C1 can be a capacitor structure. Specifically, the programming electrode G1' of the first antifuse device serves as one plate of the capacitor structure and is connected to the programming wire AF, while the first doped region SD1 serves as the other plate of the capacitor structure. In other embodiments, the first antifuse device C1 can be a transistor structure. The programming electrode G1' of the first antifuse device serves as the gate of the transistor structure, and the first doped region SD1 serves as one of the source and drain electrodes of the transistor structure. Furthermore, the first antifuse device C1 also includes another doped region to serve as the other source and drain electrode of the transistor structure. This doped region can be configured to be in a floating state or electrically connected to the programming wire AF.

[0027] The second antifuse unit 22 includes a second selection transistor T2 and a second antifuse device C2, which share a second doped region SD2. This allows the second antifuse device C2 to be electrically connected to the bit line BL after the second selection transistor T2 is turned on, so that the second antifuse device C2 can be programmed or read.

[0028] The second antifuse device C2 can be a capacitor structure. Specifically, the programming electrode G2' of the second antifuse device serves as one plate of the capacitor structure and is connected to the programming wire AF, while the second doped region SD2 serves as the other plate of the capacitor structure. In other embodiments, the second antifuse device C2 can be a transistor structure. The programming electrode G2' of the second antifuse device serves as the gate of the transistor structure, and the second doped region SD2 serves as one of the source and drain electrodes of the transistor structure. Furthermore, the second antifuse device C2 also includes another doped region to serve as the other source and drain electrode of the transistor structure. This doped region can be configured to be in a floating state or electrically connected to the programming wire AF.

[0029] The first selection transistor T1 and the second selection transistor T2 share the third doped region SD3. Thus, compared to spacing the two antifuse units apart, the antifuse integrated unit 2 helps reduce the number of doped regions, thereby improving the integration density of the antifuse array structure.

[0030] It is worth noting that the third doped region SD3 includes either the source or drain of the first selection transistor T1 and either the source or drain of the second selection transistor T2; the first doped region SD1 includes the other one of the source or drain of the first selection transistor T1; and the second doped region SD2 includes the other one of the source or drain of the second selection transistor T2. In other words, the positions of the source and drain of the first selection transistor T1 can be interchanged, and the positions of the source and drain of the second selection transistor T2 can also be interchanged.

[0031] In some embodiments, the first antifuse device C1, the first selection transistor T1, the second selection transistor T2, and the second antifuse device C2 are arranged sequentially along the first direction X, thereby increasing the arrangement density of the antifuse integrated unit 2 and improving the integration density of the antifuse array structure. Specifically, the programming electrode G1' of the first antifuse device, the gate G1 of the first selection transistor, the gate G2 of the second selection transistor, and the programming electrode G2' of the second antifuse device are arranged along the first direction X, that is, the arrangement direction of the four is also parallel to the arrangement direction of the first doped region SD1, the third doped region SD3, and the second doped region SD2.

[0032] In some embodiments, the first selection transistor T1 and the second selection transistor T2 are arranged in a centrally symmetrical configuration, as are the first antifuse device C1 and the second antifuse device C2. This central symmetry allows for a more regular arrangement of the antifuse integrated units 2, which is beneficial for improving the uniformity of the antifuse array structure and for facilitating its fabrication. Both the first selection transistor T1 and the second selection transistor T2 can be either N-type transistors or both P-type transistors. (Reference) Figure 4 Taking two N-type transistors as an example, the substrate 1 may include a deep NP well 12 and a P well 11 stacked together.

[0033] refer to Figures 6-10 The connection and positional relationships between the antifuse integrated unit 2, the word line WL, the bit line BL, and the programming electrode will be explained in detail below.

[0034] Multiple bit lines BL extend along the second direction Y, that is, multiple bit lines BL are arranged at intervals along the first direction X. Each bit line BL is electrically connected to the third doped region SD3 in the same column of antifuse integrated unit 2. It should be noted that the column direction can be understood as the second direction Y, and the row direction can be understood as the first direction X.

[0035] Multiple programming leads AF extend along the second direction Y, i.e., the programming leads AF are arranged parallel to the bit line BL. Each programming lead AF is electrically connected to the programming electrode G1' of the first antifuse device in the same row of antifuse integration units 2, or electrically connected to the programming electrode G2' of the second antifuse device in the same row of antifuse integration units 2. That is, the programming electrodes G1' and G2' of the first and second antifuse devices in the same antifuse integration unit 2 are electrically connected to two different programming leads AF.

[0036] Multiple word lines WL extend along a first direction X, and each word line WL is connected to the gate G1 of a first selection transistor and / or the gate G2 of a second selection transistor in at least one row of antifuse integrated cells 2. An example will be provided below.

[0037] Example 1, for reference Figures 6-8 , Figures 6-7 Different top views of two antifuse array structures are shown. Figure 8 for Figures 6-7 The equivalent circuit diagram of the antifuse array structure is shown. The gate G1 of the first selection transistor and the gate G2 of the second selection transistor in the same antifuse integrated cell 2 are connected to the same word line WL. For example, the first selection transistor T1 and the second selection transistor T2 of all antifuse integrated cells 2 in the same row are connected to the same word line WL.

[0038] In some embodiments, reference Figure 6 In the second direction Y, adjacent rows of antifuse integrated units 2 share a word line WL. This means multiple word lines WL are located on the same side of the antifuse integrated units 2. For example, each row of antifuse integrated units 2 has a first side 41 and a second side 42 opposite to each other in the second direction Y. Multiple word lines WL are located on the first side 41 of the antifuse integrated units 2 connected to them, or multiple word lines WL are located on the second side 42 of the antifuse integrated units 2 connected to them. This makes the arrangement of word lines WL relatively uniform, thereby reducing the parasitic capacitance between word lines WL. (Continue to refer to...) Figure 6 Multiple word lines (WL) are arranged at equal intervals, thereby improving the uniformity of the semiconductor structure.

[0039] In other embodiments, reference is made to... Figure 7 Multiple word lines WL are located on different sides of the antifuse integrated unit 2. For example, one word line WL is located on the first side 41 of the antifuse integrated unit 2 connected to it, and another word line WL is located on the second side 42 of the antifuse integrated unit 2 connected to it. That is to say, some adjacent rows of antifuse integrated units 2 do not have word lines WL, while some adjacent rows of antifuse integrated units 2 have two word lines WL. It should be noted that, due to Figure 7 Only two rows of antifuse integrated units 2 are shown, so Figure 7The two letter lines WL are not fully shown in the text. Therefore, it can be inferred that... Figure 7 The letter lines WL shown may not be arranged at equal intervals.

[0040] It is worth noting that the antifuse array structure shown in Example 1 helps reduce the number of wires. Specifically, refer to... Figure 8 Taking the four-row, three-column antifuse integrated unit 2 as an example, these antifuse integrated units 2 need to connect a total of four word lines WL and three bit lines BL, for a total of 7. Figure 3 In the antifuse array structure shown, the four-row, three-column antifuse integrated unit 2 needs to connect four bit lines BL and six word lines WL, for a total of 10, which is greater than the total number of wirings in Example 1.

[0041] Example 2, see reference Figures 9-10 , Figure 9 A top view of an antifuse array structure is shown. Figure 10 for Figure 9 The equivalent circuit diagram of the antifuse array structure is shown. The gate G1 of the first selection transistor and the gate G2 of the second selection transistor in the same antifuse integrated unit 2 are respectively connected to two different word lines WL. For two antifuse integrated units 2 arranged adjacent to each other in the second direction Y, the first selection transistor T1 of one antifuse integrated unit 2 and the second selection transistor T2 of the other antifuse integrated unit 2 are staggered and connected to the same word line WL. That is, the first selection transistors T1 of two adjacent antifuse integrated units 2 in the same column are connected to different word lines WL, and the second selection transistors T2 of two adjacent antifuse integrated units 2 in the same column are connected to different word lines WL. The gates of the selection transistors connected to the same word line WL can be cross-arranged.

[0042] In some embodiments, the gates of all first selection transistors T1 cells in the same row along the first direction X are connected to the same word line WL; the gates of all second selection transistors T2 cells in the same row along the first direction X are also connected to the same word line WL. That is, there is a word line WL between two adjacent rows of antifuse integrated cells 2, and the word line WL is connected to the gates G1 of all first selection transistors in one row of antifuse integrated cells 2 and to the gates G2 of all second selection transistors in the other row of antifuse integrated cells 2. Therefore, the connection relationship between the gates of the selection transistors and the word line WL is simpler, which is beneficial for manufacturing processes and also facilitates programming and reading operations.

[0043] In other embodiments, the gates G1 of different first selection transistors in the same row can also be connected to different word lines WL, and the gates G2 of different second selection transistors in the same row can also be connected to different word lines WL, as long as it can be ensured that the first selection transistors T1 of two adjacent antifuse integrated units 2 in the same column are connected to different word lines WL, and that the second selection transistors T2 of two adjacent antifuse integrated units 2 in the same column are connected to different word lines WL.

[0044] In some embodiments, the word lines WL are equidistant from the antifuse integrated units 2 located on opposite sides of them. For example, the spacing between adjacent word lines WL arranged in the second direction Y can be kept consistent, which is beneficial for improving the uniformity of the semiconductor structure and is more conducive to process manufacturing.

[0045] In some embodiments, reference Figure 4 In the direction perpendicular to the upper surface of substrate 1, the word line WL can be disposed on the same layer as the gate G1 of the first selection transistor and the gate G2 of the second selection transistor, and no conductive plug is required between them, which helps to reduce and simplify production costs. That is, the word line WL can directly contact one of the two sides opposite to the gate of the selection transistor in the second direction Y.

[0046] refer to Figure 4 The antifuse array structure also includes: multiple first conductive plugs 31, multiple second conductive plugs 32, and multiple third conductive plugs 33. Each first conductive plug 31 is electrically connected between a programming electrode G1' of a first antifuse device and a programming wire AF; each second conductive plug 32 is electrically connected between a programming electrode G2' of a second antifuse device and a programming wire AF; each third conductive plug 33 is electrically connected between a third doped region SD3 and a bit line BL. That is, the first conductive plugs 31, second conductive plugs 32, and third conductive plugs 33 can respectively lead out the programming electrode G1' of the first antifuse device, the programming electrode G2' of the second antifuse device, and the third doped region SD3 in a direction away from the substrate 1, thereby avoiding the programming wire AF, bit line BL, and word line WL from crossing when they are set on the same layer.

[0047] In some embodiments, the upper surfaces of the first conductive plug 31, the second conductive plug 32, and the third conductive plug 33 are flush. This allows multiple programming lines AF and multiple bit lines BL to be arranged in the same layer. Thus, the programming lines AF and bit lines BL can be formed in the same process steps; for example, they can be formed using the same patterning process and the same chemical vapor deposition process, thereby helping to reduce production costs.

[0048] In some embodiments, the first conductive plug 31, the second conductive plug 32, and the third conductive plug 33 can also be formed using the same patterning process and the same chemical vapor deposition process to reduce production costs.

[0049] Continue to refer to Figure 4 The antifuse array structure also includes an isolation structure 13, such as a shallow trench isolation (STI) structure 13, for isolating adjacent antifuse integrated units 2.

[0050] In summary, the embodiments of this disclosure change the extension directions of bit lines BL and word lines WL, and alter their connection relationships with the antifuse integrated units 2, thereby reducing the total number of bit lines BL and word lines WL. Specifically, the word lines WL extend along a first direction X, and are connected to the gates G1 of the first selection transistor and / or G2 of the second selection transistor in at least one row of antifuse integrated units 2. The bit lines BL extend along a second direction Y, and each bit line BL is electrically connected to the third doped region SD3 in the same column of antifuse integrated units 2. Because the extension direction of the bit lines BL differs from that of the active region AA, and their orthogonal projection areas on the substrate 1 are small, parasitic capacitance can be reduced.

[0051] refer to Figures 6-10 Another embodiment of this disclosure also provides a programming method that applies the antifuse array structure provided in the foregoing embodiments. It should be noted that the parts that are the same as or corresponding to those in the foregoing embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be described in detail below.

[0052] The programming method includes: obtaining the target antifuse cell to be programmed in the antifuse array structure, as well as the word line WL, programming wire AF, and bit line BL corresponding to the target antifuse cell; applying a turn-on voltage to the word line WL corresponding to the target antifuse cell to turn on the selection transistor of the target antifuse cell; applying a programming voltage to the programming wire AF corresponding to the target antifuse cell, wherein the programming voltage is greater than or equal to the breakdown voltage of the antifuse device; and applying zero voltage to the bit line BL corresponding to the target antifuse cell to break down the antifuse device in the target antifuse cell. It should be noted that the two states of the first antifuse device C1—breakdown and non-breakdown—can represent the stored binary data.

[0053] It is worth noting that, Figure 8 and Figure 10 Equivalent circuit diagrams for different antifuse array structures are shown respectively. Figure 8 and Figure 10The values ​​following "BL, WL, AF" are only used to distinguish different bit lines BL, word lines WL, and programming lines AF in the antifuse array structure. They do not constitute a limitation on the number of bit lines BL, word lines WL, and programming lines AF. In specific applications, they can be determined according to the required storage array capacity. For example, the first word line WL1 represents the word line WL of the first row, the first programming electrode AF1 represents the programming electrode AF of the first column, and the first bit line BL1 represents the bit line BL of the first column.

[0054] The following will combine Figure 8 and Figure 10 The programming method will be illustrated with examples.

[0055] refer to Figure 8 Assuming the target antifuse unit is the first antifuse unit 21 in the antifuse integrated unit 2 in the second row and first column, then an enable voltage is applied to the second word line WL2, zero voltage is applied to the first word line BL1, and a programming voltage is applied to the first programming wire AF1.

[0056] refer to Figure 10 Assuming the target antifuse unit is the first antifuse unit 21 in the antifuse integrated unit 2 in the second row and first column, then an enable voltage is applied to the first word line WL1, zero voltage is applied to the first bit line BL1, and a programming voltage is applied to the first programming wire AF1.

[0057] Non-target antifuse units include two types: the first type is an antifuse unit connected to the same word line WL and the same bit line BL as the target antifuse unit; the second type is an antifuse unit connected to a different word line WL and / or a different bit line BL than the target antifuse unit. For the first type of non-target antifuse unit, since no programming voltage is applied to its corresponding programming wire AF, its antifuse device will not break down. For the second type of non-target antifuse unit, if it is connected to a different word line WL than the target antifuse unit, zero voltage can be applied to its corresponding word line WL to turn off the select transistor; if it is connected to a different bit line BL than the target antifuse unit, the voltage difference between its corresponding bit line BL and its corresponding programming wire AF can be less than the breakdown voltage of the antifuse device. For example, the voltage of its corresponding bit line BL can be half the programming voltage, and the voltage of its corresponding programming wire AF can be zero.

[0058] In summary, the embodiments of this disclosure adjust the connection relationship between word lines WL and bit lines BL and the antifuse integrated unit 2, thereby reducing the total number of bit lines BL and word lines WL. Therefore, one bit line BL and one word line WL together connect to more antifuse units, i.e., two antifuse units are connected instead of one. These two antifuse units are connected to different programming wires AF. A programming voltage is applied to the programming wire AF corresponding to the target antifuse unit, while no programming voltage is applied to the programming wire AF corresponding to the other non-target antifuse unit. Therefore, the antifuse array structure can perform programming operations normally.

[0059] refer to Figures 6-10 Another embodiment of this disclosure also provides a reading method that applies the antifuse array structure provided in the foregoing embodiments.

[0060] The reading method includes: acquiring the target antifuse cell to be read from the antifuse array structure, as well as the word line WL, programming line AF, and bit line BL corresponding to the target antifuse cell; applying a turn-on voltage to the word line WL corresponding to the target antifuse cell to turn on the selection transistor in the target antifuse cell; applying a read voltage to the programming line AF corresponding to the target antifuse cell, wherein the read voltage is less than the breakdown voltage of the antifuse device; applying zero voltage to the bit line BL corresponding to the target antifuse cell, and setting the programming line AF corresponding to another antifuse cell electrically connected to the same bit line BL and the same word line WL as the target antifuse cell to a floating state; reading the current flowing through the target antifuse device; and determining the stored data of the target antifuse device based on the magnitude of the current.

[0061] It should be noted that when the target antifuse device is broken down, the current flowing through it is relatively large; when it is not broken down, the current flowing through it is relatively small. Therefore, the current magnitude can represent the binary data stored in the target antifuse device. Furthermore, setting the programming wire AF of another antifuse unit electrically connected to the same bit line BL and word line WL as the target antifuse unit to a floating state is to avoid reading the data stored in that antifuse unit, thus ensuring the accuracy of the read operation.

[0062] The following examples illustrate the reading method using different antifuse array structures.

[0063] Example 1, for reference Figures 6-8The gates G1 and G2 of the first and second selection transistors in the same antifuse integrated unit 2 are connected to the same word line WL. Setting the programming wire AF of another antifuse unit electrically connected to the same bit line BL and word line WL as the target antifuse unit to a floating state includes: setting the programming wire AF of another antifuse unit in the same antifuse integrated unit 2 as the target antifuse unit to a floating state. This avoids reading data stored in another non-target antifuse device in the same antifuse integrated unit 2, thereby ensuring the accuracy of data reading.

[0064] For example, refer to Figure 8 Taking the first antifuse unit 21, which is the first row and first column of the integrated antifuse unit, as an example, during reading, the first word line WL1 is given an enable voltage, the first bit line BL1 is given zero voltage, the first programming line AF1 is given a read voltage, and the second programming line AF2 is set to a floating state (high impedance state).

[0065] Example 2, see reference Figures 9-10 In the same antifuse integrated unit 2, the gates G1 and G2 of the first selection transistor are respectively connected to two different word lines WL. For two antifuse integrated units 2 arranged adjacent to each other in the second direction Y, the first selection transistor T1 of one antifuse integrated unit 2 is staggered from the second selection transistor T2 of the other antifuse integrated unit 2 and connected to the same word line WL. That is, the target antifuse unit and the non-target antifuse unit connected to the same word line WL and the same bit line BL belong to two adjacent antifuse integrated units 2 in the same column, and the target antifuse unit and the non-target antifuse unit are connected to different programming wires AF, that is, they are staggered in the second direction Y.

[0066] Setting the programming wire AF of another antifuse unit electrically connected to the target antifuse unit on the same bit line BL and word line WL to a floating state includes: setting the programming wire AF of the antifuse unit located in an adjacent row to the target antifuse unit but offset from it to a floating state. This avoids reading data stored in non-target antifuse units, thus ensuring the accuracy of data reading.

[0067] For example, refer to Figure 10 Assume the target antifuse unit is the first antifuse unit 21 of the integrated antifuse unit in the first row and first column, and the target antifuse unit and the second antifuse unit 22 of the integrated antifuse unit in the second row and first column are connected to the same word line WL and the same bit line BL. During reading, the second word line WL2 is given an enable voltage, the first bit line BL1 is given zero voltage, the first programming wire AF1 is given a read voltage, and the second programming wire AF2 is set to a floating state (high impedance state).

[0068] In summary, the embodiments of this disclosure adjust the connection relationship between the word line WL and the bit line BL and the antifuse integrated unit 2, thereby reducing the total number of bit lines BL and word lines WL. Therefore, one bit line BL and one word line WL jointly connect to two antifuse units. During reading, the voltage of the programming wire AF corresponding to the non-target antifuse unit connected to the same bit line BL and the same word line WL as the target antifuse unit can be set to a floating state, thereby avoiding read errors.

[0069] In another embodiment of this disclosure, a memory is provided, which includes the antifuse array structure provided in the foregoing embodiments, so as to reduce the parasitic capacitance in the antifuse array structure and improve the operating speed of the memory.

[0070] Specifically, memory can be a storage cell or device based on a semiconductor device or component. For example, a memory device can be volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM).

[0071] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0072] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and description of the present disclosure should fall within the scope of the patent coverage of the present disclosure.

Claims

1. An antifuse array structure, characterized in that, include: A substrate, and multiple antifuse integrated units arranged in an array on the substrate; The antifuse integrated unit includes: a first antifuse unit and a second antifuse unit; the first antifuse unit includes a first selection transistor and a first antifuse device, which share a first doped region; the second antifuse unit includes a second selection transistor and a second antifuse device, which share a second doped region; the first selection transistor and the second selection transistor share a third doped region; the programming electrode of the first antifuse device, the gate of the first selection transistor, the gate of the second selection transistor, and the programming electrode of the second antifuse device are arranged along a first direction; Multiple word lines extend along a first direction, and each word line is connected to the gate of the first selection transistor and / or the gate of the second selection transistor in at least one row of the antifuse integrated cell. Multiple bit lines extend along a second direction, and each bit line is electrically connected to a third doped region in the same column of the antifuse integrated units; the extension direction of the multiple bit lines is perpendicular to the arrangement direction of the programming electrode of the first antifuse device, the gate of the first selection transistor, the gate of the second selection transistor, and the programming electrode of the second antifuse device. Multiple programming wires extend along the second direction, and each programming wire is electrically connected to the programming electrode of the first antifuse device in the same column of the antifuse integrated unit, or electrically connected to the programming electrode of the second antifuse device in the same column of the antifuse integrated unit. The first direction is perpendicular to the second direction.

2. The antifuse array structure according to claim 1, characterized in that, The gates of the first selection transistor and the second selection transistor of the same antifuse integrated unit are connected to the same word line.

3. The antifuse array structure according to claim 2, characterized in that, There is a word line between two adjacent rows of the antifuse integrated units arranged in the second direction.

4. The antifuse array structure according to claim 3, characterized in that, The multiple lines are arranged at equal intervals.

5. The antifuse array structure according to claim 1, characterized in that, The gates of the first selection transistor and the second selection transistor of the same antifuse integrated unit are connected to different word lines; For two antifuse integrated units arranged adjacent to each other in the second direction, the first selection transistor of one antifuse integrated unit and the second selection transistor of the other antifuse integrated unit are connected to the same word line in a staggered manner.

6. The antifuse array structure according to claim 5, characterized in that, In the first direction, the gates of all the first selected transistors in the same row are connected to the same word line; The gates of all the second selection transistors in the same row in the first direction are connected to the same word line.

7. The antifuse array structure according to claim 5 or 6, characterized in that, The word line is equidistant from the antifuse integration units located on its opposite sides.

8. The antifuse array structure according to claim 1, characterized in that, Also includes: A plurality of first conductive plugs, each first conductive plug being electrically connected between a programming electrode of a first antifuse device and a programming wire; A plurality of second conductive plugs, each second conductive plug being electrically connected between a programming electrode of a second antifuse device and a programming wire; A plurality of third conductive plugs, each of the third conductive plugs being electrically connected between a third doped region and a bit line.

9. The antifuse array structure according to claim 1, characterized in that, The first selection transistor and the second selection transistor are arranged in a centrally symmetrical manner, and the first antifuse device and the second antifuse device are arranged in a centrally symmetrical manner.

10. The antifuse array structure according to claim 1, characterized in that, The third doped region includes one of the source or drain of the first selected transistor and one of the source or drain of the second selected transistor. The first doped region includes the other of the source or drain of the first selected transistor, and the second doped region includes the other of the source or drain of the second selected transistor.

11. A programming method applied to the antifuse array structure as described in any one of claims 1 to 10, characterized in that, include: Obtain the target antifuse cell to be programmed in the antifuse array structure, as well as the word line, programming wire and bit line corresponding to the target antifuse cell; An enable voltage is applied to the word line corresponding to the target antifuse unit to turn on the select transistor of the target antifuse unit, a programming voltage is applied to the programming wire corresponding to the target antifuse unit, and a zero voltage is applied to the bit line corresponding to the target antifuse unit to break down the antifuse device in the target antifuse unit.

12. A reading method, applied to the antifuse array structure as described in any one of claims 1 to 10, characterized in that, include: Obtain the target antifuse cell to be read in the antifuse array structure, as well as the word line, programming wire and bit line corresponding to the target antifuse cell; An enable voltage is applied to the word line corresponding to the target antifuse unit to turn on the select transistor in the target antifuse unit; a read voltage is applied to the programming line corresponding to the target antifuse unit; zero voltage is applied to the bit line corresponding to the target antifuse unit; and the programming line corresponding to another antifuse unit that is electrically connected to the same bit line and the same word line as the target antifuse unit is set to a floating state. Read the current flowing through the target antifuse unit; Based on the magnitude of the current, the stored data of the target antifuse unit is determined.

13. The reading method according to claim 12, characterized in that, The gates of the first selection transistor and the second selection transistor of the same antifuse integrated unit are connected to the same word line; Setting the programming wire corresponding to another antifuse unit that is electrically connected to the same bit line and the same word line as the target antifuse unit to a floating state includes: setting the programming wire corresponding to another antifuse unit that is in the same antifuse integration unit as the target antifuse unit to a floating state.

14. The reading method according to claim 12, characterized in that, The gates of the first selection transistor and the second selection transistor of the same antifuse integrated unit are respectively connected to two different word lines; For two antifuse integrated units arranged adjacent to each other in the second direction, the first selection transistor of one antifuse integrated unit and the second selection transistor of the other antifuse integrated unit are staggered and connected to the same word line; Setting the programming wire corresponding to another antifuse unit that is electrically connected to the same bit line and the same word line as the target antifuse unit to a floating state includes: setting the programming wire corresponding to the antifuse unit located in the adjacent row of the target antifuse unit and staggered from the target antifuse unit to a floating state.

15. A memory, characterized in that, The antifuse array structure includes any one of claims 1 to 10.

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