Chip and testing method for chip

Abstract

The embodiments of the present invention disclose a chip and a testing method for the chip, which relate to the field of integrated circuit technology, facilitate the detection and location of chip fracture damage, and are conducive to process improvement. The chip includes: at least one metal layer and at least one dielectric layer stacked alternately; each metal layer includes a main body pattern provided in the main body area and a first metal wire and a second metal wire provided in the edge area, the first metal wire and the second metal wire being parallel to each other and spaced a first distance apart; there is no electrical connection between the main body pattern and the first metal wire and the second metal wire; the first metal wires on each metal layer are connected end to end in series through a first via in each dielectric layer to form a first series wire, and the second metal wires on each metal layer are connected end to end in series through a second via in each dielectric layer to form a second series wire, and the first series wire and the second series wire correspond to each other.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a chip and a testing method for the chip. Background Art

[0002] During the semiconductor manufacturing process, chips are exposed to unfavorable stresses that can cause cracks in the chips, potentially impacting their proper function. After the wafer process, the chips enter the dicing process. Due to the stress within the wafer, the dicing process can also cause severe cracks, which can lead to chip failure.

[0003] Since chip manufacturing and testing are relatively expensive, in order to prevent chips with cracks from being circulated further, corresponding metal rings are usually set on the periphery of the chip when each metal layer of the chip is manufactured. The metal rings on all layers are connected in series to form a complete loop. The connectivity of the loop is tested to determine whether the chip has crack damage.

[0004] However, while this method can detect whether a chip has crack damage, it cannot locate the damage. This makes it difficult to make targeted process improvements when DCM (die crack monitor) anomalies occur, meaning when a chip has crack damage. Summary of the Invention

[0005] In view of this, an embodiment of the present invention provides a chip and a testing method for the chip, which facilitates the detection and positioning of chip fracture damage, thereby facilitating chip process improvement.

[0006] In a first aspect, an embodiment of the present invention provides a chip, comprising: at least one metal layer and at least one dielectric layer stacked alternately; each metal layer comprises a main body pattern arranged in a main body area and a first metal wire and a second metal wire arranged in an edge area, the first metal wire and the second metal wire being parallel to each other and spaced a first distance apart; the edge area surrounds the main body area; there is no electrical connection between the main body pattern and the first metal wire and the second metal wire; the first metal wires on each metal layer are connected end to end in series with each other through first vias in each dielectric layer to form a first series wire, and the second metal wires on each metal layer are connected end to end in series with each other through second vias in each dielectric layer to form a second series wire, the first series wire and the second series wire corresponding to each other; a first target end of the first series wire and a first target end of the second series wire are respectively led out of the chip through metal pins, wherein the first target end of the first series wire and the first target end of the second series wire are located on the same metal layer of the chip.

[0007] In one embodiment, the chip includes at least one series line group, wherein each series line group includes one first series line and one corresponding second series line; there is no electrical connection between the series line groups; in each series line group, one first metal line and one second metal line located in the same metal layer form a metal line group.

[0008] In one embodiment, in the same metal layer, each of the metal wire groups is distributed around the main area and pieced together into a ring with a gap, and the gap is the gap between two adjacent metal wire groups; wherein, the first metal wires in each of the metal wire groups are pieced together into a first ring with a first gap, and the first gap is the gap between the adjacent endpoints of two adjacent first metal wires; the second metal wires in each of the metal wire groups are pieced together into a second ring with a second gap, and the second gap is the gap between the adjacent endpoints of two adjacent second metal wires; and the second ring is located inside the first ring.

[0009] In one embodiment, the first metal wire and the second metal wire in the same metal wire group are equal or different in length; in different metal wire groups, the first metal wires are equal or different in length, and the second metal wires are equal or different in length.

[0010] In one embodiment, in different metal wire groups, the first distances between the first metal wire and the second metal wire are equal or different, and the first distance is a preset multiple of the line width of the first metal wire, and the preset multiple is between 0.5 times and 5 times.

[0011] In one embodiment, the metal wire groups belonging to the same series wire group are aligned or staggered with each other in a direction perpendicular to the metal layer.

[0012] In one embodiment, the number of the series line groups is 1 to 20.

[0013] In one embodiment, the first target end of the first series line is located in a first target layer, forming the first end of the first metal line of the first series line; the first target end of the second series line is located in the first target layer, forming the second end of the second metal line of the second series line; wherein the first end is the same as or different from the second end; the first target layer is the top layer or the bottom layer in the at least one metal layer.

[0014] In one embodiment, the first metal wire and the second metal wire are line segments, or are broken lines formed by splicing multiple line segments.

[0015] In one embodiment, the second target end of the first series line and the second target end of the second series line are respectively led out of the chip through metal pins, wherein the second target end of the first series line and the second target end of the second series line are located on the same metal layer of the chip.

[0016] In a second aspect, an embodiment of the present invention further provides a testing method for a chip, wherein the chip is any chip provided by the embodiments of the present invention, and the testing method includes: obtaining the measurement value of the preset electrical parameter of the chip through the metal pin corresponding to the first target end of the first series line and the metal pin corresponding to the first target end of the second series line; the preset electrical parameter includes the capacitance between the first series line and the second series line; determining whether the chip has fracture damage based on the measured value and theoretical value of the preset electrical parameter; and locating the fracture damage based on the measured value and theoretical value of the preset electrical parameter when the chip has fracture damage.

[0017] In one embodiment, determining whether the chip has fracture damage based on the measured value and theoretical value of the preset electrical parameter includes: calculating the theoretical value of the capacitance between the first series line and the second series line based on the design parameters of the chip; if the difference between the theoretical value of the capacitance and the measured value of the capacitance is within a preset range, determining that the chip has no fracture damage; if the difference between the theoretical value of the capacitance and the measured value of the capacitance is outside the preset range, determining that the chip has fracture damage.

[0018] In one embodiment, in the chip, the second target end of the first series wire and the second target end of the second series wire are respectively led out of the chip through metal pins, wherein the second target end of the first series wire and the second target end of the second series wire are located in the same metal layer of the chip; the preset electrical parameters also include at least one of the following: the resistance of the first series wire, the current flowing through the first series wire, the resistance of the second series wire, and the current flowing through the second series wire; obtaining the measurement value of the preset electrical parameter of the chip through the metal pin corresponding to the first target end of the first series wire and the metal pin corresponding to the first target end of the second series wire includes at least one of the following: obtaining the resistance of the first series wire or the current flowing through the first series wire through the metal pins corresponding to the first target end and the second target end of the first series wire; The resistance of the second series line or the current flowing through the second series line is obtained through the metal pins corresponding to the first target end and the second target end respectively; the determination of whether the chip has fracture damage according to the measured value and theoretical value of the preset electrical parameter includes at least one of the following: if the resistance of the first series line and / or the resistance of the second series line is greater than a preset resistance threshold, it is determined that the chip has fracture damage; if the resistance of the first series line and / or the resistance of the second series line is less than the preset resistance threshold, it is determined that the chip does not have fracture damage; if the current flowing through the first series line and / or the current flowing through the second series line is less than a preset current threshold, it is determined that the chip has fracture damage; if the current flowing through the first series line and / or the current flowing through the second series line is greater than the preset current threshold, it is determined that the chip does not have fracture damage.

[0019] In one embodiment, when the chip has fracture damage, locating the fracture damage according to the measured value and theoretical value of the preset electrical parameter includes: when the chip has fracture damage, determining the calculation expression of the capacitance between the first metal wire and the second metal wire in each of the metal layers according to the design parameters of the chip, and obtaining a segmented capacitance expression; determining, according to the metal layer where the first target end is located and each of the segmented capacitance expressions, a first correspondence between the location of the fracture damage and the theoretical value of the fracture capacitance when the fracture damage occurs in any of the metal layers, or a second correspondence between the location of the fracture damage and the theoretical range of the fracture capacitance, wherein the fracture capacitance is the capacitance between the first series wire and the second series wire when the fracture damage occurs; locating the fracture damage according to the measured value of the capacitance and the first correspondence or the second correspondence.

[0020] In one embodiment, the locating of the fracture damage based on the measured value of the capacitance and the first correspondence or the second correspondence includes at least one of the following: determining the metal layer where the fracture damage is located and the position of the fracture damage in the metal layer based on the measured value of the capacitance and the first correspondence; determining the metal layer where the fracture damage is located based on the measured value of the capacitance and the second correspondence.

[0021] In one embodiment, the chip includes at least one series wire group, wherein each of the series wire groups includes a first series wire and a second series wire; there is no electrical connection between the series wire groups; in each of the series wire groups, a first metal wire and a second metal wire located in the same metal layer form a metal wire group; in the case where there is fracture damage in the chip, locating the fracture damage according to the measured value and theoretical value of the preset electrical parameter includes: determining the distribution range of the fracture damage in the chip according to the position of the series wire group corresponding to the preset electrical parameter in the chip.

[0022] Embodiments of the present invention provide a chip and a chip testing method, wherein the chip includes at least one alternately stacked metal layer and at least one dielectric layer; each metal layer includes a main pattern disposed in a main region and a first metal line and a second metal line disposed in an edge region, the edge region surrounding the main region. There is no electrical connection between the main pattern and the first metal line and the second metal line. Thus, fracture damage in the chip can be detected and located using the first metal line and the second metal line located in the edge region without affecting the original structure and function of the chip. Specifically, because the first metal line and the second metal line are parallel to each other and separated by a first distance, a capacitor is formed between the first metal line and the second metal line in each metal layer. Furthermore, because the first metal lines on each metal layer are connected end-to-end in series through first vias in each dielectric layer to form a first series line, and the second metal lines on each metal layer are connected end-to-end in series through second vias in each dielectric layer to form a second series line, the first series line and the second series line correspond to each other. Therefore, this is equivalent to connecting the capacitors formed by the first metal line and the second metal line in each metal layer in parallel to form a parallel capacitor. In this way, after the first target end of the first series line and the first target end of the second series line are respectively led out of the chip through the metal pins, it is convenient to measure the size of the parallel capacitance through these two metal pins. At the same time, since the first target end and the first target end are located in the same metal layer of the chip, the measured value of the parallel capacitance is not only related to the electrical characteristics of the parallel capacitance itself, but also related to the length of the series line connected to the corresponding metal pin in the first series line and the length of the series line connected to the corresponding metal pin in the second series line. Therefore, based on the measured value of the parallel capacitance and the theoretical value of the parallel capacitance, the length of the series line connected to the corresponding metal pin in the first series line and the length of the series line connected to the corresponding metal pin in the second series line can be determined. Then, based on these two series line lengths, it is determined whether the first series line or the second series line is broken and the break is located if it occurs, thereby realizing the detection and location of chip break damage, which is conducive to further improvement of the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A schematic structural diagram of a chip provided in an embodiment of the present invention;

[0025] Figure 2A schematic diagram of a first metal wire and a second metal wire in an embodiment of the present invention;

[0026] Figure 3 is another schematic diagram of the first metal wire and the second metal wire in an embodiment of the present invention;

[0027] Figure 4 A schematic diagram of the structure of a first series line and a second series line in an embodiment of the present invention;

[0028] Figure 5 is another structural schematic diagram of the first series line and the second series line in an embodiment of the present invention;

[0029] Figure 6 Another schematic structural diagram of a chip provided in an embodiment of the present invention;

[0030] Figure 7 A schematic diagram of another structure of a chip provided by an embodiment of the present invention;

[0031] Figure 8 A schematic diagram of another structure of a chip provided in an embodiment of the present invention;

[0032] Figure 9 A schematic diagram of the positional relationship between metal wire groups in different metal layers in an embodiment of the present invention;

[0033] Figure 10 is another schematic diagram of the positional relationship between metal wire groups in different metal layers in an embodiment of the present invention;

[0034] Figure 11 A flow chart of a chip testing method provided by an embodiment of the present invention;

[0035] Figure 12 A schematic structural diagram of a chip breakage in a chip testing method provided by an embodiment of the present invention;

[0036] Figure 13 Another structural schematic diagram of a chip breakage in a chip testing method provided by an embodiment of the present invention;

[0037] Figure 14 A schematic diagram of another structure of chip breakage in a chip testing method provided by an embodiment of the present invention;

[0038] Figure 15 A schematic diagram of another structure of chip breakage in a chip testing method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0040] It should be understood that the embodiments described are only a portion of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0041] In a first aspect, an embodiment of the present invention provides a chip that facilitates detection and location of chip fracture damage, thereby facilitating chip process improvement.

[0042] like Figure 1 As shown, an embodiment of the present invention provides a chip 1 comprising:

[0043] At least one metal layer 11 and at least one dielectric layer 12 are alternately stacked; each metal layer 11 includes a main pattern 110 disposed in the main region 2 and a first metal line 111 and a second metal line 112 disposed in the edge region 3, wherein the first metal line 111 and the second metal line 112 are parallel to each other and separated by a first distance; the edge region 3 surrounds the main region 2; and there is no electrical connection between the main pattern 110 and the first metal line 111 and the second metal line 112.

[0044] The first metal wires 111 on each metal layer 11 are connected end-to-end in series through the first vias 41 in each dielectric layer 12 (the first vias 41 are shown with dotted lines because they are located within the dielectric layer 12) to form first series wires 51. The second metal wires 112 on each metal layer 11 are connected end-to-end in series through the second vias 42 in each dielectric layer 12 (the second vias 42 are shown with dotted lines because they are located within the dielectric layer 12) to form second series wires 52. The first series wires 51 and the second series wires 52 correspond to each other. (To facilitate the presentation of the specific structure of each metal layer 11 and the relationship between the metal layers, the metal layers 11 are shown spaced apart from each other. The thin line segments connecting the first metal wires 111 in different metal layers 11 merely indicate that the first metal wires 111 are electrically connected to each other and do not represent actual metal wires. The thin line segments connecting the second metal wires 112 in different metal layers 11 merely indicate that the first metal wires 112 are electrically connected to each other and do not represent actual metal wires.)

[0045] The first target end 511 of the first series line 51 and the first target end 521 of the second series line 52 are respectively led out of the chip through metal pins (not shown), wherein the first target end 511 of the first series line 51 and the first target end 521 of the second series line 52 are located on the same metal layer 11 of the chip 1.

[0046] The chip 1 provided by an embodiment of the present invention includes at least one metal layer 11 and at least one dielectric layer 12 stacked alternately. Each metal layer 11 includes a main pattern 110 disposed in the main region 2 and a first metal wire 111 and a second metal wire 112 disposed in the edge region 3. The edge region 3 surrounds the main region 2. There is no electrical connection between the main pattern 110 and the first metal wire 111 and the second metal wire 112. In this way, without affecting the original structure and function of the chip 1, the first metal wire 111 and the second metal wire 112 located in the edge region 3 can be used to detect and locate chip fracture damage. Specifically, because the first metal wire 111 and the second metal wire 112 are parallel to each other and separated by a first distance, a capacitor is formed between the first metal wire 111 and the second metal wire 112 in each metal layer 11. Furthermore, since the first metal wires 111 on each metal layer 11 are connected end-to-end in series through the first vias 41 in each dielectric layer 12 to form a first series wire 51, and the second metal wires 112 on each metal layer 11 are connected end-to-end in series through the second vias 42 in each dielectric layer 12 to form a second series wire 52, the first series wires 51 and the second series wires 52 correspond to each other. Therefore, this is equivalent to connecting the capacitors formed by the first metal wires 111 and the second metal wires 112 in each metal layer 11 in parallel to obtain a parallel capacitance. Thus, after the first target end 511 of the first series wire 51 and the first target end 521 of the second series wire 52 are respectively led out of the chip through metal pins, the magnitude of the parallel capacitance can be easily measured through these two metal pins. At the same time, since the first target end 511 and the first target end 521 are located in the same metal layer 11 of the chip 1, the measured value of the parallel capacitance is not only related to the electrical characteristics of the parallel capacitance itself, but also related to the length of the series line connected to the corresponding metal pin in the first series line 51 and the length of the series line connected to the corresponding metal pin in the second series line 52. Therefore, based on the measured value of the parallel capacitance and the theoretical value of the parallel capacitance, the length of the series line connected to the corresponding metal pin in the first series line 51 and the length of the series line connected to the corresponding metal pin in the second series line 52 can be determined, and then the two series line lengths can be used to determine whether the first series line 51 or the second series line 52 is broken and the fracture can be located if it occurs, thereby realizing fracture damage detection and positioning of the chip 1, which is conducive to further improvement of the process.

[0047] In an embodiment of the present invention, the chip 1 may include a main body region 2 and an edge region 3, wherein the main body region 2 may be located at the center of the chip 1, occupying most of the area of the chip 1, and used to manufacture the main body of the chip or realize the main functions of the chip, and the edge region 3 may be located at the edge of the chip 1, occupying a smaller area of the chip 1, and used to manufacture the first metal wire 111 and the second metal wire 112. Since the edge region 3 surrounds the periphery of the main body region 2, the first metal wire 111 and the second metal wire 112 are also distributed around the periphery of the main body region 2. Optionally, the first metal wire 111 and the second metal wire 112 may be located on one side of the main body region 2 or may be arranged around the main body region, and this is not limited in the embodiment of the present invention.

[0048] In a specific implementation, the first metal wire 111 and the second metal wire 112 can be arranged parallel to each other, and the specific shapes of the first metal wire 111 and the second metal wire 112 are not limited. Figure 2 As shown, in one example, the first metal line 111 and the second metal line 112 are line segments. In another example, as shown in FIG. Figure 3 As shown, the first metal line 111 and the second metal line 112 are broken lines formed by splicing multiple line segments.

[0049] In the embodiment of the present invention, the first metal wires 111 in each metal layer 11 can be connected end-to-end in series via the first via 41 to form a first series wire 51. The first series wire 51 can have two endpoints, namely, a first target end and a second target end. Similarly, the second metal wires 112 in each metal layer 11 can be connected end-to-end in series via the second via 42 to form a second series wire 52. The second series wire can also have two endpoints, namely, a first target end and a second target end.

[0050] like Figure 4 and Figure 5 As shown, in one embodiment, the first target end 511 of the first series line 51 can be located in the first target layer and form the first end 1111 of the first metal line 111 of the first series line 51; the first target end 521 of the second series line 52 can be located in the first target layer and form the second end 1122 of the second metal line 112 of the second series line 52; wherein the first end 1111 and the second end 1122 can be the same (see Figure 4 ), or they can be different (see Figure 5 ). Figure 4 and Figure 5 The dielectric layer and vias are not shown. That is, in the embodiment of the present invention, the first series line 51 and the second series line 52 may extend in the same or different directions in each metal layer 11. Alternatively, in one example, the first target layer may be the top or bottom layer of at least one metal layer 11.

[0051] It should be noted that, in the embodiments of the present invention, the first end 1111 and the second end 1122 being the same may mean that the first end 1111 and the second end 1122 indicate the same orientation, for example, both are the left end, or both are the right end, or both are the upper end. The first end 1111 and the second end 1122 being different may mean that the first end 1111 and the second end 1122 indicate different orientations, for example, the first end 1111 is the left end and the second end 1122 is the right end, or the first end 1111 is the upper end and the second end 1122 is the lower end, etc.

[0052] In the aforementioned embodiment, the first target end 511 of the first series line 51 and the first target end 521 of the second series line 52 are respectively led out of the chip 1 through metal pins, but the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, the other end points of the first series line 51 and the second series line 52 can also be led out of the chip 1 through metal pins. For example, Figure 6 As shown, in one embodiment, the second target end 512 of the first series wire 51 and the second target end 522 of the second series wire 52 may also be respectively led out of the chip 1 through metal pins, wherein the second target end 512 of the first series wire 51 and the second target end 522 of the second series wire 52 are located on the same metal layer 11 of the chip 1. Optionally, in an embodiment of the present invention, the metal layer 11 where the second target ends 512 and 522 are located may be different from the metal layer 11 where the first target ends 511 and 521 are located. For example, in one example, the metal layer 11 where the first target ends 511 and 521 are located may be the top layer of at least one metal layer 11, and the metal layer 11 where the second target ends 512 and 522 are located may be the bottom layer of at least one metal layer 11.

[0053] In the aforementioned embodiment, each metal layer 11 of the chip 1 may include a first metal wire 111 and a second metal wire 112 arranged in the edge region 3. The first metal wires 111 on each metal layer 11 are connected end to end in series to form a first series wire 51, and the second metal wires 112 on each metal layer 11 are connected end to end in series to form a second series wire 52. However, the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, the chip 1 may further include more first series wires 51 and second series wires 52. For example, Figure 7As shown, in one embodiment of the present invention, chip 1 may include one or more series line groups 5, wherein each series line group 5 may include a first series line 51 and a corresponding second series line 52; there is no electrical connection between the series line groups 5. In other words, in this embodiment, a first series line 51 and a corresponding second series line 52 may be combined into a series line group 5, and chip 1 may include one or more series line groups 5 as a unit. For example, in one embodiment of the present invention, the number of series line groups 5 may range from 1 to 20, such as 4, 6, 8, 12, etc.

[0054] Furthermore, if Figure 8 As shown, in one embodiment, in each series line group 5, the first metal wire 111 and the second metal wire 112 located in the same metal layer 11 can form a metal wire group 113. Depending on the number of series line groups 5, each metal layer 11 can include the same number of metal wire groups 113. Specifically, in each metal layer 11, the metal wire groups 113 can be arranged in different positions as needed. For example, in one embodiment of the present invention, in the same metal layer 11, the metal wire groups 113 can be distributed around the main region 2 and pieced together to form a ring with a gap, wherein the gap is the gap between two adjacent metal wire groups 113; wherein the first metal wires 111 in each metal wire group 113 are pieced together to form a first ring with a first gap g1, where the first gap g1 is the gap between the adjacent endpoints of two adjacent first metal wires 111; and the second metal wires 112 in each metal wire group 113 are pieced together to form a second ring with a second gap g2, where the second gap g2 is the gap between the adjacent endpoints of two adjacent second metal wires 112, and the second ring is located within the first ring. In this way, each metal wire group 112 can surround the main area 2 from multiple directions. Correspondingly, each series wire group 5 can also surround the main area 2 of the chip 1 from multiple directions. When the electrical signal of the first series wire 51 or the second series wire 52 in any one or more series wire groups 5 fails to transmit normally, it can be determined that the first series wire 51 and / or the second series wire 52 is broken, and thus it can be determined that the chip at the corresponding location has suffered a fracture. Therefore, this metal wire distribution facilitates more precise positioning of fracture damage.

[0055] For example, Figure 9 As shown in FIG. 1 , in one example, the metal wire groups 113 belonging to the same series wire group 5 can be aligned with each other in a direction perpendicular to the metal layer 11. Figure 10 As shown, in another example, the metal wire groups 113 belonging to the same series wire group 5 may also be staggered with each other in the direction perpendicular to the metal layer 11 .

[0056] In a specific implementation, the lengths of the first metal wires 111 and the second metal wires 112 in the same metal wire group 113 can be equal or different; in different metal wire groups 113, the lengths of the first metal wires 111 can be equal or different, and the lengths of the second metal wires 112 can also be equal or different.

[0057] Optionally, in different metal wire groups 113, the first distance between the first metal wire 111 and the second metal wire 112 may be equal or different. In one example, the first distance may be a preset multiple of the line width of the first metal wire 111, and the preset multiple may be, for example, between 0.5 times and 5 times.

[0058] Second, as Figure 11 As shown, corresponding to the chip provided in the above embodiments, an embodiment of the present invention further provides a testing method for a chip, wherein the chip is any chip provided in the above embodiments, and the testing method may include:

[0059] S201: Obtain a measurement value of a preset electrical parameter of the chip through a metal pin corresponding to a first target end of the first series wire and a metal pin corresponding to a first target end of the second series wire; the preset electrical parameter includes a capacitance between the first series wire and the second series wire;

[0060] S202: Determine whether the chip has fracture damage based on the measured value and theoretical value of the preset electrical parameter;

[0061] S203 : When the chip has fracture damage, locate the fracture damage according to the measured value and theoretical value of the preset electrical parameter.

[0062] The chip testing method provided by an embodiment of the present invention can obtain the measured values of the preset electrical parameters of the chip through the metal pin corresponding to the first target end of the first series line in the chip and the metal pin corresponding to the first target end of the second series line. The preset electrical parameters include the capacitance between the first series line and the second series line; based on the measured values and theoretical values of the preset electrical parameters, it is determined whether the chip has fracture damage. If the chip has fracture damage, the fracture damage is located based on the measured values and theoretical values of the preset electrical parameters. Specifically, because the first metal wire 111 and the second metal wire 112 in the chip are parallel to each other and separated by a first distance, a capacitor is formed between the first metal wire 111 and the second metal wire 112 in each metal layer. Furthermore, since the first metal wires 111 on each metal layer 11 are connected end-to-end in series through the first vias 41 in each dielectric layer 12 to form a first series wire 51, and the second metal wires 112 on each metal layer 11 are connected end-to-end in series through the second vias 42 in each dielectric layer 12 to form a second series wire 52, the first series wires 51 and the second series wires 52 correspond to each other. Therefore, this is equivalent to connecting the capacitors formed by the first metal wires 111 and the second metal wires 112 in each metal layer in parallel to obtain a parallel capacitance. Thus, after the first target end 511 of the first series wire 51 and the first target end 521 of the second series wire 52 are respectively led out of the chip through metal pins, the magnitude of the parallel capacitance can be easily measured through these two metal pins. At the same time, since the first target end 511 and the first target end 521 are located in the same metal layer 11 of the chip 1, the measured value of the parallel capacitance is not only related to the electrical characteristics of the parallel capacitance itself, but also related to the length of the series line connected to the corresponding metal pin in the first series line 51 and the length of the series line connected to the corresponding metal pin in the second series line 52. Therefore, based on the measured value of the parallel capacitance and the theoretical value of the parallel capacitance, the length of the series line connected to the corresponding metal pin in the first series line 51 and the length of the series line connected to the corresponding metal pin in the second series line 52 can be determined, and then the two series line lengths can be used to determine whether the first series line 51 or the second series line 52 is broken and the fracture can be located if it occurs, thereby realizing fracture damage detection and positioning of the chip 1, which is conducive to further improvement of the process.

[0063] Specifically, in one embodiment of the present invention, in step S201, the measurement value of the preset electrical parameter of the chip can be obtained through the metal pin corresponding to the first target end of the first series wire and the metal pin corresponding to the first target end of the second series wire. For example, the test leads of a digital multimeter or an analog multimeter can be respectively contacted with the above-mentioned two metal pins to obtain the measurement value of the preset electrical parameter of the chip, such as the measurement value of the capacitance between the first series wire and the second series wire.

[0064] After obtaining the measured values of the preset electrical parameters of the chip, in one embodiment of the present invention, in step S202, it can be determined whether the chip has fracture damage based on the measured values and theoretical values of the preset electrical parameters. In a specific implementation, determining whether the chip has fracture damage based on the measured values and theoretical values of the preset electrical parameters can include: calculating the theoretical value of the capacitance between the first series line and the second series line based on the design parameters of the chip; if the difference between the theoretical value of the capacitance and the measured value of the capacitance is within a preset range, determining that the chip has no fracture damage; if the difference between the theoretical value of the capacitance and the measured value of the capacitance is outside the preset range, determining that the chip has fracture damage.

[0065] From the description of the chip provided in the embodiment of the present invention, it can be seen that in the embodiment of the present invention, the capacitance between the first series wire and the second series wire is equal to the capacitance formed by the corresponding first metal wire and the second metal wire in each metal layer in parallel. Since each metal layer and each dielectric layer may have its own special process requirements in the semiconductor process, such as different materials and different structural dimensions, the capacitance formed by the first metal wire and the second metal wire in different metal layers may also be different. Based on this, the theoretical value of the capacitance formed by the first metal wire and the second metal wire in each metal layer can be calculated according to the specific design parameters of the chip.

[0066] Specifically, the capacitance between the first series line and the second series line is equal to the capacitance formed by the first metal line and the second metal line corresponding to each other in each metal layer in parallel. Then the theoretical capacitance value of the parallel capacitance is equal to the sum of the theoretical values of the capacitance formed by the first metal line and the second metal line corresponding to each other in each metal layer, that is,

[0067] Ctotal = C1 + C2 + ... + Ctop (1)

[0068] Where Ctotal is the theoretical value of the parallel capacitance, C1, C2, ..., Ctop are the theoretical values of the capacitance between the first and second metal lines in the first metal layer, the second metal layer, ..., and the top metal layer, respectively.

[0069] In each metal layer, the theoretical value of the capacitance between the first metal line and the second metal line can be obtained according to the following formula:

[0070] C = εS / 4πkd (2)

[0071] Wherein, ε is the dielectric constant of the dielectric layer between the first metal line and the second metal line, and S is the area between the first metal line and the second metal line, which can be calculated by the following formula:

[0072] S=Lm i × Dm i (3)

[0073] Among them, Lm i Dm is the length of the portion where the first metal line and the second metal line face each other in the i-th metal layer, i is the thickness of the portion where the first metal line and the second metal line face each other in the i-th metal layer, where i=1, 2, 3...top, and top is a positive integer.

[0074] d is the distance between the first metal line and the second metal line, that is:

[0075] d=Wm i (4)

[0076] Among them, Wm i is the distance between the first metal line and the second metal line in the i-th metal layer.

[0077] k is the electrostatic force constant.

[0078] Substituting equations (2), (3) and (4) into (1), we can obtain:

[0079] Ctotal=εLm1×Dm1 / 4πkWm1+εLm2×Dm2 / 4πkWm2+...+εLm top ×Dm top / 4πkWm top (5)

[0080] The theoretical value of the parallel capacitance calculated according to formula (5) is obtained when the first series line and the second series line are both intact, that is, the first metal line and the second metal line in each metal layer are not broken. If the actual situation is that the first series line and the second series line are both intact, then the measured value of the parallel capacitance should also be consistent with the theoretical value (that is, the difference is within the preset range). If the first metal line and / or the second metal layer in one of the metal layers is broken, then the measured value of the parallel capacitance will be significantly different from the above theoretical value (that is, the difference is outside the preset range). Therefore, based on the difference between the theoretical value and the measured value of the parallel capacitance, it can be determined whether the first series line and the second series line are broken, and then whether the chip is broken. Among them, the preset range can be set or adjusted as needed, and the difference between the measured value and the theoretical value can be an absolute value or a relative value, which is not limited in the embodiments of the present invention.

[0081] For example, Figure 12 As shown, in one embodiment of the present invention, the chip 1 includes three metal layers M1, M2, and M3 from bottom to top, which form a first series line 51 and a second series line 52 respectively. One end of the first series line 51 and one end of the second series line 52 are respectively led out of the chip from the metal layer M3 through metal pins for connecting to the test equipment. If the first metal wire and the second metal wire in the metal layer M2 are broken, only the section a of the first metal wire and the second metal wire in the metal layer M2 is connected to the metal pin and can be measured, while the section b is not connected to the metal pin and cannot be measured. In other words, the capacitance measured on the metal pin only includes the capacitance between the first metal wire and the second metal wire in the metal layer M3, and the capacitance between the first metal wire and the second metal wire in the section a of the metal layer M2, but does not include the capacitance between the first metal wire and the second metal wire in the metal layer M1. Therefore, the measured value of the parallel capacitance will be significantly different from the theoretical value of the parallel capacitance, thereby determining that the chip has fracture damage.

[0082] Furthermore, when it is determined that the chip has fracture damage, in one embodiment of the present invention, in step S203 , the fracture damage can be located according to the measured value and theoretical value of the preset electrical parameter.

[0083] Specifically, in the case where the chip has fracture damage, locating the fracture damage according to the measured value and theoretical value of the preset electrical parameter may include: in the case where the chip has fracture damage, determining the calculation expression of the capacitance between the first metal wire and the second metal wire in each of the metal layers according to the design parameters of the chip, and obtaining a segmented capacitance expression; determining, according to the metal layer where the first target end is located and each of the segmented capacitance expressions, a first correspondence between the location of the fracture damage and the theoretical value of the fracture capacitance when the fracture damage occurs in any of the metal layers, or a second correspondence between the location of the fracture damage and the theoretical range of the fracture capacitance, wherein the fracture capacitance is the capacitance between the first series wire and the second series wire when the fracture damage occurs; locating the fracture damage according to the measured value of the capacitance and the first correspondence or the second correspondence.

[0084] For example, the above segmented capacitance expression can be calculated according to formulas (2), (3), and (4). Furthermore, according to the metal layer where the first target end is located, it can be determined from which metal layer the corresponding metal pin is connected to the measuring device to measure the parallel capacitance. This is of great significance for determining the location of the fracture damage. Specifically, the closer the metal layer where the fracture is located is to the metal layer where the first target end is located, the shorter the length of the series line connected to the metal pin in the first series line and / or the second series line, and the smaller the measured value of the parallel capacitance. Conversely, the farther the metal layer where the fracture is located is from the metal layer where the first target end is located, the longer the length of the series line connected to the metal pin in the first series line and / or the second series line, and the larger the measured value of the parallel capacitance. Therefore, according to the metal layer where the first target end is located and each segmented capacitance expression, the first corresponding relationship between the location of the fracture damage and the theoretical value of the fracture capacitance, or the second corresponding relationship between the location of the fracture damage and the theoretical range of the fracture capacitance, can be determined when the fracture damage occurs in any of the metal layers. The theoretical value of the fracture capacitance can be a specific capacitance value, and the theoretical range of the fracture capacitance can be a capacitance value range. The first corresponding relationship and the second corresponding relationship may be, for example, a functional relationship.

[0085] Optionally, in one example, locating the fracture damage according to the measured value of the capacitance and the first correspondence or the second correspondence may include one or more of the following: determining the metal layer where the fracture damage is located and the position of the fracture damage in the metal layer according to the measured value of the capacitance and the first correspondence; determining the metal layer where the fracture damage is located according to the measured value of the capacitance and the second correspondence. For example, the measured value of the parallel capacitance may be substituted into the first correspondence to determine the metal layer where the fracture damage is located and the position of the fracture damage in the metal layer. For another example, the measured value of the parallel capacitance may be substituted into the second correspondence to check in which theoretical range of fracture capacitance the measured value of the parallel capacitance is, thereby determining the metal layer where the fracture damage is located.

[0086] In an embodiment of the present invention, the accuracy of locating the fracture damage may vary depending on the different ways in which the first metal wires in each metal layer are connected in series to form the first series wire, the different ways in which the second metal wires are connected in series to form the second series wire, and the different fracture conditions of the first series wire and the second series wire.

[0087] Specifically, see Figure 13In one embodiment of the present invention, a first target end 511 of a first series line 51 in a chip is located in a first target layer, forming a first end 1111 of a first metal line 111 of the first series line 51. A first target end 521 of a second series line 52 in the chip is located in a first target layer, forming a second end 1122 of a second metal line 112 of the second series line 52. The first target end 511 of the first series line 51 and the first target end 521 of the second series line 52 are each led out of the chip via metal pins. The first end 1111 and the second end 1122 are identical, for example, both are right ends.

[0088] In an embodiment of the present invention, if the first series wire and / or the second series wire is broken, the measured value of the parallel capacitance can not only determine which metal layer the break is located in, but also the specific location of the break in the metal layer. This is because when the break is in different locations in the metal layer, the length of the first metal wire and / or the second metal wire in the metal layer connected to the metal pin will also be different, and thus, the capacitance connected to the measurement circuit will also be different. The longer the first metal wire and the second metal wire connected to the metal pin, the greater the capacitance connected to the measurement circuit. The shorter the first metal wire and the second metal wire connected to the metal pin, the smaller the capacitance connected to the measurement circuit.

[0089] It can be understood that since the first metal wire and the second metal wire are equivalent to two opposite plates of a capacitor, if the fracture damage causes the lengths of the first metal wire and the second metal wire connected to the metal pin to be different, the capacitance between the first metal wire and the second metal wire shall be calculated based on the length of the metal wire with the shorter connection length.

[0090] and Figure 13 In contrast to the embodiment shown, see Figure 14 In another embodiment of the present invention, the first end 1111 is different from the second end 1122. For example, the first end 1111 is the right end and the second end 1122 is the left end. In one example, if the first metal wire and the second metal wire in a certain metal layer are both broken, and the breakage causes the parts of the first metal wire and the second metal wire connected to the metal pin to not face each other (see Figure 14 In the example, segment a of the first metal wire and segment a of the second metal wire are staggered with each other), so they cannot form a capacitor as a corresponding capacitor substrate. In other words, in this metal layer, no matter where the fracture occurs, the measured value of the parallel capacitance is the same, and the capacitance between the first metal wire and the second metal wire in the metal layer is not included. In this case, only the metal layer where the fracture is located can be determined, and the specific location of the fracture in the metal layer cannot be further determined. Specifically, it is possible to check which theoretical range of fracture capacitance the measured value of the capacitance is within, thereby determining in which metal layer the fracture damage occurs.

[0091] Still Figure 12 Taking the chip shown as an example, according to the expressions of each segment capacitance, the theoretical value of the segment capacitance of the M1 layer is C1, the theoretical value of the segment capacitance of the M2 layer is C2, and the theoretical value of the segment capacitance of the M3 layer is C3. The first target end is located at the M3 layer. The second corresponding relationship includes:

[0092] If the M1 layer is fractured, the theoretical range of the corresponding fracture capacitance is greater than C2+C3 and less than C1+C2+C3. That is, if the measured value of the parallel capacitance is between (C2+C3) and (C1+C2+C3), it can be determined that the M1 layer has been fractured.

[0093] If the M2 layer is fractured, the theoretical range of the corresponding fracture capacitance is greater than C3 and less than C2+C3. That is, if the measured value of the parallel capacitance is between C3 and (C2+C3), it can be determined that the M2 layer is fractured.

[0094] If the M3 layer is fractured, the theoretical range of the corresponding fracture capacitance is less than C3. That is, if the measured value of the parallel capacitance is less than C3, it can be determined that the M3 layer is fractured.

[0095] See also Figure 15 In another example, if only one of the first and second metal wires in a metal layer is broken while the other is intact, portions of the first and second metal wires connected to the metal pins (segment a) still face each other, forming a corresponding capacitor. Therefore, the specific location of the break in the metal layer can be determined based on the measured value of the parallel capacitance.

[0096] Furthermore, based on locating the fracture damage according to preset electrical parameters, in some embodiments of the present invention, the accuracy of fracture locating can be improved by making use of the layout changes of the first series line and the second series line in the chip.

[0097] Specifically, in one embodiment of the present invention, the chip may include at least one series wire group, wherein each series wire group includes a first series wire and a second series wire; there is no electrical connection between the series wire groups; in each series wire group, a first metal wire and a second metal wire located in the same metal layer form a metal wire group; based on this, step S203, when the chip has fracture damage, locates the fracture damage according to the measured value and theoretical value of the preset electrical parameter. Specifically, it may include: determining the distribution range of the fracture damage in the chip according to the position of the series wire group corresponding to the preset electrical parameter in the chip. In this way, if there are multiple fractures in the chip, they can be located more specifically and separately through these series wire groups. Among them, the positioning method and principle of the fracture damage of each series wire group have been described in detail in the previous text and will not be repeated here.

[0098] In the aforementioned embodiment, whether the chip is fractured or damaged is determined by comparing the measured value and theoretical value of the capacitance between the first series line and the second series line, but the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, whether the chip is fractured or damaged may be determined by other methods.

[0099] Specifically, in one embodiment, in a chip, the second target end of the first series wire and the second target end of the second series wire are each connected to the chip via a metal pin, wherein the second target end of the first series wire and the second target end of the second series wire are located on the same metal layer of the chip. As previously described, the first target end of the first series wire and the first target end of the second series wire are each connected to the chip via a metal pin, wherein the first target end of the first series wire and the first target end of the second series wire are located on the same metal layer of the chip. In this way, both endpoints of the first series wire are connected to the chip via metal pins. Similarly, both endpoints of the second series wire are also connected to the chip via metal pins. Therefore, the electrical parameters that can be measured for the first and second series wires are more diverse.

[0100] Illustratively, in one embodiment of the present invention, the preset electrical parameters also include one or more of the following: the resistance of the first series wire, the current flowing through the first series wire, the resistance of the second series wire, and the current flowing through the second series wire; based on this, in step S201, obtaining the measured values of the preset electrical parameters of the chip through the metal pins corresponding to the first target end of the first series wire and the metal pins corresponding to the first target end of the second series wire may include one or more of the following: obtaining the resistance of the first series wire or the current flowing through the first series wire through the metal pins corresponding to the first target end and the second target end of the first series wire respectively; obtaining the resistance of the second series wire or the current flowing through the second series wire through the metal pins corresponding to the first target end and the second target end of the second series wire respectively.

[0101] Accordingly, in step S202, determining whether the chip has fracture damage based on the measured value and theoretical value of the preset electrical parameter may include one or more of the following: if the resistance of the first series wire and / or the resistance of the second series wire is greater than a preset resistance threshold, determining that the chip has fracture damage; if the resistance of the first series wire and / or the resistance of the second series wire is less than the preset resistance threshold, determining that the chip does not have fracture damage; if the current flowing through the first series wire and / or the current flowing through the second series wire is less than a preset current threshold, determining that the chip has fracture damage; if the current flowing through the first series wire and / or the current flowing through the second series wire is greater than a preset current threshold, determining that the chip does not have fracture damage. The preset resistance threshold may be a very large resistance value, close to the resistance value in a short circuit situation, such as 500 megohms. Thus, if the resistance of the first series wire and / or the resistance of the second series wire is greater than the preset resistance threshold, it can be considered that there is a short circuit in the first series wire and / or the second series wire, that is, the chip has fracture damage. The preset current threshold can be a very small current value, close to the current value of 0 in the case of a short circuit, for example 0.001 microamperes. In this way, if the current flowing through the first series line and / or the current flowing through the second series line is greater than the preset current threshold, it can be determined that there is no short circuit in the first series line and / or the second chip, that is, there is no breakage damage in the chip.

[0102] In the embodiment of the present invention, resistance detection or current detection can more quickly and directly determine whether the first and second series lines are broken. After the presence of the broken damage is determined, the broken damage can be further located by capacitance measurement.

[0103] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0104] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0105] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0106] For the convenience of description, the above device is described as being divided into various units / modules based on their functions. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0107] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0108] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A chip, characterized in that: include: At least one metal layer and at least one dielectric layer are alternately stacked; each of the metal layers includes a main body pattern disposed in a main body region and a first metal line and a second metal line disposed in an edge region, the first metal line and the second metal line being parallel to each other and spaced a first distance apart; The edge area surrounds the periphery of the main body area; There is no electrical connection between the main pattern and the first metal line and the second metal line; The first metal wires on each metal layer are connected end to end in series via the first via holes in each dielectric layer to form a first series wire, and the second metal wires on each metal layer are connected end to end in series via the second via holes in each dielectric layer to form a second series wire, the first series wire and the second series wire correspond to each other, and there is no electrical connection between the first series wire and the second series wire; The first target end of the first series line and the first target end of the second series line are respectively led out of the chip through metal pins, wherein the first target end of the first series line and the first target end of the second series line are located on the same metal layer of the chip; The metal pin corresponding to the first target end of the first series line and the metal pin corresponding to the first target end of the second series line are used to measure preset electrical parameters of the chip to determine the length of the series line connected to the corresponding metal pin in the first series line and the length of the series line connected to the corresponding metal pin in the second series line, wherein the preset electrical parameters include the capacitance between the first series line and the second series line.

2. The chip according to claim 1, characterized in that The chip includes at least one series line group, wherein each series line group includes one first series line and one corresponding second series line; and there is no electrical connection between the series line groups; In each of the series line groups, one first metal line and one second metal line located in the same metal layer form a metal line group.

3. The chip according to claim 2, characterized in that In the same metal layer, each metal wire group is distributed around the main area and pieced together to form a ring with a gap, and the gap is the gap between two adjacent metal wire groups; wherein, the first metal wires in each metal wire group are pieced together to form a first ring with a first gap, and the first gap is the gap between the adjacent endpoints of two adjacent first metal wires; the second metal wires in each metal wire group are pieced together to form a second ring with a second gap, and the second gap is the gap between the adjacent endpoints of two adjacent second metal wires; and the second ring is located inside the first ring.

4. The chip according to claim 2, characterized in that The first metal wires and the second metal wires in the same metal wire group are equal or different in length; in different metal wire groups, the first metal wires are equal or different in length, and the second metal wires are equal or different in length.

5. The chip according to claim 2, characterized in that In different metal wire groups, the first distances between the first metal wire and the second metal wire are equal or different, and the first distance is a preset multiple of the line width of the first metal wire, and the preset multiple is between 0.5 times and 5 times.

6. The chip according to claim 2, characterized in that The metal wire groups belonging to the same series wire group are aligned or staggered with each other in a direction perpendicular to the metal layer.

7. The chip according to claim 2, characterized in that The number of the series line groups is 1 to 20.

8. The chip according to any one of claims 1 to 7, characterized in that The first target end of the first series line is located in the first target layer and forms the first end of the first metal line of the first series line; The first target end of the second series line is located in the first target layer and forms the second end of the second metal line of the second series line; The first end is the same as or different from the second end; and the first target layer is the top layer or the bottom layer in the at least one metal layer.

9. The chip according to any one of claims 1 to 7, characterized in that The first metal wire and the second metal wire are line segments, or are broken lines formed by splicing multiple line segments.

10. The chip according to any one of claims 1 to 7, characterized in that The second target end of the first series line and the second target end of the second series line are respectively led out of the chip through metal pins, wherein the second target end of the first series line and the second target end of the second series line are located in the same metal layer of the chip.

11. A chip testing method, characterized in that: The chip is the chip according to claim 1, and the testing method comprises: Obtaining a measurement value of a preset electrical parameter of the chip through a metal pin corresponding to the first target end of the first series wire and a metal pin corresponding to the first target end of the second series wire; the preset electrical parameter includes a capacitance between the first series wire and the second series wire; Determining whether the chip has fracture damage based on the measured value and theoretical value of the preset electrical parameter; In the case that the chip has fracture damage, the fracture damage is located according to the measured value and theoretical value of the preset electrical parameter.

12. The testing method according to claim 11, characterized in that: Determining whether the chip has fracture damage according to the measured value and theoretical value of the preset electrical parameter includes: Calculating a theoretical value of capacitance between the first series line and the second series line according to design parameters of the chip; If the difference between the theoretical value of the capacitance and the measured value of the capacitance is within a preset range, it is determined that the chip does not have any fracture damage; If the difference between the theoretical value of the capacitance and the measured value of the capacitance is outside the preset range, it is determined that the chip has fracture damage.

13. The testing method according to claim 11, characterized in that: In the chip, the second target end of the first series wire and the second target end of the second series wire are respectively led out of the chip through metal pins, wherein the second target end of the first series wire and the second target end of the second series wire are located on the same metal layer of the chip; The preset electrical parameter further includes at least one of the following: resistance of the first series line, current flowing through the first series line, resistance of the second series line, current flowing through the second series line; Obtaining a measurement value of a preset electrical parameter of the chip through the metal pin corresponding to the first target end of the first series wire and the metal pin corresponding to the first target end of the second series wire includes at least one of the following: obtaining the resistance of the first series line or the current flowing through the first series line through metal pins corresponding to the first target end and the second target end of the first series line; obtaining the resistance of the second series line or the current flowing through the second series line through the metal pins corresponding to the first target end and the second target end of the second series line; Determining whether the chip has fracture damage based on the measured value and the theoretical value of the preset electrical parameter includes at least one of the following: If the resistance of the first series line and / or the resistance of the second series line is greater than a preset resistance threshold, determining that the chip has fracture damage; If the resistance of the first series line and / or the resistance of the second series line is less than the preset resistance threshold, it is determined that the chip does not have any fracture damage; If the current flowing through the first series line and / or the current flowing through the second series line is less than a preset current threshold, determining that the chip has fracture damage; If the current flowing through the first series line and / or the current flowing through the second series line is greater than a preset current threshold, it is determined that the chip does not have any fracture damage.

14. The testing method according to claim 11, characterized in that: When the chip has fracture damage, locating the fracture damage according to the measured value and theoretical value of the preset electrical parameter includes: In the case where the chip has fracture damage, determining a calculation expression for the capacitance between the first metal wire and the second metal wire in each metal layer according to the design parameters of the chip, to obtain a segmented capacitance expression; Determining, based on the metal layer where the first target end is located and each of the segmented capacitance expressions, a first correspondence between a location of the fracture damage and a theoretical value of the fracture capacitance, or a second correspondence between a location of the fracture damage and a theoretical range of the fracture capacitance, when fracture damage occurs in any of the metal layers, wherein the fracture capacitance is the capacitance between the first series line and the second series line when fracture damage occurs; The fracture damage is located according to the measured value of the capacitance and the first corresponding relationship or the second corresponding relationship.

15. The testing method according to claim 14, characterized in that: The locating of the fracture damage according to the measured value of the capacitance and the first corresponding relationship or the second corresponding relationship includes at least one of the following: determining the metal layer where the fracture damage is located and the position of the fracture damage in the metal layer according to the measured value of the capacitance and the first corresponding relationship; The metal layer where the fracture damage is located is determined according to the measured value of the capacitance and the second corresponding relationship.

16. The testing method according to claim 11, characterized in that: The chip includes at least one series line group, wherein each series line group includes one first series line and one second series line; and there is no electrical connection between the series line groups; In each of the series line groups, one first metal line and one second metal line located in the same metal layer form a metal line group; When the chip has fracture damage, locating the fracture damage according to the measured value and theoretical value of the preset electrical parameter includes: The distribution range of the fracture damage in the chip is determined according to the position of the series line group corresponding to the preset electrical parameters in the chip.

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